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1802d0be | 1 | // SPDX-License-Identifier: GPL-2.0-only |
0df4fabe YW |
2 | /* |
3 | * Copyright (c) 2015-2016 MediaTek Inc. | |
4 | * Author: Yong Wu <yong.wu@mediatek.com> | |
0df4fabe | 5 | */ |
ef0f0986 | 6 | #include <linux/bitfield.h> |
0df4fabe YW |
7 | #include <linux/bug.h> |
8 | #include <linux/clk.h> | |
9 | #include <linux/component.h> | |
10 | #include <linux/device.h> | |
803cf9e5 | 11 | #include <linux/dma-direct.h> |
0df4fabe YW |
12 | #include <linux/err.h> |
13 | #include <linux/interrupt.h> | |
14 | #include <linux/io.h> | |
15 | #include <linux/iommu.h> | |
16 | #include <linux/iopoll.h> | |
17 | #include <linux/list.h> | |
c2c59456 | 18 | #include <linux/mfd/syscon.h> |
18d8c74e | 19 | #include <linux/module.h> |
0df4fabe | 20 | #include <linux/of_address.h> |
0df4fabe YW |
21 | #include <linux/of_irq.h> |
22 | #include <linux/of_platform.h> | |
23 | #include <linux/platform_device.h> | |
baf94e6e | 24 | #include <linux/pm_runtime.h> |
c2c59456 | 25 | #include <linux/regmap.h> |
0df4fabe YW |
26 | #include <linux/slab.h> |
27 | #include <linux/spinlock.h> | |
c2c59456 | 28 | #include <linux/soc/mediatek/infracfg.h> |
0df4fabe | 29 | #include <asm/barrier.h> |
0df4fabe YW |
30 | #include <soc/mediatek/smi.h> |
31 | ||
9ca340c9 | 32 | #include "mtk_iommu.h" |
0df4fabe YW |
33 | |
34 | #define REG_MMU_PT_BASE_ADDR 0x000 | |
907ba6a1 | 35 | #define MMU_PT_ADDR_MASK GENMASK(31, 7) |
0df4fabe YW |
36 | |
37 | #define REG_MMU_INVALIDATE 0x020 | |
38 | #define F_ALL_INVLD 0x2 | |
39 | #define F_MMU_INV_RANGE 0x1 | |
40 | ||
41 | #define REG_MMU_INVLD_START_A 0x024 | |
42 | #define REG_MMU_INVLD_END_A 0x028 | |
43 | ||
068c86e9 | 44 | #define REG_MMU_INV_SEL_GEN2 0x02c |
b053bc71 | 45 | #define REG_MMU_INV_SEL_GEN1 0x038 |
0df4fabe YW |
46 | #define F_INVLD_EN0 BIT(0) |
47 | #define F_INVLD_EN1 BIT(1) | |
48 | ||
75eed350 | 49 | #define REG_MMU_MISC_CTRL 0x048 |
4bb2bf4c CH |
50 | #define F_MMU_IN_ORDER_WR_EN_MASK (BIT(1) | BIT(17)) |
51 | #define F_MMU_STANDARD_AXI_MODE_MASK (BIT(3) | BIT(19)) | |
52 | ||
0df4fabe | 53 | #define REG_MMU_DCM_DIS 0x050 |
35c1b48d CH |
54 | #define REG_MMU_WR_LEN_CTRL 0x054 |
55 | #define F_MMU_WR_THROT_DIS_MASK (BIT(5) | BIT(21)) | |
0df4fabe YW |
56 | |
57 | #define REG_MMU_CTRL_REG 0x110 | |
acb3c92a | 58 | #define F_MMU_TF_PROT_TO_PROGRAM_ADDR (2 << 4) |
0df4fabe | 59 | #define F_MMU_PREFETCH_RT_REPLACE_MOD BIT(4) |
acb3c92a | 60 | #define F_MMU_TF_PROT_TO_PROGRAM_ADDR_MT8173 (2 << 5) |
0df4fabe YW |
61 | |
62 | #define REG_MMU_IVRP_PADDR 0x114 | |
70ca608b | 63 | |
30e2fccf YW |
64 | #define REG_MMU_VLD_PA_RNG 0x118 |
65 | #define F_MMU_VLD_PA_RNG(EA, SA) (((EA) << 8) | (SA)) | |
0df4fabe YW |
66 | |
67 | #define REG_MMU_INT_CONTROL0 0x120 | |
68 | #define F_L2_MULIT_HIT_EN BIT(0) | |
69 | #define F_TABLE_WALK_FAULT_INT_EN BIT(1) | |
70 | #define F_PREETCH_FIFO_OVERFLOW_INT_EN BIT(2) | |
71 | #define F_MISS_FIFO_OVERFLOW_INT_EN BIT(3) | |
72 | #define F_PREFETCH_FIFO_ERR_INT_EN BIT(5) | |
73 | #define F_MISS_FIFO_ERR_INT_EN BIT(6) | |
74 | #define F_INT_CLR_BIT BIT(12) | |
75 | ||
76 | #define REG_MMU_INT_MAIN_CONTROL 0x124 | |
15a01f4c YW |
77 | /* mmu0 | mmu1 */ |
78 | #define F_INT_TRANSLATION_FAULT (BIT(0) | BIT(7)) | |
79 | #define F_INT_MAIN_MULTI_HIT_FAULT (BIT(1) | BIT(8)) | |
80 | #define F_INT_INVALID_PA_FAULT (BIT(2) | BIT(9)) | |
81 | #define F_INT_ENTRY_REPLACEMENT_FAULT (BIT(3) | BIT(10)) | |
82 | #define F_INT_TLB_MISS_FAULT (BIT(4) | BIT(11)) | |
83 | #define F_INT_MISS_TRANSACTION_FIFO_FAULT (BIT(5) | BIT(12)) | |
84 | #define F_INT_PRETETCH_TRANSATION_FIFO_FAULT (BIT(6) | BIT(13)) | |
0df4fabe YW |
85 | |
86 | #define REG_MMU_CPE_DONE 0x12C | |
87 | ||
88 | #define REG_MMU_FAULT_ST1 0x134 | |
15a01f4c YW |
89 | #define F_REG_MMU0_FAULT_MASK GENMASK(6, 0) |
90 | #define F_REG_MMU1_FAULT_MASK GENMASK(13, 7) | |
0df4fabe | 91 | |
15a01f4c | 92 | #define REG_MMU0_FAULT_VA 0x13c |
ef0f0986 YW |
93 | #define F_MMU_INVAL_VA_31_12_MASK GENMASK(31, 12) |
94 | #define F_MMU_INVAL_VA_34_32_MASK GENMASK(11, 9) | |
95 | #define F_MMU_INVAL_PA_34_32_MASK GENMASK(8, 6) | |
0df4fabe YW |
96 | #define F_MMU_FAULT_VA_WRITE_BIT BIT(1) |
97 | #define F_MMU_FAULT_VA_LAYER_BIT BIT(0) | |
98 | ||
15a01f4c YW |
99 | #define REG_MMU0_INVLD_PA 0x140 |
100 | #define REG_MMU1_FAULT_VA 0x144 | |
101 | #define REG_MMU1_INVLD_PA 0x148 | |
102 | #define REG_MMU0_INT_ID 0x150 | |
103 | #define REG_MMU1_INT_ID 0x154 | |
37276e00 CH |
104 | #define F_MMU_INT_ID_COMM_ID(a) (((a) >> 9) & 0x7) |
105 | #define F_MMU_INT_ID_SUB_COMM_ID(a) (((a) >> 7) & 0x3) | |
15a01f4c YW |
106 | #define F_MMU_INT_ID_LARB_ID(a) (((a) >> 7) & 0x7) |
107 | #define F_MMU_INT_ID_PORT_ID(a) (((a) >> 2) & 0x1f) | |
0df4fabe | 108 | |
829316b3 | 109 | #define MTK_PROTECT_PA_ALIGN 256 |
0df4fabe | 110 | |
6b717796 CH |
111 | #define HAS_4GB_MODE BIT(0) |
112 | /* HW will use the EMI clock if there isn't the "bclk". */ | |
113 | #define HAS_BCLK BIT(1) | |
114 | #define HAS_VLD_PA_RNG BIT(2) | |
115 | #define RESET_AXI BIT(3) | |
4bb2bf4c | 116 | #define OUT_ORDER_WR_EN BIT(4) |
37276e00 | 117 | #define HAS_SUB_COMM BIT(5) |
35c1b48d | 118 | #define WR_THROT_EN BIT(6) |
d1b5ef00 | 119 | #define HAS_LEGACY_IVRP_PADDR BIT(7) |
2f317da4 | 120 | #define IOVA_34_EN BIT(8) |
6b717796 CH |
121 | |
122 | #define MTK_IOMMU_HAS_FLAG(pdata, _x) \ | |
123 | ((((pdata)->flags) & (_x)) == (_x)) | |
124 | ||
0df4fabe | 125 | struct mtk_iommu_domain { |
0df4fabe YW |
126 | struct io_pgtable_cfg cfg; |
127 | struct io_pgtable_ops *iop; | |
128 | ||
08500c43 | 129 | struct mtk_iommu_data *data; |
0df4fabe YW |
130 | struct iommu_domain domain; |
131 | }; | |
132 | ||
b65f5016 | 133 | static const struct iommu_ops mtk_iommu_ops; |
0df4fabe | 134 | |
7f37a91d YW |
135 | static int mtk_iommu_hw_init(const struct mtk_iommu_data *data); |
136 | ||
bfed8731 YW |
137 | #define MTK_IOMMU_TLB_ADDR(iova) ({ \ |
138 | dma_addr_t _addr = iova; \ | |
139 | ((lower_32_bits(_addr) & GENMASK(31, 12)) | upper_32_bits(_addr));\ | |
140 | }) | |
141 | ||
76ce6546 YW |
142 | /* |
143 | * In M4U 4GB mode, the physical address is remapped as below: | |
144 | * | |
145 | * CPU Physical address: | |
146 | * ==================== | |
147 | * | |
148 | * 0 1G 2G 3G 4G 5G | |
149 | * |---A---|---B---|---C---|---D---|---E---| | |
150 | * +--I/O--+------------Memory-------------+ | |
151 | * | |
152 | * IOMMU output physical address: | |
153 | * ============================= | |
154 | * | |
155 | * 4G 5G 6G 7G 8G | |
156 | * |---E---|---B---|---C---|---D---| | |
157 | * +------------Memory-------------+ | |
158 | * | |
159 | * The Region 'A'(I/O) can NOT be mapped by M4U; For Region 'B'/'C'/'D', the | |
160 | * bit32 of the CPU physical address always is needed to set, and for Region | |
161 | * 'E', the CPU physical address keep as is. | |
162 | * Additionally, The iommu consumers always use the CPU phyiscal address. | |
163 | */ | |
b4dad40e | 164 | #define MTK_IOMMU_4GB_MODE_REMAP_BASE 0x140000000UL |
76ce6546 | 165 | |
7c3a2ec0 YW |
166 | static LIST_HEAD(m4ulist); /* List all the M4U HWs */ |
167 | ||
168 | #define for_each_m4u(data) list_for_each_entry(data, &m4ulist, list) | |
169 | ||
585e58f4 YW |
170 | struct mtk_iommu_iova_region { |
171 | dma_addr_t iova_base; | |
172 | unsigned long long size; | |
173 | }; | |
174 | ||
175 | static const struct mtk_iommu_iova_region single_domain[] = { | |
176 | {.iova_base = 0, .size = SZ_4G}, | |
177 | }; | |
178 | ||
9e3489e0 YW |
179 | static const struct mtk_iommu_iova_region mt8192_multi_dom[] = { |
180 | { .iova_base = 0x0, .size = SZ_4G}, /* disp: 0 ~ 4G */ | |
181 | #if IS_ENABLED(CONFIG_ARCH_DMA_ADDR_T_64BIT) | |
182 | { .iova_base = SZ_4G, .size = SZ_4G}, /* vdec: 4G ~ 8G */ | |
183 | { .iova_base = SZ_4G * 2, .size = SZ_4G}, /* CAM/MDP: 8G ~ 12G */ | |
184 | { .iova_base = 0x240000000ULL, .size = 0x4000000}, /* CCU0 */ | |
185 | { .iova_base = 0x244000000ULL, .size = 0x4000000}, /* CCU1 */ | |
186 | #endif | |
187 | }; | |
188 | ||
7c3a2ec0 YW |
189 | /* |
190 | * There may be 1 or 2 M4U HWs, But we always expect they are in the same domain | |
191 | * for the performance. | |
192 | * | |
193 | * Here always return the mtk_iommu_data of the first probed M4U where the | |
194 | * iommu domain information is recorded. | |
195 | */ | |
196 | static struct mtk_iommu_data *mtk_iommu_get_m4u_data(void) | |
197 | { | |
198 | struct mtk_iommu_data *data; | |
199 | ||
200 | for_each_m4u(data) | |
201 | return data; | |
202 | ||
203 | return NULL; | |
204 | } | |
205 | ||
0df4fabe YW |
206 | static struct mtk_iommu_domain *to_mtk_domain(struct iommu_domain *dom) |
207 | { | |
208 | return container_of(dom, struct mtk_iommu_domain, domain); | |
209 | } | |
210 | ||
0954d61a | 211 | static void mtk_iommu_tlb_flush_all(struct mtk_iommu_data *data) |
0df4fabe | 212 | { |
7c3a2ec0 | 213 | for_each_m4u(data) { |
c0b57581 YW |
214 | if (pm_runtime_get_if_in_use(data->dev) <= 0) |
215 | continue; | |
216 | ||
7c3a2ec0 | 217 | writel_relaxed(F_INVLD_EN1 | F_INVLD_EN0, |
b053bc71 | 218 | data->base + data->plat_data->inv_sel_reg); |
7c3a2ec0 YW |
219 | writel_relaxed(F_ALL_INVLD, data->base + REG_MMU_INVALIDATE); |
220 | wmb(); /* Make sure the tlb flush all done */ | |
c0b57581 YW |
221 | |
222 | pm_runtime_put(data->dev); | |
7c3a2ec0 | 223 | } |
0df4fabe YW |
224 | } |
225 | ||
1f4fd624 | 226 | static void mtk_iommu_tlb_flush_range_sync(unsigned long iova, size_t size, |
0954d61a YW |
227 | size_t granule, |
228 | struct mtk_iommu_data *data) | |
0df4fabe | 229 | { |
c0b57581 | 230 | bool has_pm = !!data->dev->pm_domain; |
1f4fd624 YW |
231 | unsigned long flags; |
232 | int ret; | |
233 | u32 tmp; | |
0df4fabe | 234 | |
7c3a2ec0 | 235 | for_each_m4u(data) { |
c0b57581 YW |
236 | if (has_pm) { |
237 | if (pm_runtime_get_if_in_use(data->dev) <= 0) | |
238 | continue; | |
239 | } | |
240 | ||
1f4fd624 | 241 | spin_lock_irqsave(&data->tlb_lock, flags); |
7c3a2ec0 | 242 | writel_relaxed(F_INVLD_EN1 | F_INVLD_EN0, |
b053bc71 | 243 | data->base + data->plat_data->inv_sel_reg); |
0df4fabe | 244 | |
bfed8731 YW |
245 | writel_relaxed(MTK_IOMMU_TLB_ADDR(iova), |
246 | data->base + REG_MMU_INVLD_START_A); | |
247 | writel_relaxed(MTK_IOMMU_TLB_ADDR(iova + size - 1), | |
7c3a2ec0 YW |
248 | data->base + REG_MMU_INVLD_END_A); |
249 | writel_relaxed(F_MMU_INV_RANGE, | |
250 | data->base + REG_MMU_INVALIDATE); | |
98a8f63e | 251 | |
1f4fd624 | 252 | /* tlb sync */ |
7c3a2ec0 | 253 | ret = readl_poll_timeout_atomic(data->base + REG_MMU_CPE_DONE, |
c90ae4a6 | 254 | tmp, tmp != 0, 10, 1000); |
7c3a2ec0 YW |
255 | if (ret) { |
256 | dev_warn(data->dev, | |
257 | "Partial TLB flush timed out, falling back to full flush\n"); | |
0954d61a | 258 | mtk_iommu_tlb_flush_all(data); |
7c3a2ec0 YW |
259 | } |
260 | /* Clear the CPE status */ | |
261 | writel_relaxed(0, data->base + REG_MMU_CPE_DONE); | |
1f4fd624 | 262 | spin_unlock_irqrestore(&data->tlb_lock, flags); |
c0b57581 YW |
263 | |
264 | if (has_pm) | |
265 | pm_runtime_put(data->dev); | |
0df4fabe | 266 | } |
0df4fabe YW |
267 | } |
268 | ||
0df4fabe YW |
269 | static irqreturn_t mtk_iommu_isr(int irq, void *dev_id) |
270 | { | |
271 | struct mtk_iommu_data *data = dev_id; | |
272 | struct mtk_iommu_domain *dom = data->m4u_dom; | |
37276e00 | 273 | unsigned int fault_larb, fault_port, sub_comm = 0; |
ef0f0986 YW |
274 | u32 int_state, regval, va34_32, pa34_32; |
275 | u64 fault_iova, fault_pa; | |
0df4fabe YW |
276 | bool layer, write; |
277 | ||
278 | /* Read error info from registers */ | |
279 | int_state = readl_relaxed(data->base + REG_MMU_FAULT_ST1); | |
15a01f4c YW |
280 | if (int_state & F_REG_MMU0_FAULT_MASK) { |
281 | regval = readl_relaxed(data->base + REG_MMU0_INT_ID); | |
282 | fault_iova = readl_relaxed(data->base + REG_MMU0_FAULT_VA); | |
283 | fault_pa = readl_relaxed(data->base + REG_MMU0_INVLD_PA); | |
284 | } else { | |
285 | regval = readl_relaxed(data->base + REG_MMU1_INT_ID); | |
286 | fault_iova = readl_relaxed(data->base + REG_MMU1_FAULT_VA); | |
287 | fault_pa = readl_relaxed(data->base + REG_MMU1_INVLD_PA); | |
288 | } | |
0df4fabe YW |
289 | layer = fault_iova & F_MMU_FAULT_VA_LAYER_BIT; |
290 | write = fault_iova & F_MMU_FAULT_VA_WRITE_BIT; | |
ef0f0986 YW |
291 | if (MTK_IOMMU_HAS_FLAG(data->plat_data, IOVA_34_EN)) { |
292 | va34_32 = FIELD_GET(F_MMU_INVAL_VA_34_32_MASK, fault_iova); | |
293 | pa34_32 = FIELD_GET(F_MMU_INVAL_PA_34_32_MASK, fault_iova); | |
294 | fault_iova = fault_iova & F_MMU_INVAL_VA_31_12_MASK; | |
295 | fault_iova |= (u64)va34_32 << 32; | |
296 | fault_pa |= (u64)pa34_32 << 32; | |
297 | } | |
298 | ||
15a01f4c | 299 | fault_port = F_MMU_INT_ID_PORT_ID(regval); |
37276e00 CH |
300 | if (MTK_IOMMU_HAS_FLAG(data->plat_data, HAS_SUB_COMM)) { |
301 | fault_larb = F_MMU_INT_ID_COMM_ID(regval); | |
302 | sub_comm = F_MMU_INT_ID_SUB_COMM_ID(regval); | |
303 | } else { | |
304 | fault_larb = F_MMU_INT_ID_LARB_ID(regval); | |
305 | } | |
306 | fault_larb = data->plat_data->larbid_remap[fault_larb][sub_comm]; | |
b3e5eee7 | 307 | |
0df4fabe YW |
308 | if (report_iommu_fault(&dom->domain, data->dev, fault_iova, |
309 | write ? IOMMU_FAULT_WRITE : IOMMU_FAULT_READ)) { | |
310 | dev_err_ratelimited( | |
311 | data->dev, | |
ef0f0986 | 312 | "fault type=0x%x iova=0x%llx pa=0x%llx larb=%d port=%d layer=%d %s\n", |
0df4fabe YW |
313 | int_state, fault_iova, fault_pa, fault_larb, fault_port, |
314 | layer, write ? "write" : "read"); | |
315 | } | |
316 | ||
317 | /* Interrupt clear */ | |
318 | regval = readl_relaxed(data->base + REG_MMU_INT_CONTROL0); | |
319 | regval |= F_INT_CLR_BIT; | |
320 | writel_relaxed(regval, data->base + REG_MMU_INT_CONTROL0); | |
321 | ||
322 | mtk_iommu_tlb_flush_all(data); | |
323 | ||
324 | return IRQ_HANDLED; | |
325 | } | |
326 | ||
803cf9e5 YW |
327 | static int mtk_iommu_get_domain_id(struct device *dev, |
328 | const struct mtk_iommu_plat_data *plat_data) | |
329 | { | |
330 | const struct mtk_iommu_iova_region *rgn = plat_data->iova_region; | |
331 | const struct bus_dma_region *dma_rgn = dev->dma_range_map; | |
332 | int i, candidate = -1; | |
333 | dma_addr_t dma_end; | |
334 | ||
335 | if (!dma_rgn || plat_data->iova_region_nr == 1) | |
336 | return 0; | |
337 | ||
338 | dma_end = dma_rgn->dma_start + dma_rgn->size - 1; | |
339 | for (i = 0; i < plat_data->iova_region_nr; i++, rgn++) { | |
340 | /* Best fit. */ | |
341 | if (dma_rgn->dma_start == rgn->iova_base && | |
342 | dma_end == rgn->iova_base + rgn->size - 1) | |
343 | return i; | |
344 | /* ok if it is inside this region. */ | |
345 | if (dma_rgn->dma_start >= rgn->iova_base && | |
346 | dma_end < rgn->iova_base + rgn->size) | |
347 | candidate = i; | |
348 | } | |
349 | ||
350 | if (candidate >= 0) | |
351 | return candidate; | |
352 | dev_err(dev, "Can NOT find the iommu domain id(%pad 0x%llx).\n", | |
353 | &dma_rgn->dma_start, dma_rgn->size); | |
354 | return -EINVAL; | |
355 | } | |
356 | ||
8d2c749e YW |
357 | static void mtk_iommu_config(struct mtk_iommu_data *data, struct device *dev, |
358 | bool enable, unsigned int domid) | |
0df4fabe | 359 | { |
0df4fabe YW |
360 | struct mtk_smi_larb_iommu *larb_mmu; |
361 | unsigned int larbid, portid; | |
a9bf2eec | 362 | struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev); |
8d2c749e | 363 | const struct mtk_iommu_iova_region *region; |
58f0d1d5 | 364 | int i; |
0df4fabe | 365 | |
58f0d1d5 RM |
366 | for (i = 0; i < fwspec->num_ids; ++i) { |
367 | larbid = MTK_M4U_TO_LARB(fwspec->ids[i]); | |
368 | portid = MTK_M4U_TO_PORT(fwspec->ids[i]); | |
8d2c749e | 369 | |
1ee9feb2 | 370 | larb_mmu = &data->larb_imu[larbid]; |
0df4fabe | 371 | |
8d2c749e YW |
372 | region = data->plat_data->iova_region + domid; |
373 | larb_mmu->bank[portid] = upper_32_bits(region->iova_base); | |
374 | ||
375 | dev_dbg(dev, "%s iommu for larb(%s) port %d dom %d bank %d.\n", | |
376 | enable ? "enable" : "disable", dev_name(larb_mmu->dev), | |
377 | portid, domid, larb_mmu->bank[portid]); | |
0df4fabe YW |
378 | |
379 | if (enable) | |
380 | larb_mmu->mmu |= MTK_SMI_MMU_EN(portid); | |
381 | else | |
382 | larb_mmu->mmu &= ~MTK_SMI_MMU_EN(portid); | |
383 | } | |
384 | } | |
385 | ||
4f956c97 | 386 | static int mtk_iommu_domain_finalise(struct mtk_iommu_domain *dom, |
c3045f39 YW |
387 | struct mtk_iommu_data *data, |
388 | unsigned int domid) | |
0df4fabe | 389 | { |
c3045f39 YW |
390 | const struct mtk_iommu_iova_region *region; |
391 | ||
392 | /* Use the exist domain as there is only one pgtable here. */ | |
393 | if (data->m4u_dom) { | |
394 | dom->iop = data->m4u_dom->iop; | |
395 | dom->cfg = data->m4u_dom->cfg; | |
396 | dom->domain.pgsize_bitmap = data->m4u_dom->cfg.pgsize_bitmap; | |
397 | goto update_iova_region; | |
398 | } | |
399 | ||
0df4fabe YW |
400 | dom->cfg = (struct io_pgtable_cfg) { |
401 | .quirks = IO_PGTABLE_QUIRK_ARM_NS | | |
402 | IO_PGTABLE_QUIRK_NO_PERMS | | |
b4dad40e | 403 | IO_PGTABLE_QUIRK_ARM_MTK_EXT, |
0df4fabe | 404 | .pgsize_bitmap = mtk_iommu_ops.pgsize_bitmap, |
2f317da4 | 405 | .ias = MTK_IOMMU_HAS_FLAG(data->plat_data, IOVA_34_EN) ? 34 : 32, |
0df4fabe YW |
406 | .iommu_dev = data->dev, |
407 | }; | |
408 | ||
9bdfe4c1 YW |
409 | if (MTK_IOMMU_HAS_FLAG(data->plat_data, HAS_4GB_MODE)) |
410 | dom->cfg.oas = data->enable_4GB ? 33 : 32; | |
411 | else | |
412 | dom->cfg.oas = 35; | |
413 | ||
0df4fabe YW |
414 | dom->iop = alloc_io_pgtable_ops(ARM_V7S, &dom->cfg, data); |
415 | if (!dom->iop) { | |
416 | dev_err(data->dev, "Failed to alloc io pgtable\n"); | |
417 | return -EINVAL; | |
418 | } | |
419 | ||
420 | /* Update our support page sizes bitmap */ | |
d16e0faa | 421 | dom->domain.pgsize_bitmap = dom->cfg.pgsize_bitmap; |
b7875eb9 | 422 | |
c3045f39 YW |
423 | update_iova_region: |
424 | /* Update the iova region for this domain */ | |
425 | region = data->plat_data->iova_region + domid; | |
426 | dom->domain.geometry.aperture_start = region->iova_base; | |
427 | dom->domain.geometry.aperture_end = region->iova_base + region->size - 1; | |
b7875eb9 | 428 | dom->domain.geometry.force_aperture = true; |
0df4fabe YW |
429 | return 0; |
430 | } | |
431 | ||
432 | static struct iommu_domain *mtk_iommu_domain_alloc(unsigned type) | |
433 | { | |
434 | struct mtk_iommu_domain *dom; | |
435 | ||
436 | if (type != IOMMU_DOMAIN_DMA) | |
437 | return NULL; | |
438 | ||
439 | dom = kzalloc(sizeof(*dom), GFP_KERNEL); | |
440 | if (!dom) | |
441 | return NULL; | |
442 | ||
0df4fabe YW |
443 | return &dom->domain; |
444 | } | |
445 | ||
446 | static void mtk_iommu_domain_free(struct iommu_domain *domain) | |
447 | { | |
0df4fabe YW |
448 | kfree(to_mtk_domain(domain)); |
449 | } | |
450 | ||
451 | static int mtk_iommu_attach_device(struct iommu_domain *domain, | |
452 | struct device *dev) | |
453 | { | |
3524b559 | 454 | struct mtk_iommu_data *data = dev_iommu_priv_get(dev); |
0df4fabe | 455 | struct mtk_iommu_domain *dom = to_mtk_domain(domain); |
c0b57581 | 456 | struct device *m4udev = data->dev; |
803cf9e5 | 457 | int ret, domid; |
0df4fabe | 458 | |
803cf9e5 YW |
459 | domid = mtk_iommu_get_domain_id(dev, data->plat_data); |
460 | if (domid < 0) | |
461 | return domid; | |
462 | ||
4f956c97 | 463 | if (!dom->data) { |
c3045f39 | 464 | if (mtk_iommu_domain_finalise(dom, data, domid)) |
4f956c97 YW |
465 | return -ENODEV; |
466 | dom->data = data; | |
467 | } | |
468 | ||
7f37a91d | 469 | if (!data->m4u_dom) { /* Initialize the M4U HW */ |
c0b57581 YW |
470 | ret = pm_runtime_resume_and_get(m4udev); |
471 | if (ret < 0) | |
472 | return ret; | |
473 | ||
7f37a91d | 474 | ret = mtk_iommu_hw_init(data); |
c0b57581 YW |
475 | if (ret) { |
476 | pm_runtime_put(m4udev); | |
7f37a91d | 477 | return ret; |
c0b57581 | 478 | } |
0df4fabe | 479 | data->m4u_dom = dom; |
d1e5f26f | 480 | writel(dom->cfg.arm_v7s_cfg.ttbr & MMU_PT_ADDR_MASK, |
4b00f5ac | 481 | data->base + REG_MMU_PT_BASE_ADDR); |
c0b57581 YW |
482 | |
483 | pm_runtime_put(m4udev); | |
7c3a2ec0 YW |
484 | } |
485 | ||
8d2c749e | 486 | mtk_iommu_config(data, dev, true, domid); |
0df4fabe YW |
487 | return 0; |
488 | } | |
489 | ||
490 | static void mtk_iommu_detach_device(struct iommu_domain *domain, | |
491 | struct device *dev) | |
492 | { | |
3524b559 | 493 | struct mtk_iommu_data *data = dev_iommu_priv_get(dev); |
0df4fabe | 494 | |
8d2c749e | 495 | mtk_iommu_config(data, dev, false, 0); |
0df4fabe YW |
496 | } |
497 | ||
498 | static int mtk_iommu_map(struct iommu_domain *domain, unsigned long iova, | |
781ca2de | 499 | phys_addr_t paddr, size_t size, int prot, gfp_t gfp) |
0df4fabe YW |
500 | { |
501 | struct mtk_iommu_domain *dom = to_mtk_domain(domain); | |
0df4fabe | 502 | |
b4dad40e | 503 | /* The "4GB mode" M4U physically can not use the lower remap of Dram. */ |
08500c43 | 504 | if (dom->data->enable_4GB) |
b4dad40e YW |
505 | paddr |= BIT_ULL(32); |
506 | ||
60829b4d | 507 | /* Synchronize with the tlb_lock */ |
f34ce7a7 | 508 | return dom->iop->map(dom->iop, iova, paddr, size, prot, gfp); |
0df4fabe YW |
509 | } |
510 | ||
511 | static size_t mtk_iommu_unmap(struct iommu_domain *domain, | |
56f8af5e WD |
512 | unsigned long iova, size_t size, |
513 | struct iommu_iotlb_gather *gather) | |
0df4fabe YW |
514 | { |
515 | struct mtk_iommu_domain *dom = to_mtk_domain(domain); | |
0df4fabe | 516 | |
3136895c | 517 | iommu_iotlb_gather_add_range(gather, iova, size); |
60829b4d | 518 | return dom->iop->unmap(dom->iop, iova, size, gather); |
0df4fabe YW |
519 | } |
520 | ||
56f8af5e WD |
521 | static void mtk_iommu_flush_iotlb_all(struct iommu_domain *domain) |
522 | { | |
08500c43 YW |
523 | struct mtk_iommu_domain *dom = to_mtk_domain(domain); |
524 | ||
525 | mtk_iommu_tlb_flush_all(dom->data); | |
56f8af5e WD |
526 | } |
527 | ||
528 | static void mtk_iommu_iotlb_sync(struct iommu_domain *domain, | |
529 | struct iommu_iotlb_gather *gather) | |
4d689b61 | 530 | { |
08500c43 | 531 | struct mtk_iommu_domain *dom = to_mtk_domain(domain); |
862c3715 | 532 | size_t length = gather->end - gather->start + 1; |
da3cc91b | 533 | |
1f4fd624 | 534 | mtk_iommu_tlb_flush_range_sync(gather->start, length, gather->pgsize, |
08500c43 | 535 | dom->data); |
4d689b61 RM |
536 | } |
537 | ||
20143451 YW |
538 | static void mtk_iommu_sync_map(struct iommu_domain *domain, unsigned long iova, |
539 | size_t size) | |
540 | { | |
08500c43 | 541 | struct mtk_iommu_domain *dom = to_mtk_domain(domain); |
20143451 | 542 | |
08500c43 | 543 | mtk_iommu_tlb_flush_range_sync(iova, size, size, dom->data); |
20143451 YW |
544 | } |
545 | ||
0df4fabe YW |
546 | static phys_addr_t mtk_iommu_iova_to_phys(struct iommu_domain *domain, |
547 | dma_addr_t iova) | |
548 | { | |
549 | struct mtk_iommu_domain *dom = to_mtk_domain(domain); | |
0df4fabe YW |
550 | phys_addr_t pa; |
551 | ||
0df4fabe | 552 | pa = dom->iop->iova_to_phys(dom->iop, iova); |
08500c43 | 553 | if (dom->data->enable_4GB && pa >= MTK_IOMMU_4GB_MODE_REMAP_BASE) |
b4dad40e | 554 | pa &= ~BIT_ULL(32); |
30e2fccf | 555 | |
0df4fabe YW |
556 | return pa; |
557 | } | |
558 | ||
80e4592a | 559 | static struct iommu_device *mtk_iommu_probe_device(struct device *dev) |
0df4fabe | 560 | { |
a9bf2eec | 561 | struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev); |
b16c0170 | 562 | struct mtk_iommu_data *data; |
0df4fabe | 563 | |
a9bf2eec | 564 | if (!fwspec || fwspec->ops != &mtk_iommu_ops) |
80e4592a | 565 | return ERR_PTR(-ENODEV); /* Not a iommu client device */ |
0df4fabe | 566 | |
3524b559 | 567 | data = dev_iommu_priv_get(dev); |
b16c0170 | 568 | |
80e4592a | 569 | return &data->iommu; |
0df4fabe YW |
570 | } |
571 | ||
80e4592a | 572 | static void mtk_iommu_release_device(struct device *dev) |
0df4fabe | 573 | { |
a9bf2eec | 574 | struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev); |
b16c0170 | 575 | |
a9bf2eec | 576 | if (!fwspec || fwspec->ops != &mtk_iommu_ops) |
0df4fabe YW |
577 | return; |
578 | ||
58f0d1d5 | 579 | iommu_fwspec_free(dev); |
0df4fabe YW |
580 | } |
581 | ||
582 | static struct iommu_group *mtk_iommu_device_group(struct device *dev) | |
583 | { | |
7c3a2ec0 | 584 | struct mtk_iommu_data *data = mtk_iommu_get_m4u_data(); |
c3045f39 | 585 | struct iommu_group *group; |
803cf9e5 | 586 | int domid; |
0df4fabe | 587 | |
58f0d1d5 | 588 | if (!data) |
0df4fabe YW |
589 | return ERR_PTR(-ENODEV); |
590 | ||
803cf9e5 YW |
591 | domid = mtk_iommu_get_domain_id(dev, data->plat_data); |
592 | if (domid < 0) | |
593 | return ERR_PTR(domid); | |
594 | ||
c3045f39 YW |
595 | group = data->m4u_group[domid]; |
596 | if (!group) { | |
597 | group = iommu_group_alloc(); | |
598 | if (!IS_ERR(group)) | |
599 | data->m4u_group[domid] = group; | |
3a8d40b6 | 600 | } else { |
c3045f39 | 601 | iommu_group_ref_get(group); |
0df4fabe | 602 | } |
c3045f39 | 603 | return group; |
0df4fabe YW |
604 | } |
605 | ||
606 | static int mtk_iommu_of_xlate(struct device *dev, struct of_phandle_args *args) | |
607 | { | |
0df4fabe YW |
608 | struct platform_device *m4updev; |
609 | ||
610 | if (args->args_count != 1) { | |
611 | dev_err(dev, "invalid #iommu-cells(%d) property for IOMMU\n", | |
612 | args->args_count); | |
613 | return -EINVAL; | |
614 | } | |
615 | ||
3524b559 | 616 | if (!dev_iommu_priv_get(dev)) { |
0df4fabe YW |
617 | /* Get the m4u device */ |
618 | m4updev = of_find_device_by_node(args->np); | |
0df4fabe YW |
619 | if (WARN_ON(!m4updev)) |
620 | return -EINVAL; | |
621 | ||
3524b559 | 622 | dev_iommu_priv_set(dev, platform_get_drvdata(m4updev)); |
0df4fabe YW |
623 | } |
624 | ||
58f0d1d5 | 625 | return iommu_fwspec_add_ids(dev, args->args, 1); |
0df4fabe YW |
626 | } |
627 | ||
ab1d5281 YW |
628 | static void mtk_iommu_get_resv_regions(struct device *dev, |
629 | struct list_head *head) | |
630 | { | |
631 | struct mtk_iommu_data *data = dev_iommu_priv_get(dev); | |
632 | unsigned int domid = mtk_iommu_get_domain_id(dev, data->plat_data), i; | |
633 | const struct mtk_iommu_iova_region *resv, *curdom; | |
634 | struct iommu_resv_region *region; | |
635 | int prot = IOMMU_WRITE | IOMMU_READ; | |
636 | ||
7a566173 | 637 | if ((int)domid < 0) |
ab1d5281 YW |
638 | return; |
639 | curdom = data->plat_data->iova_region + domid; | |
640 | for (i = 0; i < data->plat_data->iova_region_nr; i++) { | |
641 | resv = data->plat_data->iova_region + i; | |
642 | ||
643 | /* Only reserve when the region is inside the current domain */ | |
644 | if (resv->iova_base <= curdom->iova_base || | |
645 | resv->iova_base + resv->size >= curdom->iova_base + curdom->size) | |
646 | continue; | |
647 | ||
648 | region = iommu_alloc_resv_region(resv->iova_base, resv->size, | |
649 | prot, IOMMU_RESV_RESERVED); | |
650 | if (!region) | |
651 | return; | |
652 | ||
653 | list_add_tail(®ion->list, head); | |
654 | } | |
655 | } | |
656 | ||
b65f5016 | 657 | static const struct iommu_ops mtk_iommu_ops = { |
0df4fabe YW |
658 | .domain_alloc = mtk_iommu_domain_alloc, |
659 | .domain_free = mtk_iommu_domain_free, | |
660 | .attach_dev = mtk_iommu_attach_device, | |
661 | .detach_dev = mtk_iommu_detach_device, | |
662 | .map = mtk_iommu_map, | |
663 | .unmap = mtk_iommu_unmap, | |
56f8af5e | 664 | .flush_iotlb_all = mtk_iommu_flush_iotlb_all, |
4d689b61 | 665 | .iotlb_sync = mtk_iommu_iotlb_sync, |
20143451 | 666 | .iotlb_sync_map = mtk_iommu_sync_map, |
0df4fabe | 667 | .iova_to_phys = mtk_iommu_iova_to_phys, |
80e4592a JR |
668 | .probe_device = mtk_iommu_probe_device, |
669 | .release_device = mtk_iommu_release_device, | |
0df4fabe YW |
670 | .device_group = mtk_iommu_device_group, |
671 | .of_xlate = mtk_iommu_of_xlate, | |
ab1d5281 YW |
672 | .get_resv_regions = mtk_iommu_get_resv_regions, |
673 | .put_resv_regions = generic_iommu_put_resv_regions, | |
0df4fabe | 674 | .pgsize_bitmap = SZ_4K | SZ_64K | SZ_1M | SZ_16M, |
18d8c74e | 675 | .owner = THIS_MODULE, |
0df4fabe YW |
676 | }; |
677 | ||
678 | static int mtk_iommu_hw_init(const struct mtk_iommu_data *data) | |
679 | { | |
680 | u32 regval; | |
0df4fabe | 681 | |
86444413 | 682 | if (data->plat_data->m4u_plat == M4U_MT8173) { |
acb3c92a YW |
683 | regval = F_MMU_PREFETCH_RT_REPLACE_MOD | |
684 | F_MMU_TF_PROT_TO_PROGRAM_ADDR_MT8173; | |
86444413 CH |
685 | } else { |
686 | regval = readl_relaxed(data->base + REG_MMU_CTRL_REG); | |
687 | regval |= F_MMU_TF_PROT_TO_PROGRAM_ADDR; | |
688 | } | |
0df4fabe YW |
689 | writel_relaxed(regval, data->base + REG_MMU_CTRL_REG); |
690 | ||
691 | regval = F_L2_MULIT_HIT_EN | | |
692 | F_TABLE_WALK_FAULT_INT_EN | | |
693 | F_PREETCH_FIFO_OVERFLOW_INT_EN | | |
694 | F_MISS_FIFO_OVERFLOW_INT_EN | | |
695 | F_PREFETCH_FIFO_ERR_INT_EN | | |
696 | F_MISS_FIFO_ERR_INT_EN; | |
697 | writel_relaxed(regval, data->base + REG_MMU_INT_CONTROL0); | |
698 | ||
699 | regval = F_INT_TRANSLATION_FAULT | | |
700 | F_INT_MAIN_MULTI_HIT_FAULT | | |
701 | F_INT_INVALID_PA_FAULT | | |
702 | F_INT_ENTRY_REPLACEMENT_FAULT | | |
703 | F_INT_TLB_MISS_FAULT | | |
704 | F_INT_MISS_TRANSACTION_FIFO_FAULT | | |
705 | F_INT_PRETETCH_TRANSATION_FIFO_FAULT; | |
706 | writel_relaxed(regval, data->base + REG_MMU_INT_MAIN_CONTROL); | |
707 | ||
d1b5ef00 | 708 | if (MTK_IOMMU_HAS_FLAG(data->plat_data, HAS_LEGACY_IVRP_PADDR)) |
70ca608b YW |
709 | regval = (data->protect_base >> 1) | (data->enable_4GB << 31); |
710 | else | |
711 | regval = lower_32_bits(data->protect_base) | | |
712 | upper_32_bits(data->protect_base); | |
713 | writel_relaxed(regval, data->base + REG_MMU_IVRP_PADDR); | |
714 | ||
6b717796 CH |
715 | if (data->enable_4GB && |
716 | MTK_IOMMU_HAS_FLAG(data->plat_data, HAS_VLD_PA_RNG)) { | |
30e2fccf YW |
717 | /* |
718 | * If 4GB mode is enabled, the validate PA range is from | |
719 | * 0x1_0000_0000 to 0x1_ffff_ffff. here record bit[32:30]. | |
720 | */ | |
721 | regval = F_MMU_VLD_PA_RNG(7, 4); | |
722 | writel_relaxed(regval, data->base + REG_MMU_VLD_PA_RNG); | |
723 | } | |
0df4fabe | 724 | writel_relaxed(0, data->base + REG_MMU_DCM_DIS); |
35c1b48d CH |
725 | if (MTK_IOMMU_HAS_FLAG(data->plat_data, WR_THROT_EN)) { |
726 | /* write command throttling mode */ | |
727 | regval = readl_relaxed(data->base + REG_MMU_WR_LEN_CTRL); | |
728 | regval &= ~F_MMU_WR_THROT_DIS_MASK; | |
729 | writel_relaxed(regval, data->base + REG_MMU_WR_LEN_CTRL); | |
730 | } | |
e6dec923 | 731 | |
6b717796 | 732 | if (MTK_IOMMU_HAS_FLAG(data->plat_data, RESET_AXI)) { |
75eed350 | 733 | /* The register is called STANDARD_AXI_MODE in this case */ |
4bb2bf4c CH |
734 | regval = 0; |
735 | } else { | |
736 | regval = readl_relaxed(data->base + REG_MMU_MISC_CTRL); | |
737 | regval &= ~F_MMU_STANDARD_AXI_MODE_MASK; | |
738 | if (MTK_IOMMU_HAS_FLAG(data->plat_data, OUT_ORDER_WR_EN)) | |
739 | regval &= ~F_MMU_IN_ORDER_WR_EN_MASK; | |
75eed350 | 740 | } |
4bb2bf4c | 741 | writel_relaxed(regval, data->base + REG_MMU_MISC_CTRL); |
0df4fabe YW |
742 | |
743 | if (devm_request_irq(data->dev, data->irq, mtk_iommu_isr, 0, | |
744 | dev_name(data->dev), (void *)data)) { | |
745 | writel_relaxed(0, data->base + REG_MMU_PT_BASE_ADDR); | |
0df4fabe YW |
746 | dev_err(data->dev, "Failed @ IRQ-%d Request\n", data->irq); |
747 | return -ENODEV; | |
748 | } | |
749 | ||
750 | return 0; | |
751 | } | |
752 | ||
0df4fabe YW |
753 | static const struct component_master_ops mtk_iommu_com_ops = { |
754 | .bind = mtk_iommu_bind, | |
755 | .unbind = mtk_iommu_unbind, | |
756 | }; | |
757 | ||
758 | static int mtk_iommu_probe(struct platform_device *pdev) | |
759 | { | |
760 | struct mtk_iommu_data *data; | |
761 | struct device *dev = &pdev->dev; | |
baf94e6e YW |
762 | struct device_node *larbnode, *smicomm_node; |
763 | struct platform_device *plarbdev; | |
764 | struct device_link *link; | |
0df4fabe | 765 | struct resource *res; |
b16c0170 | 766 | resource_size_t ioaddr; |
0df4fabe | 767 | struct component_match *match = NULL; |
c2c59456 | 768 | struct regmap *infracfg; |
0df4fabe | 769 | void *protect; |
0b6c0ad3 | 770 | int i, larb_nr, ret; |
c2c59456 MC |
771 | u32 val; |
772 | char *p; | |
0df4fabe YW |
773 | |
774 | data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL); | |
775 | if (!data) | |
776 | return -ENOMEM; | |
777 | data->dev = dev; | |
cecdce9d | 778 | data->plat_data = of_device_get_match_data(dev); |
0df4fabe YW |
779 | |
780 | /* Protect memory. HW will access here while translation fault.*/ | |
781 | protect = devm_kzalloc(dev, MTK_PROTECT_PA_ALIGN * 2, GFP_KERNEL); | |
782 | if (!protect) | |
783 | return -ENOMEM; | |
784 | data->protect_base = ALIGN(virt_to_phys(protect), MTK_PROTECT_PA_ALIGN); | |
785 | ||
c2c59456 MC |
786 | if (MTK_IOMMU_HAS_FLAG(data->plat_data, HAS_4GB_MODE)) { |
787 | switch (data->plat_data->m4u_plat) { | |
788 | case M4U_MT2712: | |
789 | p = "mediatek,mt2712-infracfg"; | |
790 | break; | |
791 | case M4U_MT8173: | |
792 | p = "mediatek,mt8173-infracfg"; | |
793 | break; | |
794 | default: | |
795 | p = NULL; | |
796 | } | |
797 | ||
798 | infracfg = syscon_regmap_lookup_by_compatible(p); | |
799 | ||
800 | if (IS_ERR(infracfg)) | |
801 | return PTR_ERR(infracfg); | |
802 | ||
803 | ret = regmap_read(infracfg, REG_INFRA_MISC, &val); | |
804 | if (ret) | |
805 | return ret; | |
806 | data->enable_4GB = !!(val & F_DDR_4GB_SUPPORT_EN); | |
807 | } | |
01e23c93 | 808 | |
0df4fabe YW |
809 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
810 | data->base = devm_ioremap_resource(dev, res); | |
811 | if (IS_ERR(data->base)) | |
812 | return PTR_ERR(data->base); | |
b16c0170 | 813 | ioaddr = res->start; |
0df4fabe YW |
814 | |
815 | data->irq = platform_get_irq(pdev, 0); | |
816 | if (data->irq < 0) | |
817 | return data->irq; | |
818 | ||
6b717796 | 819 | if (MTK_IOMMU_HAS_FLAG(data->plat_data, HAS_BCLK)) { |
2aa4c259 YW |
820 | data->bclk = devm_clk_get(dev, "bclk"); |
821 | if (IS_ERR(data->bclk)) | |
822 | return PTR_ERR(data->bclk); | |
823 | } | |
0df4fabe YW |
824 | |
825 | larb_nr = of_count_phandle_with_args(dev->of_node, | |
826 | "mediatek,larbs", NULL); | |
827 | if (larb_nr < 0) | |
828 | return larb_nr; | |
0df4fabe YW |
829 | |
830 | for (i = 0; i < larb_nr; i++) { | |
e6dec923 | 831 | u32 id; |
0df4fabe YW |
832 | |
833 | larbnode = of_parse_phandle(dev->of_node, "mediatek,larbs", i); | |
834 | if (!larbnode) | |
835 | return -EINVAL; | |
836 | ||
1eb8e4e2 WY |
837 | if (!of_device_is_available(larbnode)) { |
838 | of_node_put(larbnode); | |
0df4fabe | 839 | continue; |
1eb8e4e2 | 840 | } |
0df4fabe | 841 | |
e6dec923 YW |
842 | ret = of_property_read_u32(larbnode, "mediatek,larb-id", &id); |
843 | if (ret)/* The id is consecutive if there is no this property */ | |
844 | id = i; | |
845 | ||
0df4fabe | 846 | plarbdev = of_find_device_by_node(larbnode); |
1eb8e4e2 WY |
847 | if (!plarbdev) { |
848 | of_node_put(larbnode); | |
e6dec923 | 849 | return -EPROBE_DEFER; |
1eb8e4e2 | 850 | } |
1ee9feb2 | 851 | data->larb_imu[id].dev = &plarbdev->dev; |
0df4fabe | 852 | |
00c7c81f RK |
853 | component_match_add_release(dev, &match, release_of, |
854 | compare_of, larbnode); | |
0df4fabe YW |
855 | } |
856 | ||
baf94e6e YW |
857 | /* Get smi-common dev from the last larb. */ |
858 | smicomm_node = of_parse_phandle(larbnode, "mediatek,smi", 0); | |
859 | if (!smicomm_node) | |
860 | return -EINVAL; | |
861 | ||
862 | plarbdev = of_find_device_by_node(smicomm_node); | |
863 | of_node_put(smicomm_node); | |
864 | data->smicomm_dev = &plarbdev->dev; | |
865 | ||
c0b57581 YW |
866 | pm_runtime_enable(dev); |
867 | ||
baf94e6e YW |
868 | link = device_link_add(data->smicomm_dev, dev, |
869 | DL_FLAG_STATELESS | DL_FLAG_PM_RUNTIME); | |
870 | if (!link) { | |
a92a90ac DC |
871 | dev_err(dev, "Unable to link %s.\n", dev_name(data->smicomm_dev)); |
872 | ret = -EINVAL; | |
c0b57581 | 873 | goto out_runtime_disable; |
baf94e6e YW |
874 | } |
875 | ||
0df4fabe YW |
876 | platform_set_drvdata(pdev, data); |
877 | ||
b16c0170 JR |
878 | ret = iommu_device_sysfs_add(&data->iommu, dev, NULL, |
879 | "mtk-iommu.%pa", &ioaddr); | |
880 | if (ret) | |
baf94e6e | 881 | goto out_link_remove; |
b16c0170 | 882 | |
2d471b20 | 883 | ret = iommu_device_register(&data->iommu, &mtk_iommu_ops, dev); |
b16c0170 | 884 | if (ret) |
986d9ec5 | 885 | goto out_sysfs_remove; |
b16c0170 | 886 | |
da3cc91b | 887 | spin_lock_init(&data->tlb_lock); |
7c3a2ec0 YW |
888 | list_add_tail(&data->list, &m4ulist); |
889 | ||
986d9ec5 YW |
890 | if (!iommu_present(&platform_bus_type)) { |
891 | ret = bus_set_iommu(&platform_bus_type, &mtk_iommu_ops); | |
892 | if (ret) | |
893 | goto out_list_del; | |
894 | } | |
0df4fabe | 895 | |
986d9ec5 YW |
896 | ret = component_master_add_with_match(dev, &mtk_iommu_com_ops, match); |
897 | if (ret) | |
898 | goto out_bus_set_null; | |
899 | return ret; | |
900 | ||
901 | out_bus_set_null: | |
902 | bus_set_iommu(&platform_bus_type, NULL); | |
903 | out_list_del: | |
904 | list_del(&data->list); | |
905 | iommu_device_unregister(&data->iommu); | |
906 | out_sysfs_remove: | |
907 | iommu_device_sysfs_remove(&data->iommu); | |
baf94e6e YW |
908 | out_link_remove: |
909 | device_link_remove(data->smicomm_dev, dev); | |
c0b57581 YW |
910 | out_runtime_disable: |
911 | pm_runtime_disable(dev); | |
986d9ec5 | 912 | return ret; |
0df4fabe YW |
913 | } |
914 | ||
915 | static int mtk_iommu_remove(struct platform_device *pdev) | |
916 | { | |
917 | struct mtk_iommu_data *data = platform_get_drvdata(pdev); | |
918 | ||
b16c0170 JR |
919 | iommu_device_sysfs_remove(&data->iommu); |
920 | iommu_device_unregister(&data->iommu); | |
921 | ||
0df4fabe YW |
922 | if (iommu_present(&platform_bus_type)) |
923 | bus_set_iommu(&platform_bus_type, NULL); | |
924 | ||
0df4fabe | 925 | clk_disable_unprepare(data->bclk); |
baf94e6e | 926 | device_link_remove(data->smicomm_dev, &pdev->dev); |
c0b57581 | 927 | pm_runtime_disable(&pdev->dev); |
0df4fabe YW |
928 | devm_free_irq(&pdev->dev, data->irq, data); |
929 | component_master_del(&pdev->dev, &mtk_iommu_com_ops); | |
930 | return 0; | |
931 | } | |
932 | ||
34665c79 | 933 | static int __maybe_unused mtk_iommu_runtime_suspend(struct device *dev) |
0df4fabe YW |
934 | { |
935 | struct mtk_iommu_data *data = dev_get_drvdata(dev); | |
936 | struct mtk_iommu_suspend_reg *reg = &data->reg; | |
937 | void __iomem *base = data->base; | |
938 | ||
35c1b48d | 939 | reg->wr_len_ctrl = readl_relaxed(base + REG_MMU_WR_LEN_CTRL); |
75eed350 | 940 | reg->misc_ctrl = readl_relaxed(base + REG_MMU_MISC_CTRL); |
0df4fabe YW |
941 | reg->dcm_dis = readl_relaxed(base + REG_MMU_DCM_DIS); |
942 | reg->ctrl_reg = readl_relaxed(base + REG_MMU_CTRL_REG); | |
943 | reg->int_control0 = readl_relaxed(base + REG_MMU_INT_CONTROL0); | |
944 | reg->int_main_control = readl_relaxed(base + REG_MMU_INT_MAIN_CONTROL); | |
70ca608b | 945 | reg->ivrp_paddr = readl_relaxed(base + REG_MMU_IVRP_PADDR); |
b9475b34 | 946 | reg->vld_pa_rng = readl_relaxed(base + REG_MMU_VLD_PA_RNG); |
6254b64f | 947 | clk_disable_unprepare(data->bclk); |
0df4fabe YW |
948 | return 0; |
949 | } | |
950 | ||
34665c79 | 951 | static int __maybe_unused mtk_iommu_runtime_resume(struct device *dev) |
0df4fabe YW |
952 | { |
953 | struct mtk_iommu_data *data = dev_get_drvdata(dev); | |
954 | struct mtk_iommu_suspend_reg *reg = &data->reg; | |
907ba6a1 | 955 | struct mtk_iommu_domain *m4u_dom = data->m4u_dom; |
0df4fabe | 956 | void __iomem *base = data->base; |
6254b64f | 957 | int ret; |
0df4fabe | 958 | |
6254b64f YW |
959 | ret = clk_prepare_enable(data->bclk); |
960 | if (ret) { | |
961 | dev_err(data->dev, "Failed to enable clk(%d) in resume\n", ret); | |
962 | return ret; | |
963 | } | |
b34ea31f DH |
964 | |
965 | /* | |
966 | * Uppon first resume, only enable the clk and return, since the values of the | |
967 | * registers are not yet set. | |
968 | */ | |
969 | if (!m4u_dom) | |
970 | return 0; | |
971 | ||
35c1b48d | 972 | writel_relaxed(reg->wr_len_ctrl, base + REG_MMU_WR_LEN_CTRL); |
75eed350 | 973 | writel_relaxed(reg->misc_ctrl, base + REG_MMU_MISC_CTRL); |
0df4fabe YW |
974 | writel_relaxed(reg->dcm_dis, base + REG_MMU_DCM_DIS); |
975 | writel_relaxed(reg->ctrl_reg, base + REG_MMU_CTRL_REG); | |
976 | writel_relaxed(reg->int_control0, base + REG_MMU_INT_CONTROL0); | |
977 | writel_relaxed(reg->int_main_control, base + REG_MMU_INT_MAIN_CONTROL); | |
70ca608b | 978 | writel_relaxed(reg->ivrp_paddr, base + REG_MMU_IVRP_PADDR); |
b9475b34 | 979 | writel_relaxed(reg->vld_pa_rng, base + REG_MMU_VLD_PA_RNG); |
c0b57581 | 980 | writel(m4u_dom->cfg.arm_v7s_cfg.ttbr & MMU_PT_ADDR_MASK, base + REG_MMU_PT_BASE_ADDR); |
0df4fabe YW |
981 | return 0; |
982 | } | |
983 | ||
e6dec923 | 984 | static const struct dev_pm_ops mtk_iommu_pm_ops = { |
34665c79 YW |
985 | SET_RUNTIME_PM_OPS(mtk_iommu_runtime_suspend, mtk_iommu_runtime_resume, NULL) |
986 | SET_LATE_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, | |
987 | pm_runtime_force_resume) | |
0df4fabe YW |
988 | }; |
989 | ||
cecdce9d YW |
990 | static const struct mtk_iommu_plat_data mt2712_data = { |
991 | .m4u_plat = M4U_MT2712, | |
6b717796 | 992 | .flags = HAS_4GB_MODE | HAS_BCLK | HAS_VLD_PA_RNG, |
b053bc71 | 993 | .inv_sel_reg = REG_MMU_INV_SEL_GEN1, |
585e58f4 YW |
994 | .iova_region = single_domain, |
995 | .iova_region_nr = ARRAY_SIZE(single_domain), | |
37276e00 | 996 | .larbid_remap = {{0}, {1}, {2}, {3}, {4}, {5}, {6}, {7}}, |
cecdce9d YW |
997 | }; |
998 | ||
068c86e9 CH |
999 | static const struct mtk_iommu_plat_data mt6779_data = { |
1000 | .m4u_plat = M4U_MT6779, | |
1001 | .flags = HAS_SUB_COMM | OUT_ORDER_WR_EN | WR_THROT_EN, | |
1002 | .inv_sel_reg = REG_MMU_INV_SEL_GEN2, | |
585e58f4 YW |
1003 | .iova_region = single_domain, |
1004 | .iova_region_nr = ARRAY_SIZE(single_domain), | |
068c86e9 | 1005 | .larbid_remap = {{0}, {1}, {2}, {3}, {5}, {7, 8}, {10}, {9}}, |
cecdce9d YW |
1006 | }; |
1007 | ||
3c213562 FP |
1008 | static const struct mtk_iommu_plat_data mt8167_data = { |
1009 | .m4u_plat = M4U_MT8167, | |
1010 | .flags = RESET_AXI | HAS_LEGACY_IVRP_PADDR, | |
1011 | .inv_sel_reg = REG_MMU_INV_SEL_GEN1, | |
585e58f4 YW |
1012 | .iova_region = single_domain, |
1013 | .iova_region_nr = ARRAY_SIZE(single_domain), | |
3c213562 FP |
1014 | .larbid_remap = {{0}, {1}, {2}}, /* Linear mapping. */ |
1015 | }; | |
1016 | ||
cecdce9d YW |
1017 | static const struct mtk_iommu_plat_data mt8173_data = { |
1018 | .m4u_plat = M4U_MT8173, | |
d1b5ef00 FP |
1019 | .flags = HAS_4GB_MODE | HAS_BCLK | RESET_AXI | |
1020 | HAS_LEGACY_IVRP_PADDR, | |
b053bc71 | 1021 | .inv_sel_reg = REG_MMU_INV_SEL_GEN1, |
585e58f4 YW |
1022 | .iova_region = single_domain, |
1023 | .iova_region_nr = ARRAY_SIZE(single_domain), | |
37276e00 | 1024 | .larbid_remap = {{0}, {1}, {2}, {3}, {4}, {5}}, /* Linear mapping. */ |
cecdce9d YW |
1025 | }; |
1026 | ||
907ba6a1 YW |
1027 | static const struct mtk_iommu_plat_data mt8183_data = { |
1028 | .m4u_plat = M4U_MT8183, | |
6b717796 | 1029 | .flags = RESET_AXI, |
b053bc71 | 1030 | .inv_sel_reg = REG_MMU_INV_SEL_GEN1, |
585e58f4 YW |
1031 | .iova_region = single_domain, |
1032 | .iova_region_nr = ARRAY_SIZE(single_domain), | |
37276e00 | 1033 | .larbid_remap = {{0}, {4}, {5}, {6}, {7}, {2}, {3}, {1}}, |
907ba6a1 YW |
1034 | }; |
1035 | ||
9e3489e0 YW |
1036 | static const struct mtk_iommu_plat_data mt8192_data = { |
1037 | .m4u_plat = M4U_MT8192, | |
1038 | .flags = HAS_BCLK | HAS_SUB_COMM | OUT_ORDER_WR_EN | | |
1039 | WR_THROT_EN | IOVA_34_EN, | |
1040 | .inv_sel_reg = REG_MMU_INV_SEL_GEN2, | |
1041 | .iova_region = mt8192_multi_dom, | |
1042 | .iova_region_nr = ARRAY_SIZE(mt8192_multi_dom), | |
1043 | .larbid_remap = {{0}, {1}, {4, 5}, {7}, {2}, {9, 11, 19, 20}, | |
1044 | {0, 14, 16}, {0, 13, 18, 17}}, | |
1045 | }; | |
1046 | ||
0df4fabe | 1047 | static const struct of_device_id mtk_iommu_of_ids[] = { |
cecdce9d | 1048 | { .compatible = "mediatek,mt2712-m4u", .data = &mt2712_data}, |
068c86e9 | 1049 | { .compatible = "mediatek,mt6779-m4u", .data = &mt6779_data}, |
3c213562 | 1050 | { .compatible = "mediatek,mt8167-m4u", .data = &mt8167_data}, |
cecdce9d | 1051 | { .compatible = "mediatek,mt8173-m4u", .data = &mt8173_data}, |
907ba6a1 | 1052 | { .compatible = "mediatek,mt8183-m4u", .data = &mt8183_data}, |
9e3489e0 | 1053 | { .compatible = "mediatek,mt8192-m4u", .data = &mt8192_data}, |
0df4fabe YW |
1054 | {} |
1055 | }; | |
1056 | ||
1057 | static struct platform_driver mtk_iommu_driver = { | |
1058 | .probe = mtk_iommu_probe, | |
1059 | .remove = mtk_iommu_remove, | |
1060 | .driver = { | |
1061 | .name = "mtk-iommu", | |
f53dd978 | 1062 | .of_match_table = mtk_iommu_of_ids, |
0df4fabe YW |
1063 | .pm = &mtk_iommu_pm_ops, |
1064 | } | |
1065 | }; | |
18d8c74e | 1066 | module_platform_driver(mtk_iommu_driver); |
0df4fabe | 1067 | |
18d8c74e YW |
1068 | MODULE_DESCRIPTION("IOMMU API for MediaTek M4U implementations"); |
1069 | MODULE_LICENSE("GPL v2"); |