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0df4fabe YW |
1 | /* |
2 | * Copyright (c) 2015-2016 MediaTek Inc. | |
3 | * Author: Yong Wu <yong.wu@mediatek.com> | |
4 | * | |
5 | * This program is free software; you can redistribute it and/or modify | |
6 | * it under the terms of the GNU General Public License version 2 as | |
7 | * published by the Free Software Foundation. | |
8 | * | |
9 | * This program is distributed in the hope that it will be useful, | |
10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
12 | * GNU General Public License for more details. | |
13 | */ | |
01e23c93 | 14 | #include <linux/bootmem.h> |
0df4fabe YW |
15 | #include <linux/bug.h> |
16 | #include <linux/clk.h> | |
17 | #include <linux/component.h> | |
18 | #include <linux/device.h> | |
19 | #include <linux/dma-iommu.h> | |
20 | #include <linux/err.h> | |
21 | #include <linux/interrupt.h> | |
22 | #include <linux/io.h> | |
23 | #include <linux/iommu.h> | |
24 | #include <linux/iopoll.h> | |
25 | #include <linux/list.h> | |
26 | #include <linux/of_address.h> | |
27 | #include <linux/of_iommu.h> | |
28 | #include <linux/of_irq.h> | |
29 | #include <linux/of_platform.h> | |
30 | #include <linux/platform_device.h> | |
31 | #include <linux/slab.h> | |
32 | #include <linux/spinlock.h> | |
33 | #include <asm/barrier.h> | |
0df4fabe YW |
34 | #include <soc/mediatek/smi.h> |
35 | ||
9ca340c9 | 36 | #include "mtk_iommu.h" |
0df4fabe YW |
37 | |
38 | #define REG_MMU_PT_BASE_ADDR 0x000 | |
39 | ||
40 | #define REG_MMU_INVALIDATE 0x020 | |
41 | #define F_ALL_INVLD 0x2 | |
42 | #define F_MMU_INV_RANGE 0x1 | |
43 | ||
44 | #define REG_MMU_INVLD_START_A 0x024 | |
45 | #define REG_MMU_INVLD_END_A 0x028 | |
46 | ||
47 | #define REG_MMU_INV_SEL 0x038 | |
48 | #define F_INVLD_EN0 BIT(0) | |
49 | #define F_INVLD_EN1 BIT(1) | |
50 | ||
51 | #define REG_MMU_STANDARD_AXI_MODE 0x048 | |
52 | #define REG_MMU_DCM_DIS 0x050 | |
53 | ||
54 | #define REG_MMU_CTRL_REG 0x110 | |
55 | #define F_MMU_PREFETCH_RT_REPLACE_MOD BIT(4) | |
e6dec923 YW |
56 | #define F_MMU_TF_PROTECT_SEL_SHIFT(data) \ |
57 | ((data)->m4u_plat == M4U_MT2712 ? 4 : 5) | |
58 | /* It's named by F_MMU_TF_PROT_SEL in mt2712. */ | |
59 | #define F_MMU_TF_PROTECT_SEL(prot, data) \ | |
60 | (((prot) & 0x3) << F_MMU_TF_PROTECT_SEL_SHIFT(data)) | |
0df4fabe YW |
61 | |
62 | #define REG_MMU_IVRP_PADDR 0x114 | |
01e23c93 | 63 | #define F_MMU_IVRP_PA_SET(pa, ext) (((pa) >> 1) | ((!!(ext)) << 31)) |
30e2fccf YW |
64 | #define REG_MMU_VLD_PA_RNG 0x118 |
65 | #define F_MMU_VLD_PA_RNG(EA, SA) (((EA) << 8) | (SA)) | |
0df4fabe YW |
66 | |
67 | #define REG_MMU_INT_CONTROL0 0x120 | |
68 | #define F_L2_MULIT_HIT_EN BIT(0) | |
69 | #define F_TABLE_WALK_FAULT_INT_EN BIT(1) | |
70 | #define F_PREETCH_FIFO_OVERFLOW_INT_EN BIT(2) | |
71 | #define F_MISS_FIFO_OVERFLOW_INT_EN BIT(3) | |
72 | #define F_PREFETCH_FIFO_ERR_INT_EN BIT(5) | |
73 | #define F_MISS_FIFO_ERR_INT_EN BIT(6) | |
74 | #define F_INT_CLR_BIT BIT(12) | |
75 | ||
76 | #define REG_MMU_INT_MAIN_CONTROL 0x124 | |
77 | #define F_INT_TRANSLATION_FAULT BIT(0) | |
78 | #define F_INT_MAIN_MULTI_HIT_FAULT BIT(1) | |
79 | #define F_INT_INVALID_PA_FAULT BIT(2) | |
80 | #define F_INT_ENTRY_REPLACEMENT_FAULT BIT(3) | |
81 | #define F_INT_TLB_MISS_FAULT BIT(4) | |
82 | #define F_INT_MISS_TRANSACTION_FIFO_FAULT BIT(5) | |
83 | #define F_INT_PRETETCH_TRANSATION_FIFO_FAULT BIT(6) | |
84 | ||
85 | #define REG_MMU_CPE_DONE 0x12C | |
86 | ||
87 | #define REG_MMU_FAULT_ST1 0x134 | |
88 | ||
89 | #define REG_MMU_FAULT_VA 0x13c | |
0df4fabe YW |
90 | #define F_MMU_FAULT_VA_WRITE_BIT BIT(1) |
91 | #define F_MMU_FAULT_VA_LAYER_BIT BIT(0) | |
92 | ||
93 | #define REG_MMU_INVLD_PA 0x140 | |
94 | #define REG_MMU_INT_ID 0x150 | |
95 | #define F_MMU0_INT_ID_LARB_ID(a) (((a) >> 7) & 0x7) | |
96 | #define F_MMU0_INT_ID_PORT_ID(a) (((a) >> 2) & 0x1f) | |
97 | ||
98 | #define MTK_PROTECT_PA_ALIGN 128 | |
99 | ||
a9467d95 YW |
100 | /* |
101 | * Get the local arbiter ID and the portid within the larb arbiter | |
102 | * from mtk_m4u_id which is defined by MTK_M4U_ID. | |
103 | */ | |
e6dec923 | 104 | #define MTK_M4U_TO_LARB(id) (((id) >> 5) & 0xf) |
a9467d95 YW |
105 | #define MTK_M4U_TO_PORT(id) ((id) & 0x1f) |
106 | ||
0df4fabe YW |
107 | struct mtk_iommu_domain { |
108 | spinlock_t pgtlock; /* lock for page table */ | |
109 | ||
110 | struct io_pgtable_cfg cfg; | |
111 | struct io_pgtable_ops *iop; | |
112 | ||
113 | struct iommu_domain domain; | |
114 | }; | |
115 | ||
0df4fabe YW |
116 | static struct iommu_ops mtk_iommu_ops; |
117 | ||
7c3a2ec0 YW |
118 | static LIST_HEAD(m4ulist); /* List all the M4U HWs */ |
119 | ||
120 | #define for_each_m4u(data) list_for_each_entry(data, &m4ulist, list) | |
121 | ||
122 | /* | |
123 | * There may be 1 or 2 M4U HWs, But we always expect they are in the same domain | |
124 | * for the performance. | |
125 | * | |
126 | * Here always return the mtk_iommu_data of the first probed M4U where the | |
127 | * iommu domain information is recorded. | |
128 | */ | |
129 | static struct mtk_iommu_data *mtk_iommu_get_m4u_data(void) | |
130 | { | |
131 | struct mtk_iommu_data *data; | |
132 | ||
133 | for_each_m4u(data) | |
134 | return data; | |
135 | ||
136 | return NULL; | |
137 | } | |
138 | ||
0df4fabe YW |
139 | static struct mtk_iommu_domain *to_mtk_domain(struct iommu_domain *dom) |
140 | { | |
141 | return container_of(dom, struct mtk_iommu_domain, domain); | |
142 | } | |
143 | ||
144 | static void mtk_iommu_tlb_flush_all(void *cookie) | |
145 | { | |
146 | struct mtk_iommu_data *data = cookie; | |
147 | ||
7c3a2ec0 YW |
148 | for_each_m4u(data) { |
149 | writel_relaxed(F_INVLD_EN1 | F_INVLD_EN0, | |
150 | data->base + REG_MMU_INV_SEL); | |
151 | writel_relaxed(F_ALL_INVLD, data->base + REG_MMU_INVALIDATE); | |
152 | wmb(); /* Make sure the tlb flush all done */ | |
153 | } | |
0df4fabe YW |
154 | } |
155 | ||
156 | static void mtk_iommu_tlb_add_flush_nosync(unsigned long iova, size_t size, | |
157 | size_t granule, bool leaf, | |
158 | void *cookie) | |
159 | { | |
160 | struct mtk_iommu_data *data = cookie; | |
161 | ||
7c3a2ec0 YW |
162 | for_each_m4u(data) { |
163 | writel_relaxed(F_INVLD_EN1 | F_INVLD_EN0, | |
164 | data->base + REG_MMU_INV_SEL); | |
0df4fabe | 165 | |
7c3a2ec0 YW |
166 | writel_relaxed(iova, data->base + REG_MMU_INVLD_START_A); |
167 | writel_relaxed(iova + size - 1, | |
168 | data->base + REG_MMU_INVLD_END_A); | |
169 | writel_relaxed(F_MMU_INV_RANGE, | |
170 | data->base + REG_MMU_INVALIDATE); | |
171 | data->tlb_flush_active = true; | |
172 | } | |
0df4fabe YW |
173 | } |
174 | ||
175 | static void mtk_iommu_tlb_sync(void *cookie) | |
176 | { | |
177 | struct mtk_iommu_data *data = cookie; | |
178 | int ret; | |
179 | u32 tmp; | |
180 | ||
7c3a2ec0 YW |
181 | for_each_m4u(data) { |
182 | /* Avoid timing out if there's nothing to wait for */ | |
183 | if (!data->tlb_flush_active) | |
184 | return; | |
98a8f63e | 185 | |
7c3a2ec0 YW |
186 | ret = readl_poll_timeout_atomic(data->base + REG_MMU_CPE_DONE, |
187 | tmp, tmp != 0, 10, 100000); | |
188 | if (ret) { | |
189 | dev_warn(data->dev, | |
190 | "Partial TLB flush timed out, falling back to full flush\n"); | |
191 | mtk_iommu_tlb_flush_all(cookie); | |
192 | } | |
193 | /* Clear the CPE status */ | |
194 | writel_relaxed(0, data->base + REG_MMU_CPE_DONE); | |
195 | data->tlb_flush_active = false; | |
0df4fabe | 196 | } |
0df4fabe YW |
197 | } |
198 | ||
199 | static const struct iommu_gather_ops mtk_iommu_gather_ops = { | |
200 | .tlb_flush_all = mtk_iommu_tlb_flush_all, | |
201 | .tlb_add_flush = mtk_iommu_tlb_add_flush_nosync, | |
202 | .tlb_sync = mtk_iommu_tlb_sync, | |
203 | }; | |
204 | ||
205 | static irqreturn_t mtk_iommu_isr(int irq, void *dev_id) | |
206 | { | |
207 | struct mtk_iommu_data *data = dev_id; | |
208 | struct mtk_iommu_domain *dom = data->m4u_dom; | |
209 | u32 int_state, regval, fault_iova, fault_pa; | |
210 | unsigned int fault_larb, fault_port; | |
211 | bool layer, write; | |
212 | ||
213 | /* Read error info from registers */ | |
214 | int_state = readl_relaxed(data->base + REG_MMU_FAULT_ST1); | |
215 | fault_iova = readl_relaxed(data->base + REG_MMU_FAULT_VA); | |
216 | layer = fault_iova & F_MMU_FAULT_VA_LAYER_BIT; | |
217 | write = fault_iova & F_MMU_FAULT_VA_WRITE_BIT; | |
0df4fabe YW |
218 | fault_pa = readl_relaxed(data->base + REG_MMU_INVLD_PA); |
219 | regval = readl_relaxed(data->base + REG_MMU_INT_ID); | |
220 | fault_larb = F_MMU0_INT_ID_LARB_ID(regval); | |
221 | fault_port = F_MMU0_INT_ID_PORT_ID(regval); | |
222 | ||
223 | if (report_iommu_fault(&dom->domain, data->dev, fault_iova, | |
224 | write ? IOMMU_FAULT_WRITE : IOMMU_FAULT_READ)) { | |
225 | dev_err_ratelimited( | |
226 | data->dev, | |
227 | "fault type=0x%x iova=0x%x pa=0x%x larb=%d port=%d layer=%d %s\n", | |
228 | int_state, fault_iova, fault_pa, fault_larb, fault_port, | |
229 | layer, write ? "write" : "read"); | |
230 | } | |
231 | ||
232 | /* Interrupt clear */ | |
233 | regval = readl_relaxed(data->base + REG_MMU_INT_CONTROL0); | |
234 | regval |= F_INT_CLR_BIT; | |
235 | writel_relaxed(regval, data->base + REG_MMU_INT_CONTROL0); | |
236 | ||
237 | mtk_iommu_tlb_flush_all(data); | |
238 | ||
239 | return IRQ_HANDLED; | |
240 | } | |
241 | ||
242 | static void mtk_iommu_config(struct mtk_iommu_data *data, | |
243 | struct device *dev, bool enable) | |
244 | { | |
0df4fabe YW |
245 | struct mtk_smi_larb_iommu *larb_mmu; |
246 | unsigned int larbid, portid; | |
58f0d1d5 RM |
247 | struct iommu_fwspec *fwspec = dev->iommu_fwspec; |
248 | int i; | |
0df4fabe | 249 | |
58f0d1d5 RM |
250 | for (i = 0; i < fwspec->num_ids; ++i) { |
251 | larbid = MTK_M4U_TO_LARB(fwspec->ids[i]); | |
252 | portid = MTK_M4U_TO_PORT(fwspec->ids[i]); | |
0df4fabe YW |
253 | larb_mmu = &data->smi_imu.larb_imu[larbid]; |
254 | ||
255 | dev_dbg(dev, "%s iommu port: %d\n", | |
256 | enable ? "enable" : "disable", portid); | |
257 | ||
258 | if (enable) | |
259 | larb_mmu->mmu |= MTK_SMI_MMU_EN(portid); | |
260 | else | |
261 | larb_mmu->mmu &= ~MTK_SMI_MMU_EN(portid); | |
262 | } | |
263 | } | |
264 | ||
4b00f5ac | 265 | static int mtk_iommu_domain_finalise(struct mtk_iommu_domain *dom) |
0df4fabe | 266 | { |
4b00f5ac | 267 | struct mtk_iommu_data *data = mtk_iommu_get_m4u_data(); |
0df4fabe YW |
268 | |
269 | spin_lock_init(&dom->pgtlock); | |
270 | ||
271 | dom->cfg = (struct io_pgtable_cfg) { | |
272 | .quirks = IO_PGTABLE_QUIRK_ARM_NS | | |
273 | IO_PGTABLE_QUIRK_NO_PERMS | | |
274 | IO_PGTABLE_QUIRK_TLBI_ON_MAP, | |
275 | .pgsize_bitmap = mtk_iommu_ops.pgsize_bitmap, | |
276 | .ias = 32, | |
277 | .oas = 32, | |
278 | .tlb = &mtk_iommu_gather_ops, | |
279 | .iommu_dev = data->dev, | |
280 | }; | |
281 | ||
01e23c93 YW |
282 | if (data->enable_4GB) |
283 | dom->cfg.quirks |= IO_PGTABLE_QUIRK_ARM_MTK_4GB; | |
284 | ||
0df4fabe YW |
285 | dom->iop = alloc_io_pgtable_ops(ARM_V7S, &dom->cfg, data); |
286 | if (!dom->iop) { | |
287 | dev_err(data->dev, "Failed to alloc io pgtable\n"); | |
288 | return -EINVAL; | |
289 | } | |
290 | ||
291 | /* Update our support page sizes bitmap */ | |
d16e0faa | 292 | dom->domain.pgsize_bitmap = dom->cfg.pgsize_bitmap; |
0df4fabe YW |
293 | return 0; |
294 | } | |
295 | ||
296 | static struct iommu_domain *mtk_iommu_domain_alloc(unsigned type) | |
297 | { | |
298 | struct mtk_iommu_domain *dom; | |
299 | ||
300 | if (type != IOMMU_DOMAIN_DMA) | |
301 | return NULL; | |
302 | ||
303 | dom = kzalloc(sizeof(*dom), GFP_KERNEL); | |
304 | if (!dom) | |
305 | return NULL; | |
306 | ||
4b00f5ac YW |
307 | if (iommu_get_dma_cookie(&dom->domain)) |
308 | goto free_dom; | |
309 | ||
310 | if (mtk_iommu_domain_finalise(dom)) | |
311 | goto put_dma_cookie; | |
0df4fabe YW |
312 | |
313 | dom->domain.geometry.aperture_start = 0; | |
314 | dom->domain.geometry.aperture_end = DMA_BIT_MASK(32); | |
315 | dom->domain.geometry.force_aperture = true; | |
316 | ||
317 | return &dom->domain; | |
4b00f5ac YW |
318 | |
319 | put_dma_cookie: | |
320 | iommu_put_dma_cookie(&dom->domain); | |
321 | free_dom: | |
322 | kfree(dom); | |
323 | return NULL; | |
0df4fabe YW |
324 | } |
325 | ||
326 | static void mtk_iommu_domain_free(struct iommu_domain *domain) | |
327 | { | |
4b00f5ac YW |
328 | struct mtk_iommu_domain *dom = to_mtk_domain(domain); |
329 | ||
330 | free_io_pgtable_ops(dom->iop); | |
0df4fabe YW |
331 | iommu_put_dma_cookie(domain); |
332 | kfree(to_mtk_domain(domain)); | |
333 | } | |
334 | ||
335 | static int mtk_iommu_attach_device(struct iommu_domain *domain, | |
336 | struct device *dev) | |
337 | { | |
338 | struct mtk_iommu_domain *dom = to_mtk_domain(domain); | |
4b00f5ac | 339 | struct mtk_iommu_data *data = dev->iommu_fwspec->iommu_priv; |
0df4fabe | 340 | |
4b00f5ac | 341 | if (!data) |
0df4fabe YW |
342 | return -ENODEV; |
343 | ||
4b00f5ac | 344 | /* Update the pgtable base address register of the M4U HW */ |
0df4fabe YW |
345 | if (!data->m4u_dom) { |
346 | data->m4u_dom = dom; | |
4b00f5ac YW |
347 | writel(dom->cfg.arm_v7s_cfg.ttbr[0], |
348 | data->base + REG_MMU_PT_BASE_ADDR); | |
7c3a2ec0 YW |
349 | } |
350 | ||
4b00f5ac | 351 | mtk_iommu_config(data, dev, true); |
0df4fabe YW |
352 | return 0; |
353 | } | |
354 | ||
355 | static void mtk_iommu_detach_device(struct iommu_domain *domain, | |
356 | struct device *dev) | |
357 | { | |
58f0d1d5 | 358 | struct mtk_iommu_data *data = dev->iommu_fwspec->iommu_priv; |
0df4fabe | 359 | |
58f0d1d5 | 360 | if (!data) |
0df4fabe YW |
361 | return; |
362 | ||
0df4fabe YW |
363 | mtk_iommu_config(data, dev, false); |
364 | } | |
365 | ||
366 | static int mtk_iommu_map(struct iommu_domain *domain, unsigned long iova, | |
367 | phys_addr_t paddr, size_t size, int prot) | |
368 | { | |
369 | struct mtk_iommu_domain *dom = to_mtk_domain(domain); | |
370 | unsigned long flags; | |
371 | int ret; | |
372 | ||
373 | spin_lock_irqsave(&dom->pgtlock, flags); | |
374 | ret = dom->iop->map(dom->iop, iova, paddr, size, prot); | |
375 | spin_unlock_irqrestore(&dom->pgtlock, flags); | |
376 | ||
377 | return ret; | |
378 | } | |
379 | ||
380 | static size_t mtk_iommu_unmap(struct iommu_domain *domain, | |
381 | unsigned long iova, size_t size) | |
382 | { | |
383 | struct mtk_iommu_domain *dom = to_mtk_domain(domain); | |
384 | unsigned long flags; | |
385 | size_t unmapsz; | |
386 | ||
387 | spin_lock_irqsave(&dom->pgtlock, flags); | |
388 | unmapsz = dom->iop->unmap(dom->iop, iova, size); | |
389 | spin_unlock_irqrestore(&dom->pgtlock, flags); | |
390 | ||
391 | return unmapsz; | |
392 | } | |
393 | ||
394 | static phys_addr_t mtk_iommu_iova_to_phys(struct iommu_domain *domain, | |
395 | dma_addr_t iova) | |
396 | { | |
397 | struct mtk_iommu_domain *dom = to_mtk_domain(domain); | |
30e2fccf | 398 | struct mtk_iommu_data *data = mtk_iommu_get_m4u_data(); |
0df4fabe YW |
399 | unsigned long flags; |
400 | phys_addr_t pa; | |
401 | ||
402 | spin_lock_irqsave(&dom->pgtlock, flags); | |
403 | pa = dom->iop->iova_to_phys(dom->iop, iova); | |
404 | spin_unlock_irqrestore(&dom->pgtlock, flags); | |
405 | ||
30e2fccf YW |
406 | if (data->enable_4GB) |
407 | pa |= BIT(32); | |
408 | ||
0df4fabe YW |
409 | return pa; |
410 | } | |
411 | ||
412 | static int mtk_iommu_add_device(struct device *dev) | |
413 | { | |
b16c0170 | 414 | struct mtk_iommu_data *data; |
0df4fabe YW |
415 | struct iommu_group *group; |
416 | ||
58f0d1d5 RM |
417 | if (!dev->iommu_fwspec || dev->iommu_fwspec->ops != &mtk_iommu_ops) |
418 | return -ENODEV; /* Not a iommu client device */ | |
0df4fabe | 419 | |
b16c0170 JR |
420 | data = dev->iommu_fwspec->iommu_priv; |
421 | iommu_device_link(&data->iommu, dev); | |
422 | ||
0df4fabe YW |
423 | group = iommu_group_get_for_dev(dev); |
424 | if (IS_ERR(group)) | |
425 | return PTR_ERR(group); | |
426 | ||
427 | iommu_group_put(group); | |
428 | return 0; | |
429 | } | |
430 | ||
431 | static void mtk_iommu_remove_device(struct device *dev) | |
432 | { | |
b16c0170 JR |
433 | struct mtk_iommu_data *data; |
434 | ||
58f0d1d5 | 435 | if (!dev->iommu_fwspec || dev->iommu_fwspec->ops != &mtk_iommu_ops) |
0df4fabe YW |
436 | return; |
437 | ||
b16c0170 JR |
438 | data = dev->iommu_fwspec->iommu_priv; |
439 | iommu_device_unlink(&data->iommu, dev); | |
440 | ||
0df4fabe | 441 | iommu_group_remove_device(dev); |
58f0d1d5 | 442 | iommu_fwspec_free(dev); |
0df4fabe YW |
443 | } |
444 | ||
445 | static struct iommu_group *mtk_iommu_device_group(struct device *dev) | |
446 | { | |
7c3a2ec0 | 447 | struct mtk_iommu_data *data = mtk_iommu_get_m4u_data(); |
0df4fabe | 448 | |
58f0d1d5 | 449 | if (!data) |
0df4fabe YW |
450 | return ERR_PTR(-ENODEV); |
451 | ||
452 | /* All the client devices are in the same m4u iommu-group */ | |
0df4fabe YW |
453 | if (!data->m4u_group) { |
454 | data->m4u_group = iommu_group_alloc(); | |
455 | if (IS_ERR(data->m4u_group)) | |
456 | dev_err(dev, "Failed to allocate M4U IOMMU group\n"); | |
3a8d40b6 RM |
457 | } else { |
458 | iommu_group_ref_get(data->m4u_group); | |
0df4fabe YW |
459 | } |
460 | return data->m4u_group; | |
461 | } | |
462 | ||
463 | static int mtk_iommu_of_xlate(struct device *dev, struct of_phandle_args *args) | |
464 | { | |
0df4fabe YW |
465 | struct platform_device *m4updev; |
466 | ||
467 | if (args->args_count != 1) { | |
468 | dev_err(dev, "invalid #iommu-cells(%d) property for IOMMU\n", | |
469 | args->args_count); | |
470 | return -EINVAL; | |
471 | } | |
472 | ||
58f0d1d5 | 473 | if (!dev->iommu_fwspec->iommu_priv) { |
0df4fabe YW |
474 | /* Get the m4u device */ |
475 | m4updev = of_find_device_by_node(args->np); | |
0df4fabe YW |
476 | if (WARN_ON(!m4updev)) |
477 | return -EINVAL; | |
478 | ||
58f0d1d5 | 479 | dev->iommu_fwspec->iommu_priv = platform_get_drvdata(m4updev); |
0df4fabe YW |
480 | } |
481 | ||
58f0d1d5 | 482 | return iommu_fwspec_add_ids(dev, args->args, 1); |
0df4fabe YW |
483 | } |
484 | ||
485 | static struct iommu_ops mtk_iommu_ops = { | |
486 | .domain_alloc = mtk_iommu_domain_alloc, | |
487 | .domain_free = mtk_iommu_domain_free, | |
488 | .attach_dev = mtk_iommu_attach_device, | |
489 | .detach_dev = mtk_iommu_detach_device, | |
490 | .map = mtk_iommu_map, | |
491 | .unmap = mtk_iommu_unmap, | |
492 | .map_sg = default_iommu_map_sg, | |
493 | .iova_to_phys = mtk_iommu_iova_to_phys, | |
494 | .add_device = mtk_iommu_add_device, | |
495 | .remove_device = mtk_iommu_remove_device, | |
496 | .device_group = mtk_iommu_device_group, | |
497 | .of_xlate = mtk_iommu_of_xlate, | |
498 | .pgsize_bitmap = SZ_4K | SZ_64K | SZ_1M | SZ_16M, | |
499 | }; | |
500 | ||
501 | static int mtk_iommu_hw_init(const struct mtk_iommu_data *data) | |
502 | { | |
503 | u32 regval; | |
504 | int ret; | |
505 | ||
506 | ret = clk_prepare_enable(data->bclk); | |
507 | if (ret) { | |
508 | dev_err(data->dev, "Failed to enable iommu bclk(%d)\n", ret); | |
509 | return ret; | |
510 | } | |
511 | ||
e6dec923 YW |
512 | regval = F_MMU_TF_PROTECT_SEL(2, data); |
513 | if (data->m4u_plat == M4U_MT8173) | |
514 | regval |= F_MMU_PREFETCH_RT_REPLACE_MOD; | |
0df4fabe YW |
515 | writel_relaxed(regval, data->base + REG_MMU_CTRL_REG); |
516 | ||
517 | regval = F_L2_MULIT_HIT_EN | | |
518 | F_TABLE_WALK_FAULT_INT_EN | | |
519 | F_PREETCH_FIFO_OVERFLOW_INT_EN | | |
520 | F_MISS_FIFO_OVERFLOW_INT_EN | | |
521 | F_PREFETCH_FIFO_ERR_INT_EN | | |
522 | F_MISS_FIFO_ERR_INT_EN; | |
523 | writel_relaxed(regval, data->base + REG_MMU_INT_CONTROL0); | |
524 | ||
525 | regval = F_INT_TRANSLATION_FAULT | | |
526 | F_INT_MAIN_MULTI_HIT_FAULT | | |
527 | F_INT_INVALID_PA_FAULT | | |
528 | F_INT_ENTRY_REPLACEMENT_FAULT | | |
529 | F_INT_TLB_MISS_FAULT | | |
530 | F_INT_MISS_TRANSACTION_FIFO_FAULT | | |
531 | F_INT_PRETETCH_TRANSATION_FIFO_FAULT; | |
532 | writel_relaxed(regval, data->base + REG_MMU_INT_MAIN_CONTROL); | |
533 | ||
01e23c93 | 534 | writel_relaxed(F_MMU_IVRP_PA_SET(data->protect_base, data->enable_4GB), |
0df4fabe | 535 | data->base + REG_MMU_IVRP_PADDR); |
4f1c8ea1 | 536 | if (data->enable_4GB && data->m4u_plat != M4U_MT8173) { |
30e2fccf YW |
537 | /* |
538 | * If 4GB mode is enabled, the validate PA range is from | |
539 | * 0x1_0000_0000 to 0x1_ffff_ffff. here record bit[32:30]. | |
540 | */ | |
541 | regval = F_MMU_VLD_PA_RNG(7, 4); | |
542 | writel_relaxed(regval, data->base + REG_MMU_VLD_PA_RNG); | |
543 | } | |
0df4fabe | 544 | writel_relaxed(0, data->base + REG_MMU_DCM_DIS); |
e6dec923 YW |
545 | |
546 | /* It's MISC control register whose default value is ok except mt8173.*/ | |
547 | if (data->m4u_plat == M4U_MT8173) | |
548 | writel_relaxed(0, data->base + REG_MMU_STANDARD_AXI_MODE); | |
0df4fabe YW |
549 | |
550 | if (devm_request_irq(data->dev, data->irq, mtk_iommu_isr, 0, | |
551 | dev_name(data->dev), (void *)data)) { | |
552 | writel_relaxed(0, data->base + REG_MMU_PT_BASE_ADDR); | |
553 | clk_disable_unprepare(data->bclk); | |
554 | dev_err(data->dev, "Failed @ IRQ-%d Request\n", data->irq); | |
555 | return -ENODEV; | |
556 | } | |
557 | ||
558 | return 0; | |
559 | } | |
560 | ||
0df4fabe YW |
561 | static const struct component_master_ops mtk_iommu_com_ops = { |
562 | .bind = mtk_iommu_bind, | |
563 | .unbind = mtk_iommu_unbind, | |
564 | }; | |
565 | ||
566 | static int mtk_iommu_probe(struct platform_device *pdev) | |
567 | { | |
568 | struct mtk_iommu_data *data; | |
569 | struct device *dev = &pdev->dev; | |
570 | struct resource *res; | |
b16c0170 | 571 | resource_size_t ioaddr; |
0df4fabe YW |
572 | struct component_match *match = NULL; |
573 | void *protect; | |
0b6c0ad3 | 574 | int i, larb_nr, ret; |
0df4fabe YW |
575 | |
576 | data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL); | |
577 | if (!data) | |
578 | return -ENOMEM; | |
579 | data->dev = dev; | |
e6dec923 | 580 | data->m4u_plat = (enum mtk_iommu_plat)of_device_get_match_data(dev); |
0df4fabe YW |
581 | |
582 | /* Protect memory. HW will access here while translation fault.*/ | |
583 | protect = devm_kzalloc(dev, MTK_PROTECT_PA_ALIGN * 2, GFP_KERNEL); | |
584 | if (!protect) | |
585 | return -ENOMEM; | |
586 | data->protect_base = ALIGN(virt_to_phys(protect), MTK_PROTECT_PA_ALIGN); | |
587 | ||
01e23c93 | 588 | /* Whether the current dram is over 4GB */ |
30e2fccf | 589 | data->enable_4GB = !!(max_pfn > (BIT(32) >> PAGE_SHIFT)); |
01e23c93 | 590 | |
0df4fabe YW |
591 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
592 | data->base = devm_ioremap_resource(dev, res); | |
593 | if (IS_ERR(data->base)) | |
594 | return PTR_ERR(data->base); | |
b16c0170 | 595 | ioaddr = res->start; |
0df4fabe YW |
596 | |
597 | data->irq = platform_get_irq(pdev, 0); | |
598 | if (data->irq < 0) | |
599 | return data->irq; | |
600 | ||
601 | data->bclk = devm_clk_get(dev, "bclk"); | |
602 | if (IS_ERR(data->bclk)) | |
603 | return PTR_ERR(data->bclk); | |
604 | ||
605 | larb_nr = of_count_phandle_with_args(dev->of_node, | |
606 | "mediatek,larbs", NULL); | |
607 | if (larb_nr < 0) | |
608 | return larb_nr; | |
609 | data->smi_imu.larb_nr = larb_nr; | |
610 | ||
611 | for (i = 0; i < larb_nr; i++) { | |
612 | struct device_node *larbnode; | |
613 | struct platform_device *plarbdev; | |
e6dec923 | 614 | u32 id; |
0df4fabe YW |
615 | |
616 | larbnode = of_parse_phandle(dev->of_node, "mediatek,larbs", i); | |
617 | if (!larbnode) | |
618 | return -EINVAL; | |
619 | ||
620 | if (!of_device_is_available(larbnode)) | |
621 | continue; | |
622 | ||
e6dec923 YW |
623 | ret = of_property_read_u32(larbnode, "mediatek,larb-id", &id); |
624 | if (ret)/* The id is consecutive if there is no this property */ | |
625 | id = i; | |
626 | ||
0df4fabe | 627 | plarbdev = of_find_device_by_node(larbnode); |
e6dec923 YW |
628 | if (!plarbdev) |
629 | return -EPROBE_DEFER; | |
630 | data->smi_imu.larb_imu[id].dev = &plarbdev->dev; | |
0df4fabe | 631 | |
00c7c81f RK |
632 | component_match_add_release(dev, &match, release_of, |
633 | compare_of, larbnode); | |
0df4fabe YW |
634 | } |
635 | ||
636 | platform_set_drvdata(pdev, data); | |
637 | ||
638 | ret = mtk_iommu_hw_init(data); | |
639 | if (ret) | |
640 | return ret; | |
641 | ||
b16c0170 JR |
642 | ret = iommu_device_sysfs_add(&data->iommu, dev, NULL, |
643 | "mtk-iommu.%pa", &ioaddr); | |
644 | if (ret) | |
645 | return ret; | |
646 | ||
647 | iommu_device_set_ops(&data->iommu, &mtk_iommu_ops); | |
648 | iommu_device_set_fwnode(&data->iommu, &pdev->dev.of_node->fwnode); | |
649 | ||
650 | ret = iommu_device_register(&data->iommu); | |
651 | if (ret) | |
652 | return ret; | |
653 | ||
7c3a2ec0 YW |
654 | list_add_tail(&data->list, &m4ulist); |
655 | ||
0df4fabe YW |
656 | if (!iommu_present(&platform_bus_type)) |
657 | bus_set_iommu(&platform_bus_type, &mtk_iommu_ops); | |
658 | ||
659 | return component_master_add_with_match(dev, &mtk_iommu_com_ops, match); | |
660 | } | |
661 | ||
662 | static int mtk_iommu_remove(struct platform_device *pdev) | |
663 | { | |
664 | struct mtk_iommu_data *data = platform_get_drvdata(pdev); | |
665 | ||
b16c0170 JR |
666 | iommu_device_sysfs_remove(&data->iommu); |
667 | iommu_device_unregister(&data->iommu); | |
668 | ||
0df4fabe YW |
669 | if (iommu_present(&platform_bus_type)) |
670 | bus_set_iommu(&platform_bus_type, NULL); | |
671 | ||
0df4fabe YW |
672 | clk_disable_unprepare(data->bclk); |
673 | devm_free_irq(&pdev->dev, data->irq, data); | |
674 | component_master_del(&pdev->dev, &mtk_iommu_com_ops); | |
675 | return 0; | |
676 | } | |
677 | ||
fd99f796 | 678 | static int __maybe_unused mtk_iommu_suspend(struct device *dev) |
0df4fabe YW |
679 | { |
680 | struct mtk_iommu_data *data = dev_get_drvdata(dev); | |
681 | struct mtk_iommu_suspend_reg *reg = &data->reg; | |
682 | void __iomem *base = data->base; | |
683 | ||
684 | reg->standard_axi_mode = readl_relaxed(base + | |
685 | REG_MMU_STANDARD_AXI_MODE); | |
686 | reg->dcm_dis = readl_relaxed(base + REG_MMU_DCM_DIS); | |
687 | reg->ctrl_reg = readl_relaxed(base + REG_MMU_CTRL_REG); | |
688 | reg->int_control0 = readl_relaxed(base + REG_MMU_INT_CONTROL0); | |
689 | reg->int_main_control = readl_relaxed(base + REG_MMU_INT_MAIN_CONTROL); | |
6254b64f | 690 | clk_disable_unprepare(data->bclk); |
0df4fabe YW |
691 | return 0; |
692 | } | |
693 | ||
fd99f796 | 694 | static int __maybe_unused mtk_iommu_resume(struct device *dev) |
0df4fabe YW |
695 | { |
696 | struct mtk_iommu_data *data = dev_get_drvdata(dev); | |
697 | struct mtk_iommu_suspend_reg *reg = &data->reg; | |
698 | void __iomem *base = data->base; | |
6254b64f | 699 | int ret; |
0df4fabe | 700 | |
6254b64f YW |
701 | ret = clk_prepare_enable(data->bclk); |
702 | if (ret) { | |
703 | dev_err(data->dev, "Failed to enable clk(%d) in resume\n", ret); | |
704 | return ret; | |
705 | } | |
0df4fabe YW |
706 | writel_relaxed(reg->standard_axi_mode, |
707 | base + REG_MMU_STANDARD_AXI_MODE); | |
708 | writel_relaxed(reg->dcm_dis, base + REG_MMU_DCM_DIS); | |
709 | writel_relaxed(reg->ctrl_reg, base + REG_MMU_CTRL_REG); | |
710 | writel_relaxed(reg->int_control0, base + REG_MMU_INT_CONTROL0); | |
711 | writel_relaxed(reg->int_main_control, base + REG_MMU_INT_MAIN_CONTROL); | |
01e23c93 | 712 | writel_relaxed(F_MMU_IVRP_PA_SET(data->protect_base, data->enable_4GB), |
0df4fabe | 713 | base + REG_MMU_IVRP_PADDR); |
e6dec923 YW |
714 | if (data->m4u_dom) |
715 | writel(data->m4u_dom->cfg.arm_v7s_cfg.ttbr[0], | |
716 | base + REG_MMU_PT_BASE_ADDR); | |
0df4fabe YW |
717 | return 0; |
718 | } | |
719 | ||
e6dec923 | 720 | static const struct dev_pm_ops mtk_iommu_pm_ops = { |
6254b64f | 721 | SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(mtk_iommu_suspend, mtk_iommu_resume) |
0df4fabe YW |
722 | }; |
723 | ||
724 | static const struct of_device_id mtk_iommu_of_ids[] = { | |
e6dec923 YW |
725 | { .compatible = "mediatek,mt2712-m4u", .data = (void *)M4U_MT2712}, |
726 | { .compatible = "mediatek,mt8173-m4u", .data = (void *)M4U_MT8173}, | |
0df4fabe YW |
727 | {} |
728 | }; | |
729 | ||
730 | static struct platform_driver mtk_iommu_driver = { | |
731 | .probe = mtk_iommu_probe, | |
732 | .remove = mtk_iommu_remove, | |
733 | .driver = { | |
734 | .name = "mtk-iommu", | |
e6dec923 | 735 | .of_match_table = of_match_ptr(mtk_iommu_of_ids), |
0df4fabe YW |
736 | .pm = &mtk_iommu_pm_ops, |
737 | } | |
738 | }; | |
739 | ||
e6dec923 | 740 | static int __init mtk_iommu_init(void) |
0df4fabe YW |
741 | { |
742 | int ret; | |
0df4fabe YW |
743 | |
744 | ret = platform_driver_register(&mtk_iommu_driver); | |
e6dec923 YW |
745 | if (ret != 0) |
746 | pr_err("Failed to register MTK IOMMU driver\n"); | |
0df4fabe | 747 | |
e6dec923 | 748 | return ret; |
0df4fabe YW |
749 | } |
750 | ||
e6dec923 | 751 | subsys_initcall(mtk_iommu_init) |