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1802d0be | 1 | // SPDX-License-Identifier: GPL-2.0-only |
0df4fabe YW |
2 | /* |
3 | * Copyright (c) 2015-2016 MediaTek Inc. | |
4 | * Author: Yong Wu <yong.wu@mediatek.com> | |
0df4fabe | 5 | */ |
57c8a661 | 6 | #include <linux/memblock.h> |
0df4fabe YW |
7 | #include <linux/bug.h> |
8 | #include <linux/clk.h> | |
9 | #include <linux/component.h> | |
10 | #include <linux/device.h> | |
11 | #include <linux/dma-iommu.h> | |
12 | #include <linux/err.h> | |
13 | #include <linux/interrupt.h> | |
14 | #include <linux/io.h> | |
15 | #include <linux/iommu.h> | |
16 | #include <linux/iopoll.h> | |
17 | #include <linux/list.h> | |
18 | #include <linux/of_address.h> | |
19 | #include <linux/of_iommu.h> | |
20 | #include <linux/of_irq.h> | |
21 | #include <linux/of_platform.h> | |
22 | #include <linux/platform_device.h> | |
23 | #include <linux/slab.h> | |
24 | #include <linux/spinlock.h> | |
25 | #include <asm/barrier.h> | |
0df4fabe YW |
26 | #include <soc/mediatek/smi.h> |
27 | ||
9ca340c9 | 28 | #include "mtk_iommu.h" |
0df4fabe YW |
29 | |
30 | #define REG_MMU_PT_BASE_ADDR 0x000 | |
907ba6a1 | 31 | #define MMU_PT_ADDR_MASK GENMASK(31, 7) |
0df4fabe YW |
32 | |
33 | #define REG_MMU_INVALIDATE 0x020 | |
34 | #define F_ALL_INVLD 0x2 | |
35 | #define F_MMU_INV_RANGE 0x1 | |
36 | ||
37 | #define REG_MMU_INVLD_START_A 0x024 | |
38 | #define REG_MMU_INVLD_END_A 0x028 | |
39 | ||
40 | #define REG_MMU_INV_SEL 0x038 | |
41 | #define F_INVLD_EN0 BIT(0) | |
42 | #define F_INVLD_EN1 BIT(1) | |
43 | ||
44 | #define REG_MMU_STANDARD_AXI_MODE 0x048 | |
45 | #define REG_MMU_DCM_DIS 0x050 | |
46 | ||
47 | #define REG_MMU_CTRL_REG 0x110 | |
acb3c92a | 48 | #define F_MMU_TF_PROT_TO_PROGRAM_ADDR (2 << 4) |
0df4fabe | 49 | #define F_MMU_PREFETCH_RT_REPLACE_MOD BIT(4) |
acb3c92a | 50 | #define F_MMU_TF_PROT_TO_PROGRAM_ADDR_MT8173 (2 << 5) |
0df4fabe YW |
51 | |
52 | #define REG_MMU_IVRP_PADDR 0x114 | |
70ca608b | 53 | |
30e2fccf YW |
54 | #define REG_MMU_VLD_PA_RNG 0x118 |
55 | #define F_MMU_VLD_PA_RNG(EA, SA) (((EA) << 8) | (SA)) | |
0df4fabe YW |
56 | |
57 | #define REG_MMU_INT_CONTROL0 0x120 | |
58 | #define F_L2_MULIT_HIT_EN BIT(0) | |
59 | #define F_TABLE_WALK_FAULT_INT_EN BIT(1) | |
60 | #define F_PREETCH_FIFO_OVERFLOW_INT_EN BIT(2) | |
61 | #define F_MISS_FIFO_OVERFLOW_INT_EN BIT(3) | |
62 | #define F_PREFETCH_FIFO_ERR_INT_EN BIT(5) | |
63 | #define F_MISS_FIFO_ERR_INT_EN BIT(6) | |
64 | #define F_INT_CLR_BIT BIT(12) | |
65 | ||
66 | #define REG_MMU_INT_MAIN_CONTROL 0x124 | |
15a01f4c YW |
67 | /* mmu0 | mmu1 */ |
68 | #define F_INT_TRANSLATION_FAULT (BIT(0) | BIT(7)) | |
69 | #define F_INT_MAIN_MULTI_HIT_FAULT (BIT(1) | BIT(8)) | |
70 | #define F_INT_INVALID_PA_FAULT (BIT(2) | BIT(9)) | |
71 | #define F_INT_ENTRY_REPLACEMENT_FAULT (BIT(3) | BIT(10)) | |
72 | #define F_INT_TLB_MISS_FAULT (BIT(4) | BIT(11)) | |
73 | #define F_INT_MISS_TRANSACTION_FIFO_FAULT (BIT(5) | BIT(12)) | |
74 | #define F_INT_PRETETCH_TRANSATION_FIFO_FAULT (BIT(6) | BIT(13)) | |
0df4fabe YW |
75 | |
76 | #define REG_MMU_CPE_DONE 0x12C | |
77 | ||
78 | #define REG_MMU_FAULT_ST1 0x134 | |
15a01f4c YW |
79 | #define F_REG_MMU0_FAULT_MASK GENMASK(6, 0) |
80 | #define F_REG_MMU1_FAULT_MASK GENMASK(13, 7) | |
0df4fabe | 81 | |
15a01f4c | 82 | #define REG_MMU0_FAULT_VA 0x13c |
0df4fabe YW |
83 | #define F_MMU_FAULT_VA_WRITE_BIT BIT(1) |
84 | #define F_MMU_FAULT_VA_LAYER_BIT BIT(0) | |
85 | ||
15a01f4c YW |
86 | #define REG_MMU0_INVLD_PA 0x140 |
87 | #define REG_MMU1_FAULT_VA 0x144 | |
88 | #define REG_MMU1_INVLD_PA 0x148 | |
89 | #define REG_MMU0_INT_ID 0x150 | |
90 | #define REG_MMU1_INT_ID 0x154 | |
91 | #define F_MMU_INT_ID_LARB_ID(a) (((a) >> 7) & 0x7) | |
92 | #define F_MMU_INT_ID_PORT_ID(a) (((a) >> 2) & 0x1f) | |
0df4fabe YW |
93 | |
94 | #define MTK_PROTECT_PA_ALIGN 128 | |
95 | ||
a9467d95 YW |
96 | /* |
97 | * Get the local arbiter ID and the portid within the larb arbiter | |
98 | * from mtk_m4u_id which is defined by MTK_M4U_ID. | |
99 | */ | |
e6dec923 | 100 | #define MTK_M4U_TO_LARB(id) (((id) >> 5) & 0xf) |
a9467d95 YW |
101 | #define MTK_M4U_TO_PORT(id) ((id) & 0x1f) |
102 | ||
0df4fabe YW |
103 | struct mtk_iommu_domain { |
104 | spinlock_t pgtlock; /* lock for page table */ | |
105 | ||
106 | struct io_pgtable_cfg cfg; | |
107 | struct io_pgtable_ops *iop; | |
108 | ||
109 | struct iommu_domain domain; | |
110 | }; | |
111 | ||
b65f5016 | 112 | static const struct iommu_ops mtk_iommu_ops; |
0df4fabe | 113 | |
76ce6546 YW |
114 | /* |
115 | * In M4U 4GB mode, the physical address is remapped as below: | |
116 | * | |
117 | * CPU Physical address: | |
118 | * ==================== | |
119 | * | |
120 | * 0 1G 2G 3G 4G 5G | |
121 | * |---A---|---B---|---C---|---D---|---E---| | |
122 | * +--I/O--+------------Memory-------------+ | |
123 | * | |
124 | * IOMMU output physical address: | |
125 | * ============================= | |
126 | * | |
127 | * 4G 5G 6G 7G 8G | |
128 | * |---E---|---B---|---C---|---D---| | |
129 | * +------------Memory-------------+ | |
130 | * | |
131 | * The Region 'A'(I/O) can NOT be mapped by M4U; For Region 'B'/'C'/'D', the | |
132 | * bit32 of the CPU physical address always is needed to set, and for Region | |
133 | * 'E', the CPU physical address keep as is. | |
134 | * Additionally, The iommu consumers always use the CPU phyiscal address. | |
135 | */ | |
b4dad40e | 136 | #define MTK_IOMMU_4GB_MODE_REMAP_BASE 0x140000000UL |
76ce6546 | 137 | |
7c3a2ec0 YW |
138 | static LIST_HEAD(m4ulist); /* List all the M4U HWs */ |
139 | ||
140 | #define for_each_m4u(data) list_for_each_entry(data, &m4ulist, list) | |
141 | ||
142 | /* | |
143 | * There may be 1 or 2 M4U HWs, But we always expect they are in the same domain | |
144 | * for the performance. | |
145 | * | |
146 | * Here always return the mtk_iommu_data of the first probed M4U where the | |
147 | * iommu domain information is recorded. | |
148 | */ | |
149 | static struct mtk_iommu_data *mtk_iommu_get_m4u_data(void) | |
150 | { | |
151 | struct mtk_iommu_data *data; | |
152 | ||
153 | for_each_m4u(data) | |
154 | return data; | |
155 | ||
156 | return NULL; | |
157 | } | |
158 | ||
0df4fabe YW |
159 | static struct mtk_iommu_domain *to_mtk_domain(struct iommu_domain *dom) |
160 | { | |
161 | return container_of(dom, struct mtk_iommu_domain, domain); | |
162 | } | |
163 | ||
164 | static void mtk_iommu_tlb_flush_all(void *cookie) | |
165 | { | |
166 | struct mtk_iommu_data *data = cookie; | |
167 | ||
7c3a2ec0 YW |
168 | for_each_m4u(data) { |
169 | writel_relaxed(F_INVLD_EN1 | F_INVLD_EN0, | |
170 | data->base + REG_MMU_INV_SEL); | |
171 | writel_relaxed(F_ALL_INVLD, data->base + REG_MMU_INVALIDATE); | |
172 | wmb(); /* Make sure the tlb flush all done */ | |
173 | } | |
0df4fabe YW |
174 | } |
175 | ||
176 | static void mtk_iommu_tlb_add_flush_nosync(unsigned long iova, size_t size, | |
177 | size_t granule, bool leaf, | |
178 | void *cookie) | |
179 | { | |
180 | struct mtk_iommu_data *data = cookie; | |
181 | ||
7c3a2ec0 YW |
182 | for_each_m4u(data) { |
183 | writel_relaxed(F_INVLD_EN1 | F_INVLD_EN0, | |
184 | data->base + REG_MMU_INV_SEL); | |
0df4fabe | 185 | |
7c3a2ec0 YW |
186 | writel_relaxed(iova, data->base + REG_MMU_INVLD_START_A); |
187 | writel_relaxed(iova + size - 1, | |
188 | data->base + REG_MMU_INVLD_END_A); | |
189 | writel_relaxed(F_MMU_INV_RANGE, | |
190 | data->base + REG_MMU_INVALIDATE); | |
191 | data->tlb_flush_active = true; | |
192 | } | |
0df4fabe YW |
193 | } |
194 | ||
195 | static void mtk_iommu_tlb_sync(void *cookie) | |
196 | { | |
197 | struct mtk_iommu_data *data = cookie; | |
198 | int ret; | |
199 | u32 tmp; | |
200 | ||
7c3a2ec0 YW |
201 | for_each_m4u(data) { |
202 | /* Avoid timing out if there's nothing to wait for */ | |
203 | if (!data->tlb_flush_active) | |
204 | return; | |
98a8f63e | 205 | |
7c3a2ec0 YW |
206 | ret = readl_poll_timeout_atomic(data->base + REG_MMU_CPE_DONE, |
207 | tmp, tmp != 0, 10, 100000); | |
208 | if (ret) { | |
209 | dev_warn(data->dev, | |
210 | "Partial TLB flush timed out, falling back to full flush\n"); | |
211 | mtk_iommu_tlb_flush_all(cookie); | |
212 | } | |
213 | /* Clear the CPE status */ | |
214 | writel_relaxed(0, data->base + REG_MMU_CPE_DONE); | |
215 | data->tlb_flush_active = false; | |
0df4fabe | 216 | } |
0df4fabe YW |
217 | } |
218 | ||
05aed941 WD |
219 | static void mtk_iommu_tlb_flush_walk(unsigned long iova, size_t size, |
220 | size_t granule, void *cookie) | |
221 | { | |
da3cc91b YW |
222 | struct mtk_iommu_data *data = cookie; |
223 | unsigned long flags; | |
224 | ||
225 | spin_lock_irqsave(&data->tlb_lock, flags); | |
05aed941 WD |
226 | mtk_iommu_tlb_add_flush_nosync(iova, size, granule, false, cookie); |
227 | mtk_iommu_tlb_sync(cookie); | |
da3cc91b | 228 | spin_unlock_irqrestore(&data->tlb_lock, flags); |
05aed941 WD |
229 | } |
230 | ||
231 | static void mtk_iommu_tlb_flush_leaf(unsigned long iova, size_t size, | |
232 | size_t granule, void *cookie) | |
233 | { | |
da3cc91b YW |
234 | struct mtk_iommu_data *data = cookie; |
235 | unsigned long flags; | |
236 | ||
237 | spin_lock_irqsave(&data->tlb_lock, flags); | |
05aed941 WD |
238 | mtk_iommu_tlb_add_flush_nosync(iova, size, granule, true, cookie); |
239 | mtk_iommu_tlb_sync(cookie); | |
da3cc91b | 240 | spin_unlock_irqrestore(&data->tlb_lock, flags); |
05aed941 WD |
241 | } |
242 | ||
3951c41a WD |
243 | static void mtk_iommu_tlb_flush_page_nosync(struct iommu_iotlb_gather *gather, |
244 | unsigned long iova, size_t granule, | |
abfd6fe0 WD |
245 | void *cookie) |
246 | { | |
da3cc91b | 247 | struct mtk_iommu_data *data = cookie; |
a7a04ea3 | 248 | struct iommu_domain *domain = &data->m4u_dom->domain; |
da3cc91b | 249 | |
a7a04ea3 | 250 | iommu_iotlb_gather_add_page(domain, gather, iova, granule); |
abfd6fe0 WD |
251 | } |
252 | ||
298f7889 | 253 | static const struct iommu_flush_ops mtk_iommu_flush_ops = { |
0df4fabe | 254 | .tlb_flush_all = mtk_iommu_tlb_flush_all, |
05aed941 WD |
255 | .tlb_flush_walk = mtk_iommu_tlb_flush_walk, |
256 | .tlb_flush_leaf = mtk_iommu_tlb_flush_leaf, | |
abfd6fe0 | 257 | .tlb_add_page = mtk_iommu_tlb_flush_page_nosync, |
0df4fabe YW |
258 | }; |
259 | ||
260 | static irqreturn_t mtk_iommu_isr(int irq, void *dev_id) | |
261 | { | |
262 | struct mtk_iommu_data *data = dev_id; | |
263 | struct mtk_iommu_domain *dom = data->m4u_dom; | |
264 | u32 int_state, regval, fault_iova, fault_pa; | |
265 | unsigned int fault_larb, fault_port; | |
266 | bool layer, write; | |
267 | ||
268 | /* Read error info from registers */ | |
269 | int_state = readl_relaxed(data->base + REG_MMU_FAULT_ST1); | |
15a01f4c YW |
270 | if (int_state & F_REG_MMU0_FAULT_MASK) { |
271 | regval = readl_relaxed(data->base + REG_MMU0_INT_ID); | |
272 | fault_iova = readl_relaxed(data->base + REG_MMU0_FAULT_VA); | |
273 | fault_pa = readl_relaxed(data->base + REG_MMU0_INVLD_PA); | |
274 | } else { | |
275 | regval = readl_relaxed(data->base + REG_MMU1_INT_ID); | |
276 | fault_iova = readl_relaxed(data->base + REG_MMU1_FAULT_VA); | |
277 | fault_pa = readl_relaxed(data->base + REG_MMU1_INVLD_PA); | |
278 | } | |
0df4fabe YW |
279 | layer = fault_iova & F_MMU_FAULT_VA_LAYER_BIT; |
280 | write = fault_iova & F_MMU_FAULT_VA_WRITE_BIT; | |
15a01f4c YW |
281 | fault_larb = F_MMU_INT_ID_LARB_ID(regval); |
282 | fault_port = F_MMU_INT_ID_PORT_ID(regval); | |
0df4fabe | 283 | |
b3e5eee7 YW |
284 | fault_larb = data->plat_data->larbid_remap[fault_larb]; |
285 | ||
0df4fabe YW |
286 | if (report_iommu_fault(&dom->domain, data->dev, fault_iova, |
287 | write ? IOMMU_FAULT_WRITE : IOMMU_FAULT_READ)) { | |
288 | dev_err_ratelimited( | |
289 | data->dev, | |
290 | "fault type=0x%x iova=0x%x pa=0x%x larb=%d port=%d layer=%d %s\n", | |
291 | int_state, fault_iova, fault_pa, fault_larb, fault_port, | |
292 | layer, write ? "write" : "read"); | |
293 | } | |
294 | ||
295 | /* Interrupt clear */ | |
296 | regval = readl_relaxed(data->base + REG_MMU_INT_CONTROL0); | |
297 | regval |= F_INT_CLR_BIT; | |
298 | writel_relaxed(regval, data->base + REG_MMU_INT_CONTROL0); | |
299 | ||
300 | mtk_iommu_tlb_flush_all(data); | |
301 | ||
302 | return IRQ_HANDLED; | |
303 | } | |
304 | ||
305 | static void mtk_iommu_config(struct mtk_iommu_data *data, | |
306 | struct device *dev, bool enable) | |
307 | { | |
0df4fabe YW |
308 | struct mtk_smi_larb_iommu *larb_mmu; |
309 | unsigned int larbid, portid; | |
a9bf2eec | 310 | struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev); |
58f0d1d5 | 311 | int i; |
0df4fabe | 312 | |
58f0d1d5 RM |
313 | for (i = 0; i < fwspec->num_ids; ++i) { |
314 | larbid = MTK_M4U_TO_LARB(fwspec->ids[i]); | |
315 | portid = MTK_M4U_TO_PORT(fwspec->ids[i]); | |
1ee9feb2 | 316 | larb_mmu = &data->larb_imu[larbid]; |
0df4fabe YW |
317 | |
318 | dev_dbg(dev, "%s iommu port: %d\n", | |
319 | enable ? "enable" : "disable", portid); | |
320 | ||
321 | if (enable) | |
322 | larb_mmu->mmu |= MTK_SMI_MMU_EN(portid); | |
323 | else | |
324 | larb_mmu->mmu &= ~MTK_SMI_MMU_EN(portid); | |
325 | } | |
326 | } | |
327 | ||
4b00f5ac | 328 | static int mtk_iommu_domain_finalise(struct mtk_iommu_domain *dom) |
0df4fabe | 329 | { |
4b00f5ac | 330 | struct mtk_iommu_data *data = mtk_iommu_get_m4u_data(); |
0df4fabe YW |
331 | |
332 | spin_lock_init(&dom->pgtlock); | |
333 | ||
334 | dom->cfg = (struct io_pgtable_cfg) { | |
335 | .quirks = IO_PGTABLE_QUIRK_ARM_NS | | |
336 | IO_PGTABLE_QUIRK_NO_PERMS | | |
b4dad40e YW |
337 | IO_PGTABLE_QUIRK_TLBI_ON_MAP | |
338 | IO_PGTABLE_QUIRK_ARM_MTK_EXT, | |
0df4fabe YW |
339 | .pgsize_bitmap = mtk_iommu_ops.pgsize_bitmap, |
340 | .ias = 32, | |
b4dad40e | 341 | .oas = 34, |
298f7889 | 342 | .tlb = &mtk_iommu_flush_ops, |
0df4fabe YW |
343 | .iommu_dev = data->dev, |
344 | }; | |
345 | ||
346 | dom->iop = alloc_io_pgtable_ops(ARM_V7S, &dom->cfg, data); | |
347 | if (!dom->iop) { | |
348 | dev_err(data->dev, "Failed to alloc io pgtable\n"); | |
349 | return -EINVAL; | |
350 | } | |
351 | ||
352 | /* Update our support page sizes bitmap */ | |
d16e0faa | 353 | dom->domain.pgsize_bitmap = dom->cfg.pgsize_bitmap; |
0df4fabe YW |
354 | return 0; |
355 | } | |
356 | ||
357 | static struct iommu_domain *mtk_iommu_domain_alloc(unsigned type) | |
358 | { | |
359 | struct mtk_iommu_domain *dom; | |
360 | ||
361 | if (type != IOMMU_DOMAIN_DMA) | |
362 | return NULL; | |
363 | ||
364 | dom = kzalloc(sizeof(*dom), GFP_KERNEL); | |
365 | if (!dom) | |
366 | return NULL; | |
367 | ||
4b00f5ac YW |
368 | if (iommu_get_dma_cookie(&dom->domain)) |
369 | goto free_dom; | |
370 | ||
371 | if (mtk_iommu_domain_finalise(dom)) | |
372 | goto put_dma_cookie; | |
0df4fabe YW |
373 | |
374 | dom->domain.geometry.aperture_start = 0; | |
375 | dom->domain.geometry.aperture_end = DMA_BIT_MASK(32); | |
376 | dom->domain.geometry.force_aperture = true; | |
377 | ||
378 | return &dom->domain; | |
4b00f5ac YW |
379 | |
380 | put_dma_cookie: | |
381 | iommu_put_dma_cookie(&dom->domain); | |
382 | free_dom: | |
383 | kfree(dom); | |
384 | return NULL; | |
0df4fabe YW |
385 | } |
386 | ||
387 | static void mtk_iommu_domain_free(struct iommu_domain *domain) | |
388 | { | |
4b00f5ac YW |
389 | struct mtk_iommu_domain *dom = to_mtk_domain(domain); |
390 | ||
391 | free_io_pgtable_ops(dom->iop); | |
0df4fabe YW |
392 | iommu_put_dma_cookie(domain); |
393 | kfree(to_mtk_domain(domain)); | |
394 | } | |
395 | ||
396 | static int mtk_iommu_attach_device(struct iommu_domain *domain, | |
397 | struct device *dev) | |
398 | { | |
399 | struct mtk_iommu_domain *dom = to_mtk_domain(domain); | |
a9bf2eec | 400 | struct mtk_iommu_data *data = dev_iommu_fwspec_get(dev)->iommu_priv; |
0df4fabe | 401 | |
4b00f5ac | 402 | if (!data) |
0df4fabe YW |
403 | return -ENODEV; |
404 | ||
4b00f5ac | 405 | /* Update the pgtable base address register of the M4U HW */ |
0df4fabe YW |
406 | if (!data->m4u_dom) { |
407 | data->m4u_dom = dom; | |
907ba6a1 | 408 | writel(dom->cfg.arm_v7s_cfg.ttbr[0] & MMU_PT_ADDR_MASK, |
4b00f5ac | 409 | data->base + REG_MMU_PT_BASE_ADDR); |
7c3a2ec0 YW |
410 | } |
411 | ||
4b00f5ac | 412 | mtk_iommu_config(data, dev, true); |
0df4fabe YW |
413 | return 0; |
414 | } | |
415 | ||
416 | static void mtk_iommu_detach_device(struct iommu_domain *domain, | |
417 | struct device *dev) | |
418 | { | |
a9bf2eec | 419 | struct mtk_iommu_data *data = dev_iommu_fwspec_get(dev)->iommu_priv; |
0df4fabe | 420 | |
58f0d1d5 | 421 | if (!data) |
0df4fabe YW |
422 | return; |
423 | ||
0df4fabe YW |
424 | mtk_iommu_config(data, dev, false); |
425 | } | |
426 | ||
427 | static int mtk_iommu_map(struct iommu_domain *domain, unsigned long iova, | |
428 | phys_addr_t paddr, size_t size, int prot) | |
429 | { | |
430 | struct mtk_iommu_domain *dom = to_mtk_domain(domain); | |
b4dad40e | 431 | struct mtk_iommu_data *data = mtk_iommu_get_m4u_data(); |
0df4fabe YW |
432 | unsigned long flags; |
433 | int ret; | |
434 | ||
b4dad40e YW |
435 | /* The "4GB mode" M4U physically can not use the lower remap of Dram. */ |
436 | if (data->enable_4GB) | |
437 | paddr |= BIT_ULL(32); | |
438 | ||
0df4fabe | 439 | spin_lock_irqsave(&dom->pgtlock, flags); |
b4dad40e | 440 | ret = dom->iop->map(dom->iop, iova, paddr, size, prot); |
0df4fabe YW |
441 | spin_unlock_irqrestore(&dom->pgtlock, flags); |
442 | ||
443 | return ret; | |
444 | } | |
445 | ||
446 | static size_t mtk_iommu_unmap(struct iommu_domain *domain, | |
56f8af5e WD |
447 | unsigned long iova, size_t size, |
448 | struct iommu_iotlb_gather *gather) | |
0df4fabe YW |
449 | { |
450 | struct mtk_iommu_domain *dom = to_mtk_domain(domain); | |
451 | unsigned long flags; | |
452 | size_t unmapsz; | |
453 | ||
454 | spin_lock_irqsave(&dom->pgtlock, flags); | |
a2d3a382 | 455 | unmapsz = dom->iop->unmap(dom->iop, iova, size, gather); |
0df4fabe YW |
456 | spin_unlock_irqrestore(&dom->pgtlock, flags); |
457 | ||
458 | return unmapsz; | |
459 | } | |
460 | ||
56f8af5e WD |
461 | static void mtk_iommu_flush_iotlb_all(struct iommu_domain *domain) |
462 | { | |
2009122f | 463 | mtk_iommu_tlb_flush_all(mtk_iommu_get_m4u_data()); |
56f8af5e WD |
464 | } |
465 | ||
466 | static void mtk_iommu_iotlb_sync(struct iommu_domain *domain, | |
467 | struct iommu_iotlb_gather *gather) | |
4d689b61 | 468 | { |
da3cc91b | 469 | struct mtk_iommu_data *data = mtk_iommu_get_m4u_data(); |
a7a04ea3 | 470 | size_t length = gather->end - gather->start; |
da3cc91b YW |
471 | unsigned long flags; |
472 | ||
a7a04ea3 YW |
473 | if (gather->start == ULONG_MAX) |
474 | return; | |
475 | ||
da3cc91b | 476 | spin_lock_irqsave(&data->tlb_lock, flags); |
a7a04ea3 YW |
477 | mtk_iommu_tlb_add_flush_nosync(gather->start, length, gather->pgsize, |
478 | false, data); | |
da3cc91b YW |
479 | mtk_iommu_tlb_sync(data); |
480 | spin_unlock_irqrestore(&data->tlb_lock, flags); | |
4d689b61 RM |
481 | } |
482 | ||
0df4fabe YW |
483 | static phys_addr_t mtk_iommu_iova_to_phys(struct iommu_domain *domain, |
484 | dma_addr_t iova) | |
485 | { | |
486 | struct mtk_iommu_domain *dom = to_mtk_domain(domain); | |
30e2fccf | 487 | struct mtk_iommu_data *data = mtk_iommu_get_m4u_data(); |
0df4fabe YW |
488 | unsigned long flags; |
489 | phys_addr_t pa; | |
490 | ||
491 | spin_lock_irqsave(&dom->pgtlock, flags); | |
492 | pa = dom->iop->iova_to_phys(dom->iop, iova); | |
493 | spin_unlock_irqrestore(&dom->pgtlock, flags); | |
494 | ||
b4dad40e YW |
495 | if (data->enable_4GB && pa >= MTK_IOMMU_4GB_MODE_REMAP_BASE) |
496 | pa &= ~BIT_ULL(32); | |
30e2fccf | 497 | |
0df4fabe YW |
498 | return pa; |
499 | } | |
500 | ||
501 | static int mtk_iommu_add_device(struct device *dev) | |
502 | { | |
a9bf2eec | 503 | struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev); |
b16c0170 | 504 | struct mtk_iommu_data *data; |
0df4fabe YW |
505 | struct iommu_group *group; |
506 | ||
a9bf2eec | 507 | if (!fwspec || fwspec->ops != &mtk_iommu_ops) |
58f0d1d5 | 508 | return -ENODEV; /* Not a iommu client device */ |
0df4fabe | 509 | |
a9bf2eec | 510 | data = fwspec->iommu_priv; |
b16c0170 JR |
511 | iommu_device_link(&data->iommu, dev); |
512 | ||
0df4fabe YW |
513 | group = iommu_group_get_for_dev(dev); |
514 | if (IS_ERR(group)) | |
515 | return PTR_ERR(group); | |
516 | ||
517 | iommu_group_put(group); | |
518 | return 0; | |
519 | } | |
520 | ||
521 | static void mtk_iommu_remove_device(struct device *dev) | |
522 | { | |
a9bf2eec | 523 | struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev); |
b16c0170 JR |
524 | struct mtk_iommu_data *data; |
525 | ||
a9bf2eec | 526 | if (!fwspec || fwspec->ops != &mtk_iommu_ops) |
0df4fabe YW |
527 | return; |
528 | ||
a9bf2eec | 529 | data = fwspec->iommu_priv; |
b16c0170 JR |
530 | iommu_device_unlink(&data->iommu, dev); |
531 | ||
0df4fabe | 532 | iommu_group_remove_device(dev); |
58f0d1d5 | 533 | iommu_fwspec_free(dev); |
0df4fabe YW |
534 | } |
535 | ||
536 | static struct iommu_group *mtk_iommu_device_group(struct device *dev) | |
537 | { | |
7c3a2ec0 | 538 | struct mtk_iommu_data *data = mtk_iommu_get_m4u_data(); |
0df4fabe | 539 | |
58f0d1d5 | 540 | if (!data) |
0df4fabe YW |
541 | return ERR_PTR(-ENODEV); |
542 | ||
543 | /* All the client devices are in the same m4u iommu-group */ | |
0df4fabe YW |
544 | if (!data->m4u_group) { |
545 | data->m4u_group = iommu_group_alloc(); | |
546 | if (IS_ERR(data->m4u_group)) | |
547 | dev_err(dev, "Failed to allocate M4U IOMMU group\n"); | |
3a8d40b6 RM |
548 | } else { |
549 | iommu_group_ref_get(data->m4u_group); | |
0df4fabe YW |
550 | } |
551 | return data->m4u_group; | |
552 | } | |
553 | ||
554 | static int mtk_iommu_of_xlate(struct device *dev, struct of_phandle_args *args) | |
555 | { | |
a9bf2eec | 556 | struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev); |
0df4fabe YW |
557 | struct platform_device *m4updev; |
558 | ||
559 | if (args->args_count != 1) { | |
560 | dev_err(dev, "invalid #iommu-cells(%d) property for IOMMU\n", | |
561 | args->args_count); | |
562 | return -EINVAL; | |
563 | } | |
564 | ||
a9bf2eec | 565 | if (!fwspec->iommu_priv) { |
0df4fabe YW |
566 | /* Get the m4u device */ |
567 | m4updev = of_find_device_by_node(args->np); | |
0df4fabe YW |
568 | if (WARN_ON(!m4updev)) |
569 | return -EINVAL; | |
570 | ||
a9bf2eec | 571 | fwspec->iommu_priv = platform_get_drvdata(m4updev); |
0df4fabe YW |
572 | } |
573 | ||
58f0d1d5 | 574 | return iommu_fwspec_add_ids(dev, args->args, 1); |
0df4fabe YW |
575 | } |
576 | ||
b65f5016 | 577 | static const struct iommu_ops mtk_iommu_ops = { |
0df4fabe YW |
578 | .domain_alloc = mtk_iommu_domain_alloc, |
579 | .domain_free = mtk_iommu_domain_free, | |
580 | .attach_dev = mtk_iommu_attach_device, | |
581 | .detach_dev = mtk_iommu_detach_device, | |
582 | .map = mtk_iommu_map, | |
583 | .unmap = mtk_iommu_unmap, | |
56f8af5e | 584 | .flush_iotlb_all = mtk_iommu_flush_iotlb_all, |
4d689b61 | 585 | .iotlb_sync = mtk_iommu_iotlb_sync, |
0df4fabe YW |
586 | .iova_to_phys = mtk_iommu_iova_to_phys, |
587 | .add_device = mtk_iommu_add_device, | |
588 | .remove_device = mtk_iommu_remove_device, | |
589 | .device_group = mtk_iommu_device_group, | |
590 | .of_xlate = mtk_iommu_of_xlate, | |
591 | .pgsize_bitmap = SZ_4K | SZ_64K | SZ_1M | SZ_16M, | |
592 | }; | |
593 | ||
594 | static int mtk_iommu_hw_init(const struct mtk_iommu_data *data) | |
595 | { | |
596 | u32 regval; | |
597 | int ret; | |
598 | ||
599 | ret = clk_prepare_enable(data->bclk); | |
600 | if (ret) { | |
601 | dev_err(data->dev, "Failed to enable iommu bclk(%d)\n", ret); | |
602 | return ret; | |
603 | } | |
604 | ||
cecdce9d | 605 | if (data->plat_data->m4u_plat == M4U_MT8173) |
acb3c92a YW |
606 | regval = F_MMU_PREFETCH_RT_REPLACE_MOD | |
607 | F_MMU_TF_PROT_TO_PROGRAM_ADDR_MT8173; | |
608 | else | |
609 | regval = F_MMU_TF_PROT_TO_PROGRAM_ADDR; | |
0df4fabe YW |
610 | writel_relaxed(regval, data->base + REG_MMU_CTRL_REG); |
611 | ||
612 | regval = F_L2_MULIT_HIT_EN | | |
613 | F_TABLE_WALK_FAULT_INT_EN | | |
614 | F_PREETCH_FIFO_OVERFLOW_INT_EN | | |
615 | F_MISS_FIFO_OVERFLOW_INT_EN | | |
616 | F_PREFETCH_FIFO_ERR_INT_EN | | |
617 | F_MISS_FIFO_ERR_INT_EN; | |
618 | writel_relaxed(regval, data->base + REG_MMU_INT_CONTROL0); | |
619 | ||
620 | regval = F_INT_TRANSLATION_FAULT | | |
621 | F_INT_MAIN_MULTI_HIT_FAULT | | |
622 | F_INT_INVALID_PA_FAULT | | |
623 | F_INT_ENTRY_REPLACEMENT_FAULT | | |
624 | F_INT_TLB_MISS_FAULT | | |
625 | F_INT_MISS_TRANSACTION_FIFO_FAULT | | |
626 | F_INT_PRETETCH_TRANSATION_FIFO_FAULT; | |
627 | writel_relaxed(regval, data->base + REG_MMU_INT_MAIN_CONTROL); | |
628 | ||
cecdce9d | 629 | if (data->plat_data->m4u_plat == M4U_MT8173) |
70ca608b YW |
630 | regval = (data->protect_base >> 1) | (data->enable_4GB << 31); |
631 | else | |
632 | regval = lower_32_bits(data->protect_base) | | |
633 | upper_32_bits(data->protect_base); | |
634 | writel_relaxed(regval, data->base + REG_MMU_IVRP_PADDR); | |
635 | ||
2b326d8b | 636 | if (data->enable_4GB && data->plat_data->has_vld_pa_rng) { |
30e2fccf YW |
637 | /* |
638 | * If 4GB mode is enabled, the validate PA range is from | |
639 | * 0x1_0000_0000 to 0x1_ffff_ffff. here record bit[32:30]. | |
640 | */ | |
641 | regval = F_MMU_VLD_PA_RNG(7, 4); | |
642 | writel_relaxed(regval, data->base + REG_MMU_VLD_PA_RNG); | |
643 | } | |
0df4fabe | 644 | writel_relaxed(0, data->base + REG_MMU_DCM_DIS); |
e6dec923 | 645 | |
50822b0b | 646 | if (data->plat_data->reset_axi) |
e6dec923 | 647 | writel_relaxed(0, data->base + REG_MMU_STANDARD_AXI_MODE); |
0df4fabe YW |
648 | |
649 | if (devm_request_irq(data->dev, data->irq, mtk_iommu_isr, 0, | |
650 | dev_name(data->dev), (void *)data)) { | |
651 | writel_relaxed(0, data->base + REG_MMU_PT_BASE_ADDR); | |
652 | clk_disable_unprepare(data->bclk); | |
653 | dev_err(data->dev, "Failed @ IRQ-%d Request\n", data->irq); | |
654 | return -ENODEV; | |
655 | } | |
656 | ||
657 | return 0; | |
658 | } | |
659 | ||
0df4fabe YW |
660 | static const struct component_master_ops mtk_iommu_com_ops = { |
661 | .bind = mtk_iommu_bind, | |
662 | .unbind = mtk_iommu_unbind, | |
663 | }; | |
664 | ||
665 | static int mtk_iommu_probe(struct platform_device *pdev) | |
666 | { | |
667 | struct mtk_iommu_data *data; | |
668 | struct device *dev = &pdev->dev; | |
669 | struct resource *res; | |
b16c0170 | 670 | resource_size_t ioaddr; |
0df4fabe YW |
671 | struct component_match *match = NULL; |
672 | void *protect; | |
0b6c0ad3 | 673 | int i, larb_nr, ret; |
0df4fabe YW |
674 | |
675 | data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL); | |
676 | if (!data) | |
677 | return -ENOMEM; | |
678 | data->dev = dev; | |
cecdce9d | 679 | data->plat_data = of_device_get_match_data(dev); |
0df4fabe YW |
680 | |
681 | /* Protect memory. HW will access here while translation fault.*/ | |
682 | protect = devm_kzalloc(dev, MTK_PROTECT_PA_ALIGN * 2, GFP_KERNEL); | |
683 | if (!protect) | |
684 | return -ENOMEM; | |
685 | data->protect_base = ALIGN(virt_to_phys(protect), MTK_PROTECT_PA_ALIGN); | |
686 | ||
01e23c93 | 687 | /* Whether the current dram is over 4GB */ |
41939980 | 688 | data->enable_4GB = !!(max_pfn > (BIT_ULL(32) >> PAGE_SHIFT)); |
b4dad40e YW |
689 | if (!data->plat_data->has_4gb_mode) |
690 | data->enable_4GB = false; | |
01e23c93 | 691 | |
0df4fabe YW |
692 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
693 | data->base = devm_ioremap_resource(dev, res); | |
694 | if (IS_ERR(data->base)) | |
695 | return PTR_ERR(data->base); | |
b16c0170 | 696 | ioaddr = res->start; |
0df4fabe YW |
697 | |
698 | data->irq = platform_get_irq(pdev, 0); | |
699 | if (data->irq < 0) | |
700 | return data->irq; | |
701 | ||
2aa4c259 YW |
702 | if (data->plat_data->has_bclk) { |
703 | data->bclk = devm_clk_get(dev, "bclk"); | |
704 | if (IS_ERR(data->bclk)) | |
705 | return PTR_ERR(data->bclk); | |
706 | } | |
0df4fabe YW |
707 | |
708 | larb_nr = of_count_phandle_with_args(dev->of_node, | |
709 | "mediatek,larbs", NULL); | |
710 | if (larb_nr < 0) | |
711 | return larb_nr; | |
0df4fabe YW |
712 | |
713 | for (i = 0; i < larb_nr; i++) { | |
714 | struct device_node *larbnode; | |
715 | struct platform_device *plarbdev; | |
e6dec923 | 716 | u32 id; |
0df4fabe YW |
717 | |
718 | larbnode = of_parse_phandle(dev->of_node, "mediatek,larbs", i); | |
719 | if (!larbnode) | |
720 | return -EINVAL; | |
721 | ||
1eb8e4e2 WY |
722 | if (!of_device_is_available(larbnode)) { |
723 | of_node_put(larbnode); | |
0df4fabe | 724 | continue; |
1eb8e4e2 | 725 | } |
0df4fabe | 726 | |
e6dec923 YW |
727 | ret = of_property_read_u32(larbnode, "mediatek,larb-id", &id); |
728 | if (ret)/* The id is consecutive if there is no this property */ | |
729 | id = i; | |
730 | ||
0df4fabe | 731 | plarbdev = of_find_device_by_node(larbnode); |
1eb8e4e2 WY |
732 | if (!plarbdev) { |
733 | of_node_put(larbnode); | |
e6dec923 | 734 | return -EPROBE_DEFER; |
1eb8e4e2 | 735 | } |
1ee9feb2 | 736 | data->larb_imu[id].dev = &plarbdev->dev; |
0df4fabe | 737 | |
00c7c81f RK |
738 | component_match_add_release(dev, &match, release_of, |
739 | compare_of, larbnode); | |
0df4fabe YW |
740 | } |
741 | ||
742 | platform_set_drvdata(pdev, data); | |
743 | ||
744 | ret = mtk_iommu_hw_init(data); | |
745 | if (ret) | |
746 | return ret; | |
747 | ||
b16c0170 JR |
748 | ret = iommu_device_sysfs_add(&data->iommu, dev, NULL, |
749 | "mtk-iommu.%pa", &ioaddr); | |
750 | if (ret) | |
751 | return ret; | |
752 | ||
753 | iommu_device_set_ops(&data->iommu, &mtk_iommu_ops); | |
754 | iommu_device_set_fwnode(&data->iommu, &pdev->dev.of_node->fwnode); | |
755 | ||
756 | ret = iommu_device_register(&data->iommu); | |
757 | if (ret) | |
758 | return ret; | |
759 | ||
da3cc91b | 760 | spin_lock_init(&data->tlb_lock); |
7c3a2ec0 YW |
761 | list_add_tail(&data->list, &m4ulist); |
762 | ||
0df4fabe YW |
763 | if (!iommu_present(&platform_bus_type)) |
764 | bus_set_iommu(&platform_bus_type, &mtk_iommu_ops); | |
765 | ||
766 | return component_master_add_with_match(dev, &mtk_iommu_com_ops, match); | |
767 | } | |
768 | ||
769 | static int mtk_iommu_remove(struct platform_device *pdev) | |
770 | { | |
771 | struct mtk_iommu_data *data = platform_get_drvdata(pdev); | |
772 | ||
b16c0170 JR |
773 | iommu_device_sysfs_remove(&data->iommu); |
774 | iommu_device_unregister(&data->iommu); | |
775 | ||
0df4fabe YW |
776 | if (iommu_present(&platform_bus_type)) |
777 | bus_set_iommu(&platform_bus_type, NULL); | |
778 | ||
0df4fabe YW |
779 | clk_disable_unprepare(data->bclk); |
780 | devm_free_irq(&pdev->dev, data->irq, data); | |
781 | component_master_del(&pdev->dev, &mtk_iommu_com_ops); | |
782 | return 0; | |
783 | } | |
784 | ||
fd99f796 | 785 | static int __maybe_unused mtk_iommu_suspend(struct device *dev) |
0df4fabe YW |
786 | { |
787 | struct mtk_iommu_data *data = dev_get_drvdata(dev); | |
788 | struct mtk_iommu_suspend_reg *reg = &data->reg; | |
789 | void __iomem *base = data->base; | |
790 | ||
791 | reg->standard_axi_mode = readl_relaxed(base + | |
792 | REG_MMU_STANDARD_AXI_MODE); | |
793 | reg->dcm_dis = readl_relaxed(base + REG_MMU_DCM_DIS); | |
794 | reg->ctrl_reg = readl_relaxed(base + REG_MMU_CTRL_REG); | |
795 | reg->int_control0 = readl_relaxed(base + REG_MMU_INT_CONTROL0); | |
796 | reg->int_main_control = readl_relaxed(base + REG_MMU_INT_MAIN_CONTROL); | |
70ca608b | 797 | reg->ivrp_paddr = readl_relaxed(base + REG_MMU_IVRP_PADDR); |
b9475b34 | 798 | reg->vld_pa_rng = readl_relaxed(base + REG_MMU_VLD_PA_RNG); |
6254b64f | 799 | clk_disable_unprepare(data->bclk); |
0df4fabe YW |
800 | return 0; |
801 | } | |
802 | ||
fd99f796 | 803 | static int __maybe_unused mtk_iommu_resume(struct device *dev) |
0df4fabe YW |
804 | { |
805 | struct mtk_iommu_data *data = dev_get_drvdata(dev); | |
806 | struct mtk_iommu_suspend_reg *reg = &data->reg; | |
907ba6a1 | 807 | struct mtk_iommu_domain *m4u_dom = data->m4u_dom; |
0df4fabe | 808 | void __iomem *base = data->base; |
6254b64f | 809 | int ret; |
0df4fabe | 810 | |
6254b64f YW |
811 | ret = clk_prepare_enable(data->bclk); |
812 | if (ret) { | |
813 | dev_err(data->dev, "Failed to enable clk(%d) in resume\n", ret); | |
814 | return ret; | |
815 | } | |
0df4fabe YW |
816 | writel_relaxed(reg->standard_axi_mode, |
817 | base + REG_MMU_STANDARD_AXI_MODE); | |
818 | writel_relaxed(reg->dcm_dis, base + REG_MMU_DCM_DIS); | |
819 | writel_relaxed(reg->ctrl_reg, base + REG_MMU_CTRL_REG); | |
820 | writel_relaxed(reg->int_control0, base + REG_MMU_INT_CONTROL0); | |
821 | writel_relaxed(reg->int_main_control, base + REG_MMU_INT_MAIN_CONTROL); | |
70ca608b | 822 | writel_relaxed(reg->ivrp_paddr, base + REG_MMU_IVRP_PADDR); |
b9475b34 | 823 | writel_relaxed(reg->vld_pa_rng, base + REG_MMU_VLD_PA_RNG); |
907ba6a1 YW |
824 | if (m4u_dom) |
825 | writel(m4u_dom->cfg.arm_v7s_cfg.ttbr[0] & MMU_PT_ADDR_MASK, | |
e6dec923 | 826 | base + REG_MMU_PT_BASE_ADDR); |
0df4fabe YW |
827 | return 0; |
828 | } | |
829 | ||
e6dec923 | 830 | static const struct dev_pm_ops mtk_iommu_pm_ops = { |
6254b64f | 831 | SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(mtk_iommu_suspend, mtk_iommu_resume) |
0df4fabe YW |
832 | }; |
833 | ||
cecdce9d YW |
834 | static const struct mtk_iommu_plat_data mt2712_data = { |
835 | .m4u_plat = M4U_MT2712, | |
b4dad40e | 836 | .has_4gb_mode = true, |
2aa4c259 | 837 | .has_bclk = true, |
2b326d8b | 838 | .has_vld_pa_rng = true, |
b3e5eee7 | 839 | .larbid_remap = {0, 1, 2, 3, 4, 5, 6, 7, 8, 9}, |
cecdce9d YW |
840 | }; |
841 | ||
842 | static const struct mtk_iommu_plat_data mt8173_data = { | |
843 | .m4u_plat = M4U_MT8173, | |
b4dad40e | 844 | .has_4gb_mode = true, |
2aa4c259 | 845 | .has_bclk = true, |
50822b0b | 846 | .reset_axi = true, |
b3e5eee7 | 847 | .larbid_remap = {0, 1, 2, 3, 4, 5}, /* Linear mapping. */ |
cecdce9d YW |
848 | }; |
849 | ||
907ba6a1 YW |
850 | static const struct mtk_iommu_plat_data mt8183_data = { |
851 | .m4u_plat = M4U_MT8183, | |
852 | .reset_axi = true, | |
853 | .larbid_remap = {0, 4, 5, 6, 7, 2, 3, 1}, | |
854 | }; | |
855 | ||
0df4fabe | 856 | static const struct of_device_id mtk_iommu_of_ids[] = { |
cecdce9d YW |
857 | { .compatible = "mediatek,mt2712-m4u", .data = &mt2712_data}, |
858 | { .compatible = "mediatek,mt8173-m4u", .data = &mt8173_data}, | |
907ba6a1 | 859 | { .compatible = "mediatek,mt8183-m4u", .data = &mt8183_data}, |
0df4fabe YW |
860 | {} |
861 | }; | |
862 | ||
863 | static struct platform_driver mtk_iommu_driver = { | |
864 | .probe = mtk_iommu_probe, | |
865 | .remove = mtk_iommu_remove, | |
866 | .driver = { | |
867 | .name = "mtk-iommu", | |
e6dec923 | 868 | .of_match_table = of_match_ptr(mtk_iommu_of_ids), |
0df4fabe YW |
869 | .pm = &mtk_iommu_pm_ops, |
870 | } | |
871 | }; | |
872 | ||
e6dec923 | 873 | static int __init mtk_iommu_init(void) |
0df4fabe YW |
874 | { |
875 | int ret; | |
0df4fabe YW |
876 | |
877 | ret = platform_driver_register(&mtk_iommu_driver); | |
e6dec923 YW |
878 | if (ret != 0) |
879 | pr_err("Failed to register MTK IOMMU driver\n"); | |
0df4fabe | 880 | |
e6dec923 | 881 | return ret; |
0df4fabe YW |
882 | } |
883 | ||
e6dec923 | 884 | subsys_initcall(mtk_iommu_init) |