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Commit | Line | Data |
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1802d0be | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
9ca340c9 HZ |
2 | /* |
3 | * Copyright (c) 2015-2016 MediaTek Inc. | |
4 | * Author: Honghui Zhang <honghui.zhang@mediatek.com> | |
9ca340c9 HZ |
5 | */ |
6 | ||
7 | #ifndef _MTK_IOMMU_H_ | |
8 | #define _MTK_IOMMU_H_ | |
9 | ||
10 | #include <linux/clk.h> | |
11 | #include <linux/component.h> | |
12 | #include <linux/device.h> | |
13 | #include <linux/io.h> | |
b77cf11f | 14 | #include <linux/io-pgtable.h> |
9ca340c9 HZ |
15 | #include <linux/iommu.h> |
16 | #include <linux/list.h> | |
17 | #include <linux/spinlock.h> | |
397e18b4 | 18 | #include <linux/dma-mapping.h> |
9ca340c9 | 19 | #include <soc/mediatek/smi.h> |
66a28915 | 20 | #include <dt-bindings/memory/mtk-memory-port.h> |
9ca340c9 | 21 | |
37276e00 CH |
22 | #define MTK_LARB_COM_MAX 8 |
23 | #define MTK_LARB_SUBCOM_MAX 4 | |
24 | ||
c3045f39 YW |
25 | #define MTK_IOMMU_GROUP_MAX 8 |
26 | ||
9ca340c9 | 27 | struct mtk_iommu_suspend_reg { |
75eed350 CH |
28 | union { |
29 | u32 standard_axi_mode;/* v1 */ | |
30 | u32 misc_ctrl;/* v2 */ | |
31 | }; | |
9ca340c9 HZ |
32 | u32 dcm_dis; |
33 | u32 ctrl_reg; | |
34 | u32 int_control0; | |
35 | u32 int_main_control; | |
70ca608b | 36 | u32 ivrp_paddr; |
b9475b34 | 37 | u32 vld_pa_rng; |
35c1b48d | 38 | u32 wr_len_ctrl; |
9ca340c9 HZ |
39 | }; |
40 | ||
e6dec923 YW |
41 | enum mtk_iommu_plat { |
42 | M4U_MT2701, | |
43 | M4U_MT2712, | |
068c86e9 | 44 | M4U_MT6779, |
3c213562 | 45 | M4U_MT8167, |
e6dec923 | 46 | M4U_MT8173, |
907ba6a1 | 47 | M4U_MT8183, |
9e3489e0 | 48 | M4U_MT8192, |
e6dec923 YW |
49 | }; |
50 | ||
585e58f4 YW |
51 | struct mtk_iommu_iova_region; |
52 | ||
cecdce9d YW |
53 | struct mtk_iommu_plat_data { |
54 | enum mtk_iommu_plat m4u_plat; | |
6b717796 | 55 | u32 flags; |
b053bc71 | 56 | u32 inv_sel_reg; |
585e58f4 YW |
57 | |
58 | unsigned int iova_region_nr; | |
59 | const struct mtk_iommu_iova_region *iova_region; | |
37276e00 | 60 | unsigned char larbid_remap[MTK_LARB_COM_MAX][MTK_LARB_SUBCOM_MAX]; |
cecdce9d YW |
61 | }; |
62 | ||
9ca340c9 HZ |
63 | struct mtk_iommu_domain; |
64 | ||
65 | struct mtk_iommu_data { | |
66 | void __iomem *base; | |
67 | int irq; | |
68 | struct device *dev; | |
69 | struct clk *bclk; | |
70 | phys_addr_t protect_base; /* protect memory base */ | |
71 | struct mtk_iommu_suspend_reg reg; | |
72 | struct mtk_iommu_domain *m4u_dom; | |
c3045f39 | 73 | struct iommu_group *m4u_group[MTK_IOMMU_GROUP_MAX]; |
9ca340c9 | 74 | bool enable_4GB; |
da3cc91b | 75 | spinlock_t tlb_lock; /* lock for tlb range flush */ |
b16c0170 JR |
76 | |
77 | struct iommu_device iommu; | |
cecdce9d | 78 | const struct mtk_iommu_plat_data *plat_data; |
baf94e6e | 79 | struct device *smicomm_dev; |
7c3a2ec0 | 80 | |
58960172 JR |
81 | struct dma_iommu_mapping *mapping; /* For mtk_iommu_v1.c */ |
82 | ||
7c3a2ec0 | 83 | struct list_head list; |
1ee9feb2 | 84 | struct mtk_smi_larb_iommu larb_imu[MTK_LARB_NR_MAX]; |
9ca340c9 HZ |
85 | }; |
86 | ||
9a8a5dcf | 87 | static inline int compare_of(struct device *dev, void *data) |
9ca340c9 HZ |
88 | { |
89 | return dev->of_node == data; | |
90 | } | |
91 | ||
00c7c81f RK |
92 | static inline void release_of(struct device *dev, void *data) |
93 | { | |
94 | of_node_put(data); | |
95 | } | |
96 | ||
9a8a5dcf | 97 | static inline int mtk_iommu_bind(struct device *dev) |
9ca340c9 HZ |
98 | { |
99 | struct mtk_iommu_data *data = dev_get_drvdata(dev); | |
100 | ||
1ee9feb2 | 101 | return component_bind_all(dev, &data->larb_imu); |
9ca340c9 HZ |
102 | } |
103 | ||
9a8a5dcf | 104 | static inline void mtk_iommu_unbind(struct device *dev) |
9ca340c9 HZ |
105 | { |
106 | struct mtk_iommu_data *data = dev_get_drvdata(dev); | |
107 | ||
1ee9feb2 | 108 | component_unbind_all(dev, &data->larb_imu); |
9ca340c9 HZ |
109 | } |
110 | ||
111 | #endif |