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Commit | Line | Data |
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a9dcad5e HD |
1 | /* |
2 | * omap iommu: tlb and pagetable primitives | |
3 | * | |
c127c7dc | 4 | * Copyright (C) 2008-2010 Nokia Corporation |
a9dcad5e HD |
5 | * |
6 | * Written by Hiroshi DOYU <Hiroshi.DOYU@nokia.com>, | |
7 | * Paul Mundt and Toshihiro Kobayashi | |
8 | * | |
9 | * This program is free software; you can redistribute it and/or modify | |
10 | * it under the terms of the GNU General Public License version 2 as | |
11 | * published by the Free Software Foundation. | |
12 | */ | |
13 | ||
14 | #include <linux/err.h> | |
15 | #include <linux/module.h> | |
5a0e3ad6 | 16 | #include <linux/slab.h> |
a9dcad5e HD |
17 | #include <linux/interrupt.h> |
18 | #include <linux/ioport.h> | |
a9dcad5e | 19 | #include <linux/platform_device.h> |
f626b52d | 20 | #include <linux/iommu.h> |
c8d35c84 | 21 | #include <linux/omap-iommu.h> |
f626b52d OBC |
22 | #include <linux/mutex.h> |
23 | #include <linux/spinlock.h> | |
ed1c7de2 | 24 | #include <linux/io.h> |
ebf7cda0 | 25 | #include <linux/pm_runtime.h> |
a9dcad5e HD |
26 | |
27 | #include <asm/cacheflush.h> | |
28 | ||
2ab7c848 | 29 | #include <linux/platform_data/iommu-omap.h> |
a9dcad5e | 30 | |
2f7702af | 31 | #include "omap-iopgtable.h" |
ed1c7de2 | 32 | #include "omap-iommu.h" |
a9dcad5e | 33 | |
37c2836c HD |
34 | #define for_each_iotlb_cr(obj, n, __i, cr) \ |
35 | for (__i = 0; \ | |
36 | (__i < (n)) && (cr = __iotlb_read_cr((obj), __i), true); \ | |
37 | __i++) | |
38 | ||
66bc8cf3 OBC |
39 | /* bitmap of the page sizes currently supported */ |
40 | #define OMAP_IOMMU_PGSIZES (SZ_4K | SZ_64K | SZ_1M | SZ_16M) | |
41 | ||
f626b52d OBC |
42 | /** |
43 | * struct omap_iommu_domain - omap iommu domain | |
44 | * @pgtable: the page table | |
45 | * @iommu_dev: an omap iommu device attached to this domain. only a single | |
46 | * iommu device can be attached for now. | |
803b5277 | 47 | * @dev: Device using this domain. |
f626b52d OBC |
48 | * @lock: domain lock, should be taken when attaching/detaching |
49 | */ | |
50 | struct omap_iommu_domain { | |
51 | u32 *pgtable; | |
6c32df43 | 52 | struct omap_iommu *iommu_dev; |
803b5277 | 53 | struct device *dev; |
f626b52d OBC |
54 | spinlock_t lock; |
55 | }; | |
56 | ||
7bd9e25f IY |
57 | #define MMU_LOCK_BASE_SHIFT 10 |
58 | #define MMU_LOCK_BASE_MASK (0x1f << MMU_LOCK_BASE_SHIFT) | |
59 | #define MMU_LOCK_BASE(x) \ | |
60 | ((x & MMU_LOCK_BASE_MASK) >> MMU_LOCK_BASE_SHIFT) | |
61 | ||
62 | #define MMU_LOCK_VICT_SHIFT 4 | |
63 | #define MMU_LOCK_VICT_MASK (0x1f << MMU_LOCK_VICT_SHIFT) | |
64 | #define MMU_LOCK_VICT(x) \ | |
65 | ((x & MMU_LOCK_VICT_MASK) >> MMU_LOCK_VICT_SHIFT) | |
66 | ||
67 | struct iotlb_lock { | |
68 | short base; | |
69 | short vict; | |
70 | }; | |
71 | ||
a9dcad5e HD |
72 | /* accommodate the difference between omap1 and omap2/3 */ |
73 | static const struct iommu_functions *arch_iommu; | |
74 | ||
75 | static struct platform_driver omap_iommu_driver; | |
76 | static struct kmem_cache *iopte_cachep; | |
77 | ||
78 | /** | |
6c32df43 | 79 | * omap_install_iommu_arch - Install archtecure specific iommu functions |
a9dcad5e HD |
80 | * @ops: a pointer to architecture specific iommu functions |
81 | * | |
82 | * There are several kind of iommu algorithm(tlb, pagetable) among | |
83 | * omap series. This interface installs such an iommu algorighm. | |
84 | **/ | |
6c32df43 | 85 | int omap_install_iommu_arch(const struct iommu_functions *ops) |
a9dcad5e HD |
86 | { |
87 | if (arch_iommu) | |
88 | return -EBUSY; | |
89 | ||
90 | arch_iommu = ops; | |
91 | return 0; | |
92 | } | |
6c32df43 | 93 | EXPORT_SYMBOL_GPL(omap_install_iommu_arch); |
a9dcad5e HD |
94 | |
95 | /** | |
6c32df43 | 96 | * omap_uninstall_iommu_arch - Uninstall archtecure specific iommu functions |
a9dcad5e HD |
97 | * @ops: a pointer to architecture specific iommu functions |
98 | * | |
99 | * This interface uninstalls the iommu algorighm installed previously. | |
100 | **/ | |
6c32df43 | 101 | void omap_uninstall_iommu_arch(const struct iommu_functions *ops) |
a9dcad5e HD |
102 | { |
103 | if (arch_iommu != ops) | |
104 | pr_err("%s: not your arch\n", __func__); | |
105 | ||
106 | arch_iommu = NULL; | |
107 | } | |
6c32df43 | 108 | EXPORT_SYMBOL_GPL(omap_uninstall_iommu_arch); |
a9dcad5e HD |
109 | |
110 | /** | |
6c32df43 | 111 | * omap_iommu_save_ctx - Save registers for pm off-mode support |
fabdbca8 | 112 | * @dev: client device |
a9dcad5e | 113 | **/ |
fabdbca8 | 114 | void omap_iommu_save_ctx(struct device *dev) |
a9dcad5e | 115 | { |
fabdbca8 OBC |
116 | struct omap_iommu *obj = dev_to_omap_iommu(dev); |
117 | ||
a9dcad5e HD |
118 | arch_iommu->save_ctx(obj); |
119 | } | |
6c32df43 | 120 | EXPORT_SYMBOL_GPL(omap_iommu_save_ctx); |
a9dcad5e HD |
121 | |
122 | /** | |
6c32df43 | 123 | * omap_iommu_restore_ctx - Restore registers for pm off-mode support |
fabdbca8 | 124 | * @dev: client device |
a9dcad5e | 125 | **/ |
fabdbca8 | 126 | void omap_iommu_restore_ctx(struct device *dev) |
a9dcad5e | 127 | { |
fabdbca8 OBC |
128 | struct omap_iommu *obj = dev_to_omap_iommu(dev); |
129 | ||
a9dcad5e HD |
130 | arch_iommu->restore_ctx(obj); |
131 | } | |
6c32df43 | 132 | EXPORT_SYMBOL_GPL(omap_iommu_restore_ctx); |
a9dcad5e HD |
133 | |
134 | /** | |
6c32df43 | 135 | * omap_iommu_arch_version - Return running iommu arch version |
a9dcad5e | 136 | **/ |
6c32df43 | 137 | u32 omap_iommu_arch_version(void) |
a9dcad5e HD |
138 | { |
139 | return arch_iommu->version; | |
140 | } | |
6c32df43 | 141 | EXPORT_SYMBOL_GPL(omap_iommu_arch_version); |
a9dcad5e | 142 | |
6c32df43 | 143 | static int iommu_enable(struct omap_iommu *obj) |
a9dcad5e HD |
144 | { |
145 | int err; | |
72b15b6a ORL |
146 | struct platform_device *pdev = to_platform_device(obj->dev); |
147 | struct iommu_platform_data *pdata = pdev->dev.platform_data; | |
a9dcad5e | 148 | |
0af125ca | 149 | if (!pdata) |
a9dcad5e HD |
150 | return -EINVAL; |
151 | ||
ef4815ab MH |
152 | if (!arch_iommu) |
153 | return -ENODEV; | |
154 | ||
72b15b6a ORL |
155 | if (pdata->deassert_reset) { |
156 | err = pdata->deassert_reset(pdev, pdata->reset_name); | |
157 | if (err) { | |
158 | dev_err(obj->dev, "deassert_reset failed: %d\n", err); | |
159 | return err; | |
160 | } | |
161 | } | |
162 | ||
ebf7cda0 | 163 | pm_runtime_get_sync(obj->dev); |
a9dcad5e HD |
164 | |
165 | err = arch_iommu->enable(obj); | |
166 | ||
a9dcad5e HD |
167 | return err; |
168 | } | |
169 | ||
6c32df43 | 170 | static void iommu_disable(struct omap_iommu *obj) |
a9dcad5e | 171 | { |
72b15b6a ORL |
172 | struct platform_device *pdev = to_platform_device(obj->dev); |
173 | struct iommu_platform_data *pdata = pdev->dev.platform_data; | |
174 | ||
0af125ca | 175 | if (!pdata) |
a9dcad5e HD |
176 | return; |
177 | ||
a9dcad5e HD |
178 | arch_iommu->disable(obj); |
179 | ||
ebf7cda0 | 180 | pm_runtime_put_sync(obj->dev); |
72b15b6a ORL |
181 | |
182 | if (pdata->assert_reset) | |
183 | pdata->assert_reset(pdev, pdata->reset_name); | |
a9dcad5e HD |
184 | } |
185 | ||
186 | /* | |
187 | * TLB operations | |
188 | */ | |
6c32df43 | 189 | void omap_iotlb_cr_to_e(struct cr_regs *cr, struct iotlb_entry *e) |
a9dcad5e HD |
190 | { |
191 | BUG_ON(!cr || !e); | |
192 | ||
193 | arch_iommu->cr_to_e(cr, e); | |
194 | } | |
6c32df43 | 195 | EXPORT_SYMBOL_GPL(omap_iotlb_cr_to_e); |
a9dcad5e HD |
196 | |
197 | static inline int iotlb_cr_valid(struct cr_regs *cr) | |
198 | { | |
199 | if (!cr) | |
200 | return -EINVAL; | |
201 | ||
202 | return arch_iommu->cr_valid(cr); | |
203 | } | |
204 | ||
6c32df43 | 205 | static inline struct cr_regs *iotlb_alloc_cr(struct omap_iommu *obj, |
a9dcad5e HD |
206 | struct iotlb_entry *e) |
207 | { | |
208 | if (!e) | |
209 | return NULL; | |
210 | ||
211 | return arch_iommu->alloc_cr(obj, e); | |
212 | } | |
213 | ||
e1f23813 | 214 | static u32 iotlb_cr_to_virt(struct cr_regs *cr) |
a9dcad5e HD |
215 | { |
216 | return arch_iommu->cr_to_virt(cr); | |
217 | } | |
a9dcad5e HD |
218 | |
219 | static u32 get_iopte_attr(struct iotlb_entry *e) | |
220 | { | |
221 | return arch_iommu->get_pte_attr(e); | |
222 | } | |
223 | ||
6c32df43 | 224 | static u32 iommu_report_fault(struct omap_iommu *obj, u32 *da) |
a9dcad5e HD |
225 | { |
226 | return arch_iommu->fault_isr(obj, da); | |
227 | } | |
228 | ||
6c32df43 | 229 | static void iotlb_lock_get(struct omap_iommu *obj, struct iotlb_lock *l) |
a9dcad5e HD |
230 | { |
231 | u32 val; | |
232 | ||
233 | val = iommu_read_reg(obj, MMU_LOCK); | |
234 | ||
235 | l->base = MMU_LOCK_BASE(val); | |
236 | l->vict = MMU_LOCK_VICT(val); | |
237 | ||
a9dcad5e HD |
238 | } |
239 | ||
6c32df43 | 240 | static void iotlb_lock_set(struct omap_iommu *obj, struct iotlb_lock *l) |
a9dcad5e HD |
241 | { |
242 | u32 val; | |
243 | ||
a9dcad5e HD |
244 | val = (l->base << MMU_LOCK_BASE_SHIFT); |
245 | val |= (l->vict << MMU_LOCK_VICT_SHIFT); | |
246 | ||
247 | iommu_write_reg(obj, val, MMU_LOCK); | |
248 | } | |
249 | ||
6c32df43 | 250 | static void iotlb_read_cr(struct omap_iommu *obj, struct cr_regs *cr) |
a9dcad5e HD |
251 | { |
252 | arch_iommu->tlb_read_cr(obj, cr); | |
253 | } | |
254 | ||
6c32df43 | 255 | static void iotlb_load_cr(struct omap_iommu *obj, struct cr_regs *cr) |
a9dcad5e HD |
256 | { |
257 | arch_iommu->tlb_load_cr(obj, cr); | |
258 | ||
259 | iommu_write_reg(obj, 1, MMU_FLUSH_ENTRY); | |
260 | iommu_write_reg(obj, 1, MMU_LD_TLB); | |
261 | } | |
262 | ||
263 | /** | |
264 | * iotlb_dump_cr - Dump an iommu tlb entry into buf | |
265 | * @obj: target iommu | |
266 | * @cr: contents of cam and ram register | |
267 | * @buf: output buffer | |
268 | **/ | |
6c32df43 | 269 | static inline ssize_t iotlb_dump_cr(struct omap_iommu *obj, struct cr_regs *cr, |
a9dcad5e HD |
270 | char *buf) |
271 | { | |
272 | BUG_ON(!cr || !buf); | |
273 | ||
274 | return arch_iommu->dump_cr(obj, cr, buf); | |
275 | } | |
276 | ||
37c2836c | 277 | /* only used in iotlb iteration for-loop */ |
6c32df43 | 278 | static struct cr_regs __iotlb_read_cr(struct omap_iommu *obj, int n) |
37c2836c HD |
279 | { |
280 | struct cr_regs cr; | |
281 | struct iotlb_lock l; | |
282 | ||
283 | iotlb_lock_get(obj, &l); | |
284 | l.vict = n; | |
285 | iotlb_lock_set(obj, &l); | |
286 | iotlb_read_cr(obj, &cr); | |
287 | ||
288 | return cr; | |
289 | } | |
290 | ||
a9dcad5e HD |
291 | /** |
292 | * load_iotlb_entry - Set an iommu tlb entry | |
293 | * @obj: target iommu | |
294 | * @e: an iommu tlb entry info | |
295 | **/ | |
5da14a47 | 296 | #ifdef PREFETCH_IOTLB |
6c32df43 | 297 | static int load_iotlb_entry(struct omap_iommu *obj, struct iotlb_entry *e) |
a9dcad5e | 298 | { |
a9dcad5e HD |
299 | int err = 0; |
300 | struct iotlb_lock l; | |
301 | struct cr_regs *cr; | |
302 | ||
303 | if (!obj || !obj->nr_tlb_entries || !e) | |
304 | return -EINVAL; | |
305 | ||
ebf7cda0 | 306 | pm_runtime_get_sync(obj->dev); |
a9dcad5e | 307 | |
be6d8026 KH |
308 | iotlb_lock_get(obj, &l); |
309 | if (l.base == obj->nr_tlb_entries) { | |
310 | dev_warn(obj->dev, "%s: preserve entries full\n", __func__); | |
a9dcad5e HD |
311 | err = -EBUSY; |
312 | goto out; | |
313 | } | |
be6d8026 | 314 | if (!e->prsvd) { |
37c2836c HD |
315 | int i; |
316 | struct cr_regs tmp; | |
be6d8026 | 317 | |
37c2836c | 318 | for_each_iotlb_cr(obj, obj->nr_tlb_entries, i, tmp) |
be6d8026 KH |
319 | if (!iotlb_cr_valid(&tmp)) |
320 | break; | |
37c2836c | 321 | |
be6d8026 KH |
322 | if (i == obj->nr_tlb_entries) { |
323 | dev_dbg(obj->dev, "%s: full: no entry\n", __func__); | |
324 | err = -EBUSY; | |
325 | goto out; | |
326 | } | |
37c2836c HD |
327 | |
328 | iotlb_lock_get(obj, &l); | |
be6d8026 KH |
329 | } else { |
330 | l.vict = l.base; | |
331 | iotlb_lock_set(obj, &l); | |
332 | } | |
a9dcad5e HD |
333 | |
334 | cr = iotlb_alloc_cr(obj, e); | |
335 | if (IS_ERR(cr)) { | |
ebf7cda0 | 336 | pm_runtime_put_sync(obj->dev); |
a9dcad5e HD |
337 | return PTR_ERR(cr); |
338 | } | |
339 | ||
340 | iotlb_load_cr(obj, cr); | |
341 | kfree(cr); | |
342 | ||
be6d8026 KH |
343 | if (e->prsvd) |
344 | l.base++; | |
a9dcad5e HD |
345 | /* increment victim for next tlb load */ |
346 | if (++l.vict == obj->nr_tlb_entries) | |
be6d8026 | 347 | l.vict = l.base; |
a9dcad5e HD |
348 | iotlb_lock_set(obj, &l); |
349 | out: | |
ebf7cda0 | 350 | pm_runtime_put_sync(obj->dev); |
a9dcad5e HD |
351 | return err; |
352 | } | |
a9dcad5e | 353 | |
5da14a47 OBC |
354 | #else /* !PREFETCH_IOTLB */ |
355 | ||
6c32df43 | 356 | static int load_iotlb_entry(struct omap_iommu *obj, struct iotlb_entry *e) |
5da14a47 OBC |
357 | { |
358 | return 0; | |
359 | } | |
360 | ||
361 | #endif /* !PREFETCH_IOTLB */ | |
362 | ||
6c32df43 | 363 | static int prefetch_iotlb_entry(struct omap_iommu *obj, struct iotlb_entry *e) |
5da14a47 OBC |
364 | { |
365 | return load_iotlb_entry(obj, e); | |
366 | } | |
a9dcad5e HD |
367 | |
368 | /** | |
369 | * flush_iotlb_page - Clear an iommu tlb entry | |
370 | * @obj: target iommu | |
371 | * @da: iommu device virtual address | |
372 | * | |
373 | * Clear an iommu tlb entry which includes 'da' address. | |
374 | **/ | |
6c32df43 | 375 | static void flush_iotlb_page(struct omap_iommu *obj, u32 da) |
a9dcad5e | 376 | { |
a9dcad5e | 377 | int i; |
37c2836c | 378 | struct cr_regs cr; |
a9dcad5e | 379 | |
ebf7cda0 | 380 | pm_runtime_get_sync(obj->dev); |
a9dcad5e | 381 | |
37c2836c | 382 | for_each_iotlb_cr(obj, obj->nr_tlb_entries, i, cr) { |
a9dcad5e HD |
383 | u32 start; |
384 | size_t bytes; | |
385 | ||
a9dcad5e HD |
386 | if (!iotlb_cr_valid(&cr)) |
387 | continue; | |
388 | ||
389 | start = iotlb_cr_to_virt(&cr); | |
390 | bytes = iopgsz_to_bytes(cr.cam & 3); | |
391 | ||
392 | if ((start <= da) && (da < start + bytes)) { | |
393 | dev_dbg(obj->dev, "%s: %08x<=%08x(%x)\n", | |
394 | __func__, start, da, bytes); | |
0fa035e5 | 395 | iotlb_load_cr(obj, &cr); |
a9dcad5e HD |
396 | iommu_write_reg(obj, 1, MMU_FLUSH_ENTRY); |
397 | } | |
398 | } | |
ebf7cda0 | 399 | pm_runtime_put_sync(obj->dev); |
a9dcad5e HD |
400 | |
401 | if (i == obj->nr_tlb_entries) | |
402 | dev_dbg(obj->dev, "%s: no page for %08x\n", __func__, da); | |
403 | } | |
a9dcad5e HD |
404 | |
405 | /** | |
406 | * flush_iotlb_all - Clear all iommu tlb entries | |
407 | * @obj: target iommu | |
408 | **/ | |
6c32df43 | 409 | static void flush_iotlb_all(struct omap_iommu *obj) |
a9dcad5e HD |
410 | { |
411 | struct iotlb_lock l; | |
412 | ||
ebf7cda0 | 413 | pm_runtime_get_sync(obj->dev); |
a9dcad5e HD |
414 | |
415 | l.base = 0; | |
416 | l.vict = 0; | |
417 | iotlb_lock_set(obj, &l); | |
418 | ||
419 | iommu_write_reg(obj, 1, MMU_GFLUSH); | |
420 | ||
ebf7cda0 | 421 | pm_runtime_put_sync(obj->dev); |
a9dcad5e | 422 | } |
ddfa975a | 423 | |
e4efd94b | 424 | #if defined(CONFIG_OMAP_IOMMU_DEBUG) || defined(CONFIG_OMAP_IOMMU_DEBUG_MODULE) |
a9dcad5e | 425 | |
6c32df43 | 426 | ssize_t omap_iommu_dump_ctx(struct omap_iommu *obj, char *buf, ssize_t bytes) |
a9dcad5e | 427 | { |
a9dcad5e HD |
428 | if (!obj || !buf) |
429 | return -EINVAL; | |
430 | ||
ebf7cda0 | 431 | pm_runtime_get_sync(obj->dev); |
a9dcad5e | 432 | |
14e0e679 | 433 | bytes = arch_iommu->dump_ctx(obj, buf, bytes); |
a9dcad5e | 434 | |
ebf7cda0 | 435 | pm_runtime_put_sync(obj->dev); |
a9dcad5e HD |
436 | |
437 | return bytes; | |
438 | } | |
6c32df43 | 439 | EXPORT_SYMBOL_GPL(omap_iommu_dump_ctx); |
a9dcad5e | 440 | |
6c32df43 OBC |
441 | static int |
442 | __dump_tlb_entries(struct omap_iommu *obj, struct cr_regs *crs, int num) | |
a9dcad5e HD |
443 | { |
444 | int i; | |
37c2836c HD |
445 | struct iotlb_lock saved; |
446 | struct cr_regs tmp; | |
a9dcad5e HD |
447 | struct cr_regs *p = crs; |
448 | ||
ebf7cda0 | 449 | pm_runtime_get_sync(obj->dev); |
a9dcad5e | 450 | iotlb_lock_get(obj, &saved); |
a9dcad5e | 451 | |
37c2836c | 452 | for_each_iotlb_cr(obj, num, i, tmp) { |
a9dcad5e HD |
453 | if (!iotlb_cr_valid(&tmp)) |
454 | continue; | |
a9dcad5e HD |
455 | *p++ = tmp; |
456 | } | |
37c2836c | 457 | |
a9dcad5e | 458 | iotlb_lock_set(obj, &saved); |
ebf7cda0 | 459 | pm_runtime_put_sync(obj->dev); |
a9dcad5e HD |
460 | |
461 | return p - crs; | |
462 | } | |
463 | ||
464 | /** | |
6c32df43 | 465 | * omap_dump_tlb_entries - dump cr arrays to given buffer |
a9dcad5e HD |
466 | * @obj: target iommu |
467 | * @buf: output buffer | |
468 | **/ | |
6c32df43 | 469 | size_t omap_dump_tlb_entries(struct omap_iommu *obj, char *buf, ssize_t bytes) |
a9dcad5e | 470 | { |
14e0e679 | 471 | int i, num; |
a9dcad5e HD |
472 | struct cr_regs *cr; |
473 | char *p = buf; | |
474 | ||
14e0e679 HD |
475 | num = bytes / sizeof(*cr); |
476 | num = min(obj->nr_tlb_entries, num); | |
477 | ||
478 | cr = kcalloc(num, sizeof(*cr), GFP_KERNEL); | |
a9dcad5e HD |
479 | if (!cr) |
480 | return 0; | |
481 | ||
14e0e679 HD |
482 | num = __dump_tlb_entries(obj, cr, num); |
483 | for (i = 0; i < num; i++) | |
a9dcad5e HD |
484 | p += iotlb_dump_cr(obj, cr + i, p); |
485 | kfree(cr); | |
486 | ||
487 | return p - buf; | |
488 | } | |
6c32df43 | 489 | EXPORT_SYMBOL_GPL(omap_dump_tlb_entries); |
a9dcad5e | 490 | |
6c32df43 | 491 | int omap_foreach_iommu_device(void *data, int (*fn)(struct device *, void *)) |
a9dcad5e HD |
492 | { |
493 | return driver_for_each_device(&omap_iommu_driver.driver, | |
494 | NULL, data, fn); | |
495 | } | |
6c32df43 | 496 | EXPORT_SYMBOL_GPL(omap_foreach_iommu_device); |
a9dcad5e HD |
497 | |
498 | #endif /* CONFIG_OMAP_IOMMU_DEBUG_MODULE */ | |
499 | ||
500 | /* | |
501 | * H/W pagetable operations | |
502 | */ | |
503 | static void flush_iopgd_range(u32 *first, u32 *last) | |
504 | { | |
505 | /* FIXME: L2 cache should be taken care of if it exists */ | |
506 | do { | |
507 | asm("mcr p15, 0, %0, c7, c10, 1 @ flush_pgd" | |
508 | : : "r" (first)); | |
509 | first += L1_CACHE_BYTES / sizeof(*first); | |
510 | } while (first <= last); | |
511 | } | |
512 | ||
513 | static void flush_iopte_range(u32 *first, u32 *last) | |
514 | { | |
515 | /* FIXME: L2 cache should be taken care of if it exists */ | |
516 | do { | |
517 | asm("mcr p15, 0, %0, c7, c10, 1 @ flush_pte" | |
518 | : : "r" (first)); | |
519 | first += L1_CACHE_BYTES / sizeof(*first); | |
520 | } while (first <= last); | |
521 | } | |
522 | ||
523 | static void iopte_free(u32 *iopte) | |
524 | { | |
525 | /* Note: freed iopte's must be clean ready for re-use */ | |
526 | kmem_cache_free(iopte_cachep, iopte); | |
527 | } | |
528 | ||
6c32df43 | 529 | static u32 *iopte_alloc(struct omap_iommu *obj, u32 *iopgd, u32 da) |
a9dcad5e HD |
530 | { |
531 | u32 *iopte; | |
532 | ||
533 | /* a table has already existed */ | |
534 | if (*iopgd) | |
535 | goto pte_ready; | |
536 | ||
537 | /* | |
538 | * do the allocation outside the page table lock | |
539 | */ | |
540 | spin_unlock(&obj->page_table_lock); | |
541 | iopte = kmem_cache_zalloc(iopte_cachep, GFP_KERNEL); | |
542 | spin_lock(&obj->page_table_lock); | |
543 | ||
544 | if (!*iopgd) { | |
545 | if (!iopte) | |
546 | return ERR_PTR(-ENOMEM); | |
547 | ||
548 | *iopgd = virt_to_phys(iopte) | IOPGD_TABLE; | |
549 | flush_iopgd_range(iopgd, iopgd); | |
550 | ||
551 | dev_vdbg(obj->dev, "%s: a new pte:%p\n", __func__, iopte); | |
552 | } else { | |
553 | /* We raced, free the reduniovant table */ | |
554 | iopte_free(iopte); | |
555 | } | |
556 | ||
557 | pte_ready: | |
558 | iopte = iopte_offset(iopgd, da); | |
559 | ||
560 | dev_vdbg(obj->dev, | |
561 | "%s: da:%08x pgd:%p *pgd:%08x pte:%p *pte:%08x\n", | |
562 | __func__, da, iopgd, *iopgd, iopte, *iopte); | |
563 | ||
564 | return iopte; | |
565 | } | |
566 | ||
6c32df43 | 567 | static int iopgd_alloc_section(struct omap_iommu *obj, u32 da, u32 pa, u32 prot) |
a9dcad5e HD |
568 | { |
569 | u32 *iopgd = iopgd_offset(obj, da); | |
570 | ||
4abb7617 HD |
571 | if ((da | pa) & ~IOSECTION_MASK) { |
572 | dev_err(obj->dev, "%s: %08x:%08x should aligned on %08lx\n", | |
573 | __func__, da, pa, IOSECTION_SIZE); | |
574 | return -EINVAL; | |
575 | } | |
576 | ||
a9dcad5e HD |
577 | *iopgd = (pa & IOSECTION_MASK) | prot | IOPGD_SECTION; |
578 | flush_iopgd_range(iopgd, iopgd); | |
579 | return 0; | |
580 | } | |
581 | ||
6c32df43 | 582 | static int iopgd_alloc_super(struct omap_iommu *obj, u32 da, u32 pa, u32 prot) |
a9dcad5e HD |
583 | { |
584 | u32 *iopgd = iopgd_offset(obj, da); | |
585 | int i; | |
586 | ||
4abb7617 HD |
587 | if ((da | pa) & ~IOSUPER_MASK) { |
588 | dev_err(obj->dev, "%s: %08x:%08x should aligned on %08lx\n", | |
589 | __func__, da, pa, IOSUPER_SIZE); | |
590 | return -EINVAL; | |
591 | } | |
592 | ||
a9dcad5e HD |
593 | for (i = 0; i < 16; i++) |
594 | *(iopgd + i) = (pa & IOSUPER_MASK) | prot | IOPGD_SUPER; | |
595 | flush_iopgd_range(iopgd, iopgd + 15); | |
596 | return 0; | |
597 | } | |
598 | ||
6c32df43 | 599 | static int iopte_alloc_page(struct omap_iommu *obj, u32 da, u32 pa, u32 prot) |
a9dcad5e HD |
600 | { |
601 | u32 *iopgd = iopgd_offset(obj, da); | |
602 | u32 *iopte = iopte_alloc(obj, iopgd, da); | |
603 | ||
604 | if (IS_ERR(iopte)) | |
605 | return PTR_ERR(iopte); | |
606 | ||
607 | *iopte = (pa & IOPAGE_MASK) | prot | IOPTE_SMALL; | |
608 | flush_iopte_range(iopte, iopte); | |
609 | ||
610 | dev_vdbg(obj->dev, "%s: da:%08x pa:%08x pte:%p *pte:%08x\n", | |
611 | __func__, da, pa, iopte, *iopte); | |
612 | ||
613 | return 0; | |
614 | } | |
615 | ||
6c32df43 | 616 | static int iopte_alloc_large(struct omap_iommu *obj, u32 da, u32 pa, u32 prot) |
a9dcad5e HD |
617 | { |
618 | u32 *iopgd = iopgd_offset(obj, da); | |
619 | u32 *iopte = iopte_alloc(obj, iopgd, da); | |
620 | int i; | |
621 | ||
4abb7617 HD |
622 | if ((da | pa) & ~IOLARGE_MASK) { |
623 | dev_err(obj->dev, "%s: %08x:%08x should aligned on %08lx\n", | |
624 | __func__, da, pa, IOLARGE_SIZE); | |
625 | return -EINVAL; | |
626 | } | |
627 | ||
a9dcad5e HD |
628 | if (IS_ERR(iopte)) |
629 | return PTR_ERR(iopte); | |
630 | ||
631 | for (i = 0; i < 16; i++) | |
632 | *(iopte + i) = (pa & IOLARGE_MASK) | prot | IOPTE_LARGE; | |
633 | flush_iopte_range(iopte, iopte + 15); | |
634 | return 0; | |
635 | } | |
636 | ||
6c32df43 OBC |
637 | static int |
638 | iopgtable_store_entry_core(struct omap_iommu *obj, struct iotlb_entry *e) | |
a9dcad5e | 639 | { |
6c32df43 | 640 | int (*fn)(struct omap_iommu *, u32, u32, u32); |
a9dcad5e HD |
641 | u32 prot; |
642 | int err; | |
643 | ||
644 | if (!obj || !e) | |
645 | return -EINVAL; | |
646 | ||
647 | switch (e->pgsz) { | |
648 | case MMU_CAM_PGSZ_16M: | |
649 | fn = iopgd_alloc_super; | |
650 | break; | |
651 | case MMU_CAM_PGSZ_1M: | |
652 | fn = iopgd_alloc_section; | |
653 | break; | |
654 | case MMU_CAM_PGSZ_64K: | |
655 | fn = iopte_alloc_large; | |
656 | break; | |
657 | case MMU_CAM_PGSZ_4K: | |
658 | fn = iopte_alloc_page; | |
659 | break; | |
660 | default: | |
661 | fn = NULL; | |
662 | BUG(); | |
663 | break; | |
664 | } | |
665 | ||
666 | prot = get_iopte_attr(e); | |
667 | ||
668 | spin_lock(&obj->page_table_lock); | |
669 | err = fn(obj, e->da, e->pa, prot); | |
670 | spin_unlock(&obj->page_table_lock); | |
671 | ||
672 | return err; | |
673 | } | |
674 | ||
675 | /** | |
6c32df43 | 676 | * omap_iopgtable_store_entry - Make an iommu pte entry |
a9dcad5e HD |
677 | * @obj: target iommu |
678 | * @e: an iommu tlb entry info | |
679 | **/ | |
6c32df43 | 680 | int omap_iopgtable_store_entry(struct omap_iommu *obj, struct iotlb_entry *e) |
a9dcad5e HD |
681 | { |
682 | int err; | |
683 | ||
684 | flush_iotlb_page(obj, e->da); | |
685 | err = iopgtable_store_entry_core(obj, e); | |
a9dcad5e | 686 | if (!err) |
5da14a47 | 687 | prefetch_iotlb_entry(obj, e); |
a9dcad5e HD |
688 | return err; |
689 | } | |
6c32df43 | 690 | EXPORT_SYMBOL_GPL(omap_iopgtable_store_entry); |
a9dcad5e HD |
691 | |
692 | /** | |
693 | * iopgtable_lookup_entry - Lookup an iommu pte entry | |
694 | * @obj: target iommu | |
695 | * @da: iommu device virtual address | |
696 | * @ppgd: iommu pgd entry pointer to be returned | |
697 | * @ppte: iommu pte entry pointer to be returned | |
698 | **/ | |
e1f23813 OBC |
699 | static void |
700 | iopgtable_lookup_entry(struct omap_iommu *obj, u32 da, u32 **ppgd, u32 **ppte) | |
a9dcad5e HD |
701 | { |
702 | u32 *iopgd, *iopte = NULL; | |
703 | ||
704 | iopgd = iopgd_offset(obj, da); | |
705 | if (!*iopgd) | |
706 | goto out; | |
707 | ||
a1a54456 | 708 | if (iopgd_is_table(*iopgd)) |
a9dcad5e HD |
709 | iopte = iopte_offset(iopgd, da); |
710 | out: | |
711 | *ppgd = iopgd; | |
712 | *ppte = iopte; | |
713 | } | |
a9dcad5e | 714 | |
6c32df43 | 715 | static size_t iopgtable_clear_entry_core(struct omap_iommu *obj, u32 da) |
a9dcad5e HD |
716 | { |
717 | size_t bytes; | |
718 | u32 *iopgd = iopgd_offset(obj, da); | |
719 | int nent = 1; | |
720 | ||
721 | if (!*iopgd) | |
722 | return 0; | |
723 | ||
a1a54456 | 724 | if (iopgd_is_table(*iopgd)) { |
a9dcad5e HD |
725 | int i; |
726 | u32 *iopte = iopte_offset(iopgd, da); | |
727 | ||
728 | bytes = IOPTE_SIZE; | |
729 | if (*iopte & IOPTE_LARGE) { | |
730 | nent *= 16; | |
731 | /* rewind to the 1st entry */ | |
c127c7dc | 732 | iopte = iopte_offset(iopgd, (da & IOLARGE_MASK)); |
a9dcad5e HD |
733 | } |
734 | bytes *= nent; | |
735 | memset(iopte, 0, nent * sizeof(*iopte)); | |
736 | flush_iopte_range(iopte, iopte + (nent - 1) * sizeof(*iopte)); | |
737 | ||
738 | /* | |
739 | * do table walk to check if this table is necessary or not | |
740 | */ | |
741 | iopte = iopte_offset(iopgd, 0); | |
742 | for (i = 0; i < PTRS_PER_IOPTE; i++) | |
743 | if (iopte[i]) | |
744 | goto out; | |
745 | ||
746 | iopte_free(iopte); | |
747 | nent = 1; /* for the next L1 entry */ | |
748 | } else { | |
749 | bytes = IOPGD_SIZE; | |
dcc730dc | 750 | if ((*iopgd & IOPGD_SUPER) == IOPGD_SUPER) { |
a9dcad5e HD |
751 | nent *= 16; |
752 | /* rewind to the 1st entry */ | |
8d33ea58 | 753 | iopgd = iopgd_offset(obj, (da & IOSUPER_MASK)); |
a9dcad5e HD |
754 | } |
755 | bytes *= nent; | |
756 | } | |
757 | memset(iopgd, 0, nent * sizeof(*iopgd)); | |
758 | flush_iopgd_range(iopgd, iopgd + (nent - 1) * sizeof(*iopgd)); | |
759 | out: | |
760 | return bytes; | |
761 | } | |
762 | ||
763 | /** | |
764 | * iopgtable_clear_entry - Remove an iommu pte entry | |
765 | * @obj: target iommu | |
766 | * @da: iommu device virtual address | |
767 | **/ | |
6c32df43 | 768 | static size_t iopgtable_clear_entry(struct omap_iommu *obj, u32 da) |
a9dcad5e HD |
769 | { |
770 | size_t bytes; | |
771 | ||
772 | spin_lock(&obj->page_table_lock); | |
773 | ||
774 | bytes = iopgtable_clear_entry_core(obj, da); | |
775 | flush_iotlb_page(obj, da); | |
776 | ||
777 | spin_unlock(&obj->page_table_lock); | |
778 | ||
779 | return bytes; | |
780 | } | |
a9dcad5e | 781 | |
6c32df43 | 782 | static void iopgtable_clear_entry_all(struct omap_iommu *obj) |
a9dcad5e HD |
783 | { |
784 | int i; | |
785 | ||
786 | spin_lock(&obj->page_table_lock); | |
787 | ||
788 | for (i = 0; i < PTRS_PER_IOPGD; i++) { | |
789 | u32 da; | |
790 | u32 *iopgd; | |
791 | ||
792 | da = i << IOPGD_SHIFT; | |
793 | iopgd = iopgd_offset(obj, da); | |
794 | ||
795 | if (!*iopgd) | |
796 | continue; | |
797 | ||
a1a54456 | 798 | if (iopgd_is_table(*iopgd)) |
a9dcad5e HD |
799 | iopte_free(iopte_offset(iopgd, 0)); |
800 | ||
801 | *iopgd = 0; | |
802 | flush_iopgd_range(iopgd, iopgd); | |
803 | } | |
804 | ||
805 | flush_iotlb_all(obj); | |
806 | ||
807 | spin_unlock(&obj->page_table_lock); | |
808 | } | |
809 | ||
810 | /* | |
811 | * Device IOMMU generic operations | |
812 | */ | |
813 | static irqreturn_t iommu_fault_handler(int irq, void *data) | |
814 | { | |
d594f1f3 | 815 | u32 da, errs; |
a9dcad5e | 816 | u32 *iopgd, *iopte; |
6c32df43 | 817 | struct omap_iommu *obj = data; |
e7f10f02 | 818 | struct iommu_domain *domain = obj->domain; |
a9dcad5e HD |
819 | |
820 | if (!obj->refcount) | |
821 | return IRQ_NONE; | |
822 | ||
d594f1f3 | 823 | errs = iommu_report_fault(obj, &da); |
c56b2ddd LP |
824 | if (errs == 0) |
825 | return IRQ_HANDLED; | |
d594f1f3 DC |
826 | |
827 | /* Fault callback or TLB/PTE Dynamic loading */ | |
e7f10f02 | 828 | if (!report_iommu_fault(domain, obj->dev, da, 0)) |
a9dcad5e HD |
829 | return IRQ_HANDLED; |
830 | ||
37b29810 HD |
831 | iommu_disable(obj); |
832 | ||
a9dcad5e HD |
833 | iopgd = iopgd_offset(obj, da); |
834 | ||
a1a54456 | 835 | if (!iopgd_is_table(*iopgd)) { |
d594f1f3 DC |
836 | dev_err(obj->dev, "%s: errs:0x%08x da:0x%08x pgd:0x%p " |
837 | "*pgd:px%08x\n", obj->name, errs, da, iopgd, *iopgd); | |
a9dcad5e HD |
838 | return IRQ_NONE; |
839 | } | |
840 | ||
841 | iopte = iopte_offset(iopgd, da); | |
842 | ||
d594f1f3 DC |
843 | dev_err(obj->dev, "%s: errs:0x%08x da:0x%08x pgd:0x%p *pgd:0x%08x " |
844 | "pte:0x%p *pte:0x%08x\n", obj->name, errs, da, iopgd, *iopgd, | |
845 | iopte, *iopte); | |
a9dcad5e HD |
846 | |
847 | return IRQ_NONE; | |
848 | } | |
849 | ||
850 | static int device_match_by_alias(struct device *dev, void *data) | |
851 | { | |
6c32df43 | 852 | struct omap_iommu *obj = to_iommu(dev); |
a9dcad5e HD |
853 | const char *name = data; |
854 | ||
855 | pr_debug("%s: %s %s\n", __func__, obj->name, name); | |
856 | ||
857 | return strcmp(obj->name, name) == 0; | |
858 | } | |
859 | ||
860 | /** | |
f626b52d | 861 | * omap_iommu_attach() - attach iommu device to an iommu domain |
fabdbca8 | 862 | * @name: name of target omap iommu device |
f626b52d | 863 | * @iopgd: page table |
a9dcad5e | 864 | **/ |
fabdbca8 | 865 | static struct omap_iommu *omap_iommu_attach(const char *name, u32 *iopgd) |
a9dcad5e HD |
866 | { |
867 | int err = -ENOMEM; | |
fabdbca8 OBC |
868 | struct device *dev; |
869 | struct omap_iommu *obj; | |
870 | ||
871 | dev = driver_find_device(&omap_iommu_driver.driver, NULL, | |
872 | (void *)name, | |
873 | device_match_by_alias); | |
874 | if (!dev) | |
875 | return NULL; | |
876 | ||
877 | obj = to_iommu(dev); | |
a9dcad5e | 878 | |
f626b52d | 879 | spin_lock(&obj->iommu_lock); |
a9dcad5e | 880 | |
f626b52d OBC |
881 | /* an iommu device can only be attached once */ |
882 | if (++obj->refcount > 1) { | |
883 | dev_err(dev, "%s: already attached!\n", obj->name); | |
884 | err = -EBUSY; | |
885 | goto err_enable; | |
a9dcad5e HD |
886 | } |
887 | ||
f626b52d OBC |
888 | obj->iopgd = iopgd; |
889 | err = iommu_enable(obj); | |
890 | if (err) | |
891 | goto err_enable; | |
892 | flush_iotlb_all(obj); | |
893 | ||
a9dcad5e HD |
894 | if (!try_module_get(obj->owner)) |
895 | goto err_module; | |
896 | ||
f626b52d | 897 | spin_unlock(&obj->iommu_lock); |
a9dcad5e HD |
898 | |
899 | dev_dbg(obj->dev, "%s: %s\n", __func__, obj->name); | |
900 | return obj; | |
901 | ||
902 | err_module: | |
903 | if (obj->refcount == 1) | |
904 | iommu_disable(obj); | |
905 | err_enable: | |
906 | obj->refcount--; | |
f626b52d | 907 | spin_unlock(&obj->iommu_lock); |
a9dcad5e HD |
908 | return ERR_PTR(err); |
909 | } | |
a9dcad5e HD |
910 | |
911 | /** | |
f626b52d | 912 | * omap_iommu_detach - release iommu device |
a9dcad5e HD |
913 | * @obj: target iommu |
914 | **/ | |
6c32df43 | 915 | static void omap_iommu_detach(struct omap_iommu *obj) |
a9dcad5e | 916 | { |
acf9d467 | 917 | if (!obj || IS_ERR(obj)) |
a9dcad5e HD |
918 | return; |
919 | ||
f626b52d | 920 | spin_lock(&obj->iommu_lock); |
a9dcad5e HD |
921 | |
922 | if (--obj->refcount == 0) | |
923 | iommu_disable(obj); | |
924 | ||
925 | module_put(obj->owner); | |
926 | ||
f626b52d | 927 | obj->iopgd = NULL; |
d594f1f3 | 928 | |
f626b52d | 929 | spin_unlock(&obj->iommu_lock); |
d594f1f3 | 930 | |
a9dcad5e | 931 | dev_dbg(obj->dev, "%s: %s\n", __func__, obj->name); |
d594f1f3 | 932 | } |
d594f1f3 | 933 | |
a9dcad5e HD |
934 | /* |
935 | * OMAP Device MMU(IOMMU) detection | |
936 | */ | |
d34d6517 | 937 | static int omap_iommu_probe(struct platform_device *pdev) |
a9dcad5e HD |
938 | { |
939 | int err = -ENODEV; | |
a9dcad5e | 940 | int irq; |
6c32df43 | 941 | struct omap_iommu *obj; |
a9dcad5e HD |
942 | struct resource *res; |
943 | struct iommu_platform_data *pdata = pdev->dev.platform_data; | |
944 | ||
a9dcad5e HD |
945 | obj = kzalloc(sizeof(*obj) + MMU_REG_SIZE, GFP_KERNEL); |
946 | if (!obj) | |
947 | return -ENOMEM; | |
948 | ||
a9dcad5e HD |
949 | obj->nr_tlb_entries = pdata->nr_tlb_entries; |
950 | obj->name = pdata->name; | |
951 | obj->dev = &pdev->dev; | |
952 | obj->ctx = (void *)obj + sizeof(*obj); | |
c7f4ab26 GLF |
953 | obj->da_start = pdata->da_start; |
954 | obj->da_end = pdata->da_end; | |
a9dcad5e | 955 | |
f626b52d | 956 | spin_lock_init(&obj->iommu_lock); |
a9dcad5e HD |
957 | mutex_init(&obj->mmap_lock); |
958 | spin_lock_init(&obj->page_table_lock); | |
959 | INIT_LIST_HEAD(&obj->mmap); | |
960 | ||
961 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
962 | if (!res) { | |
963 | err = -ENODEV; | |
964 | goto err_mem; | |
965 | } | |
a9dcad5e HD |
966 | |
967 | res = request_mem_region(res->start, resource_size(res), | |
968 | dev_name(&pdev->dev)); | |
969 | if (!res) { | |
970 | err = -EIO; | |
971 | goto err_mem; | |
972 | } | |
973 | ||
da4a0f76 AK |
974 | obj->regbase = ioremap(res->start, resource_size(res)); |
975 | if (!obj->regbase) { | |
976 | err = -ENOMEM; | |
977 | goto err_ioremap; | |
978 | } | |
979 | ||
a9dcad5e HD |
980 | irq = platform_get_irq(pdev, 0); |
981 | if (irq < 0) { | |
982 | err = -ENODEV; | |
983 | goto err_irq; | |
984 | } | |
985 | err = request_irq(irq, iommu_fault_handler, IRQF_SHARED, | |
986 | dev_name(&pdev->dev), obj); | |
987 | if (err < 0) | |
988 | goto err_irq; | |
989 | platform_set_drvdata(pdev, obj); | |
990 | ||
ebf7cda0 ORL |
991 | pm_runtime_irq_safe(obj->dev); |
992 | pm_runtime_enable(obj->dev); | |
993 | ||
a9dcad5e HD |
994 | dev_info(&pdev->dev, "%s registered\n", obj->name); |
995 | return 0; | |
996 | ||
a9dcad5e | 997 | err_irq: |
a9dcad5e | 998 | iounmap(obj->regbase); |
da4a0f76 AK |
999 | err_ioremap: |
1000 | release_mem_region(res->start, resource_size(res)); | |
a9dcad5e | 1001 | err_mem: |
a9dcad5e HD |
1002 | kfree(obj); |
1003 | return err; | |
1004 | } | |
1005 | ||
d34d6517 | 1006 | static int omap_iommu_remove(struct platform_device *pdev) |
a9dcad5e HD |
1007 | { |
1008 | int irq; | |
1009 | struct resource *res; | |
6c32df43 | 1010 | struct omap_iommu *obj = platform_get_drvdata(pdev); |
a9dcad5e HD |
1011 | |
1012 | platform_set_drvdata(pdev, NULL); | |
1013 | ||
1014 | iopgtable_clear_entry_all(obj); | |
a9dcad5e HD |
1015 | |
1016 | irq = platform_get_irq(pdev, 0); | |
1017 | free_irq(irq, obj); | |
1018 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
1019 | release_mem_region(res->start, resource_size(res)); | |
1020 | iounmap(obj->regbase); | |
1021 | ||
ebf7cda0 ORL |
1022 | pm_runtime_disable(obj->dev); |
1023 | ||
a9dcad5e HD |
1024 | dev_info(&pdev->dev, "%s removed\n", obj->name); |
1025 | kfree(obj); | |
1026 | return 0; | |
1027 | } | |
1028 | ||
1029 | static struct platform_driver omap_iommu_driver = { | |
1030 | .probe = omap_iommu_probe, | |
d34d6517 | 1031 | .remove = omap_iommu_remove, |
a9dcad5e HD |
1032 | .driver = { |
1033 | .name = "omap-iommu", | |
1034 | }, | |
1035 | }; | |
1036 | ||
1037 | static void iopte_cachep_ctor(void *iopte) | |
1038 | { | |
1039 | clean_dcache_area(iopte, IOPTE_TABLE_SIZE); | |
1040 | } | |
1041 | ||
ed1c7de2 TL |
1042 | static u32 iotlb_init_entry(struct iotlb_entry *e, u32 da, u32 pa, |
1043 | u32 flags) | |
1044 | { | |
1045 | memset(e, 0, sizeof(*e)); | |
1046 | ||
1047 | e->da = da; | |
1048 | e->pa = pa; | |
1049 | e->valid = 1; | |
1050 | /* FIXME: add OMAP1 support */ | |
1051 | e->pgsz = flags & MMU_CAM_PGSZ_MASK; | |
1052 | e->endian = flags & MMU_RAM_ENDIAN_MASK; | |
1053 | e->elsz = flags & MMU_RAM_ELSZ_MASK; | |
1054 | e->mixed = flags & MMU_RAM_MIXED_MASK; | |
1055 | ||
1056 | return iopgsz_to_bytes(e->pgsz); | |
1057 | } | |
1058 | ||
f626b52d | 1059 | static int omap_iommu_map(struct iommu_domain *domain, unsigned long da, |
5009065d | 1060 | phys_addr_t pa, size_t bytes, int prot) |
f626b52d OBC |
1061 | { |
1062 | struct omap_iommu_domain *omap_domain = domain->priv; | |
6c32df43 | 1063 | struct omap_iommu *oiommu = omap_domain->iommu_dev; |
f626b52d | 1064 | struct device *dev = oiommu->dev; |
f626b52d OBC |
1065 | struct iotlb_entry e; |
1066 | int omap_pgsz; | |
1067 | u32 ret, flags; | |
1068 | ||
1069 | /* we only support mapping a single iommu page for now */ | |
1070 | omap_pgsz = bytes_to_iopgsz(bytes); | |
1071 | if (omap_pgsz < 0) { | |
1072 | dev_err(dev, "invalid size to map: %d\n", bytes); | |
1073 | return -EINVAL; | |
1074 | } | |
1075 | ||
1076 | dev_dbg(dev, "mapping da 0x%lx to pa 0x%x size 0x%x\n", da, pa, bytes); | |
1077 | ||
1078 | flags = omap_pgsz | prot; | |
1079 | ||
1080 | iotlb_init_entry(&e, da, pa, flags); | |
1081 | ||
6c32df43 | 1082 | ret = omap_iopgtable_store_entry(oiommu, &e); |
b4550d41 | 1083 | if (ret) |
6c32df43 | 1084 | dev_err(dev, "omap_iopgtable_store_entry failed: %d\n", ret); |
f626b52d | 1085 | |
b4550d41 | 1086 | return ret; |
f626b52d OBC |
1087 | } |
1088 | ||
5009065d OBC |
1089 | static size_t omap_iommu_unmap(struct iommu_domain *domain, unsigned long da, |
1090 | size_t size) | |
f626b52d OBC |
1091 | { |
1092 | struct omap_iommu_domain *omap_domain = domain->priv; | |
6c32df43 | 1093 | struct omap_iommu *oiommu = omap_domain->iommu_dev; |
f626b52d | 1094 | struct device *dev = oiommu->dev; |
f626b52d | 1095 | |
5009065d | 1096 | dev_dbg(dev, "unmapping da 0x%lx size %u\n", da, size); |
f626b52d | 1097 | |
5009065d | 1098 | return iopgtable_clear_entry(oiommu, da); |
f626b52d OBC |
1099 | } |
1100 | ||
1101 | static int | |
1102 | omap_iommu_attach_dev(struct iommu_domain *domain, struct device *dev) | |
1103 | { | |
1104 | struct omap_iommu_domain *omap_domain = domain->priv; | |
6c32df43 | 1105 | struct omap_iommu *oiommu; |
fabdbca8 | 1106 | struct omap_iommu_arch_data *arch_data = dev->archdata.iommu; |
f626b52d OBC |
1107 | int ret = 0; |
1108 | ||
1109 | spin_lock(&omap_domain->lock); | |
1110 | ||
1111 | /* only a single device is supported per domain for now */ | |
1112 | if (omap_domain->iommu_dev) { | |
1113 | dev_err(dev, "iommu domain is already attached\n"); | |
1114 | ret = -EBUSY; | |
1115 | goto out; | |
1116 | } | |
1117 | ||
1118 | /* get a handle to and enable the omap iommu */ | |
fabdbca8 | 1119 | oiommu = omap_iommu_attach(arch_data->name, omap_domain->pgtable); |
f626b52d OBC |
1120 | if (IS_ERR(oiommu)) { |
1121 | ret = PTR_ERR(oiommu); | |
1122 | dev_err(dev, "can't get omap iommu: %d\n", ret); | |
1123 | goto out; | |
1124 | } | |
1125 | ||
fabdbca8 | 1126 | omap_domain->iommu_dev = arch_data->iommu_dev = oiommu; |
803b5277 | 1127 | omap_domain->dev = dev; |
e7f10f02 | 1128 | oiommu->domain = domain; |
f626b52d OBC |
1129 | |
1130 | out: | |
1131 | spin_unlock(&omap_domain->lock); | |
1132 | return ret; | |
1133 | } | |
1134 | ||
803b5277 ORL |
1135 | static void _omap_iommu_detach_dev(struct omap_iommu_domain *omap_domain, |
1136 | struct device *dev) | |
f626b52d | 1137 | { |
fabdbca8 | 1138 | struct omap_iommu *oiommu = dev_to_omap_iommu(dev); |
803b5277 | 1139 | struct omap_iommu_arch_data *arch_data = dev->archdata.iommu; |
f626b52d OBC |
1140 | |
1141 | /* only a single device is supported per domain for now */ | |
1142 | if (omap_domain->iommu_dev != oiommu) { | |
1143 | dev_err(dev, "invalid iommu device\n"); | |
803b5277 | 1144 | return; |
f626b52d OBC |
1145 | } |
1146 | ||
1147 | iopgtable_clear_entry_all(oiommu); | |
1148 | ||
1149 | omap_iommu_detach(oiommu); | |
1150 | ||
fabdbca8 | 1151 | omap_domain->iommu_dev = arch_data->iommu_dev = NULL; |
803b5277 ORL |
1152 | omap_domain->dev = NULL; |
1153 | } | |
f626b52d | 1154 | |
803b5277 ORL |
1155 | static void omap_iommu_detach_dev(struct iommu_domain *domain, |
1156 | struct device *dev) | |
1157 | { | |
1158 | struct omap_iommu_domain *omap_domain = domain->priv; | |
1159 | ||
1160 | spin_lock(&omap_domain->lock); | |
1161 | _omap_iommu_detach_dev(omap_domain, dev); | |
f626b52d OBC |
1162 | spin_unlock(&omap_domain->lock); |
1163 | } | |
1164 | ||
1165 | static int omap_iommu_domain_init(struct iommu_domain *domain) | |
1166 | { | |
1167 | struct omap_iommu_domain *omap_domain; | |
1168 | ||
1169 | omap_domain = kzalloc(sizeof(*omap_domain), GFP_KERNEL); | |
1170 | if (!omap_domain) { | |
1171 | pr_err("kzalloc failed\n"); | |
1172 | goto out; | |
1173 | } | |
1174 | ||
1175 | omap_domain->pgtable = kzalloc(IOPGD_TABLE_SIZE, GFP_KERNEL); | |
1176 | if (!omap_domain->pgtable) { | |
1177 | pr_err("kzalloc failed\n"); | |
1178 | goto fail_nomem; | |
1179 | } | |
1180 | ||
1181 | /* | |
1182 | * should never fail, but please keep this around to ensure | |
1183 | * we keep the hardware happy | |
1184 | */ | |
1185 | BUG_ON(!IS_ALIGNED((long)omap_domain->pgtable, IOPGD_TABLE_SIZE)); | |
1186 | ||
1187 | clean_dcache_area(omap_domain->pgtable, IOPGD_TABLE_SIZE); | |
1188 | spin_lock_init(&omap_domain->lock); | |
1189 | ||
1190 | domain->priv = omap_domain; | |
1191 | ||
2c6edb0c JR |
1192 | domain->geometry.aperture_start = 0; |
1193 | domain->geometry.aperture_end = (1ULL << 32) - 1; | |
1194 | domain->geometry.force_aperture = true; | |
1195 | ||
f626b52d OBC |
1196 | return 0; |
1197 | ||
1198 | fail_nomem: | |
1199 | kfree(omap_domain); | |
1200 | out: | |
1201 | return -ENOMEM; | |
1202 | } | |
1203 | ||
f626b52d OBC |
1204 | static void omap_iommu_domain_destroy(struct iommu_domain *domain) |
1205 | { | |
1206 | struct omap_iommu_domain *omap_domain = domain->priv; | |
1207 | ||
1208 | domain->priv = NULL; | |
1209 | ||
803b5277 ORL |
1210 | /* |
1211 | * An iommu device is still attached | |
1212 | * (currently, only one device can be attached) ? | |
1213 | */ | |
1214 | if (omap_domain->iommu_dev) | |
1215 | _omap_iommu_detach_dev(omap_domain, omap_domain->dev); | |
1216 | ||
f626b52d OBC |
1217 | kfree(omap_domain->pgtable); |
1218 | kfree(omap_domain); | |
1219 | } | |
1220 | ||
1221 | static phys_addr_t omap_iommu_iova_to_phys(struct iommu_domain *domain, | |
bb5547ac | 1222 | dma_addr_t da) |
f626b52d OBC |
1223 | { |
1224 | struct omap_iommu_domain *omap_domain = domain->priv; | |
6c32df43 | 1225 | struct omap_iommu *oiommu = omap_domain->iommu_dev; |
f626b52d OBC |
1226 | struct device *dev = oiommu->dev; |
1227 | u32 *pgd, *pte; | |
1228 | phys_addr_t ret = 0; | |
1229 | ||
1230 | iopgtable_lookup_entry(oiommu, da, &pgd, &pte); | |
1231 | ||
1232 | if (pte) { | |
1233 | if (iopte_is_small(*pte)) | |
1234 | ret = omap_iommu_translate(*pte, da, IOPTE_MASK); | |
1235 | else if (iopte_is_large(*pte)) | |
1236 | ret = omap_iommu_translate(*pte, da, IOLARGE_MASK); | |
1237 | else | |
1a36ea81 | 1238 | dev_err(dev, "bogus pte 0x%x, da 0x%lx", *pte, da); |
f626b52d OBC |
1239 | } else { |
1240 | if (iopgd_is_section(*pgd)) | |
1241 | ret = omap_iommu_translate(*pgd, da, IOSECTION_MASK); | |
1242 | else if (iopgd_is_super(*pgd)) | |
1243 | ret = omap_iommu_translate(*pgd, da, IOSUPER_MASK); | |
1244 | else | |
1a36ea81 | 1245 | dev_err(dev, "bogus pgd 0x%x, da 0x%lx", *pgd, da); |
f626b52d OBC |
1246 | } |
1247 | ||
1248 | return ret; | |
1249 | } | |
1250 | ||
1251 | static int omap_iommu_domain_has_cap(struct iommu_domain *domain, | |
1252 | unsigned long cap) | |
1253 | { | |
1254 | return 0; | |
1255 | } | |
1256 | ||
1257 | static struct iommu_ops omap_iommu_ops = { | |
1258 | .domain_init = omap_iommu_domain_init, | |
1259 | .domain_destroy = omap_iommu_domain_destroy, | |
1260 | .attach_dev = omap_iommu_attach_dev, | |
1261 | .detach_dev = omap_iommu_detach_dev, | |
1262 | .map = omap_iommu_map, | |
1263 | .unmap = omap_iommu_unmap, | |
1264 | .iova_to_phys = omap_iommu_iova_to_phys, | |
1265 | .domain_has_cap = omap_iommu_domain_has_cap, | |
66bc8cf3 | 1266 | .pgsize_bitmap = OMAP_IOMMU_PGSIZES, |
f626b52d OBC |
1267 | }; |
1268 | ||
a9dcad5e HD |
1269 | static int __init omap_iommu_init(void) |
1270 | { | |
1271 | struct kmem_cache *p; | |
1272 | const unsigned long flags = SLAB_HWCACHE_ALIGN; | |
1273 | size_t align = 1 << 10; /* L2 pagetable alignement */ | |
1274 | ||
1275 | p = kmem_cache_create("iopte_cache", IOPTE_TABLE_SIZE, align, flags, | |
1276 | iopte_cachep_ctor); | |
1277 | if (!p) | |
1278 | return -ENOMEM; | |
1279 | iopte_cachep = p; | |
1280 | ||
a65bc64f | 1281 | bus_set_iommu(&platform_bus_type, &omap_iommu_ops); |
f626b52d | 1282 | |
a9dcad5e HD |
1283 | return platform_driver_register(&omap_iommu_driver); |
1284 | } | |
435792d9 OBC |
1285 | /* must be ready before omap3isp is probed */ |
1286 | subsys_initcall(omap_iommu_init); | |
a9dcad5e HD |
1287 | |
1288 | static void __exit omap_iommu_exit(void) | |
1289 | { | |
1290 | kmem_cache_destroy(iopte_cachep); | |
1291 | ||
1292 | platform_driver_unregister(&omap_iommu_driver); | |
1293 | } | |
1294 | module_exit(omap_iommu_exit); | |
1295 | ||
1296 | MODULE_DESCRIPTION("omap iommu: tlb and pagetable primitives"); | |
1297 | MODULE_ALIAS("platform:omap-iommu"); | |
1298 | MODULE_AUTHOR("Hiroshi DOYU, Paul Mundt and Toshihiro Kobayashi"); | |
1299 | MODULE_LICENSE("GPL v2"); |