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Commit | Line | Data |
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a9dcad5e HD |
1 | /* |
2 | * omap iommu: tlb and pagetable primitives | |
3 | * | |
c127c7dc | 4 | * Copyright (C) 2008-2010 Nokia Corporation |
a9dcad5e HD |
5 | * |
6 | * Written by Hiroshi DOYU <Hiroshi.DOYU@nokia.com>, | |
7 | * Paul Mundt and Toshihiro Kobayashi | |
8 | * | |
9 | * This program is free software; you can redistribute it and/or modify | |
10 | * it under the terms of the GNU General Public License version 2 as | |
11 | * published by the Free Software Foundation. | |
12 | */ | |
13 | ||
14 | #include <linux/err.h> | |
15 | #include <linux/module.h> | |
5a0e3ad6 | 16 | #include <linux/slab.h> |
a9dcad5e HD |
17 | #include <linux/interrupt.h> |
18 | #include <linux/ioport.h> | |
19 | #include <linux/clk.h> | |
20 | #include <linux/platform_device.h> | |
f626b52d | 21 | #include <linux/iommu.h> |
c8d35c84 | 22 | #include <linux/omap-iommu.h> |
f626b52d OBC |
23 | #include <linux/mutex.h> |
24 | #include <linux/spinlock.h> | |
ed1c7de2 | 25 | #include <linux/io.h> |
a9dcad5e HD |
26 | |
27 | #include <asm/cacheflush.h> | |
28 | ||
ce491cf8 | 29 | #include <plat/iommu.h> |
a9dcad5e | 30 | |
2f7702af | 31 | #include "omap-iopgtable.h" |
ed1c7de2 | 32 | #include "omap-iommu.h" |
a9dcad5e | 33 | |
37c2836c HD |
34 | #define for_each_iotlb_cr(obj, n, __i, cr) \ |
35 | for (__i = 0; \ | |
36 | (__i < (n)) && (cr = __iotlb_read_cr((obj), __i), true); \ | |
37 | __i++) | |
38 | ||
66bc8cf3 OBC |
39 | /* bitmap of the page sizes currently supported */ |
40 | #define OMAP_IOMMU_PGSIZES (SZ_4K | SZ_64K | SZ_1M | SZ_16M) | |
41 | ||
f626b52d OBC |
42 | /** |
43 | * struct omap_iommu_domain - omap iommu domain | |
44 | * @pgtable: the page table | |
45 | * @iommu_dev: an omap iommu device attached to this domain. only a single | |
46 | * iommu device can be attached for now. | |
803b5277 | 47 | * @dev: Device using this domain. |
f626b52d OBC |
48 | * @lock: domain lock, should be taken when attaching/detaching |
49 | */ | |
50 | struct omap_iommu_domain { | |
51 | u32 *pgtable; | |
6c32df43 | 52 | struct omap_iommu *iommu_dev; |
803b5277 | 53 | struct device *dev; |
f626b52d OBC |
54 | spinlock_t lock; |
55 | }; | |
56 | ||
a9dcad5e HD |
57 | /* accommodate the difference between omap1 and omap2/3 */ |
58 | static const struct iommu_functions *arch_iommu; | |
59 | ||
60 | static struct platform_driver omap_iommu_driver; | |
61 | static struct kmem_cache *iopte_cachep; | |
62 | ||
63 | /** | |
6c32df43 | 64 | * omap_install_iommu_arch - Install archtecure specific iommu functions |
a9dcad5e HD |
65 | * @ops: a pointer to architecture specific iommu functions |
66 | * | |
67 | * There are several kind of iommu algorithm(tlb, pagetable) among | |
68 | * omap series. This interface installs such an iommu algorighm. | |
69 | **/ | |
6c32df43 | 70 | int omap_install_iommu_arch(const struct iommu_functions *ops) |
a9dcad5e HD |
71 | { |
72 | if (arch_iommu) | |
73 | return -EBUSY; | |
74 | ||
75 | arch_iommu = ops; | |
76 | return 0; | |
77 | } | |
6c32df43 | 78 | EXPORT_SYMBOL_GPL(omap_install_iommu_arch); |
a9dcad5e HD |
79 | |
80 | /** | |
6c32df43 | 81 | * omap_uninstall_iommu_arch - Uninstall archtecure specific iommu functions |
a9dcad5e HD |
82 | * @ops: a pointer to architecture specific iommu functions |
83 | * | |
84 | * This interface uninstalls the iommu algorighm installed previously. | |
85 | **/ | |
6c32df43 | 86 | void omap_uninstall_iommu_arch(const struct iommu_functions *ops) |
a9dcad5e HD |
87 | { |
88 | if (arch_iommu != ops) | |
89 | pr_err("%s: not your arch\n", __func__); | |
90 | ||
91 | arch_iommu = NULL; | |
92 | } | |
6c32df43 | 93 | EXPORT_SYMBOL_GPL(omap_uninstall_iommu_arch); |
a9dcad5e HD |
94 | |
95 | /** | |
6c32df43 | 96 | * omap_iommu_save_ctx - Save registers for pm off-mode support |
fabdbca8 | 97 | * @dev: client device |
a9dcad5e | 98 | **/ |
fabdbca8 | 99 | void omap_iommu_save_ctx(struct device *dev) |
a9dcad5e | 100 | { |
fabdbca8 OBC |
101 | struct omap_iommu *obj = dev_to_omap_iommu(dev); |
102 | ||
a9dcad5e HD |
103 | arch_iommu->save_ctx(obj); |
104 | } | |
6c32df43 | 105 | EXPORT_SYMBOL_GPL(omap_iommu_save_ctx); |
a9dcad5e HD |
106 | |
107 | /** | |
6c32df43 | 108 | * omap_iommu_restore_ctx - Restore registers for pm off-mode support |
fabdbca8 | 109 | * @dev: client device |
a9dcad5e | 110 | **/ |
fabdbca8 | 111 | void omap_iommu_restore_ctx(struct device *dev) |
a9dcad5e | 112 | { |
fabdbca8 OBC |
113 | struct omap_iommu *obj = dev_to_omap_iommu(dev); |
114 | ||
a9dcad5e HD |
115 | arch_iommu->restore_ctx(obj); |
116 | } | |
6c32df43 | 117 | EXPORT_SYMBOL_GPL(omap_iommu_restore_ctx); |
a9dcad5e HD |
118 | |
119 | /** | |
6c32df43 | 120 | * omap_iommu_arch_version - Return running iommu arch version |
a9dcad5e | 121 | **/ |
6c32df43 | 122 | u32 omap_iommu_arch_version(void) |
a9dcad5e HD |
123 | { |
124 | return arch_iommu->version; | |
125 | } | |
6c32df43 | 126 | EXPORT_SYMBOL_GPL(omap_iommu_arch_version); |
a9dcad5e | 127 | |
6c32df43 | 128 | static int iommu_enable(struct omap_iommu *obj) |
a9dcad5e HD |
129 | { |
130 | int err; | |
131 | ||
132 | if (!obj) | |
133 | return -EINVAL; | |
134 | ||
ef4815ab MH |
135 | if (!arch_iommu) |
136 | return -ENODEV; | |
137 | ||
a9dcad5e HD |
138 | clk_enable(obj->clk); |
139 | ||
140 | err = arch_iommu->enable(obj); | |
141 | ||
142 | clk_disable(obj->clk); | |
143 | return err; | |
144 | } | |
145 | ||
6c32df43 | 146 | static void iommu_disable(struct omap_iommu *obj) |
a9dcad5e HD |
147 | { |
148 | if (!obj) | |
149 | return; | |
150 | ||
151 | clk_enable(obj->clk); | |
152 | ||
153 | arch_iommu->disable(obj); | |
154 | ||
155 | clk_disable(obj->clk); | |
156 | } | |
157 | ||
158 | /* | |
159 | * TLB operations | |
160 | */ | |
6c32df43 | 161 | void omap_iotlb_cr_to_e(struct cr_regs *cr, struct iotlb_entry *e) |
a9dcad5e HD |
162 | { |
163 | BUG_ON(!cr || !e); | |
164 | ||
165 | arch_iommu->cr_to_e(cr, e); | |
166 | } | |
6c32df43 | 167 | EXPORT_SYMBOL_GPL(omap_iotlb_cr_to_e); |
a9dcad5e HD |
168 | |
169 | static inline int iotlb_cr_valid(struct cr_regs *cr) | |
170 | { | |
171 | if (!cr) | |
172 | return -EINVAL; | |
173 | ||
174 | return arch_iommu->cr_valid(cr); | |
175 | } | |
176 | ||
6c32df43 | 177 | static inline struct cr_regs *iotlb_alloc_cr(struct omap_iommu *obj, |
a9dcad5e HD |
178 | struct iotlb_entry *e) |
179 | { | |
180 | if (!e) | |
181 | return NULL; | |
182 | ||
183 | return arch_iommu->alloc_cr(obj, e); | |
184 | } | |
185 | ||
e1f23813 | 186 | static u32 iotlb_cr_to_virt(struct cr_regs *cr) |
a9dcad5e HD |
187 | { |
188 | return arch_iommu->cr_to_virt(cr); | |
189 | } | |
a9dcad5e HD |
190 | |
191 | static u32 get_iopte_attr(struct iotlb_entry *e) | |
192 | { | |
193 | return arch_iommu->get_pte_attr(e); | |
194 | } | |
195 | ||
6c32df43 | 196 | static u32 iommu_report_fault(struct omap_iommu *obj, u32 *da) |
a9dcad5e HD |
197 | { |
198 | return arch_iommu->fault_isr(obj, da); | |
199 | } | |
200 | ||
6c32df43 | 201 | static void iotlb_lock_get(struct omap_iommu *obj, struct iotlb_lock *l) |
a9dcad5e HD |
202 | { |
203 | u32 val; | |
204 | ||
205 | val = iommu_read_reg(obj, MMU_LOCK); | |
206 | ||
207 | l->base = MMU_LOCK_BASE(val); | |
208 | l->vict = MMU_LOCK_VICT(val); | |
209 | ||
a9dcad5e HD |
210 | } |
211 | ||
6c32df43 | 212 | static void iotlb_lock_set(struct omap_iommu *obj, struct iotlb_lock *l) |
a9dcad5e HD |
213 | { |
214 | u32 val; | |
215 | ||
a9dcad5e HD |
216 | val = (l->base << MMU_LOCK_BASE_SHIFT); |
217 | val |= (l->vict << MMU_LOCK_VICT_SHIFT); | |
218 | ||
219 | iommu_write_reg(obj, val, MMU_LOCK); | |
220 | } | |
221 | ||
6c32df43 | 222 | static void iotlb_read_cr(struct omap_iommu *obj, struct cr_regs *cr) |
a9dcad5e HD |
223 | { |
224 | arch_iommu->tlb_read_cr(obj, cr); | |
225 | } | |
226 | ||
6c32df43 | 227 | static void iotlb_load_cr(struct omap_iommu *obj, struct cr_regs *cr) |
a9dcad5e HD |
228 | { |
229 | arch_iommu->tlb_load_cr(obj, cr); | |
230 | ||
231 | iommu_write_reg(obj, 1, MMU_FLUSH_ENTRY); | |
232 | iommu_write_reg(obj, 1, MMU_LD_TLB); | |
233 | } | |
234 | ||
235 | /** | |
236 | * iotlb_dump_cr - Dump an iommu tlb entry into buf | |
237 | * @obj: target iommu | |
238 | * @cr: contents of cam and ram register | |
239 | * @buf: output buffer | |
240 | **/ | |
6c32df43 | 241 | static inline ssize_t iotlb_dump_cr(struct omap_iommu *obj, struct cr_regs *cr, |
a9dcad5e HD |
242 | char *buf) |
243 | { | |
244 | BUG_ON(!cr || !buf); | |
245 | ||
246 | return arch_iommu->dump_cr(obj, cr, buf); | |
247 | } | |
248 | ||
37c2836c | 249 | /* only used in iotlb iteration for-loop */ |
6c32df43 | 250 | static struct cr_regs __iotlb_read_cr(struct omap_iommu *obj, int n) |
37c2836c HD |
251 | { |
252 | struct cr_regs cr; | |
253 | struct iotlb_lock l; | |
254 | ||
255 | iotlb_lock_get(obj, &l); | |
256 | l.vict = n; | |
257 | iotlb_lock_set(obj, &l); | |
258 | iotlb_read_cr(obj, &cr); | |
259 | ||
260 | return cr; | |
261 | } | |
262 | ||
a9dcad5e HD |
263 | /** |
264 | * load_iotlb_entry - Set an iommu tlb entry | |
265 | * @obj: target iommu | |
266 | * @e: an iommu tlb entry info | |
267 | **/ | |
5da14a47 | 268 | #ifdef PREFETCH_IOTLB |
6c32df43 | 269 | static int load_iotlb_entry(struct omap_iommu *obj, struct iotlb_entry *e) |
a9dcad5e | 270 | { |
a9dcad5e HD |
271 | int err = 0; |
272 | struct iotlb_lock l; | |
273 | struct cr_regs *cr; | |
274 | ||
275 | if (!obj || !obj->nr_tlb_entries || !e) | |
276 | return -EINVAL; | |
277 | ||
278 | clk_enable(obj->clk); | |
279 | ||
be6d8026 KH |
280 | iotlb_lock_get(obj, &l); |
281 | if (l.base == obj->nr_tlb_entries) { | |
282 | dev_warn(obj->dev, "%s: preserve entries full\n", __func__); | |
a9dcad5e HD |
283 | err = -EBUSY; |
284 | goto out; | |
285 | } | |
be6d8026 | 286 | if (!e->prsvd) { |
37c2836c HD |
287 | int i; |
288 | struct cr_regs tmp; | |
be6d8026 | 289 | |
37c2836c | 290 | for_each_iotlb_cr(obj, obj->nr_tlb_entries, i, tmp) |
be6d8026 KH |
291 | if (!iotlb_cr_valid(&tmp)) |
292 | break; | |
37c2836c | 293 | |
be6d8026 KH |
294 | if (i == obj->nr_tlb_entries) { |
295 | dev_dbg(obj->dev, "%s: full: no entry\n", __func__); | |
296 | err = -EBUSY; | |
297 | goto out; | |
298 | } | |
37c2836c HD |
299 | |
300 | iotlb_lock_get(obj, &l); | |
be6d8026 KH |
301 | } else { |
302 | l.vict = l.base; | |
303 | iotlb_lock_set(obj, &l); | |
304 | } | |
a9dcad5e HD |
305 | |
306 | cr = iotlb_alloc_cr(obj, e); | |
307 | if (IS_ERR(cr)) { | |
308 | clk_disable(obj->clk); | |
309 | return PTR_ERR(cr); | |
310 | } | |
311 | ||
312 | iotlb_load_cr(obj, cr); | |
313 | kfree(cr); | |
314 | ||
be6d8026 KH |
315 | if (e->prsvd) |
316 | l.base++; | |
a9dcad5e HD |
317 | /* increment victim for next tlb load */ |
318 | if (++l.vict == obj->nr_tlb_entries) | |
be6d8026 | 319 | l.vict = l.base; |
a9dcad5e HD |
320 | iotlb_lock_set(obj, &l); |
321 | out: | |
322 | clk_disable(obj->clk); | |
323 | return err; | |
324 | } | |
a9dcad5e | 325 | |
5da14a47 OBC |
326 | #else /* !PREFETCH_IOTLB */ |
327 | ||
6c32df43 | 328 | static int load_iotlb_entry(struct omap_iommu *obj, struct iotlb_entry *e) |
5da14a47 OBC |
329 | { |
330 | return 0; | |
331 | } | |
332 | ||
333 | #endif /* !PREFETCH_IOTLB */ | |
334 | ||
6c32df43 | 335 | static int prefetch_iotlb_entry(struct omap_iommu *obj, struct iotlb_entry *e) |
5da14a47 OBC |
336 | { |
337 | return load_iotlb_entry(obj, e); | |
338 | } | |
a9dcad5e HD |
339 | |
340 | /** | |
341 | * flush_iotlb_page - Clear an iommu tlb entry | |
342 | * @obj: target iommu | |
343 | * @da: iommu device virtual address | |
344 | * | |
345 | * Clear an iommu tlb entry which includes 'da' address. | |
346 | **/ | |
6c32df43 | 347 | static void flush_iotlb_page(struct omap_iommu *obj, u32 da) |
a9dcad5e | 348 | { |
a9dcad5e | 349 | int i; |
37c2836c | 350 | struct cr_regs cr; |
a9dcad5e HD |
351 | |
352 | clk_enable(obj->clk); | |
353 | ||
37c2836c | 354 | for_each_iotlb_cr(obj, obj->nr_tlb_entries, i, cr) { |
a9dcad5e HD |
355 | u32 start; |
356 | size_t bytes; | |
357 | ||
a9dcad5e HD |
358 | if (!iotlb_cr_valid(&cr)) |
359 | continue; | |
360 | ||
361 | start = iotlb_cr_to_virt(&cr); | |
362 | bytes = iopgsz_to_bytes(cr.cam & 3); | |
363 | ||
364 | if ((start <= da) && (da < start + bytes)) { | |
365 | dev_dbg(obj->dev, "%s: %08x<=%08x(%x)\n", | |
366 | __func__, start, da, bytes); | |
0fa035e5 | 367 | iotlb_load_cr(obj, &cr); |
a9dcad5e HD |
368 | iommu_write_reg(obj, 1, MMU_FLUSH_ENTRY); |
369 | } | |
370 | } | |
371 | clk_disable(obj->clk); | |
372 | ||
373 | if (i == obj->nr_tlb_entries) | |
374 | dev_dbg(obj->dev, "%s: no page for %08x\n", __func__, da); | |
375 | } | |
a9dcad5e HD |
376 | |
377 | /** | |
378 | * flush_iotlb_all - Clear all iommu tlb entries | |
379 | * @obj: target iommu | |
380 | **/ | |
6c32df43 | 381 | static void flush_iotlb_all(struct omap_iommu *obj) |
a9dcad5e HD |
382 | { |
383 | struct iotlb_lock l; | |
384 | ||
385 | clk_enable(obj->clk); | |
386 | ||
387 | l.base = 0; | |
388 | l.vict = 0; | |
389 | iotlb_lock_set(obj, &l); | |
390 | ||
391 | iommu_write_reg(obj, 1, MMU_GFLUSH); | |
392 | ||
393 | clk_disable(obj->clk); | |
394 | } | |
ddfa975a | 395 | |
e4efd94b | 396 | #if defined(CONFIG_OMAP_IOMMU_DEBUG) || defined(CONFIG_OMAP_IOMMU_DEBUG_MODULE) |
a9dcad5e | 397 | |
6c32df43 | 398 | ssize_t omap_iommu_dump_ctx(struct omap_iommu *obj, char *buf, ssize_t bytes) |
a9dcad5e | 399 | { |
a9dcad5e HD |
400 | if (!obj || !buf) |
401 | return -EINVAL; | |
402 | ||
403 | clk_enable(obj->clk); | |
404 | ||
14e0e679 | 405 | bytes = arch_iommu->dump_ctx(obj, buf, bytes); |
a9dcad5e HD |
406 | |
407 | clk_disable(obj->clk); | |
408 | ||
409 | return bytes; | |
410 | } | |
6c32df43 | 411 | EXPORT_SYMBOL_GPL(omap_iommu_dump_ctx); |
a9dcad5e | 412 | |
6c32df43 OBC |
413 | static int |
414 | __dump_tlb_entries(struct omap_iommu *obj, struct cr_regs *crs, int num) | |
a9dcad5e HD |
415 | { |
416 | int i; | |
37c2836c HD |
417 | struct iotlb_lock saved; |
418 | struct cr_regs tmp; | |
a9dcad5e HD |
419 | struct cr_regs *p = crs; |
420 | ||
421 | clk_enable(obj->clk); | |
a9dcad5e | 422 | iotlb_lock_get(obj, &saved); |
a9dcad5e | 423 | |
37c2836c | 424 | for_each_iotlb_cr(obj, num, i, tmp) { |
a9dcad5e HD |
425 | if (!iotlb_cr_valid(&tmp)) |
426 | continue; | |
a9dcad5e HD |
427 | *p++ = tmp; |
428 | } | |
37c2836c | 429 | |
a9dcad5e HD |
430 | iotlb_lock_set(obj, &saved); |
431 | clk_disable(obj->clk); | |
432 | ||
433 | return p - crs; | |
434 | } | |
435 | ||
436 | /** | |
6c32df43 | 437 | * omap_dump_tlb_entries - dump cr arrays to given buffer |
a9dcad5e HD |
438 | * @obj: target iommu |
439 | * @buf: output buffer | |
440 | **/ | |
6c32df43 | 441 | size_t omap_dump_tlb_entries(struct omap_iommu *obj, char *buf, ssize_t bytes) |
a9dcad5e | 442 | { |
14e0e679 | 443 | int i, num; |
a9dcad5e HD |
444 | struct cr_regs *cr; |
445 | char *p = buf; | |
446 | ||
14e0e679 HD |
447 | num = bytes / sizeof(*cr); |
448 | num = min(obj->nr_tlb_entries, num); | |
449 | ||
450 | cr = kcalloc(num, sizeof(*cr), GFP_KERNEL); | |
a9dcad5e HD |
451 | if (!cr) |
452 | return 0; | |
453 | ||
14e0e679 HD |
454 | num = __dump_tlb_entries(obj, cr, num); |
455 | for (i = 0; i < num; i++) | |
a9dcad5e HD |
456 | p += iotlb_dump_cr(obj, cr + i, p); |
457 | kfree(cr); | |
458 | ||
459 | return p - buf; | |
460 | } | |
6c32df43 | 461 | EXPORT_SYMBOL_GPL(omap_dump_tlb_entries); |
a9dcad5e | 462 | |
6c32df43 | 463 | int omap_foreach_iommu_device(void *data, int (*fn)(struct device *, void *)) |
a9dcad5e HD |
464 | { |
465 | return driver_for_each_device(&omap_iommu_driver.driver, | |
466 | NULL, data, fn); | |
467 | } | |
6c32df43 | 468 | EXPORT_SYMBOL_GPL(omap_foreach_iommu_device); |
a9dcad5e HD |
469 | |
470 | #endif /* CONFIG_OMAP_IOMMU_DEBUG_MODULE */ | |
471 | ||
472 | /* | |
473 | * H/W pagetable operations | |
474 | */ | |
475 | static void flush_iopgd_range(u32 *first, u32 *last) | |
476 | { | |
477 | /* FIXME: L2 cache should be taken care of if it exists */ | |
478 | do { | |
479 | asm("mcr p15, 0, %0, c7, c10, 1 @ flush_pgd" | |
480 | : : "r" (first)); | |
481 | first += L1_CACHE_BYTES / sizeof(*first); | |
482 | } while (first <= last); | |
483 | } | |
484 | ||
485 | static void flush_iopte_range(u32 *first, u32 *last) | |
486 | { | |
487 | /* FIXME: L2 cache should be taken care of if it exists */ | |
488 | do { | |
489 | asm("mcr p15, 0, %0, c7, c10, 1 @ flush_pte" | |
490 | : : "r" (first)); | |
491 | first += L1_CACHE_BYTES / sizeof(*first); | |
492 | } while (first <= last); | |
493 | } | |
494 | ||
495 | static void iopte_free(u32 *iopte) | |
496 | { | |
497 | /* Note: freed iopte's must be clean ready for re-use */ | |
498 | kmem_cache_free(iopte_cachep, iopte); | |
499 | } | |
500 | ||
6c32df43 | 501 | static u32 *iopte_alloc(struct omap_iommu *obj, u32 *iopgd, u32 da) |
a9dcad5e HD |
502 | { |
503 | u32 *iopte; | |
504 | ||
505 | /* a table has already existed */ | |
506 | if (*iopgd) | |
507 | goto pte_ready; | |
508 | ||
509 | /* | |
510 | * do the allocation outside the page table lock | |
511 | */ | |
512 | spin_unlock(&obj->page_table_lock); | |
513 | iopte = kmem_cache_zalloc(iopte_cachep, GFP_KERNEL); | |
514 | spin_lock(&obj->page_table_lock); | |
515 | ||
516 | if (!*iopgd) { | |
517 | if (!iopte) | |
518 | return ERR_PTR(-ENOMEM); | |
519 | ||
520 | *iopgd = virt_to_phys(iopte) | IOPGD_TABLE; | |
521 | flush_iopgd_range(iopgd, iopgd); | |
522 | ||
523 | dev_vdbg(obj->dev, "%s: a new pte:%p\n", __func__, iopte); | |
524 | } else { | |
525 | /* We raced, free the reduniovant table */ | |
526 | iopte_free(iopte); | |
527 | } | |
528 | ||
529 | pte_ready: | |
530 | iopte = iopte_offset(iopgd, da); | |
531 | ||
532 | dev_vdbg(obj->dev, | |
533 | "%s: da:%08x pgd:%p *pgd:%08x pte:%p *pte:%08x\n", | |
534 | __func__, da, iopgd, *iopgd, iopte, *iopte); | |
535 | ||
536 | return iopte; | |
537 | } | |
538 | ||
6c32df43 | 539 | static int iopgd_alloc_section(struct omap_iommu *obj, u32 da, u32 pa, u32 prot) |
a9dcad5e HD |
540 | { |
541 | u32 *iopgd = iopgd_offset(obj, da); | |
542 | ||
4abb7617 HD |
543 | if ((da | pa) & ~IOSECTION_MASK) { |
544 | dev_err(obj->dev, "%s: %08x:%08x should aligned on %08lx\n", | |
545 | __func__, da, pa, IOSECTION_SIZE); | |
546 | return -EINVAL; | |
547 | } | |
548 | ||
a9dcad5e HD |
549 | *iopgd = (pa & IOSECTION_MASK) | prot | IOPGD_SECTION; |
550 | flush_iopgd_range(iopgd, iopgd); | |
551 | return 0; | |
552 | } | |
553 | ||
6c32df43 | 554 | static int iopgd_alloc_super(struct omap_iommu *obj, u32 da, u32 pa, u32 prot) |
a9dcad5e HD |
555 | { |
556 | u32 *iopgd = iopgd_offset(obj, da); | |
557 | int i; | |
558 | ||
4abb7617 HD |
559 | if ((da | pa) & ~IOSUPER_MASK) { |
560 | dev_err(obj->dev, "%s: %08x:%08x should aligned on %08lx\n", | |
561 | __func__, da, pa, IOSUPER_SIZE); | |
562 | return -EINVAL; | |
563 | } | |
564 | ||
a9dcad5e HD |
565 | for (i = 0; i < 16; i++) |
566 | *(iopgd + i) = (pa & IOSUPER_MASK) | prot | IOPGD_SUPER; | |
567 | flush_iopgd_range(iopgd, iopgd + 15); | |
568 | return 0; | |
569 | } | |
570 | ||
6c32df43 | 571 | static int iopte_alloc_page(struct omap_iommu *obj, u32 da, u32 pa, u32 prot) |
a9dcad5e HD |
572 | { |
573 | u32 *iopgd = iopgd_offset(obj, da); | |
574 | u32 *iopte = iopte_alloc(obj, iopgd, da); | |
575 | ||
576 | if (IS_ERR(iopte)) | |
577 | return PTR_ERR(iopte); | |
578 | ||
579 | *iopte = (pa & IOPAGE_MASK) | prot | IOPTE_SMALL; | |
580 | flush_iopte_range(iopte, iopte); | |
581 | ||
582 | dev_vdbg(obj->dev, "%s: da:%08x pa:%08x pte:%p *pte:%08x\n", | |
583 | __func__, da, pa, iopte, *iopte); | |
584 | ||
585 | return 0; | |
586 | } | |
587 | ||
6c32df43 | 588 | static int iopte_alloc_large(struct omap_iommu *obj, u32 da, u32 pa, u32 prot) |
a9dcad5e HD |
589 | { |
590 | u32 *iopgd = iopgd_offset(obj, da); | |
591 | u32 *iopte = iopte_alloc(obj, iopgd, da); | |
592 | int i; | |
593 | ||
4abb7617 HD |
594 | if ((da | pa) & ~IOLARGE_MASK) { |
595 | dev_err(obj->dev, "%s: %08x:%08x should aligned on %08lx\n", | |
596 | __func__, da, pa, IOLARGE_SIZE); | |
597 | return -EINVAL; | |
598 | } | |
599 | ||
a9dcad5e HD |
600 | if (IS_ERR(iopte)) |
601 | return PTR_ERR(iopte); | |
602 | ||
603 | for (i = 0; i < 16; i++) | |
604 | *(iopte + i) = (pa & IOLARGE_MASK) | prot | IOPTE_LARGE; | |
605 | flush_iopte_range(iopte, iopte + 15); | |
606 | return 0; | |
607 | } | |
608 | ||
6c32df43 OBC |
609 | static int |
610 | iopgtable_store_entry_core(struct omap_iommu *obj, struct iotlb_entry *e) | |
a9dcad5e | 611 | { |
6c32df43 | 612 | int (*fn)(struct omap_iommu *, u32, u32, u32); |
a9dcad5e HD |
613 | u32 prot; |
614 | int err; | |
615 | ||
616 | if (!obj || !e) | |
617 | return -EINVAL; | |
618 | ||
619 | switch (e->pgsz) { | |
620 | case MMU_CAM_PGSZ_16M: | |
621 | fn = iopgd_alloc_super; | |
622 | break; | |
623 | case MMU_CAM_PGSZ_1M: | |
624 | fn = iopgd_alloc_section; | |
625 | break; | |
626 | case MMU_CAM_PGSZ_64K: | |
627 | fn = iopte_alloc_large; | |
628 | break; | |
629 | case MMU_CAM_PGSZ_4K: | |
630 | fn = iopte_alloc_page; | |
631 | break; | |
632 | default: | |
633 | fn = NULL; | |
634 | BUG(); | |
635 | break; | |
636 | } | |
637 | ||
638 | prot = get_iopte_attr(e); | |
639 | ||
640 | spin_lock(&obj->page_table_lock); | |
641 | err = fn(obj, e->da, e->pa, prot); | |
642 | spin_unlock(&obj->page_table_lock); | |
643 | ||
644 | return err; | |
645 | } | |
646 | ||
647 | /** | |
6c32df43 | 648 | * omap_iopgtable_store_entry - Make an iommu pte entry |
a9dcad5e HD |
649 | * @obj: target iommu |
650 | * @e: an iommu tlb entry info | |
651 | **/ | |
6c32df43 | 652 | int omap_iopgtable_store_entry(struct omap_iommu *obj, struct iotlb_entry *e) |
a9dcad5e HD |
653 | { |
654 | int err; | |
655 | ||
656 | flush_iotlb_page(obj, e->da); | |
657 | err = iopgtable_store_entry_core(obj, e); | |
a9dcad5e | 658 | if (!err) |
5da14a47 | 659 | prefetch_iotlb_entry(obj, e); |
a9dcad5e HD |
660 | return err; |
661 | } | |
6c32df43 | 662 | EXPORT_SYMBOL_GPL(omap_iopgtable_store_entry); |
a9dcad5e HD |
663 | |
664 | /** | |
665 | * iopgtable_lookup_entry - Lookup an iommu pte entry | |
666 | * @obj: target iommu | |
667 | * @da: iommu device virtual address | |
668 | * @ppgd: iommu pgd entry pointer to be returned | |
669 | * @ppte: iommu pte entry pointer to be returned | |
670 | **/ | |
e1f23813 OBC |
671 | static void |
672 | iopgtable_lookup_entry(struct omap_iommu *obj, u32 da, u32 **ppgd, u32 **ppte) | |
a9dcad5e HD |
673 | { |
674 | u32 *iopgd, *iopte = NULL; | |
675 | ||
676 | iopgd = iopgd_offset(obj, da); | |
677 | if (!*iopgd) | |
678 | goto out; | |
679 | ||
a1a54456 | 680 | if (iopgd_is_table(*iopgd)) |
a9dcad5e HD |
681 | iopte = iopte_offset(iopgd, da); |
682 | out: | |
683 | *ppgd = iopgd; | |
684 | *ppte = iopte; | |
685 | } | |
a9dcad5e | 686 | |
6c32df43 | 687 | static size_t iopgtable_clear_entry_core(struct omap_iommu *obj, u32 da) |
a9dcad5e HD |
688 | { |
689 | size_t bytes; | |
690 | u32 *iopgd = iopgd_offset(obj, da); | |
691 | int nent = 1; | |
692 | ||
693 | if (!*iopgd) | |
694 | return 0; | |
695 | ||
a1a54456 | 696 | if (iopgd_is_table(*iopgd)) { |
a9dcad5e HD |
697 | int i; |
698 | u32 *iopte = iopte_offset(iopgd, da); | |
699 | ||
700 | bytes = IOPTE_SIZE; | |
701 | if (*iopte & IOPTE_LARGE) { | |
702 | nent *= 16; | |
703 | /* rewind to the 1st entry */ | |
c127c7dc | 704 | iopte = iopte_offset(iopgd, (da & IOLARGE_MASK)); |
a9dcad5e HD |
705 | } |
706 | bytes *= nent; | |
707 | memset(iopte, 0, nent * sizeof(*iopte)); | |
708 | flush_iopte_range(iopte, iopte + (nent - 1) * sizeof(*iopte)); | |
709 | ||
710 | /* | |
711 | * do table walk to check if this table is necessary or not | |
712 | */ | |
713 | iopte = iopte_offset(iopgd, 0); | |
714 | for (i = 0; i < PTRS_PER_IOPTE; i++) | |
715 | if (iopte[i]) | |
716 | goto out; | |
717 | ||
718 | iopte_free(iopte); | |
719 | nent = 1; /* for the next L1 entry */ | |
720 | } else { | |
721 | bytes = IOPGD_SIZE; | |
dcc730dc | 722 | if ((*iopgd & IOPGD_SUPER) == IOPGD_SUPER) { |
a9dcad5e HD |
723 | nent *= 16; |
724 | /* rewind to the 1st entry */ | |
8d33ea58 | 725 | iopgd = iopgd_offset(obj, (da & IOSUPER_MASK)); |
a9dcad5e HD |
726 | } |
727 | bytes *= nent; | |
728 | } | |
729 | memset(iopgd, 0, nent * sizeof(*iopgd)); | |
730 | flush_iopgd_range(iopgd, iopgd + (nent - 1) * sizeof(*iopgd)); | |
731 | out: | |
732 | return bytes; | |
733 | } | |
734 | ||
735 | /** | |
736 | * iopgtable_clear_entry - Remove an iommu pte entry | |
737 | * @obj: target iommu | |
738 | * @da: iommu device virtual address | |
739 | **/ | |
6c32df43 | 740 | static size_t iopgtable_clear_entry(struct omap_iommu *obj, u32 da) |
a9dcad5e HD |
741 | { |
742 | size_t bytes; | |
743 | ||
744 | spin_lock(&obj->page_table_lock); | |
745 | ||
746 | bytes = iopgtable_clear_entry_core(obj, da); | |
747 | flush_iotlb_page(obj, da); | |
748 | ||
749 | spin_unlock(&obj->page_table_lock); | |
750 | ||
751 | return bytes; | |
752 | } | |
a9dcad5e | 753 | |
6c32df43 | 754 | static void iopgtable_clear_entry_all(struct omap_iommu *obj) |
a9dcad5e HD |
755 | { |
756 | int i; | |
757 | ||
758 | spin_lock(&obj->page_table_lock); | |
759 | ||
760 | for (i = 0; i < PTRS_PER_IOPGD; i++) { | |
761 | u32 da; | |
762 | u32 *iopgd; | |
763 | ||
764 | da = i << IOPGD_SHIFT; | |
765 | iopgd = iopgd_offset(obj, da); | |
766 | ||
767 | if (!*iopgd) | |
768 | continue; | |
769 | ||
a1a54456 | 770 | if (iopgd_is_table(*iopgd)) |
a9dcad5e HD |
771 | iopte_free(iopte_offset(iopgd, 0)); |
772 | ||
773 | *iopgd = 0; | |
774 | flush_iopgd_range(iopgd, iopgd); | |
775 | } | |
776 | ||
777 | flush_iotlb_all(obj); | |
778 | ||
779 | spin_unlock(&obj->page_table_lock); | |
780 | } | |
781 | ||
782 | /* | |
783 | * Device IOMMU generic operations | |
784 | */ | |
785 | static irqreturn_t iommu_fault_handler(int irq, void *data) | |
786 | { | |
d594f1f3 | 787 | u32 da, errs; |
a9dcad5e | 788 | u32 *iopgd, *iopte; |
6c32df43 | 789 | struct omap_iommu *obj = data; |
e7f10f02 | 790 | struct iommu_domain *domain = obj->domain; |
a9dcad5e HD |
791 | |
792 | if (!obj->refcount) | |
793 | return IRQ_NONE; | |
794 | ||
a9dcad5e | 795 | clk_enable(obj->clk); |
d594f1f3 | 796 | errs = iommu_report_fault(obj, &da); |
a9dcad5e | 797 | clk_disable(obj->clk); |
c56b2ddd LP |
798 | if (errs == 0) |
799 | return IRQ_HANDLED; | |
d594f1f3 DC |
800 | |
801 | /* Fault callback or TLB/PTE Dynamic loading */ | |
e7f10f02 | 802 | if (!report_iommu_fault(domain, obj->dev, da, 0)) |
a9dcad5e HD |
803 | return IRQ_HANDLED; |
804 | ||
37b29810 HD |
805 | iommu_disable(obj); |
806 | ||
a9dcad5e HD |
807 | iopgd = iopgd_offset(obj, da); |
808 | ||
a1a54456 | 809 | if (!iopgd_is_table(*iopgd)) { |
d594f1f3 DC |
810 | dev_err(obj->dev, "%s: errs:0x%08x da:0x%08x pgd:0x%p " |
811 | "*pgd:px%08x\n", obj->name, errs, da, iopgd, *iopgd); | |
a9dcad5e HD |
812 | return IRQ_NONE; |
813 | } | |
814 | ||
815 | iopte = iopte_offset(iopgd, da); | |
816 | ||
d594f1f3 DC |
817 | dev_err(obj->dev, "%s: errs:0x%08x da:0x%08x pgd:0x%p *pgd:0x%08x " |
818 | "pte:0x%p *pte:0x%08x\n", obj->name, errs, da, iopgd, *iopgd, | |
819 | iopte, *iopte); | |
a9dcad5e HD |
820 | |
821 | return IRQ_NONE; | |
822 | } | |
823 | ||
824 | static int device_match_by_alias(struct device *dev, void *data) | |
825 | { | |
6c32df43 | 826 | struct omap_iommu *obj = to_iommu(dev); |
a9dcad5e HD |
827 | const char *name = data; |
828 | ||
829 | pr_debug("%s: %s %s\n", __func__, obj->name, name); | |
830 | ||
831 | return strcmp(obj->name, name) == 0; | |
832 | } | |
833 | ||
834 | /** | |
f626b52d | 835 | * omap_iommu_attach() - attach iommu device to an iommu domain |
fabdbca8 | 836 | * @name: name of target omap iommu device |
f626b52d | 837 | * @iopgd: page table |
a9dcad5e | 838 | **/ |
fabdbca8 | 839 | static struct omap_iommu *omap_iommu_attach(const char *name, u32 *iopgd) |
a9dcad5e HD |
840 | { |
841 | int err = -ENOMEM; | |
fabdbca8 OBC |
842 | struct device *dev; |
843 | struct omap_iommu *obj; | |
844 | ||
845 | dev = driver_find_device(&omap_iommu_driver.driver, NULL, | |
846 | (void *)name, | |
847 | device_match_by_alias); | |
848 | if (!dev) | |
849 | return NULL; | |
850 | ||
851 | obj = to_iommu(dev); | |
a9dcad5e | 852 | |
f626b52d | 853 | spin_lock(&obj->iommu_lock); |
a9dcad5e | 854 | |
f626b52d OBC |
855 | /* an iommu device can only be attached once */ |
856 | if (++obj->refcount > 1) { | |
857 | dev_err(dev, "%s: already attached!\n", obj->name); | |
858 | err = -EBUSY; | |
859 | goto err_enable; | |
a9dcad5e HD |
860 | } |
861 | ||
f626b52d OBC |
862 | obj->iopgd = iopgd; |
863 | err = iommu_enable(obj); | |
864 | if (err) | |
865 | goto err_enable; | |
866 | flush_iotlb_all(obj); | |
867 | ||
a9dcad5e HD |
868 | if (!try_module_get(obj->owner)) |
869 | goto err_module; | |
870 | ||
f626b52d | 871 | spin_unlock(&obj->iommu_lock); |
a9dcad5e HD |
872 | |
873 | dev_dbg(obj->dev, "%s: %s\n", __func__, obj->name); | |
874 | return obj; | |
875 | ||
876 | err_module: | |
877 | if (obj->refcount == 1) | |
878 | iommu_disable(obj); | |
879 | err_enable: | |
880 | obj->refcount--; | |
f626b52d | 881 | spin_unlock(&obj->iommu_lock); |
a9dcad5e HD |
882 | return ERR_PTR(err); |
883 | } | |
a9dcad5e HD |
884 | |
885 | /** | |
f626b52d | 886 | * omap_iommu_detach - release iommu device |
a9dcad5e HD |
887 | * @obj: target iommu |
888 | **/ | |
6c32df43 | 889 | static void omap_iommu_detach(struct omap_iommu *obj) |
a9dcad5e | 890 | { |
acf9d467 | 891 | if (!obj || IS_ERR(obj)) |
a9dcad5e HD |
892 | return; |
893 | ||
f626b52d | 894 | spin_lock(&obj->iommu_lock); |
a9dcad5e HD |
895 | |
896 | if (--obj->refcount == 0) | |
897 | iommu_disable(obj); | |
898 | ||
899 | module_put(obj->owner); | |
900 | ||
f626b52d | 901 | obj->iopgd = NULL; |
d594f1f3 | 902 | |
f626b52d | 903 | spin_unlock(&obj->iommu_lock); |
d594f1f3 | 904 | |
a9dcad5e | 905 | dev_dbg(obj->dev, "%s: %s\n", __func__, obj->name); |
d594f1f3 | 906 | } |
d594f1f3 | 907 | |
a9dcad5e HD |
908 | /* |
909 | * OMAP Device MMU(IOMMU) detection | |
910 | */ | |
911 | static int __devinit omap_iommu_probe(struct platform_device *pdev) | |
912 | { | |
913 | int err = -ENODEV; | |
a9dcad5e | 914 | int irq; |
6c32df43 | 915 | struct omap_iommu *obj; |
a9dcad5e HD |
916 | struct resource *res; |
917 | struct iommu_platform_data *pdata = pdev->dev.platform_data; | |
918 | ||
919 | if (pdev->num_resources != 2) | |
920 | return -EINVAL; | |
921 | ||
922 | obj = kzalloc(sizeof(*obj) + MMU_REG_SIZE, GFP_KERNEL); | |
923 | if (!obj) | |
924 | return -ENOMEM; | |
925 | ||
926 | obj->clk = clk_get(&pdev->dev, pdata->clk_name); | |
927 | if (IS_ERR(obj->clk)) | |
928 | goto err_clk; | |
929 | ||
930 | obj->nr_tlb_entries = pdata->nr_tlb_entries; | |
931 | obj->name = pdata->name; | |
932 | obj->dev = &pdev->dev; | |
933 | obj->ctx = (void *)obj + sizeof(*obj); | |
c7f4ab26 GLF |
934 | obj->da_start = pdata->da_start; |
935 | obj->da_end = pdata->da_end; | |
a9dcad5e | 936 | |
f626b52d | 937 | spin_lock_init(&obj->iommu_lock); |
a9dcad5e HD |
938 | mutex_init(&obj->mmap_lock); |
939 | spin_lock_init(&obj->page_table_lock); | |
940 | INIT_LIST_HEAD(&obj->mmap); | |
941 | ||
942 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
943 | if (!res) { | |
944 | err = -ENODEV; | |
945 | goto err_mem; | |
946 | } | |
a9dcad5e HD |
947 | |
948 | res = request_mem_region(res->start, resource_size(res), | |
949 | dev_name(&pdev->dev)); | |
950 | if (!res) { | |
951 | err = -EIO; | |
952 | goto err_mem; | |
953 | } | |
954 | ||
da4a0f76 AK |
955 | obj->regbase = ioremap(res->start, resource_size(res)); |
956 | if (!obj->regbase) { | |
957 | err = -ENOMEM; | |
958 | goto err_ioremap; | |
959 | } | |
960 | ||
a9dcad5e HD |
961 | irq = platform_get_irq(pdev, 0); |
962 | if (irq < 0) { | |
963 | err = -ENODEV; | |
964 | goto err_irq; | |
965 | } | |
966 | err = request_irq(irq, iommu_fault_handler, IRQF_SHARED, | |
967 | dev_name(&pdev->dev), obj); | |
968 | if (err < 0) | |
969 | goto err_irq; | |
970 | platform_set_drvdata(pdev, obj); | |
971 | ||
a9dcad5e HD |
972 | dev_info(&pdev->dev, "%s registered\n", obj->name); |
973 | return 0; | |
974 | ||
a9dcad5e | 975 | err_irq: |
a9dcad5e | 976 | iounmap(obj->regbase); |
da4a0f76 AK |
977 | err_ioremap: |
978 | release_mem_region(res->start, resource_size(res)); | |
a9dcad5e HD |
979 | err_mem: |
980 | clk_put(obj->clk); | |
981 | err_clk: | |
982 | kfree(obj); | |
983 | return err; | |
984 | } | |
985 | ||
986 | static int __devexit omap_iommu_remove(struct platform_device *pdev) | |
987 | { | |
988 | int irq; | |
989 | struct resource *res; | |
6c32df43 | 990 | struct omap_iommu *obj = platform_get_drvdata(pdev); |
a9dcad5e HD |
991 | |
992 | platform_set_drvdata(pdev, NULL); | |
993 | ||
994 | iopgtable_clear_entry_all(obj); | |
a9dcad5e HD |
995 | |
996 | irq = platform_get_irq(pdev, 0); | |
997 | free_irq(irq, obj); | |
998 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
999 | release_mem_region(res->start, resource_size(res)); | |
1000 | iounmap(obj->regbase); | |
1001 | ||
1002 | clk_put(obj->clk); | |
1003 | dev_info(&pdev->dev, "%s removed\n", obj->name); | |
1004 | kfree(obj); | |
1005 | return 0; | |
1006 | } | |
1007 | ||
1008 | static struct platform_driver omap_iommu_driver = { | |
1009 | .probe = omap_iommu_probe, | |
1010 | .remove = __devexit_p(omap_iommu_remove), | |
1011 | .driver = { | |
1012 | .name = "omap-iommu", | |
1013 | }, | |
1014 | }; | |
1015 | ||
1016 | static void iopte_cachep_ctor(void *iopte) | |
1017 | { | |
1018 | clean_dcache_area(iopte, IOPTE_TABLE_SIZE); | |
1019 | } | |
1020 | ||
ed1c7de2 TL |
1021 | static u32 iotlb_init_entry(struct iotlb_entry *e, u32 da, u32 pa, |
1022 | u32 flags) | |
1023 | { | |
1024 | memset(e, 0, sizeof(*e)); | |
1025 | ||
1026 | e->da = da; | |
1027 | e->pa = pa; | |
1028 | e->valid = 1; | |
1029 | /* FIXME: add OMAP1 support */ | |
1030 | e->pgsz = flags & MMU_CAM_PGSZ_MASK; | |
1031 | e->endian = flags & MMU_RAM_ENDIAN_MASK; | |
1032 | e->elsz = flags & MMU_RAM_ELSZ_MASK; | |
1033 | e->mixed = flags & MMU_RAM_MIXED_MASK; | |
1034 | ||
1035 | return iopgsz_to_bytes(e->pgsz); | |
1036 | } | |
1037 | ||
f626b52d | 1038 | static int omap_iommu_map(struct iommu_domain *domain, unsigned long da, |
5009065d | 1039 | phys_addr_t pa, size_t bytes, int prot) |
f626b52d OBC |
1040 | { |
1041 | struct omap_iommu_domain *omap_domain = domain->priv; | |
6c32df43 | 1042 | struct omap_iommu *oiommu = omap_domain->iommu_dev; |
f626b52d | 1043 | struct device *dev = oiommu->dev; |
f626b52d OBC |
1044 | struct iotlb_entry e; |
1045 | int omap_pgsz; | |
1046 | u32 ret, flags; | |
1047 | ||
1048 | /* we only support mapping a single iommu page for now */ | |
1049 | omap_pgsz = bytes_to_iopgsz(bytes); | |
1050 | if (omap_pgsz < 0) { | |
1051 | dev_err(dev, "invalid size to map: %d\n", bytes); | |
1052 | return -EINVAL; | |
1053 | } | |
1054 | ||
1055 | dev_dbg(dev, "mapping da 0x%lx to pa 0x%x size 0x%x\n", da, pa, bytes); | |
1056 | ||
1057 | flags = omap_pgsz | prot; | |
1058 | ||
1059 | iotlb_init_entry(&e, da, pa, flags); | |
1060 | ||
6c32df43 | 1061 | ret = omap_iopgtable_store_entry(oiommu, &e); |
b4550d41 | 1062 | if (ret) |
6c32df43 | 1063 | dev_err(dev, "omap_iopgtable_store_entry failed: %d\n", ret); |
f626b52d | 1064 | |
b4550d41 | 1065 | return ret; |
f626b52d OBC |
1066 | } |
1067 | ||
5009065d OBC |
1068 | static size_t omap_iommu_unmap(struct iommu_domain *domain, unsigned long da, |
1069 | size_t size) | |
f626b52d OBC |
1070 | { |
1071 | struct omap_iommu_domain *omap_domain = domain->priv; | |
6c32df43 | 1072 | struct omap_iommu *oiommu = omap_domain->iommu_dev; |
f626b52d | 1073 | struct device *dev = oiommu->dev; |
f626b52d | 1074 | |
5009065d | 1075 | dev_dbg(dev, "unmapping da 0x%lx size %u\n", da, size); |
f626b52d | 1076 | |
5009065d | 1077 | return iopgtable_clear_entry(oiommu, da); |
f626b52d OBC |
1078 | } |
1079 | ||
1080 | static int | |
1081 | omap_iommu_attach_dev(struct iommu_domain *domain, struct device *dev) | |
1082 | { | |
1083 | struct omap_iommu_domain *omap_domain = domain->priv; | |
6c32df43 | 1084 | struct omap_iommu *oiommu; |
fabdbca8 | 1085 | struct omap_iommu_arch_data *arch_data = dev->archdata.iommu; |
f626b52d OBC |
1086 | int ret = 0; |
1087 | ||
1088 | spin_lock(&omap_domain->lock); | |
1089 | ||
1090 | /* only a single device is supported per domain for now */ | |
1091 | if (omap_domain->iommu_dev) { | |
1092 | dev_err(dev, "iommu domain is already attached\n"); | |
1093 | ret = -EBUSY; | |
1094 | goto out; | |
1095 | } | |
1096 | ||
1097 | /* get a handle to and enable the omap iommu */ | |
fabdbca8 | 1098 | oiommu = omap_iommu_attach(arch_data->name, omap_domain->pgtable); |
f626b52d OBC |
1099 | if (IS_ERR(oiommu)) { |
1100 | ret = PTR_ERR(oiommu); | |
1101 | dev_err(dev, "can't get omap iommu: %d\n", ret); | |
1102 | goto out; | |
1103 | } | |
1104 | ||
fabdbca8 | 1105 | omap_domain->iommu_dev = arch_data->iommu_dev = oiommu; |
803b5277 | 1106 | omap_domain->dev = dev; |
e7f10f02 | 1107 | oiommu->domain = domain; |
f626b52d OBC |
1108 | |
1109 | out: | |
1110 | spin_unlock(&omap_domain->lock); | |
1111 | return ret; | |
1112 | } | |
1113 | ||
803b5277 ORL |
1114 | static void _omap_iommu_detach_dev(struct omap_iommu_domain *omap_domain, |
1115 | struct device *dev) | |
f626b52d | 1116 | { |
fabdbca8 | 1117 | struct omap_iommu *oiommu = dev_to_omap_iommu(dev); |
803b5277 | 1118 | struct omap_iommu_arch_data *arch_data = dev->archdata.iommu; |
f626b52d OBC |
1119 | |
1120 | /* only a single device is supported per domain for now */ | |
1121 | if (omap_domain->iommu_dev != oiommu) { | |
1122 | dev_err(dev, "invalid iommu device\n"); | |
803b5277 | 1123 | return; |
f626b52d OBC |
1124 | } |
1125 | ||
1126 | iopgtable_clear_entry_all(oiommu); | |
1127 | ||
1128 | omap_iommu_detach(oiommu); | |
1129 | ||
fabdbca8 | 1130 | omap_domain->iommu_dev = arch_data->iommu_dev = NULL; |
803b5277 ORL |
1131 | omap_domain->dev = NULL; |
1132 | } | |
f626b52d | 1133 | |
803b5277 ORL |
1134 | static void omap_iommu_detach_dev(struct iommu_domain *domain, |
1135 | struct device *dev) | |
1136 | { | |
1137 | struct omap_iommu_domain *omap_domain = domain->priv; | |
1138 | ||
1139 | spin_lock(&omap_domain->lock); | |
1140 | _omap_iommu_detach_dev(omap_domain, dev); | |
f626b52d OBC |
1141 | spin_unlock(&omap_domain->lock); |
1142 | } | |
1143 | ||
1144 | static int omap_iommu_domain_init(struct iommu_domain *domain) | |
1145 | { | |
1146 | struct omap_iommu_domain *omap_domain; | |
1147 | ||
1148 | omap_domain = kzalloc(sizeof(*omap_domain), GFP_KERNEL); | |
1149 | if (!omap_domain) { | |
1150 | pr_err("kzalloc failed\n"); | |
1151 | goto out; | |
1152 | } | |
1153 | ||
1154 | omap_domain->pgtable = kzalloc(IOPGD_TABLE_SIZE, GFP_KERNEL); | |
1155 | if (!omap_domain->pgtable) { | |
1156 | pr_err("kzalloc failed\n"); | |
1157 | goto fail_nomem; | |
1158 | } | |
1159 | ||
1160 | /* | |
1161 | * should never fail, but please keep this around to ensure | |
1162 | * we keep the hardware happy | |
1163 | */ | |
1164 | BUG_ON(!IS_ALIGNED((long)omap_domain->pgtable, IOPGD_TABLE_SIZE)); | |
1165 | ||
1166 | clean_dcache_area(omap_domain->pgtable, IOPGD_TABLE_SIZE); | |
1167 | spin_lock_init(&omap_domain->lock); | |
1168 | ||
1169 | domain->priv = omap_domain; | |
1170 | ||
2c6edb0c JR |
1171 | domain->geometry.aperture_start = 0; |
1172 | domain->geometry.aperture_end = (1ULL << 32) - 1; | |
1173 | domain->geometry.force_aperture = true; | |
1174 | ||
f626b52d OBC |
1175 | return 0; |
1176 | ||
1177 | fail_nomem: | |
1178 | kfree(omap_domain); | |
1179 | out: | |
1180 | return -ENOMEM; | |
1181 | } | |
1182 | ||
f626b52d OBC |
1183 | static void omap_iommu_domain_destroy(struct iommu_domain *domain) |
1184 | { | |
1185 | struct omap_iommu_domain *omap_domain = domain->priv; | |
1186 | ||
1187 | domain->priv = NULL; | |
1188 | ||
803b5277 ORL |
1189 | /* |
1190 | * An iommu device is still attached | |
1191 | * (currently, only one device can be attached) ? | |
1192 | */ | |
1193 | if (omap_domain->iommu_dev) | |
1194 | _omap_iommu_detach_dev(omap_domain, omap_domain->dev); | |
1195 | ||
f626b52d OBC |
1196 | kfree(omap_domain->pgtable); |
1197 | kfree(omap_domain); | |
1198 | } | |
1199 | ||
1200 | static phys_addr_t omap_iommu_iova_to_phys(struct iommu_domain *domain, | |
1201 | unsigned long da) | |
1202 | { | |
1203 | struct omap_iommu_domain *omap_domain = domain->priv; | |
6c32df43 | 1204 | struct omap_iommu *oiommu = omap_domain->iommu_dev; |
f626b52d OBC |
1205 | struct device *dev = oiommu->dev; |
1206 | u32 *pgd, *pte; | |
1207 | phys_addr_t ret = 0; | |
1208 | ||
1209 | iopgtable_lookup_entry(oiommu, da, &pgd, &pte); | |
1210 | ||
1211 | if (pte) { | |
1212 | if (iopte_is_small(*pte)) | |
1213 | ret = omap_iommu_translate(*pte, da, IOPTE_MASK); | |
1214 | else if (iopte_is_large(*pte)) | |
1215 | ret = omap_iommu_translate(*pte, da, IOLARGE_MASK); | |
1216 | else | |
1a36ea81 | 1217 | dev_err(dev, "bogus pte 0x%x, da 0x%lx", *pte, da); |
f626b52d OBC |
1218 | } else { |
1219 | if (iopgd_is_section(*pgd)) | |
1220 | ret = omap_iommu_translate(*pgd, da, IOSECTION_MASK); | |
1221 | else if (iopgd_is_super(*pgd)) | |
1222 | ret = omap_iommu_translate(*pgd, da, IOSUPER_MASK); | |
1223 | else | |
1a36ea81 | 1224 | dev_err(dev, "bogus pgd 0x%x, da 0x%lx", *pgd, da); |
f626b52d OBC |
1225 | } |
1226 | ||
1227 | return ret; | |
1228 | } | |
1229 | ||
1230 | static int omap_iommu_domain_has_cap(struct iommu_domain *domain, | |
1231 | unsigned long cap) | |
1232 | { | |
1233 | return 0; | |
1234 | } | |
1235 | ||
1236 | static struct iommu_ops omap_iommu_ops = { | |
1237 | .domain_init = omap_iommu_domain_init, | |
1238 | .domain_destroy = omap_iommu_domain_destroy, | |
1239 | .attach_dev = omap_iommu_attach_dev, | |
1240 | .detach_dev = omap_iommu_detach_dev, | |
1241 | .map = omap_iommu_map, | |
1242 | .unmap = omap_iommu_unmap, | |
1243 | .iova_to_phys = omap_iommu_iova_to_phys, | |
1244 | .domain_has_cap = omap_iommu_domain_has_cap, | |
66bc8cf3 | 1245 | .pgsize_bitmap = OMAP_IOMMU_PGSIZES, |
f626b52d OBC |
1246 | }; |
1247 | ||
a9dcad5e HD |
1248 | static int __init omap_iommu_init(void) |
1249 | { | |
1250 | struct kmem_cache *p; | |
1251 | const unsigned long flags = SLAB_HWCACHE_ALIGN; | |
1252 | size_t align = 1 << 10; /* L2 pagetable alignement */ | |
1253 | ||
1254 | p = kmem_cache_create("iopte_cache", IOPTE_TABLE_SIZE, align, flags, | |
1255 | iopte_cachep_ctor); | |
1256 | if (!p) | |
1257 | return -ENOMEM; | |
1258 | iopte_cachep = p; | |
1259 | ||
a65bc64f | 1260 | bus_set_iommu(&platform_bus_type, &omap_iommu_ops); |
f626b52d | 1261 | |
a9dcad5e HD |
1262 | return platform_driver_register(&omap_iommu_driver); |
1263 | } | |
435792d9 OBC |
1264 | /* must be ready before omap3isp is probed */ |
1265 | subsys_initcall(omap_iommu_init); | |
a9dcad5e HD |
1266 | |
1267 | static void __exit omap_iommu_exit(void) | |
1268 | { | |
1269 | kmem_cache_destroy(iopte_cachep); | |
1270 | ||
1271 | platform_driver_unregister(&omap_iommu_driver); | |
1272 | } | |
1273 | module_exit(omap_iommu_exit); | |
1274 | ||
1275 | MODULE_DESCRIPTION("omap iommu: tlb and pagetable primitives"); | |
1276 | MODULE_ALIAS("platform:omap-iommu"); | |
1277 | MODULE_AUTHOR("Hiroshi DOYU, Paul Mundt and Toshihiro Kobayashi"); | |
1278 | MODULE_LICENSE("GPL v2"); |