[mirror_ubuntu-artful-kernel.git] / drivers / iommu / omap-iommu.h

/*
 * omap iommu: main structures
 *
 * Copyright (C) 2008-2009 Nokia Corporation
 *
 * Written by Hiroshi DOYU <Hiroshi.DOYU@nokia.com>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

#ifndef _OMAP_IOMMU_H
#define _OMAP_IOMMU_H

#include <linux/bitops.h>
#include <linux/iommu.h>

#define for_each_iotlb_cr(obj, n, __i, cr)				\
	for (__i = 0;							\
	     (__i < (n)) && (cr = __iotlb_read_cr((obj), __i), true);	\
	     __i++)

struct iotlb_entry {
	u32 da;
	u32 pa;
	u32 pgsz, prsvd, valid;
	u32 endian, elsz, mixed;
};

/**
 * struct omap_iommu_domain - omap iommu domain
 * @pgtable:	the page table
 * @iommu_dev:	an omap iommu device attached to this domain. only a single
 *		iommu device can be attached for now.
 * @dev:	Device using this domain.
 * @lock:	domain lock, should be taken when attaching/detaching
 * @domain:	generic domain handle used by iommu core code
 */
struct omap_iommu_domain {
	u32 *pgtable;
	struct omap_iommu *iommu_dev;
	struct device *dev;
	spinlock_t lock;
	struct iommu_domain domain;
};

struct omap_iommu {
	const char	*name;
	void __iomem	*regbase;
	struct regmap	*syscfg;
	struct device	*dev;
	struct iommu_domain *domain;
	struct dentry	*debug_dir;

	spinlock_t	iommu_lock;	/* global for this whole object */

	/*
	 * We don't change iopgd for a situation like pgd for a task,
	 * but share it globally for each iommu.
	 */
	u32		*iopgd;
	spinlock_t	page_table_lock; /* protect iopgd */

	int		nr_tlb_entries;

	void *ctx; /* iommu context: registres saved area */

	int has_bus_err_back;
	u32 id;

	struct iommu_device iommu;
	struct iommu_group *group;
};

/**
 * struct omap_iommu_arch_data - omap iommu private data
 * @iommu_dev: handle of the iommu device
 *
 * This is an omap iommu private data object, which binds an iommu user
 * to its iommu device. This object should be placed at the iommu user's
 * dev_archdata so generic IOMMU API can be used without having to
 * utilize omap-specific plumbing anymore.
 */
struct omap_iommu_arch_data {
	struct omap_iommu *iommu_dev;
};

struct cr_regs {
	u32 cam;
	u32 ram;
};

struct iotlb_lock {
	short base;
	short vict;
};

/**
 * dev_to_omap_iommu() - retrieves an omap iommu object from a user device
 * @dev: iommu client device
 */
static inline struct omap_iommu *dev_to_omap_iommu(struct device *dev)
{
	struct omap_iommu_arch_data *arch_data = dev->archdata.iommu;

	return arch_data->iommu_dev;
}

/*
 * MMU Register offsets
 */
#define MMU_REVISION		0x00
#define MMU_IRQSTATUS		0x18
#define MMU_IRQENABLE		0x1c
#define MMU_WALKING_ST		0x40
#define MMU_CNTL		0x44
#define MMU_FAULT_AD		0x48
#define MMU_TTB			0x4c
#define MMU_LOCK		0x50
#define MMU_LD_TLB		0x54
#define MMU_CAM			0x58
#define MMU_RAM			0x5c
#define MMU_GFLUSH		0x60
#define MMU_FLUSH_ENTRY		0x64
#define MMU_READ_CAM		0x68
#define MMU_READ_RAM		0x6c
#define MMU_EMU_FAULT_AD	0x70
#define MMU_GP_REG		0x88

#define MMU_REG_SIZE		256

/*
 * MMU Register bit definitions
 */
/* IRQSTATUS & IRQENABLE */
#define MMU_IRQ_MULTIHITFAULT	BIT(4)
#define MMU_IRQ_TABLEWALKFAULT	BIT(3)
#define MMU_IRQ_EMUMISS		BIT(2)
#define MMU_IRQ_TRANSLATIONFAULT	BIT(1)
#define MMU_IRQ_TLBMISS		BIT(0)

#define __MMU_IRQ_FAULT		\
	(MMU_IRQ_MULTIHITFAULT | MMU_IRQ_EMUMISS | MMU_IRQ_TRANSLATIONFAULT)
#define MMU_IRQ_MASK		\
	(__MMU_IRQ_FAULT | MMU_IRQ_TABLEWALKFAULT | MMU_IRQ_TLBMISS)
#define MMU_IRQ_TWL_MASK	(__MMU_IRQ_FAULT | MMU_IRQ_TABLEWALKFAULT)
#define MMU_IRQ_TLB_MISS_MASK	(__MMU_IRQ_FAULT | MMU_IRQ_TLBMISS)

/* MMU_CNTL */
#define MMU_CNTL_SHIFT		1
#define MMU_CNTL_MASK		(7 << MMU_CNTL_SHIFT)
#define MMU_CNTL_EML_TLB	BIT(3)
#define MMU_CNTL_TWL_EN		BIT(2)
#define MMU_CNTL_MMU_EN		BIT(1)

/* CAM */
#define MMU_CAM_VATAG_SHIFT	12
#define MMU_CAM_VATAG_MASK \
	((~0UL >> MMU_CAM_VATAG_SHIFT) << MMU_CAM_VATAG_SHIFT)
#define MMU_CAM_P		BIT(3)
#define MMU_CAM_V		BIT(2)
#define MMU_CAM_PGSZ_MASK	3
#define MMU_CAM_PGSZ_1M		(0 << 0)
#define MMU_CAM_PGSZ_64K	(1 << 0)
#define MMU_CAM_PGSZ_4K		(2 << 0)
#define MMU_CAM_PGSZ_16M	(3 << 0)

/* RAM */
#define MMU_RAM_PADDR_SHIFT	12
#define MMU_RAM_PADDR_MASK \
	((~0UL >> MMU_RAM_PADDR_SHIFT) << MMU_RAM_PADDR_SHIFT)

#define MMU_RAM_ENDIAN_SHIFT	9
#define MMU_RAM_ENDIAN_MASK	BIT(MMU_RAM_ENDIAN_SHIFT)
#define MMU_RAM_ENDIAN_LITTLE	(0 << MMU_RAM_ENDIAN_SHIFT)
#define MMU_RAM_ENDIAN_BIG	BIT(MMU_RAM_ENDIAN_SHIFT)

#define MMU_RAM_ELSZ_SHIFT	7
#define MMU_RAM_ELSZ_MASK	(3 << MMU_RAM_ELSZ_SHIFT)
#define MMU_RAM_ELSZ_8		(0 << MMU_RAM_ELSZ_SHIFT)
#define MMU_RAM_ELSZ_16		(1 << MMU_RAM_ELSZ_SHIFT)
#define MMU_RAM_ELSZ_32		(2 << MMU_RAM_ELSZ_SHIFT)
#define MMU_RAM_ELSZ_NONE	(3 << MMU_RAM_ELSZ_SHIFT)
#define MMU_RAM_MIXED_SHIFT	6
#define MMU_RAM_MIXED_MASK	BIT(MMU_RAM_MIXED_SHIFT)
#define MMU_RAM_MIXED		MMU_RAM_MIXED_MASK

#define MMU_GP_REG_BUS_ERR_BACK_EN	0x1

#define get_cam_va_mask(pgsz)				\
	(((pgsz) == MMU_CAM_PGSZ_16M) ? 0xff000000 :	\
	 ((pgsz) == MMU_CAM_PGSZ_1M)  ? 0xfff00000 :	\
	 ((pgsz) == MMU_CAM_PGSZ_64K) ? 0xffff0000 :	\
	 ((pgsz) == MMU_CAM_PGSZ_4K)  ? 0xfffff000 : 0)

/*
 * DSP_SYSTEM registers and bit definitions (applicable only for DRA7xx DSP)
 */
#define DSP_SYS_REVISION		0x00
#define DSP_SYS_MMU_CONFIG		0x18
#define DSP_SYS_MMU_CONFIG_EN_SHIFT	4

/*
 * utilities for super page(16MB, 1MB, 64KB and 4KB)
 */

#define iopgsz_max(bytes)			\
	(((bytes) >= SZ_16M) ? SZ_16M :		\
	 ((bytes) >= SZ_1M)  ? SZ_1M  :		\
	 ((bytes) >= SZ_64K) ? SZ_64K :		\
	 ((bytes) >= SZ_4K)  ? SZ_4K  :	0)

#define bytes_to_iopgsz(bytes)				\
	(((bytes) == SZ_16M) ? MMU_CAM_PGSZ_16M :	\
	 ((bytes) == SZ_1M)  ? MMU_CAM_PGSZ_1M  :	\
	 ((bytes) == SZ_64K) ? MMU_CAM_PGSZ_64K :	\
	 ((bytes) == SZ_4K)  ? MMU_CAM_PGSZ_4K  : -1)

#define iopgsz_to_bytes(iopgsz)				\
	(((iopgsz) == MMU_CAM_PGSZ_16M)	? SZ_16M :	\
	 ((iopgsz) == MMU_CAM_PGSZ_1M)	? SZ_1M  :	\
	 ((iopgsz) == MMU_CAM_PGSZ_64K)	? SZ_64K :	\
	 ((iopgsz) == MMU_CAM_PGSZ_4K)	? SZ_4K  : 0)

#define iopgsz_ok(bytes) (bytes_to_iopgsz(bytes) >= 0)

/*
 * global functions
 */

struct cr_regs __iotlb_read_cr(struct omap_iommu *obj, int n);
void iotlb_lock_get(struct omap_iommu *obj, struct iotlb_lock *l);
void iotlb_lock_set(struct omap_iommu *obj, struct iotlb_lock *l);

#ifdef CONFIG_OMAP_IOMMU_DEBUG
void omap_iommu_debugfs_init(void);
void omap_iommu_debugfs_exit(void);

void omap_iommu_debugfs_add(struct omap_iommu *obj);
void omap_iommu_debugfs_remove(struct omap_iommu *obj);
#else
static inline void omap_iommu_debugfs_init(void) { }
static inline void omap_iommu_debugfs_exit(void) { }

static inline void omap_iommu_debugfs_add(struct omap_iommu *obj) { }
static inline void omap_iommu_debugfs_remove(struct omap_iommu *obj) { }
#endif

/*
 * register accessors
 */
static inline u32 iommu_read_reg(struct omap_iommu *obj, size_t offs)
{
	return __raw_readl(obj->regbase + offs);
}

static inline void iommu_write_reg(struct omap_iommu *obj, u32 val, size_t offs)
{
	__raw_writel(val, obj->regbase + offs);
}

static inline int iotlb_cr_valid(struct cr_regs *cr)
{
	if (!cr)
		return -EINVAL;

	return cr->cam & MMU_CAM_V;
}

#endif /* _OMAP_IOMMU_H */
Commit	Line	Data
ed1c7de2 TL	1	/*
	2	* omap iommu: main structures
	3	*
	4	* Copyright (C) 2008-2009 Nokia Corporation
	5	*
	6	* Written by Hiroshi DOYU <Hiroshi.DOYU@nokia.com>
	7	*
	8	* This program is free software; you can redistribute it and/or modify
	9	* it under the terms of the GNU General Public License version 2 as
	10	* published by the Free Software Foundation.
	11	*/
	12
533b40cc SA	13	#ifndef _OMAP_IOMMU_H
	14	#define _OMAP_IOMMU_H
	15
eb642a3f	16	#include <linux/bitops.h>
e73b7afe	17	#include <linux/iommu.h>
eb642a3f	18
69c2c196 SA	19	#define for_each_iotlb_cr(obj, n, __i, cr) \
	20	for (__i = 0; \
	21	(__i < (n)) && (cr = __iotlb_read_cr((obj), __i), true); \
	22	__i++)
	23
ed1c7de2 TL	24	struct iotlb_entry {
	25	u32 da;
	26	u32 pa;
	27	u32 pgsz, prsvd, valid;
dc308f9f	28	u32 endian, elsz, mixed;
ed1c7de2 TL	29	};
ed1c7de2 TL	30
e73b7afe JR	31	/**
	32	* struct omap_iommu_domain - omap iommu domain
	33	* @pgtable: the page table
	34	* @iommu_dev: an omap iommu device attached to this domain. only a single
	35	* iommu device can be attached for now.
	36	* @dev: Device using this domain.
	37	* @lock: domain lock, should be taken when attaching/detaching
	38	* @domain: generic domain handle used by iommu core code
	39	*/
	40	struct omap_iommu_domain {
	41	u32 *pgtable;
	42	struct omap_iommu *iommu_dev;
	43	struct device *dev;
	44	spinlock_t lock;
	45	struct iommu_domain domain;
	46	};
	47
ed1c7de2 TL	48	struct omap_iommu {
ed1c7de2 TL	49	const char *name;
ed1c7de2	50	void __iomem *regbase;
3ca9299e	51	struct regmap *syscfg;
ed1c7de2	52	struct device *dev;
ed1c7de2	53	struct iommu_domain *domain;
61c75352	54	struct dentry *debug_dir;
ed1c7de2	55
ed1c7de2 TL	56	spinlock_t iommu_lock; /* global for this whole object */
	57
	58	/*
	59	* We don't change iopgd for a situation like pgd for a task,
	60	* but share it globally for each iommu.
	61	*/
	62	u32 *iopgd;
	63	spinlock_t page_table_lock; /* protect iopgd */
	64
	65	int nr_tlb_entries;
	66
ed1c7de2	67	void ctx; / iommu context: registres saved area */
b148d5fb SA	68
b148d5fb SA	69	int has_bus_err_back;
3ca9299e	70	u32 id;
01611fe8 JR	71
01611fe8 JR	72	struct iommu_device iommu;
28ae1e3e	73	struct iommu_group *group;
ed1c7de2 TL	74	};
ed1c7de2 TL	75
e73b7afe JR	76	/**
e73b7afe JR	77	* struct omap_iommu_arch_data - omap iommu private data
e73b7afe JR	78	* @iommu_dev: handle of the iommu device
	79	*
	80	* This is an omap iommu private data object, which binds an iommu user
	81	* to its iommu device. This object should be placed at the iommu user's
	82	* dev_archdata so generic IOMMU API can be used without having to
	83	* utilize omap-specific plumbing anymore.
	84	*/
	85	struct omap_iommu_arch_data {
e73b7afe JR	86	struct omap_iommu *iommu_dev;
	87	};
	88
ed1c7de2	89	struct cr_regs {
dc308f9f SA	90	u32 cam;
dc308f9f SA	91	u32 ram;
ed1c7de2 TL	92	};
ed1c7de2 TL	93
69c2c196 SA	94	struct iotlb_lock {
	95	short base;
	96	short vict;
	97	};
	98
ed1c7de2 TL	99	/**
	100	* dev_to_omap_iommu() - retrieves an omap iommu object from a user device
	101	* @dev: iommu client device
	102	*/
	103	static inline struct omap_iommu dev_to_omap_iommu(struct device dev)
	104	{
	105	struct omap_iommu_arch_data *arch_data = dev->archdata.iommu;
	106
	107	return arch_data->iommu_dev;
	108	}
ed1c7de2	109
ed1c7de2 TL	110	/*
	111	* MMU Register offsets
	112	*/
	113	#define MMU_REVISION 0x00
ed1c7de2 TL	114	#define MMU_IRQSTATUS 0x18
	115	#define MMU_IRQENABLE 0x1c
	116	#define MMU_WALKING_ST 0x40
	117	#define MMU_CNTL 0x44
	118	#define MMU_FAULT_AD 0x48
	119	#define MMU_TTB 0x4c
	120	#define MMU_LOCK 0x50
	121	#define MMU_LD_TLB 0x54
	122	#define MMU_CAM 0x58
	123	#define MMU_RAM 0x5c
	124	#define MMU_GFLUSH 0x60
	125	#define MMU_FLUSH_ENTRY 0x64
	126	#define MMU_READ_CAM 0x68
	127	#define MMU_READ_RAM 0x6c
	128	#define MMU_EMU_FAULT_AD 0x70
b148d5fb	129	#define MMU_GP_REG 0x88
ed1c7de2 TL	130
	131	#define MMU_REG_SIZE 256
	132
	133	/*
	134	* MMU Register bit definitions
	135	*/
bd4396f0	136	/* IRQSTATUS & IRQENABLE */
eb642a3f SA	137	#define MMU_IRQ_MULTIHITFAULT BIT(4)
	138	#define MMU_IRQ_TABLEWALKFAULT BIT(3)
	139	#define MMU_IRQ_EMUMISS BIT(2)
	140	#define MMU_IRQ_TRANSLATIONFAULT BIT(1)
	141	#define MMU_IRQ_TLBMISS BIT(0)
bd4396f0 SA	142
	143	#define __MMU_IRQ_FAULT \
	144	(MMU_IRQ_MULTIHITFAULT \| MMU_IRQ_EMUMISS \| MMU_IRQ_TRANSLATIONFAULT)
	145	#define MMU_IRQ_MASK \
	146	(__MMU_IRQ_FAULT \| MMU_IRQ_TABLEWALKFAULT \| MMU_IRQ_TLBMISS)
	147	#define MMU_IRQ_TWL_MASK (__MMU_IRQ_FAULT \| MMU_IRQ_TABLEWALKFAULT)
	148	#define MMU_IRQ_TLB_MISS_MASK (__MMU_IRQ_FAULT \| MMU_IRQ_TLBMISS)
	149
	150	/* MMU_CNTL */
	151	#define MMU_CNTL_SHIFT 1
	152	#define MMU_CNTL_MASK (7 << MMU_CNTL_SHIFT)
eb642a3f SA	153	#define MMU_CNTL_EML_TLB BIT(3)
	154	#define MMU_CNTL_TWL_EN BIT(2)
	155	#define MMU_CNTL_MMU_EN BIT(1)
bd4396f0 SA	156
bd4396f0 SA	157	/* CAM */
ed1c7de2 TL	158	#define MMU_CAM_VATAG_SHIFT 12
	159	#define MMU_CAM_VATAG_MASK \
	160	((~0UL >> MMU_CAM_VATAG_SHIFT) << MMU_CAM_VATAG_SHIFT)
eb642a3f SA	161	#define MMU_CAM_P BIT(3)
eb642a3f SA	162	#define MMU_CAM_V BIT(2)
ed1c7de2 TL	163	#define MMU_CAM_PGSZ_MASK 3
	164	#define MMU_CAM_PGSZ_1M (0 << 0)
	165	#define MMU_CAM_PGSZ_64K (1 << 0)
	166	#define MMU_CAM_PGSZ_4K (2 << 0)
	167	#define MMU_CAM_PGSZ_16M (3 << 0)
	168
bd4396f0	169	/* RAM */
ed1c7de2 TL	170	#define MMU_RAM_PADDR_SHIFT 12
	171	#define MMU_RAM_PADDR_MASK \
	172	((~0UL >> MMU_RAM_PADDR_SHIFT) << MMU_RAM_PADDR_SHIFT)
	173
baaa7b5d	174	#define MMU_RAM_ENDIAN_SHIFT 9
eb642a3f	175	#define MMU_RAM_ENDIAN_MASK BIT(MMU_RAM_ENDIAN_SHIFT)
baaa7b5d	176	#define MMU_RAM_ENDIAN_LITTLE (0 << MMU_RAM_ENDIAN_SHIFT)
eb642a3f	177	#define MMU_RAM_ENDIAN_BIG BIT(MMU_RAM_ENDIAN_SHIFT)
ed1c7de2	178
baaa7b5d	179	#define MMU_RAM_ELSZ_SHIFT 7
ed1c7de2 TL	180	#define MMU_RAM_ELSZ_MASK (3 << MMU_RAM_ELSZ_SHIFT)
	181	#define MMU_RAM_ELSZ_8 (0 << MMU_RAM_ELSZ_SHIFT)
	182	#define MMU_RAM_ELSZ_16 (1 << MMU_RAM_ELSZ_SHIFT)
	183	#define MMU_RAM_ELSZ_32 (2 << MMU_RAM_ELSZ_SHIFT)
	184	#define MMU_RAM_ELSZ_NONE (3 << MMU_RAM_ELSZ_SHIFT)
	185	#define MMU_RAM_MIXED_SHIFT 6
eb642a3f	186	#define MMU_RAM_MIXED_MASK BIT(MMU_RAM_MIXED_SHIFT)
ed1c7de2 TL	187	#define MMU_RAM_MIXED MMU_RAM_MIXED_MASK
ed1c7de2 TL	188
b148d5fb SA	189	#define MMU_GP_REG_BUS_ERR_BACK_EN 0x1
b148d5fb SA	190
bd4396f0 SA	191	#define get_cam_va_mask(pgsz) \
	192	(((pgsz) == MMU_CAM_PGSZ_16M) ? 0xff000000 : \
	193	((pgsz) == MMU_CAM_PGSZ_1M) ? 0xfff00000 : \
	194	((pgsz) == MMU_CAM_PGSZ_64K) ? 0xffff0000 : \
	195	((pgsz) == MMU_CAM_PGSZ_4K) ? 0xfffff000 : 0)
	196
3ca9299e SA	197	/*
	198	* DSP_SYSTEM registers and bit definitions (applicable only for DRA7xx DSP)
	199	*/
	200	#define DSP_SYS_REVISION 0x00
	201	#define DSP_SYS_MMU_CONFIG 0x18
	202	#define DSP_SYS_MMU_CONFIG_EN_SHIFT 4
	203
ed1c7de2 TL	204	/*
	205	* utilities for super page(16MB, 1MB, 64KB and 4KB)
	206	*/
	207
	208	#define iopgsz_max(bytes) \
	209	(((bytes) >= SZ_16M) ? SZ_16M : \
	210	((bytes) >= SZ_1M) ? SZ_1M : \
	211	((bytes) >= SZ_64K) ? SZ_64K : \
	212	((bytes) >= SZ_4K) ? SZ_4K : 0)
	213
	214	#define bytes_to_iopgsz(bytes) \
	215	(((bytes) == SZ_16M) ? MMU_CAM_PGSZ_16M : \
	216	((bytes) == SZ_1M) ? MMU_CAM_PGSZ_1M : \
	217	((bytes) == SZ_64K) ? MMU_CAM_PGSZ_64K : \
	218	((bytes) == SZ_4K) ? MMU_CAM_PGSZ_4K : -1)
	219
	220	#define iopgsz_to_bytes(iopgsz) \
	221	(((iopgsz) == MMU_CAM_PGSZ_16M) ? SZ_16M : \
	222	((iopgsz) == MMU_CAM_PGSZ_1M) ? SZ_1M : \
	223	((iopgsz) == MMU_CAM_PGSZ_64K) ? SZ_64K : \
	224	((iopgsz) == MMU_CAM_PGSZ_4K) ? SZ_4K : 0)
	225
	226	#define iopgsz_ok(bytes) (bytes_to_iopgsz(bytes) >= 0)
	227
	228	/*
	229	* global functions
	230	*/
ed1c7de2	231
69c2c196 SA	232	struct cr_regs __iotlb_read_cr(struct omap_iommu *obj, int n);
	233	void iotlb_lock_get(struct omap_iommu obj, struct iotlb_lock l);
	234	void iotlb_lock_set(struct omap_iommu obj, struct iotlb_lock l);
	235
	236	#ifdef CONFIG_OMAP_IOMMU_DEBUG
61c75352 SA	237	void omap_iommu_debugfs_init(void);
	238	void omap_iommu_debugfs_exit(void);
	239
	240	void omap_iommu_debugfs_add(struct omap_iommu *obj);
	241	void omap_iommu_debugfs_remove(struct omap_iommu *obj);
	242	#else
	243	static inline void omap_iommu_debugfs_init(void) { }
	244	static inline void omap_iommu_debugfs_exit(void) { }
	245
	246	static inline void omap_iommu_debugfs_add(struct omap_iommu *obj) { }
	247	static inline void omap_iommu_debugfs_remove(struct omap_iommu *obj) { }
	248	#endif
	249
ed1c7de2 TL	250	/*
	251	* register accessors
	252	*/
	253	static inline u32 iommu_read_reg(struct omap_iommu *obj, size_t offs)
	254	{
	255	return __raw_readl(obj->regbase + offs);
	256	}
	257
	258	static inline void iommu_write_reg(struct omap_iommu *obj, u32 val, size_t offs)
	259	{
	260	__raw_writel(val, obj->regbase + offs);
	261	}
533b40cc	262
69c2c196 SA	263	static inline int iotlb_cr_valid(struct cr_regs *cr)
	264	{
	265	if (!cr)
	266	return -EINVAL;
	267
	268	return cr->cam & MMU_CAM_V;
	269	}
	270
533b40cc	271	#endif /* _OMAP_IOMMU_H */