[mirror_ubuntu-hirsute-kernel.git] / drivers / iommu / omap-iommu.h

/* SPDX-License-Identifier: GPL-2.0-only */
/*
 * omap iommu: main structures
 *
 * Copyright (C) 2008-2009 Nokia Corporation
 *
 * Written by Hiroshi DOYU <Hiroshi.DOYU@nokia.com>
 */

#ifndef _OMAP_IOMMU_H
#define _OMAP_IOMMU_H

#include <linux/bitops.h>
#include <linux/iommu.h>

#define for_each_iotlb_cr(obj, n, __i, cr)				\
	for (__i = 0;							\
	     (__i < (n)) && (cr = __iotlb_read_cr((obj), __i), true);	\
	     __i++)

struct iotlb_entry {
	u32 da;
	u32 pa;
	u32 pgsz, prsvd, valid;
	u32 endian, elsz, mixed;
};

/**
 * struct omap_iommu_device - omap iommu device data
 * @pgtable:	page table used by an omap iommu attached to a domain
 * @iommu_dev:	pointer to store an omap iommu instance attached to a domain
 */
struct omap_iommu_device {
	u32 *pgtable;
	struct omap_iommu *iommu_dev;
};

/**
 * struct omap_iommu_domain - omap iommu domain
 * @num_iommus: number of iommus in this domain
 * @iommus:	omap iommu device data for all iommus in this domain
 * @dev:	Device using this domain.
 * @lock:	domain lock, should be taken when attaching/detaching
 * @domain:	generic domain handle used by iommu core code
 */
struct omap_iommu_domain {
	u32 num_iommus;
	struct omap_iommu_device *iommus;
	struct device *dev;
	spinlock_t lock;
	struct iommu_domain domain;
};

struct omap_iommu {
	const char	*name;
	void __iomem	*regbase;
	struct regmap	*syscfg;
	struct device	*dev;
	struct iommu_domain *domain;
	struct dentry	*debug_dir;

	spinlock_t	iommu_lock;	/* global for this whole object */

	/*
	 * We don't change iopgd for a situation like pgd for a task,
	 * but share it globally for each iommu.
	 */
	u32		*iopgd;
	spinlock_t	page_table_lock; /* protect iopgd */
	dma_addr_t	pd_dma;

	int		nr_tlb_entries;

	void *ctx; /* iommu context: registres saved area */

	int has_bus_err_back;
	u32 id;

	struct iommu_device iommu;
	struct iommu_group *group;
};

/**
 * struct omap_iommu_arch_data - omap iommu private data
 * @iommu_dev: handle of the iommu device
 *
 * This is an omap iommu private data object, which binds an iommu user
 * to its iommu device. This object should be placed at the iommu user's
 * dev_archdata so generic IOMMU API can be used without having to
 * utilize omap-specific plumbing anymore.
 */
struct omap_iommu_arch_data {
	struct omap_iommu *iommu_dev;
};

struct cr_regs {
	u32 cam;
	u32 ram;
};

struct iotlb_lock {
	short base;
	short vict;
};

/*
 * MMU Register offsets
 */
#define MMU_REVISION		0x00
#define MMU_IRQSTATUS		0x18
#define MMU_IRQENABLE		0x1c
#define MMU_WALKING_ST		0x40
#define MMU_CNTL		0x44
#define MMU_FAULT_AD		0x48
#define MMU_TTB			0x4c
#define MMU_LOCK		0x50
#define MMU_LD_TLB		0x54
#define MMU_CAM			0x58
#define MMU_RAM			0x5c
#define MMU_GFLUSH		0x60
#define MMU_FLUSH_ENTRY		0x64
#define MMU_READ_CAM		0x68
#define MMU_READ_RAM		0x6c
#define MMU_EMU_FAULT_AD	0x70
#define MMU_GP_REG		0x88

#define MMU_REG_SIZE		256

/*
 * MMU Register bit definitions
 */
/* IRQSTATUS & IRQENABLE */
#define MMU_IRQ_MULTIHITFAULT	BIT(4)
#define MMU_IRQ_TABLEWALKFAULT	BIT(3)
#define MMU_IRQ_EMUMISS		BIT(2)
#define MMU_IRQ_TRANSLATIONFAULT	BIT(1)
#define MMU_IRQ_TLBMISS		BIT(0)

#define __MMU_IRQ_FAULT		\
	(MMU_IRQ_MULTIHITFAULT | MMU_IRQ_EMUMISS | MMU_IRQ_TRANSLATIONFAULT)
#define MMU_IRQ_MASK		\
	(__MMU_IRQ_FAULT | MMU_IRQ_TABLEWALKFAULT | MMU_IRQ_TLBMISS)
#define MMU_IRQ_TWL_MASK	(__MMU_IRQ_FAULT | MMU_IRQ_TABLEWALKFAULT)
#define MMU_IRQ_TLB_MISS_MASK	(__MMU_IRQ_FAULT | MMU_IRQ_TLBMISS)

/* MMU_CNTL */
#define MMU_CNTL_SHIFT		1
#define MMU_CNTL_MASK		(7 << MMU_CNTL_SHIFT)
#define MMU_CNTL_EML_TLB	BIT(3)
#define MMU_CNTL_TWL_EN		BIT(2)
#define MMU_CNTL_MMU_EN		BIT(1)

/* CAM */
#define MMU_CAM_VATAG_SHIFT	12
#define MMU_CAM_VATAG_MASK \
	((~0UL >> MMU_CAM_VATAG_SHIFT) << MMU_CAM_VATAG_SHIFT)
#define MMU_CAM_P		BIT(3)
#define MMU_CAM_V		BIT(2)
#define MMU_CAM_PGSZ_MASK	3
#define MMU_CAM_PGSZ_1M		(0 << 0)
#define MMU_CAM_PGSZ_64K	(1 << 0)
#define MMU_CAM_PGSZ_4K		(2 << 0)
#define MMU_CAM_PGSZ_16M	(3 << 0)

/* RAM */
#define MMU_RAM_PADDR_SHIFT	12
#define MMU_RAM_PADDR_MASK \
	((~0UL >> MMU_RAM_PADDR_SHIFT) << MMU_RAM_PADDR_SHIFT)

#define MMU_RAM_ENDIAN_SHIFT	9
#define MMU_RAM_ENDIAN_MASK	BIT(MMU_RAM_ENDIAN_SHIFT)
#define MMU_RAM_ENDIAN_LITTLE	(0 << MMU_RAM_ENDIAN_SHIFT)
#define MMU_RAM_ENDIAN_BIG	BIT(MMU_RAM_ENDIAN_SHIFT)

#define MMU_RAM_ELSZ_SHIFT	7
#define MMU_RAM_ELSZ_MASK	(3 << MMU_RAM_ELSZ_SHIFT)
#define MMU_RAM_ELSZ_8		(0 << MMU_RAM_ELSZ_SHIFT)
#define MMU_RAM_ELSZ_16		(1 << MMU_RAM_ELSZ_SHIFT)
#define MMU_RAM_ELSZ_32		(2 << MMU_RAM_ELSZ_SHIFT)
#define MMU_RAM_ELSZ_NONE	(3 << MMU_RAM_ELSZ_SHIFT)
#define MMU_RAM_MIXED_SHIFT	6
#define MMU_RAM_MIXED_MASK	BIT(MMU_RAM_MIXED_SHIFT)
#define MMU_RAM_MIXED		MMU_RAM_MIXED_MASK

#define MMU_GP_REG_BUS_ERR_BACK_EN	0x1

#define get_cam_va_mask(pgsz)				\
	(((pgsz) == MMU_CAM_PGSZ_16M) ? 0xff000000 :	\
	 ((pgsz) == MMU_CAM_PGSZ_1M)  ? 0xfff00000 :	\
	 ((pgsz) == MMU_CAM_PGSZ_64K) ? 0xffff0000 :	\
	 ((pgsz) == MMU_CAM_PGSZ_4K)  ? 0xfffff000 : 0)

/*
 * DSP_SYSTEM registers and bit definitions (applicable only for DRA7xx DSP)
 */
#define DSP_SYS_REVISION		0x00
#define DSP_SYS_MMU_CONFIG		0x18
#define DSP_SYS_MMU_CONFIG_EN_SHIFT	4

/*
 * utilities for super page(16MB, 1MB, 64KB and 4KB)
 */

#define iopgsz_max(bytes)			\
	(((bytes) >= SZ_16M) ? SZ_16M :		\
	 ((bytes) >= SZ_1M)  ? SZ_1M  :		\
	 ((bytes) >= SZ_64K) ? SZ_64K :		\
	 ((bytes) >= SZ_4K)  ? SZ_4K  :	0)

#define bytes_to_iopgsz(bytes)				\
	(((bytes) == SZ_16M) ? MMU_CAM_PGSZ_16M :	\
	 ((bytes) == SZ_1M)  ? MMU_CAM_PGSZ_1M  :	\
	 ((bytes) == SZ_64K) ? MMU_CAM_PGSZ_64K :	\
	 ((bytes) == SZ_4K)  ? MMU_CAM_PGSZ_4K  : -1)

#define iopgsz_to_bytes(iopgsz)				\
	(((iopgsz) == MMU_CAM_PGSZ_16M)	? SZ_16M :	\
	 ((iopgsz) == MMU_CAM_PGSZ_1M)	? SZ_1M  :	\
	 ((iopgsz) == MMU_CAM_PGSZ_64K)	? SZ_64K :	\
	 ((iopgsz) == MMU_CAM_PGSZ_4K)	? SZ_4K  : 0)

#define iopgsz_ok(bytes) (bytes_to_iopgsz(bytes) >= 0)

/*
 * global functions
 */

struct cr_regs __iotlb_read_cr(struct omap_iommu *obj, int n);
void iotlb_lock_get(struct omap_iommu *obj, struct iotlb_lock *l);
void iotlb_lock_set(struct omap_iommu *obj, struct iotlb_lock *l);

#ifdef CONFIG_OMAP_IOMMU_DEBUG
void omap_iommu_debugfs_init(void);
void omap_iommu_debugfs_exit(void);

void omap_iommu_debugfs_add(struct omap_iommu *obj);
void omap_iommu_debugfs_remove(struct omap_iommu *obj);
#else
static inline void omap_iommu_debugfs_init(void) { }
static inline void omap_iommu_debugfs_exit(void) { }

static inline void omap_iommu_debugfs_add(struct omap_iommu *obj) { }
static inline void omap_iommu_debugfs_remove(struct omap_iommu *obj) { }
#endif

/*
 * register accessors
 */
static inline u32 iommu_read_reg(struct omap_iommu *obj, size_t offs)
{
	return __raw_readl(obj->regbase + offs);
}

static inline void iommu_write_reg(struct omap_iommu *obj, u32 val, size_t offs)
{
	__raw_writel(val, obj->regbase + offs);
}

static inline int iotlb_cr_valid(struct cr_regs *cr)
{
	if (!cr)
		return -EINVAL;

	return cr->cam & MMU_CAM_V;
}

#endif /* _OMAP_IOMMU_H */
Commit	Line	Data
d2912cb1	1	/* SPDX-License-Identifier: GPL-2.0-only */
ed1c7de2 TL	2	/*
	3	* omap iommu: main structures
	4	*
	5	* Copyright (C) 2008-2009 Nokia Corporation
	6	*
	7	* Written by Hiroshi DOYU <Hiroshi.DOYU@nokia.com>
ed1c7de2 TL	8	*/
ed1c7de2 TL	9
533b40cc SA	10	#ifndef _OMAP_IOMMU_H
	11	#define _OMAP_IOMMU_H
	12
eb642a3f	13	#include <linux/bitops.h>
e73b7afe	14	#include <linux/iommu.h>
eb642a3f	15
69c2c196 SA	16	#define for_each_iotlb_cr(obj, n, __i, cr) \
	17	for (__i = 0; \
	18	(__i < (n)) && (cr = __iotlb_read_cr((obj), __i), true); \
	19	__i++)
	20
ed1c7de2 TL	21	struct iotlb_entry {
	22	u32 da;
	23	u32 pa;
	24	u32 pgsz, prsvd, valid;
dc308f9f	25	u32 endian, elsz, mixed;
ed1c7de2 TL	26	};
ed1c7de2 TL	27
9d5018de SA	28	/**
	29	* struct omap_iommu_device - omap iommu device data
	30	* @pgtable: page table used by an omap iommu attached to a domain
	31	* @iommu_dev: pointer to store an omap iommu instance attached to a domain
	32	*/
	33	struct omap_iommu_device {
	34	u32 *pgtable;
	35	struct omap_iommu *iommu_dev;
	36	};
	37
e73b7afe JR	38	/**
e73b7afe JR	39	* struct omap_iommu_domain - omap iommu domain
9d5018de SA	40	* @num_iommus: number of iommus in this domain
9d5018de SA	41	* @iommus: omap iommu device data for all iommus in this domain
e73b7afe JR	42	* @dev: Device using this domain.
	43	* @lock: domain lock, should be taken when attaching/detaching
	44	* @domain: generic domain handle used by iommu core code
	45	*/
	46	struct omap_iommu_domain {
9d5018de SA	47	u32 num_iommus;
9d5018de SA	48	struct omap_iommu_device *iommus;
e73b7afe JR	49	struct device *dev;
	50	spinlock_t lock;
	51	struct iommu_domain domain;
	52	};
	53
ed1c7de2 TL	54	struct omap_iommu {
ed1c7de2 TL	55	const char *name;
ed1c7de2	56	void __iomem *regbase;
3ca9299e	57	struct regmap *syscfg;
ed1c7de2	58	struct device *dev;
ed1c7de2	59	struct iommu_domain *domain;
61c75352	60	struct dentry *debug_dir;
ed1c7de2	61
ed1c7de2 TL	62	spinlock_t iommu_lock; /* global for this whole object */
	63
	64	/*
	65	* We don't change iopgd for a situation like pgd for a task,
	66	* but share it globally for each iommu.
	67	*/
	68	u32 *iopgd;
	69	spinlock_t page_table_lock; /* protect iopgd */
bfee0cf0	70	dma_addr_t pd_dma;
ed1c7de2 TL	71
	72	int nr_tlb_entries;
	73
ed1c7de2	74	void ctx; / iommu context: registres saved area */
b148d5fb SA	75
b148d5fb SA	76	int has_bus_err_back;
3ca9299e	77	u32 id;
01611fe8 JR	78
01611fe8 JR	79	struct iommu_device iommu;
28ae1e3e	80	struct iommu_group *group;
ed1c7de2 TL	81	};
ed1c7de2 TL	82
e73b7afe JR	83	/**
e73b7afe JR	84	* struct omap_iommu_arch_data - omap iommu private data
e73b7afe JR	85	* @iommu_dev: handle of the iommu device
	86	*
	87	* This is an omap iommu private data object, which binds an iommu user
	88	* to its iommu device. This object should be placed at the iommu user's
	89	* dev_archdata so generic IOMMU API can be used without having to
	90	* utilize omap-specific plumbing anymore.
	91	*/
	92	struct omap_iommu_arch_data {
e73b7afe JR	93	struct omap_iommu *iommu_dev;
	94	};
	95
ed1c7de2	96	struct cr_regs {
dc308f9f SA	97	u32 cam;
dc308f9f SA	98	u32 ram;
ed1c7de2 TL	99	};
ed1c7de2 TL	100
69c2c196 SA	101	struct iotlb_lock {
	102	short base;
	103	short vict;
	104	};
	105
ed1c7de2 TL	106	/*
	107	* MMU Register offsets
	108	*/
	109	#define MMU_REVISION 0x00
ed1c7de2 TL	110	#define MMU_IRQSTATUS 0x18
	111	#define MMU_IRQENABLE 0x1c
	112	#define MMU_WALKING_ST 0x40
	113	#define MMU_CNTL 0x44
	114	#define MMU_FAULT_AD 0x48
	115	#define MMU_TTB 0x4c
	116	#define MMU_LOCK 0x50
	117	#define MMU_LD_TLB 0x54
	118	#define MMU_CAM 0x58
	119	#define MMU_RAM 0x5c
	120	#define MMU_GFLUSH 0x60
	121	#define MMU_FLUSH_ENTRY 0x64
	122	#define MMU_READ_CAM 0x68
	123	#define MMU_READ_RAM 0x6c
	124	#define MMU_EMU_FAULT_AD 0x70
b148d5fb	125	#define MMU_GP_REG 0x88
ed1c7de2 TL	126
	127	#define MMU_REG_SIZE 256
	128
	129	/*
	130	* MMU Register bit definitions
	131	*/
bd4396f0	132	/* IRQSTATUS & IRQENABLE */
eb642a3f SA	133	#define MMU_IRQ_MULTIHITFAULT BIT(4)
	134	#define MMU_IRQ_TABLEWALKFAULT BIT(3)
	135	#define MMU_IRQ_EMUMISS BIT(2)
	136	#define MMU_IRQ_TRANSLATIONFAULT BIT(1)
	137	#define MMU_IRQ_TLBMISS BIT(0)
bd4396f0 SA	138
	139	#define __MMU_IRQ_FAULT \
	140	(MMU_IRQ_MULTIHITFAULT \| MMU_IRQ_EMUMISS \| MMU_IRQ_TRANSLATIONFAULT)
	141	#define MMU_IRQ_MASK \
	142	(__MMU_IRQ_FAULT \| MMU_IRQ_TABLEWALKFAULT \| MMU_IRQ_TLBMISS)
	143	#define MMU_IRQ_TWL_MASK (__MMU_IRQ_FAULT \| MMU_IRQ_TABLEWALKFAULT)
	144	#define MMU_IRQ_TLB_MISS_MASK (__MMU_IRQ_FAULT \| MMU_IRQ_TLBMISS)
	145
	146	/* MMU_CNTL */
	147	#define MMU_CNTL_SHIFT 1
	148	#define MMU_CNTL_MASK (7 << MMU_CNTL_SHIFT)
eb642a3f SA	149	#define MMU_CNTL_EML_TLB BIT(3)
	150	#define MMU_CNTL_TWL_EN BIT(2)
	151	#define MMU_CNTL_MMU_EN BIT(1)
bd4396f0 SA	152
bd4396f0 SA	153	/* CAM */
ed1c7de2 TL	154	#define MMU_CAM_VATAG_SHIFT 12
	155	#define MMU_CAM_VATAG_MASK \
	156	((~0UL >> MMU_CAM_VATAG_SHIFT) << MMU_CAM_VATAG_SHIFT)
eb642a3f SA	157	#define MMU_CAM_P BIT(3)
eb642a3f SA	158	#define MMU_CAM_V BIT(2)
ed1c7de2 TL	159	#define MMU_CAM_PGSZ_MASK 3
	160	#define MMU_CAM_PGSZ_1M (0 << 0)
	161	#define MMU_CAM_PGSZ_64K (1 << 0)
	162	#define MMU_CAM_PGSZ_4K (2 << 0)
	163	#define MMU_CAM_PGSZ_16M (3 << 0)
	164
bd4396f0	165	/* RAM */
ed1c7de2 TL	166	#define MMU_RAM_PADDR_SHIFT 12
	167	#define MMU_RAM_PADDR_MASK \
	168	((~0UL >> MMU_RAM_PADDR_SHIFT) << MMU_RAM_PADDR_SHIFT)
	169
baaa7b5d	170	#define MMU_RAM_ENDIAN_SHIFT 9
eb642a3f	171	#define MMU_RAM_ENDIAN_MASK BIT(MMU_RAM_ENDIAN_SHIFT)
baaa7b5d	172	#define MMU_RAM_ENDIAN_LITTLE (0 << MMU_RAM_ENDIAN_SHIFT)
eb642a3f	173	#define MMU_RAM_ENDIAN_BIG BIT(MMU_RAM_ENDIAN_SHIFT)
ed1c7de2	174
baaa7b5d	175	#define MMU_RAM_ELSZ_SHIFT 7
ed1c7de2 TL	176	#define MMU_RAM_ELSZ_MASK (3 << MMU_RAM_ELSZ_SHIFT)
	177	#define MMU_RAM_ELSZ_8 (0 << MMU_RAM_ELSZ_SHIFT)
	178	#define MMU_RAM_ELSZ_16 (1 << MMU_RAM_ELSZ_SHIFT)
	179	#define MMU_RAM_ELSZ_32 (2 << MMU_RAM_ELSZ_SHIFT)
	180	#define MMU_RAM_ELSZ_NONE (3 << MMU_RAM_ELSZ_SHIFT)
	181	#define MMU_RAM_MIXED_SHIFT 6
eb642a3f	182	#define MMU_RAM_MIXED_MASK BIT(MMU_RAM_MIXED_SHIFT)
ed1c7de2 TL	183	#define MMU_RAM_MIXED MMU_RAM_MIXED_MASK
ed1c7de2 TL	184
b148d5fb SA	185	#define MMU_GP_REG_BUS_ERR_BACK_EN 0x1
b148d5fb SA	186
bd4396f0 SA	187	#define get_cam_va_mask(pgsz) \
	188	(((pgsz) == MMU_CAM_PGSZ_16M) ? 0xff000000 : \
	189	((pgsz) == MMU_CAM_PGSZ_1M) ? 0xfff00000 : \
	190	((pgsz) == MMU_CAM_PGSZ_64K) ? 0xffff0000 : \
	191	((pgsz) == MMU_CAM_PGSZ_4K) ? 0xfffff000 : 0)
	192
3ca9299e SA	193	/*
	194	* DSP_SYSTEM registers and bit definitions (applicable only for DRA7xx DSP)
	195	*/
	196	#define DSP_SYS_REVISION 0x00
	197	#define DSP_SYS_MMU_CONFIG 0x18
	198	#define DSP_SYS_MMU_CONFIG_EN_SHIFT 4
	199
ed1c7de2 TL	200	/*
	201	* utilities for super page(16MB, 1MB, 64KB and 4KB)
	202	*/
	203
	204	#define iopgsz_max(bytes) \
	205	(((bytes) >= SZ_16M) ? SZ_16M : \
	206	((bytes) >= SZ_1M) ? SZ_1M : \
	207	((bytes) >= SZ_64K) ? SZ_64K : \
	208	((bytes) >= SZ_4K) ? SZ_4K : 0)
	209
	210	#define bytes_to_iopgsz(bytes) \
	211	(((bytes) == SZ_16M) ? MMU_CAM_PGSZ_16M : \
	212	((bytes) == SZ_1M) ? MMU_CAM_PGSZ_1M : \
	213	((bytes) == SZ_64K) ? MMU_CAM_PGSZ_64K : \
	214	((bytes) == SZ_4K) ? MMU_CAM_PGSZ_4K : -1)
	215
	216	#define iopgsz_to_bytes(iopgsz) \
	217	(((iopgsz) == MMU_CAM_PGSZ_16M) ? SZ_16M : \
	218	((iopgsz) == MMU_CAM_PGSZ_1M) ? SZ_1M : \
	219	((iopgsz) == MMU_CAM_PGSZ_64K) ? SZ_64K : \
	220	((iopgsz) == MMU_CAM_PGSZ_4K) ? SZ_4K : 0)
	221
	222	#define iopgsz_ok(bytes) (bytes_to_iopgsz(bytes) >= 0)
	223
	224	/*
	225	* global functions
	226	*/
ed1c7de2	227
69c2c196 SA	228	struct cr_regs __iotlb_read_cr(struct omap_iommu *obj, int n);
	229	void iotlb_lock_get(struct omap_iommu obj, struct iotlb_lock l);
	230	void iotlb_lock_set(struct omap_iommu obj, struct iotlb_lock l);
	231
	232	#ifdef CONFIG_OMAP_IOMMU_DEBUG
61c75352 SA	233	void omap_iommu_debugfs_init(void);
	234	void omap_iommu_debugfs_exit(void);
	235
	236	void omap_iommu_debugfs_add(struct omap_iommu *obj);
	237	void omap_iommu_debugfs_remove(struct omap_iommu *obj);
	238	#else
	239	static inline void omap_iommu_debugfs_init(void) { }
	240	static inline void omap_iommu_debugfs_exit(void) { }
	241
	242	static inline void omap_iommu_debugfs_add(struct omap_iommu *obj) { }
	243	static inline void omap_iommu_debugfs_remove(struct omap_iommu *obj) { }
	244	#endif
	245
ed1c7de2 TL	246	/*
	247	* register accessors
	248	*/
	249	static inline u32 iommu_read_reg(struct omap_iommu *obj, size_t offs)
	250	{
	251	return __raw_readl(obj->regbase + offs);
	252	}
	253
	254	static inline void iommu_write_reg(struct omap_iommu *obj, u32 val, size_t offs)
	255	{
	256	__raw_writel(val, obj->regbase + offs);
	257	}
533b40cc	258
69c2c196 SA	259	static inline int iotlb_cr_valid(struct cr_regs *cr)
	260	{
	261	if (!cr)
	262	return -EINVAL;
	263
	264	return cr->cam & MMU_CAM_V;
	265	}
	266
533b40cc	267	#endif /* _OMAP_IOMMU_H */