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Commit | Line | Data |
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d2912cb1 | 1 | // SPDX-License-Identifier: GPL-2.0-only |
7a31f6f4 | 2 | /* |
89184651 | 3 | * Copyright (C) 2011-2014 NVIDIA CORPORATION. All rights reserved. |
7a31f6f4 HD |
4 | */ |
5 | ||
804cb54c | 6 | #include <linux/bitops.h> |
d1313e78 | 7 | #include <linux/debugfs.h> |
bc5e6dea | 8 | #include <linux/err.h> |
7a31f6f4 | 9 | #include <linux/iommu.h> |
89184651 | 10 | #include <linux/kernel.h> |
0760e8fa | 11 | #include <linux/of.h> |
89184651 | 12 | #include <linux/of_device.h> |
541f29bb | 13 | #include <linux/pci.h> |
89184651 TR |
14 | #include <linux/platform_device.h> |
15 | #include <linux/slab.h> | |
404d0b30 | 16 | #include <linux/spinlock.h> |
461a6946 | 17 | #include <linux/dma-mapping.h> |
306a7f91 TR |
18 | |
19 | #include <soc/tegra/ahb.h> | |
89184651 | 20 | #include <soc/tegra/mc.h> |
7a31f6f4 | 21 | |
7f4c9176 TR |
22 | struct tegra_smmu_group { |
23 | struct list_head list; | |
1ea5440e | 24 | struct tegra_smmu *smmu; |
7f4c9176 TR |
25 | const struct tegra_smmu_group_soc *soc; |
26 | struct iommu_group *group; | |
21d3c040 | 27 | unsigned int swgroup; |
7f4c9176 TR |
28 | }; |
29 | ||
89184651 TR |
30 | struct tegra_smmu { |
31 | void __iomem *regs; | |
32 | struct device *dev; | |
e6bc5933 | 33 | |
89184651 TR |
34 | struct tegra_mc *mc; |
35 | const struct tegra_smmu_soc *soc; | |
39abf8aa | 36 | |
7f4c9176 TR |
37 | struct list_head groups; |
38 | ||
804cb54c | 39 | unsigned long pfn_mask; |
11cec15b | 40 | unsigned long tlb_mask; |
804cb54c | 41 | |
89184651 TR |
42 | unsigned long *asids; |
43 | struct mutex lock; | |
39abf8aa | 44 | |
89184651 | 45 | struct list_head list; |
d1313e78 TR |
46 | |
47 | struct dentry *debugfs; | |
0b480e44 JR |
48 | |
49 | struct iommu_device iommu; /* IOMMU Core code handle */ | |
7a31f6f4 | 50 | }; |
7a31f6f4 | 51 | |
89184651 | 52 | struct tegra_smmu_as { |
d5f1a81c | 53 | struct iommu_domain domain; |
89184651 TR |
54 | struct tegra_smmu *smmu; |
55 | unsigned int use_count; | |
404d0b30 | 56 | spinlock_t lock; |
32924c76 | 57 | u32 *count; |
853520fa | 58 | struct page **pts; |
89184651 | 59 | struct page *pd; |
e3c97196 | 60 | dma_addr_t pd_dma; |
89184651 TR |
61 | unsigned id; |
62 | u32 attr; | |
7a31f6f4 HD |
63 | }; |
64 | ||
d5f1a81c JR |
65 | static struct tegra_smmu_as *to_smmu_as(struct iommu_domain *dom) |
66 | { | |
67 | return container_of(dom, struct tegra_smmu_as, domain); | |
68 | } | |
69 | ||
89184651 TR |
70 | static inline void smmu_writel(struct tegra_smmu *smmu, u32 value, |
71 | unsigned long offset) | |
72 | { | |
73 | writel(value, smmu->regs + offset); | |
74 | } | |
7a31f6f4 | 75 | |
89184651 TR |
76 | static inline u32 smmu_readl(struct tegra_smmu *smmu, unsigned long offset) |
77 | { | |
78 | return readl(smmu->regs + offset); | |
79 | } | |
5a2c937a | 80 | |
89184651 TR |
81 | #define SMMU_CONFIG 0x010 |
82 | #define SMMU_CONFIG_ENABLE (1 << 0) | |
7a31f6f4 | 83 | |
89184651 TR |
84 | #define SMMU_TLB_CONFIG 0x14 |
85 | #define SMMU_TLB_CONFIG_HIT_UNDER_MISS (1 << 29) | |
86 | #define SMMU_TLB_CONFIG_ROUND_ROBIN_ARBITRATION (1 << 28) | |
11cec15b TR |
87 | #define SMMU_TLB_CONFIG_ACTIVE_LINES(smmu) \ |
88 | ((smmu)->soc->num_tlb_lines & (smmu)->tlb_mask) | |
0760e8fa | 89 | |
89184651 TR |
90 | #define SMMU_PTC_CONFIG 0x18 |
91 | #define SMMU_PTC_CONFIG_ENABLE (1 << 29) | |
92 | #define SMMU_PTC_CONFIG_REQ_LIMIT(x) (((x) & 0x0f) << 24) | |
93 | #define SMMU_PTC_CONFIG_INDEX_MAP(x) ((x) & 0x3f) | |
39abf8aa | 94 | |
89184651 TR |
95 | #define SMMU_PTB_ASID 0x01c |
96 | #define SMMU_PTB_ASID_VALUE(x) ((x) & 0x7f) | |
a3b24915 | 97 | |
89184651 | 98 | #define SMMU_PTB_DATA 0x020 |
e3c97196 | 99 | #define SMMU_PTB_DATA_VALUE(dma, attr) ((dma) >> 12 | (attr)) |
7a31f6f4 | 100 | |
e3c97196 | 101 | #define SMMU_MK_PDE(dma, attr) ((dma) >> SMMU_PTE_SHIFT | (attr)) |
7a31f6f4 | 102 | |
89184651 TR |
103 | #define SMMU_TLB_FLUSH 0x030 |
104 | #define SMMU_TLB_FLUSH_VA_MATCH_ALL (0 << 0) | |
105 | #define SMMU_TLB_FLUSH_VA_MATCH_SECTION (2 << 0) | |
106 | #define SMMU_TLB_FLUSH_VA_MATCH_GROUP (3 << 0) | |
89184651 TR |
107 | #define SMMU_TLB_FLUSH_VA_SECTION(addr) ((((addr) & 0xffc00000) >> 12) | \ |
108 | SMMU_TLB_FLUSH_VA_MATCH_SECTION) | |
109 | #define SMMU_TLB_FLUSH_VA_GROUP(addr) ((((addr) & 0xffffc000) >> 12) | \ | |
110 | SMMU_TLB_FLUSH_VA_MATCH_GROUP) | |
111 | #define SMMU_TLB_FLUSH_ASID_MATCH (1 << 31) | |
a6870e92 | 112 | |
89184651 TR |
113 | #define SMMU_PTC_FLUSH 0x034 |
114 | #define SMMU_PTC_FLUSH_TYPE_ALL (0 << 0) | |
115 | #define SMMU_PTC_FLUSH_TYPE_ADR (1 << 0) | |
a6870e92 | 116 | |
89184651 TR |
117 | #define SMMU_PTC_FLUSH_HI 0x9b8 |
118 | #define SMMU_PTC_FLUSH_HI_MASK 0x3 | |
7a31f6f4 | 119 | |
89184651 TR |
120 | /* per-SWGROUP SMMU_*_ASID register */ |
121 | #define SMMU_ASID_ENABLE (1 << 31) | |
122 | #define SMMU_ASID_MASK 0x7f | |
123 | #define SMMU_ASID_VALUE(x) ((x) & SMMU_ASID_MASK) | |
a6870e92 | 124 | |
89184651 TR |
125 | /* page table definitions */ |
126 | #define SMMU_NUM_PDE 1024 | |
127 | #define SMMU_NUM_PTE 1024 | |
a6870e92 | 128 | |
89184651 TR |
129 | #define SMMU_SIZE_PD (SMMU_NUM_PDE * 4) |
130 | #define SMMU_SIZE_PT (SMMU_NUM_PTE * 4) | |
7a31f6f4 | 131 | |
89184651 TR |
132 | #define SMMU_PDE_SHIFT 22 |
133 | #define SMMU_PTE_SHIFT 12 | |
fe1229b9 | 134 | |
82fa58e8 NC |
135 | #define SMMU_PAGE_MASK (~(SMMU_SIZE_PT-1)) |
136 | #define SMMU_OFFSET_IN_PAGE(x) ((unsigned long)(x) & ~SMMU_PAGE_MASK) | |
137 | #define SMMU_PFN_PHYS(x) ((phys_addr_t)(x) << SMMU_PTE_SHIFT) | |
138 | #define SMMU_PHYS_PFN(x) ((unsigned long)((x) >> SMMU_PTE_SHIFT)) | |
139 | ||
89184651 TR |
140 | #define SMMU_PD_READABLE (1 << 31) |
141 | #define SMMU_PD_WRITABLE (1 << 30) | |
142 | #define SMMU_PD_NONSECURE (1 << 29) | |
7a31f6f4 | 143 | |
89184651 TR |
144 | #define SMMU_PDE_READABLE (1 << 31) |
145 | #define SMMU_PDE_WRITABLE (1 << 30) | |
146 | #define SMMU_PDE_NONSECURE (1 << 29) | |
147 | #define SMMU_PDE_NEXT (1 << 28) | |
7a31f6f4 | 148 | |
89184651 TR |
149 | #define SMMU_PTE_READABLE (1 << 31) |
150 | #define SMMU_PTE_WRITABLE (1 << 30) | |
151 | #define SMMU_PTE_NONSECURE (1 << 29) | |
7a31f6f4 | 152 | |
89184651 TR |
153 | #define SMMU_PDE_ATTR (SMMU_PDE_READABLE | SMMU_PDE_WRITABLE | \ |
154 | SMMU_PDE_NONSECURE) | |
7a31f6f4 | 155 | |
34d35f8c RK |
156 | static unsigned int iova_pd_index(unsigned long iova) |
157 | { | |
158 | return (iova >> SMMU_PDE_SHIFT) & (SMMU_NUM_PDE - 1); | |
159 | } | |
160 | ||
161 | static unsigned int iova_pt_index(unsigned long iova) | |
162 | { | |
163 | return (iova >> SMMU_PTE_SHIFT) & (SMMU_NUM_PTE - 1); | |
164 | } | |
165 | ||
e3c97196 | 166 | static bool smmu_dma_addr_valid(struct tegra_smmu *smmu, dma_addr_t addr) |
4b3c7d10 | 167 | { |
e3c97196 RK |
168 | addr >>= 12; |
169 | return (addr & smmu->pfn_mask) == addr; | |
170 | } | |
4b3c7d10 | 171 | |
96d3ab80 | 172 | static dma_addr_t smmu_pde_to_dma(struct tegra_smmu *smmu, u32 pde) |
e3c97196 | 173 | { |
96d3ab80 | 174 | return (dma_addr_t)(pde & smmu->pfn_mask) << 12; |
4b3c7d10 RK |
175 | } |
176 | ||
b8fe0382 RK |
177 | static void smmu_flush_ptc_all(struct tegra_smmu *smmu) |
178 | { | |
179 | smmu_writel(smmu, SMMU_PTC_FLUSH_TYPE_ALL, SMMU_PTC_FLUSH); | |
180 | } | |
181 | ||
e3c97196 | 182 | static inline void smmu_flush_ptc(struct tegra_smmu *smmu, dma_addr_t dma, |
89184651 | 183 | unsigned long offset) |
7a31f6f4 | 184 | { |
89184651 TR |
185 | u32 value; |
186 | ||
b8fe0382 | 187 | offset &= ~(smmu->mc->soc->atom_size - 1); |
89184651 | 188 | |
b8fe0382 | 189 | if (smmu->mc->soc->num_address_bits > 32) { |
e3c97196 RK |
190 | #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT |
191 | value = (dma >> 32) & SMMU_PTC_FLUSH_HI_MASK; | |
89184651 | 192 | #else |
b8fe0382 | 193 | value = 0; |
89184651 | 194 | #endif |
b8fe0382 | 195 | smmu_writel(smmu, value, SMMU_PTC_FLUSH_HI); |
7a31f6f4 | 196 | } |
89184651 | 197 | |
e3c97196 | 198 | value = (dma + offset) | SMMU_PTC_FLUSH_TYPE_ADR; |
89184651 | 199 | smmu_writel(smmu, value, SMMU_PTC_FLUSH); |
7a31f6f4 HD |
200 | } |
201 | ||
89184651 | 202 | static inline void smmu_flush_tlb(struct tegra_smmu *smmu) |
7a31f6f4 | 203 | { |
89184651 | 204 | smmu_writel(smmu, SMMU_TLB_FLUSH_VA_MATCH_ALL, SMMU_TLB_FLUSH); |
7a31f6f4 HD |
205 | } |
206 | ||
89184651 TR |
207 | static inline void smmu_flush_tlb_asid(struct tegra_smmu *smmu, |
208 | unsigned long asid) | |
7a31f6f4 | 209 | { |
89184651 | 210 | u32 value; |
7a31f6f4 | 211 | |
43a0541e DO |
212 | if (smmu->soc->num_asids == 4) |
213 | value = (asid & 0x3) << 29; | |
214 | else | |
215 | value = (asid & 0x7f) << 24; | |
216 | ||
217 | value |= SMMU_TLB_FLUSH_ASID_MATCH | SMMU_TLB_FLUSH_VA_MATCH_ALL; | |
89184651 | 218 | smmu_writel(smmu, value, SMMU_TLB_FLUSH); |
7a31f6f4 HD |
219 | } |
220 | ||
89184651 TR |
221 | static inline void smmu_flush_tlb_section(struct tegra_smmu *smmu, |
222 | unsigned long asid, | |
223 | unsigned long iova) | |
7a31f6f4 | 224 | { |
89184651 | 225 | u32 value; |
7a31f6f4 | 226 | |
43a0541e DO |
227 | if (smmu->soc->num_asids == 4) |
228 | value = (asid & 0x3) << 29; | |
229 | else | |
230 | value = (asid & 0x7f) << 24; | |
231 | ||
232 | value |= SMMU_TLB_FLUSH_ASID_MATCH | SMMU_TLB_FLUSH_VA_SECTION(iova); | |
89184651 | 233 | smmu_writel(smmu, value, SMMU_TLB_FLUSH); |
7a31f6f4 HD |
234 | } |
235 | ||
89184651 TR |
236 | static inline void smmu_flush_tlb_group(struct tegra_smmu *smmu, |
237 | unsigned long asid, | |
238 | unsigned long iova) | |
7a31f6f4 | 239 | { |
89184651 | 240 | u32 value; |
7a31f6f4 | 241 | |
43a0541e DO |
242 | if (smmu->soc->num_asids == 4) |
243 | value = (asid & 0x3) << 29; | |
244 | else | |
245 | value = (asid & 0x7f) << 24; | |
246 | ||
247 | value |= SMMU_TLB_FLUSH_ASID_MATCH | SMMU_TLB_FLUSH_VA_GROUP(iova); | |
89184651 | 248 | smmu_writel(smmu, value, SMMU_TLB_FLUSH); |
7a31f6f4 HD |
249 | } |
250 | ||
89184651 | 251 | static inline void smmu_flush(struct tegra_smmu *smmu) |
7a31f6f4 | 252 | { |
446152d5 | 253 | smmu_readl(smmu, SMMU_PTB_ASID); |
7a31f6f4 HD |
254 | } |
255 | ||
89184651 | 256 | static int tegra_smmu_alloc_asid(struct tegra_smmu *smmu, unsigned int *idp) |
7a31f6f4 | 257 | { |
89184651 | 258 | unsigned long id; |
7a31f6f4 | 259 | |
89184651 | 260 | id = find_first_zero_bit(smmu->asids, smmu->soc->num_asids); |
d5f583bf | 261 | if (id >= smmu->soc->num_asids) |
89184651 | 262 | return -ENOSPC; |
7a31f6f4 | 263 | |
89184651 TR |
264 | set_bit(id, smmu->asids); |
265 | *idp = id; | |
266 | ||
89184651 | 267 | return 0; |
7a31f6f4 HD |
268 | } |
269 | ||
89184651 | 270 | static void tegra_smmu_free_asid(struct tegra_smmu *smmu, unsigned int id) |
7a31f6f4 | 271 | { |
89184651 | 272 | clear_bit(id, smmu->asids); |
7a31f6f4 | 273 | } |
89184651 TR |
274 | |
275 | static bool tegra_smmu_capable(enum iommu_cap cap) | |
7a31f6f4 | 276 | { |
89184651 | 277 | return false; |
7a31f6f4 | 278 | } |
7a31f6f4 | 279 | |
d5f1a81c | 280 | static struct iommu_domain *tegra_smmu_domain_alloc(unsigned type) |
7a31f6f4 | 281 | { |
89184651 | 282 | struct tegra_smmu_as *as; |
7a31f6f4 | 283 | |
d5f1a81c JR |
284 | if (type != IOMMU_DOMAIN_UNMANAGED) |
285 | return NULL; | |
286 | ||
89184651 TR |
287 | as = kzalloc(sizeof(*as), GFP_KERNEL); |
288 | if (!as) | |
d5f1a81c | 289 | return NULL; |
7a31f6f4 | 290 | |
89184651 | 291 | as->attr = SMMU_PD_READABLE | SMMU_PD_WRITABLE | SMMU_PD_NONSECURE; |
7a31f6f4 | 292 | |
707917cb | 293 | as->pd = alloc_page(GFP_KERNEL | __GFP_DMA | __GFP_ZERO); |
89184651 TR |
294 | if (!as->pd) { |
295 | kfree(as); | |
d5f1a81c | 296 | return NULL; |
7a31f6f4 | 297 | } |
9e971a03 | 298 | |
32924c76 | 299 | as->count = kcalloc(SMMU_NUM_PDE, sizeof(u32), GFP_KERNEL); |
89184651 TR |
300 | if (!as->count) { |
301 | __free_page(as->pd); | |
302 | kfree(as); | |
d5f1a81c | 303 | return NULL; |
7a31f6f4 | 304 | } |
9e971a03 | 305 | |
853520fa RK |
306 | as->pts = kcalloc(SMMU_NUM_PDE, sizeof(*as->pts), GFP_KERNEL); |
307 | if (!as->pts) { | |
32924c76 | 308 | kfree(as->count); |
853520fa RK |
309 | __free_page(as->pd); |
310 | kfree(as); | |
311 | return NULL; | |
312 | } | |
313 | ||
404d0b30 DO |
314 | spin_lock_init(&as->lock); |
315 | ||
471d9144 | 316 | /* setup aperture */ |
7f65ef01 JR |
317 | as->domain.geometry.aperture_start = 0; |
318 | as->domain.geometry.aperture_end = 0xffffffff; | |
319 | as->domain.geometry.force_aperture = true; | |
f9a4f063 | 320 | |
d5f1a81c | 321 | return &as->domain; |
7a31f6f4 HD |
322 | } |
323 | ||
d5f1a81c | 324 | static void tegra_smmu_domain_free(struct iommu_domain *domain) |
7a31f6f4 | 325 | { |
d5f1a81c | 326 | struct tegra_smmu_as *as = to_smmu_as(domain); |
7a31f6f4 | 327 | |
89184651 | 328 | /* TODO: free page directory and page tables */ |
7a31f6f4 | 329 | |
4f97031f DO |
330 | WARN_ON_ONCE(as->use_count); |
331 | kfree(as->count); | |
332 | kfree(as->pts); | |
89184651 | 333 | kfree(as); |
7a31f6f4 HD |
334 | } |
335 | ||
89184651 TR |
336 | static const struct tegra_smmu_swgroup * |
337 | tegra_smmu_find_swgroup(struct tegra_smmu *smmu, unsigned int swgroup) | |
7a31f6f4 | 338 | { |
89184651 TR |
339 | const struct tegra_smmu_swgroup *group = NULL; |
340 | unsigned int i; | |
7a31f6f4 | 341 | |
89184651 TR |
342 | for (i = 0; i < smmu->soc->num_swgroups; i++) { |
343 | if (smmu->soc->swgroups[i].swgroup == swgroup) { | |
344 | group = &smmu->soc->swgroups[i]; | |
345 | break; | |
346 | } | |
347 | } | |
7a31f6f4 | 348 | |
89184651 | 349 | return group; |
7a31f6f4 HD |
350 | } |
351 | ||
89184651 TR |
352 | static void tegra_smmu_enable(struct tegra_smmu *smmu, unsigned int swgroup, |
353 | unsigned int asid) | |
7a31f6f4 | 354 | { |
89184651 TR |
355 | const struct tegra_smmu_swgroup *group; |
356 | unsigned int i; | |
357 | u32 value; | |
7a31f6f4 | 358 | |
e31e5929 NK |
359 | group = tegra_smmu_find_swgroup(smmu, swgroup); |
360 | if (group) { | |
361 | value = smmu_readl(smmu, group->reg); | |
362 | value &= ~SMMU_ASID_MASK; | |
363 | value |= SMMU_ASID_VALUE(asid); | |
364 | value |= SMMU_ASID_ENABLE; | |
365 | smmu_writel(smmu, value, group->reg); | |
366 | } else { | |
367 | pr_warn("%s group from swgroup %u not found\n", __func__, | |
368 | swgroup); | |
369 | /* No point moving ahead if group was not found */ | |
370 | return; | |
371 | } | |
372 | ||
89184651 TR |
373 | for (i = 0; i < smmu->soc->num_clients; i++) { |
374 | const struct tegra_mc_client *client = &smmu->soc->clients[i]; | |
7a31f6f4 | 375 | |
89184651 TR |
376 | if (client->swgroup != swgroup) |
377 | continue; | |
7a31f6f4 | 378 | |
4f1ac76e TR |
379 | value = smmu_readl(smmu, client->regs.smmu.reg); |
380 | value |= BIT(client->regs.smmu.bit); | |
381 | smmu_writel(smmu, value, client->regs.smmu.reg); | |
89184651 | 382 | } |
7a31f6f4 HD |
383 | } |
384 | ||
89184651 TR |
385 | static void tegra_smmu_disable(struct tegra_smmu *smmu, unsigned int swgroup, |
386 | unsigned int asid) | |
7a31f6f4 | 387 | { |
89184651 TR |
388 | const struct tegra_smmu_swgroup *group; |
389 | unsigned int i; | |
390 | u32 value; | |
7a31f6f4 | 391 | |
89184651 TR |
392 | group = tegra_smmu_find_swgroup(smmu, swgroup); |
393 | if (group) { | |
394 | value = smmu_readl(smmu, group->reg); | |
395 | value &= ~SMMU_ASID_MASK; | |
396 | value |= SMMU_ASID_VALUE(asid); | |
397 | value &= ~SMMU_ASID_ENABLE; | |
398 | smmu_writel(smmu, value, group->reg); | |
399 | } | |
7a31f6f4 | 400 | |
89184651 TR |
401 | for (i = 0; i < smmu->soc->num_clients; i++) { |
402 | const struct tegra_mc_client *client = &smmu->soc->clients[i]; | |
7a31f6f4 | 403 | |
89184651 TR |
404 | if (client->swgroup != swgroup) |
405 | continue; | |
7a31f6f4 | 406 | |
4f1ac76e TR |
407 | value = smmu_readl(smmu, client->regs.smmu.reg); |
408 | value &= ~BIT(client->regs.smmu.bit); | |
409 | smmu_writel(smmu, value, client->regs.smmu.reg); | |
89184651 | 410 | } |
7a31f6f4 HD |
411 | } |
412 | ||
89184651 TR |
413 | static int tegra_smmu_as_prepare(struct tegra_smmu *smmu, |
414 | struct tegra_smmu_as *as) | |
7a31f6f4 | 415 | { |
89184651 | 416 | u32 value; |
d5f583bf NC |
417 | int err = 0; |
418 | ||
419 | mutex_lock(&smmu->lock); | |
7a31f6f4 | 420 | |
89184651 TR |
421 | if (as->use_count > 0) { |
422 | as->use_count++; | |
d5f583bf | 423 | goto unlock; |
7a31f6f4 | 424 | } |
7a31f6f4 | 425 | |
e3c97196 RK |
426 | as->pd_dma = dma_map_page(smmu->dev, as->pd, 0, SMMU_SIZE_PD, |
427 | DMA_TO_DEVICE); | |
d5f583bf NC |
428 | if (dma_mapping_error(smmu->dev, as->pd_dma)) { |
429 | err = -ENOMEM; | |
430 | goto unlock; | |
431 | } | |
e3c97196 RK |
432 | |
433 | /* We can't handle 64-bit DMA addresses */ | |
434 | if (!smmu_dma_addr_valid(smmu, as->pd_dma)) { | |
435 | err = -ENOMEM; | |
436 | goto err_unmap; | |
437 | } | |
438 | ||
89184651 TR |
439 | err = tegra_smmu_alloc_asid(smmu, &as->id); |
440 | if (err < 0) | |
e3c97196 | 441 | goto err_unmap; |
7a31f6f4 | 442 | |
e3c97196 | 443 | smmu_flush_ptc(smmu, as->pd_dma, 0); |
89184651 | 444 | smmu_flush_tlb_asid(smmu, as->id); |
7a31f6f4 | 445 | |
89184651 | 446 | smmu_writel(smmu, as->id & 0x7f, SMMU_PTB_ASID); |
e3c97196 | 447 | value = SMMU_PTB_DATA_VALUE(as->pd_dma, as->attr); |
89184651 TR |
448 | smmu_writel(smmu, value, SMMU_PTB_DATA); |
449 | smmu_flush(smmu); | |
7a31f6f4 | 450 | |
89184651 TR |
451 | as->smmu = smmu; |
452 | as->use_count++; | |
7a31f6f4 | 453 | |
d5f583bf NC |
454 | mutex_unlock(&smmu->lock); |
455 | ||
89184651 | 456 | return 0; |
e3c97196 RK |
457 | |
458 | err_unmap: | |
459 | dma_unmap_page(smmu->dev, as->pd_dma, SMMU_SIZE_PD, DMA_TO_DEVICE); | |
d5f583bf NC |
460 | unlock: |
461 | mutex_unlock(&smmu->lock); | |
462 | ||
e3c97196 | 463 | return err; |
7a31f6f4 HD |
464 | } |
465 | ||
89184651 TR |
466 | static void tegra_smmu_as_unprepare(struct tegra_smmu *smmu, |
467 | struct tegra_smmu_as *as) | |
7a31f6f4 | 468 | { |
d5f583bf NC |
469 | mutex_lock(&smmu->lock); |
470 | ||
471 | if (--as->use_count > 0) { | |
472 | mutex_unlock(&smmu->lock); | |
89184651 | 473 | return; |
d5f583bf | 474 | } |
89184651 TR |
475 | |
476 | tegra_smmu_free_asid(smmu, as->id); | |
e3c97196 RK |
477 | |
478 | dma_unmap_page(smmu->dev, as->pd_dma, SMMU_SIZE_PD, DMA_TO_DEVICE); | |
479 | ||
89184651 | 480 | as->smmu = NULL; |
d5f583bf NC |
481 | |
482 | mutex_unlock(&smmu->lock); | |
7a31f6f4 HD |
483 | } |
484 | ||
89184651 TR |
485 | static int tegra_smmu_attach_dev(struct iommu_domain *domain, |
486 | struct device *dev) | |
7a31f6f4 | 487 | { |
8750d207 | 488 | struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev); |
a5616e24 | 489 | struct tegra_smmu *smmu = dev_iommu_priv_get(dev); |
d5f1a81c | 490 | struct tegra_smmu_as *as = to_smmu_as(domain); |
8750d207 NC |
491 | unsigned int index; |
492 | int err; | |
d2453b2c | 493 | |
8750d207 NC |
494 | if (!fwspec) |
495 | return -ENOENT; | |
d2453b2c | 496 | |
8750d207 | 497 | for (index = 0; index < fwspec->num_ids; index++) { |
89184651 | 498 | err = tegra_smmu_as_prepare(smmu, as); |
8750d207 NC |
499 | if (err) |
500 | goto disable; | |
89184651 | 501 | |
8750d207 | 502 | tegra_smmu_enable(smmu, fwspec->ids[index], as->id); |
7a31f6f4 | 503 | } |
7a31f6f4 | 504 | |
89184651 TR |
505 | if (index == 0) |
506 | return -ENODEV; | |
7a31f6f4 | 507 | |
89184651 | 508 | return 0; |
8750d207 NC |
509 | |
510 | disable: | |
511 | while (index--) { | |
512 | tegra_smmu_disable(smmu, fwspec->ids[index], as->id); | |
513 | tegra_smmu_as_unprepare(smmu, as); | |
514 | } | |
515 | ||
516 | return err; | |
89184651 | 517 | } |
7a31f6f4 | 518 | |
89184651 TR |
519 | static void tegra_smmu_detach_dev(struct iommu_domain *domain, struct device *dev) |
520 | { | |
8750d207 | 521 | struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev); |
d5f1a81c | 522 | struct tegra_smmu_as *as = to_smmu_as(domain); |
89184651 | 523 | struct tegra_smmu *smmu = as->smmu; |
8750d207 | 524 | unsigned int index; |
7a31f6f4 | 525 | |
8750d207 NC |
526 | if (!fwspec) |
527 | return; | |
7a31f6f4 | 528 | |
8750d207 NC |
529 | for (index = 0; index < fwspec->num_ids; index++) { |
530 | tegra_smmu_disable(smmu, fwspec->ids[index], as->id); | |
89184651 | 531 | tegra_smmu_as_unprepare(smmu, as); |
89184651 | 532 | } |
7a31f6f4 HD |
533 | } |
534 | ||
4080e99b RK |
535 | static void tegra_smmu_set_pde(struct tegra_smmu_as *as, unsigned long iova, |
536 | u32 value) | |
537 | { | |
538 | unsigned int pd_index = iova_pd_index(iova); | |
539 | struct tegra_smmu *smmu = as->smmu; | |
540 | u32 *pd = page_address(as->pd); | |
541 | unsigned long offset = pd_index * sizeof(*pd); | |
542 | ||
543 | /* Set the page directory entry first */ | |
544 | pd[pd_index] = value; | |
545 | ||
546 | /* The flush the page directory entry from caches */ | |
547 | dma_sync_single_range_for_device(smmu->dev, as->pd_dma, offset, | |
548 | sizeof(*pd), DMA_TO_DEVICE); | |
549 | ||
550 | /* And flush the iommu */ | |
551 | smmu_flush_ptc(smmu, as->pd_dma, offset); | |
552 | smmu_flush_tlb_section(smmu, as->id, iova); | |
553 | smmu_flush(smmu); | |
554 | } | |
555 | ||
0b42c7c1 RK |
556 | static u32 *tegra_smmu_pte_offset(struct page *pt_page, unsigned long iova) |
557 | { | |
558 | u32 *pt = page_address(pt_page); | |
559 | ||
560 | return pt + iova_pt_index(iova); | |
561 | } | |
562 | ||
563 | static u32 *tegra_smmu_pte_lookup(struct tegra_smmu_as *as, unsigned long iova, | |
e3c97196 | 564 | dma_addr_t *dmap) |
0b42c7c1 RK |
565 | { |
566 | unsigned int pd_index = iova_pd_index(iova); | |
96d3ab80 | 567 | struct tegra_smmu *smmu = as->smmu; |
0b42c7c1 | 568 | struct page *pt_page; |
e3c97196 | 569 | u32 *pd; |
0b42c7c1 | 570 | |
853520fa RK |
571 | pt_page = as->pts[pd_index]; |
572 | if (!pt_page) | |
0b42c7c1 RK |
573 | return NULL; |
574 | ||
e3c97196 | 575 | pd = page_address(as->pd); |
96d3ab80 | 576 | *dmap = smmu_pde_to_dma(smmu, pd[pd_index]); |
0b42c7c1 RK |
577 | |
578 | return tegra_smmu_pte_offset(pt_page, iova); | |
579 | } | |
580 | ||
89184651 | 581 | static u32 *as_get_pte(struct tegra_smmu_as *as, dma_addr_t iova, |
404d0b30 | 582 | dma_addr_t *dmap, struct page *page) |
7a31f6f4 | 583 | { |
34d35f8c | 584 | unsigned int pde = iova_pd_index(iova); |
89184651 | 585 | struct tegra_smmu *smmu = as->smmu; |
89184651 | 586 | |
853520fa | 587 | if (!as->pts[pde]) { |
e3c97196 RK |
588 | dma_addr_t dma; |
589 | ||
e3c97196 RK |
590 | dma = dma_map_page(smmu->dev, page, 0, SMMU_SIZE_PT, |
591 | DMA_TO_DEVICE); | |
592 | if (dma_mapping_error(smmu->dev, dma)) { | |
593 | __free_page(page); | |
594 | return NULL; | |
595 | } | |
596 | ||
597 | if (!smmu_dma_addr_valid(smmu, dma)) { | |
598 | dma_unmap_page(smmu->dev, dma, SMMU_SIZE_PT, | |
599 | DMA_TO_DEVICE); | |
600 | __free_page(page); | |
601 | return NULL; | |
602 | } | |
603 | ||
853520fa RK |
604 | as->pts[pde] = page; |
605 | ||
4080e99b RK |
606 | tegra_smmu_set_pde(as, iova, SMMU_MK_PDE(dma, SMMU_PDE_ATTR | |
607 | SMMU_PDE_NEXT)); | |
e3c97196 RK |
608 | |
609 | *dmap = dma; | |
89184651 | 610 | } else { |
4080e99b RK |
611 | u32 *pd = page_address(as->pd); |
612 | ||
96d3ab80 | 613 | *dmap = smmu_pde_to_dma(smmu, pd[pde]); |
7a31f6f4 HD |
614 | } |
615 | ||
7ffc6f06 RK |
616 | return tegra_smmu_pte_offset(as->pts[pde], iova); |
617 | } | |
0b42c7c1 | 618 | |
7ffc6f06 RK |
619 | static void tegra_smmu_pte_get_use(struct tegra_smmu_as *as, unsigned long iova) |
620 | { | |
621 | unsigned int pd_index = iova_pd_index(iova); | |
7a31f6f4 | 622 | |
7ffc6f06 | 623 | as->count[pd_index]++; |
89184651 | 624 | } |
39abf8aa | 625 | |
b98e34f0 | 626 | static void tegra_smmu_pte_put_use(struct tegra_smmu_as *as, unsigned long iova) |
39abf8aa | 627 | { |
34d35f8c | 628 | unsigned int pde = iova_pd_index(iova); |
853520fa | 629 | struct page *page = as->pts[pde]; |
39abf8aa | 630 | |
89184651 TR |
631 | /* |
632 | * When no entries in this page table are used anymore, return the | |
633 | * memory page to the system. | |
634 | */ | |
32924c76 | 635 | if (--as->count[pde] == 0) { |
4080e99b RK |
636 | struct tegra_smmu *smmu = as->smmu; |
637 | u32 *pd = page_address(as->pd); | |
96d3ab80 | 638 | dma_addr_t pte_dma = smmu_pde_to_dma(smmu, pd[pde]); |
39abf8aa | 639 | |
4080e99b | 640 | tegra_smmu_set_pde(as, iova, 0); |
b98e34f0 | 641 | |
e3c97196 | 642 | dma_unmap_page(smmu->dev, pte_dma, SMMU_SIZE_PT, DMA_TO_DEVICE); |
b98e34f0 | 643 | __free_page(page); |
853520fa | 644 | as->pts[pde] = NULL; |
39abf8aa | 645 | } |
39abf8aa HD |
646 | } |
647 | ||
8482ee5e | 648 | static void tegra_smmu_set_pte(struct tegra_smmu_as *as, unsigned long iova, |
e3c97196 | 649 | u32 *pte, dma_addr_t pte_dma, u32 val) |
8482ee5e RK |
650 | { |
651 | struct tegra_smmu *smmu = as->smmu; | |
82fa58e8 | 652 | unsigned long offset = SMMU_OFFSET_IN_PAGE(pte); |
8482ee5e RK |
653 | |
654 | *pte = val; | |
655 | ||
e3c97196 RK |
656 | dma_sync_single_range_for_device(smmu->dev, pte_dma, offset, |
657 | 4, DMA_TO_DEVICE); | |
658 | smmu_flush_ptc(smmu, pte_dma, offset); | |
8482ee5e RK |
659 | smmu_flush_tlb_group(smmu, as->id, iova); |
660 | smmu_flush(smmu); | |
661 | } | |
662 | ||
404d0b30 DO |
663 | static struct page *as_get_pde_page(struct tegra_smmu_as *as, |
664 | unsigned long iova, gfp_t gfp, | |
665 | unsigned long *flags) | |
666 | { | |
667 | unsigned int pde = iova_pd_index(iova); | |
668 | struct page *page = as->pts[pde]; | |
669 | ||
670 | /* at first check whether allocation needs to be done at all */ | |
671 | if (page) | |
672 | return page; | |
673 | ||
674 | /* | |
675 | * In order to prevent exhaustion of the atomic memory pool, we | |
676 | * allocate page in a sleeping context if GFP flags permit. Hence | |
677 | * spinlock needs to be unlocked and re-locked after allocation. | |
678 | */ | |
679 | if (!(gfp & __GFP_ATOMIC)) | |
680 | spin_unlock_irqrestore(&as->lock, *flags); | |
681 | ||
682 | page = alloc_page(gfp | __GFP_DMA | __GFP_ZERO); | |
683 | ||
684 | if (!(gfp & __GFP_ATOMIC)) | |
685 | spin_lock_irqsave(&as->lock, *flags); | |
686 | ||
687 | /* | |
688 | * In a case of blocking allocation, a concurrent mapping may win | |
689 | * the PDE allocation. In this case the allocated page isn't needed | |
690 | * if allocation succeeded and the allocation failure isn't fatal. | |
691 | */ | |
692 | if (as->pts[pde]) { | |
693 | if (page) | |
694 | __free_page(page); | |
695 | ||
696 | page = as->pts[pde]; | |
697 | } | |
698 | ||
699 | return page; | |
700 | } | |
701 | ||
702 | static int | |
703 | __tegra_smmu_map(struct iommu_domain *domain, unsigned long iova, | |
704 | phys_addr_t paddr, size_t size, int prot, gfp_t gfp, | |
705 | unsigned long *flags) | |
39abf8aa | 706 | { |
d5f1a81c | 707 | struct tegra_smmu_as *as = to_smmu_as(domain); |
e3c97196 | 708 | dma_addr_t pte_dma; |
404d0b30 | 709 | struct page *page; |
43d957b1 | 710 | u32 pte_attrs; |
89184651 | 711 | u32 *pte; |
39abf8aa | 712 | |
404d0b30 DO |
713 | page = as_get_pde_page(as, iova, gfp, flags); |
714 | if (!page) | |
715 | return -ENOMEM; | |
716 | ||
717 | pte = as_get_pte(as, iova, &pte_dma, page); | |
89184651 TR |
718 | if (!pte) |
719 | return -ENOMEM; | |
39abf8aa | 720 | |
7ffc6f06 RK |
721 | /* If we aren't overwriting a pre-existing entry, increment use */ |
722 | if (*pte == 0) | |
723 | tegra_smmu_pte_get_use(as, iova); | |
724 | ||
43d957b1 DO |
725 | pte_attrs = SMMU_PTE_NONSECURE; |
726 | ||
727 | if (prot & IOMMU_READ) | |
728 | pte_attrs |= SMMU_PTE_READABLE; | |
729 | ||
730 | if (prot & IOMMU_WRITE) | |
731 | pte_attrs |= SMMU_PTE_WRITABLE; | |
732 | ||
e3c97196 | 733 | tegra_smmu_set_pte(as, iova, pte, pte_dma, |
82fa58e8 | 734 | SMMU_PHYS_PFN(paddr) | pte_attrs); |
39abf8aa | 735 | |
39abf8aa HD |
736 | return 0; |
737 | } | |
738 | ||
404d0b30 DO |
739 | static size_t |
740 | __tegra_smmu_unmap(struct iommu_domain *domain, unsigned long iova, | |
741 | size_t size, struct iommu_iotlb_gather *gather) | |
39abf8aa | 742 | { |
d5f1a81c | 743 | struct tegra_smmu_as *as = to_smmu_as(domain); |
e3c97196 | 744 | dma_addr_t pte_dma; |
89184651 | 745 | u32 *pte; |
39abf8aa | 746 | |
e3c97196 | 747 | pte = tegra_smmu_pte_lookup(as, iova, &pte_dma); |
b98e34f0 | 748 | if (!pte || !*pte) |
89184651 | 749 | return 0; |
39abf8aa | 750 | |
e3c97196 | 751 | tegra_smmu_set_pte(as, iova, pte, pte_dma, 0); |
b98e34f0 RK |
752 | tegra_smmu_pte_put_use(as, iova); |
753 | ||
89184651 | 754 | return size; |
39abf8aa HD |
755 | } |
756 | ||
404d0b30 DO |
757 | static int tegra_smmu_map(struct iommu_domain *domain, unsigned long iova, |
758 | phys_addr_t paddr, size_t size, int prot, gfp_t gfp) | |
759 | { | |
760 | struct tegra_smmu_as *as = to_smmu_as(domain); | |
761 | unsigned long flags; | |
762 | int ret; | |
763 | ||
764 | spin_lock_irqsave(&as->lock, flags); | |
765 | ret = __tegra_smmu_map(domain, iova, paddr, size, prot, gfp, &flags); | |
766 | spin_unlock_irqrestore(&as->lock, flags); | |
767 | ||
768 | return ret; | |
769 | } | |
770 | ||
771 | static size_t tegra_smmu_unmap(struct iommu_domain *domain, unsigned long iova, | |
772 | size_t size, struct iommu_iotlb_gather *gather) | |
773 | { | |
774 | struct tegra_smmu_as *as = to_smmu_as(domain); | |
775 | unsigned long flags; | |
776 | ||
777 | spin_lock_irqsave(&as->lock, flags); | |
778 | size = __tegra_smmu_unmap(domain, iova, size, gather); | |
779 | spin_unlock_irqrestore(&as->lock, flags); | |
780 | ||
781 | return size; | |
782 | } | |
783 | ||
89184651 TR |
784 | static phys_addr_t tegra_smmu_iova_to_phys(struct iommu_domain *domain, |
785 | dma_addr_t iova) | |
39abf8aa | 786 | { |
d5f1a81c | 787 | struct tegra_smmu_as *as = to_smmu_as(domain); |
89184651 | 788 | unsigned long pfn; |
e3c97196 | 789 | dma_addr_t pte_dma; |
89184651 | 790 | u32 *pte; |
39abf8aa | 791 | |
e3c97196 | 792 | pte = tegra_smmu_pte_lookup(as, iova, &pte_dma); |
9113785c RK |
793 | if (!pte || !*pte) |
794 | return 0; | |
795 | ||
804cb54c | 796 | pfn = *pte & as->smmu->pfn_mask; |
39abf8aa | 797 | |
4fba9885 | 798 | return SMMU_PFN_PHYS(pfn) + SMMU_OFFSET_IN_PAGE(iova); |
39abf8aa HD |
799 | } |
800 | ||
765a9d1d NC |
801 | static struct tegra_smmu *tegra_smmu_find(struct device_node *np) |
802 | { | |
803 | struct platform_device *pdev; | |
804 | struct tegra_mc *mc; | |
805 | ||
806 | pdev = of_find_device_by_node(np); | |
807 | if (!pdev) | |
808 | return NULL; | |
809 | ||
810 | mc = platform_get_drvdata(pdev); | |
8a15f05b ML |
811 | if (!mc) { |
812 | put_device(&pdev->dev); | |
765a9d1d | 813 | return NULL; |
8a15f05b | 814 | } |
765a9d1d NC |
815 | |
816 | return mc->smmu; | |
817 | } | |
818 | ||
819 | static int tegra_smmu_configure(struct tegra_smmu *smmu, struct device *dev, | |
820 | struct of_phandle_args *args) | |
821 | { | |
822 | const struct iommu_ops *ops = smmu->iommu.ops; | |
823 | int err; | |
824 | ||
825 | err = iommu_fwspec_init(dev, &dev->of_node->fwnode, ops); | |
826 | if (err < 0) { | |
827 | dev_err(dev, "failed to initialize fwspec: %d\n", err); | |
828 | return err; | |
829 | } | |
830 | ||
831 | err = ops->of_xlate(dev, args); | |
832 | if (err < 0) { | |
833 | dev_err(dev, "failed to parse SW group ID: %d\n", err); | |
834 | iommu_fwspec_free(dev); | |
835 | return err; | |
836 | } | |
837 | ||
838 | return 0; | |
839 | } | |
840 | ||
b287ba73 | 841 | static struct iommu_device *tegra_smmu_probe_device(struct device *dev) |
7a31f6f4 | 842 | { |
765a9d1d NC |
843 | struct device_node *np = dev->of_node; |
844 | struct tegra_smmu *smmu = NULL; | |
845 | struct of_phandle_args args; | |
846 | unsigned int index = 0; | |
847 | int err; | |
848 | ||
849 | while (of_parse_phandle_with_args(np, "iommus", "#iommu-cells", index, | |
850 | &args) == 0) { | |
851 | smmu = tegra_smmu_find(args.np); | |
852 | if (smmu) { | |
853 | err = tegra_smmu_configure(smmu, dev, &args); | |
89184651 | 854 | |
8dfd0fa6 DO |
855 | if (err < 0) { |
856 | of_node_put(args.np); | |
765a9d1d | 857 | return ERR_PTR(err); |
8dfd0fa6 | 858 | } |
765a9d1d NC |
859 | } |
860 | ||
861 | of_node_put(args.np); | |
862 | index++; | |
863 | } | |
864 | ||
865 | smmu = dev_iommu_priv_get(dev); | |
7f4c9176 | 866 | if (!smmu) |
b287ba73 | 867 | return ERR_PTR(-ENODEV); |
d92e1f84 | 868 | |
b287ba73 | 869 | return &smmu->iommu; |
7a31f6f4 HD |
870 | } |
871 | ||
25938c73 | 872 | static void tegra_smmu_release_device(struct device *dev) {} |
7a31f6f4 | 873 | |
7f4c9176 TR |
874 | static const struct tegra_smmu_group_soc * |
875 | tegra_smmu_find_group(struct tegra_smmu *smmu, unsigned int swgroup) | |
876 | { | |
877 | unsigned int i, j; | |
878 | ||
879 | for (i = 0; i < smmu->soc->num_groups; i++) | |
880 | for (j = 0; j < smmu->soc->groups[i].num_swgroups; j++) | |
881 | if (smmu->soc->groups[i].swgroups[j] == swgroup) | |
882 | return &smmu->soc->groups[i]; | |
883 | ||
884 | return NULL; | |
885 | } | |
886 | ||
1ea5440e TR |
887 | static void tegra_smmu_group_release(void *iommu_data) |
888 | { | |
889 | struct tegra_smmu_group *group = iommu_data; | |
890 | struct tegra_smmu *smmu = group->smmu; | |
891 | ||
892 | mutex_lock(&smmu->lock); | |
893 | list_del(&group->list); | |
894 | mutex_unlock(&smmu->lock); | |
895 | } | |
896 | ||
cf910f61 | 897 | static struct iommu_group *tegra_smmu_device_group(struct device *dev) |
7f4c9176 | 898 | { |
cf910f61 NC |
899 | struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev); |
900 | struct tegra_smmu *smmu = dev_iommu_priv_get(dev); | |
7f4c9176 | 901 | const struct tegra_smmu_group_soc *soc; |
cf910f61 | 902 | unsigned int swgroup = fwspec->ids[0]; |
7f4c9176 | 903 | struct tegra_smmu_group *group; |
5b30fbfa | 904 | struct iommu_group *grp; |
7f4c9176 | 905 | |
21d3c040 | 906 | /* Find group_soc associating with swgroup */ |
7f4c9176 | 907 | soc = tegra_smmu_find_group(smmu, swgroup); |
7f4c9176 TR |
908 | |
909 | mutex_lock(&smmu->lock); | |
910 | ||
21d3c040 | 911 | /* Find existing iommu_group associating with swgroup or group_soc */ |
7f4c9176 | 912 | list_for_each_entry(group, &smmu->groups, list) |
21d3c040 | 913 | if ((group->swgroup == swgroup) || (soc && group->soc == soc)) { |
5b30fbfa | 914 | grp = iommu_group_ref_get(group->group); |
7f4c9176 | 915 | mutex_unlock(&smmu->lock); |
5b30fbfa | 916 | return grp; |
7f4c9176 TR |
917 | } |
918 | ||
919 | group = devm_kzalloc(smmu->dev, sizeof(*group), GFP_KERNEL); | |
920 | if (!group) { | |
921 | mutex_unlock(&smmu->lock); | |
922 | return NULL; | |
923 | } | |
924 | ||
925 | INIT_LIST_HEAD(&group->list); | |
21d3c040 | 926 | group->swgroup = swgroup; |
1ea5440e | 927 | group->smmu = smmu; |
7f4c9176 TR |
928 | group->soc = soc; |
929 | ||
541f29bb NC |
930 | if (dev_is_pci(dev)) |
931 | group->group = pci_device_group(dev); | |
932 | else | |
933 | group->group = generic_device_group(dev); | |
934 | ||
83476bfa | 935 | if (IS_ERR(group->group)) { |
7f4c9176 TR |
936 | devm_kfree(smmu->dev, group); |
937 | mutex_unlock(&smmu->lock); | |
938 | return NULL; | |
939 | } | |
940 | ||
1ea5440e | 941 | iommu_group_set_iommudata(group->group, group, tegra_smmu_group_release); |
21d3c040 NC |
942 | if (soc) |
943 | iommu_group_set_name(group->group, soc->name); | |
7f4c9176 TR |
944 | list_add_tail(&group->list, &smmu->groups); |
945 | mutex_unlock(&smmu->lock); | |
946 | ||
947 | return group->group; | |
948 | } | |
949 | ||
7f4c9176 TR |
950 | static int tegra_smmu_of_xlate(struct device *dev, |
951 | struct of_phandle_args *args) | |
952 | { | |
25938c73 NC |
953 | struct platform_device *iommu_pdev = of_find_device_by_node(args->np); |
954 | struct tegra_mc *mc = platform_get_drvdata(iommu_pdev); | |
7f4c9176 TR |
955 | u32 id = args->args[0]; |
956 | ||
25938c73 NC |
957 | /* |
958 | * Note: we are here releasing the reference of &iommu_pdev->dev, which | |
959 | * is mc->dev. Although some functions in tegra_smmu_ops may keep using | |
960 | * its private data beyond this point, it's still safe to do so because | |
961 | * the SMMU parent device is the same as the MC, so the reference count | |
962 | * isn't strictly necessary. | |
963 | */ | |
964 | put_device(&iommu_pdev->dev); | |
965 | ||
966 | dev_iommu_priv_set(dev, mc->smmu); | |
967 | ||
7f4c9176 TR |
968 | return iommu_fwspec_add_ids(dev, &id, 1); |
969 | } | |
970 | ||
89184651 TR |
971 | static const struct iommu_ops tegra_smmu_ops = { |
972 | .capable = tegra_smmu_capable, | |
d5f1a81c JR |
973 | .domain_alloc = tegra_smmu_domain_alloc, |
974 | .domain_free = tegra_smmu_domain_free, | |
89184651 TR |
975 | .attach_dev = tegra_smmu_attach_dev, |
976 | .detach_dev = tegra_smmu_detach_dev, | |
b287ba73 JR |
977 | .probe_device = tegra_smmu_probe_device, |
978 | .release_device = tegra_smmu_release_device, | |
7f4c9176 | 979 | .device_group = tegra_smmu_device_group, |
89184651 TR |
980 | .map = tegra_smmu_map, |
981 | .unmap = tegra_smmu_unmap, | |
89184651 | 982 | .iova_to_phys = tegra_smmu_iova_to_phys, |
7f4c9176 | 983 | .of_xlate = tegra_smmu_of_xlate, |
89184651 TR |
984 | .pgsize_bitmap = SZ_4K, |
985 | }; | |
7a31f6f4 | 986 | |
89184651 TR |
987 | static void tegra_smmu_ahb_enable(void) |
988 | { | |
989 | static const struct of_device_id ahb_match[] = { | |
990 | { .compatible = "nvidia,tegra30-ahb", }, | |
991 | { } | |
992 | }; | |
993 | struct device_node *ahb; | |
7a31f6f4 | 994 | |
89184651 TR |
995 | ahb = of_find_matching_node(NULL, ahb_match); |
996 | if (ahb) { | |
997 | tegra_ahb_enable_smmu(ahb); | |
998 | of_node_put(ahb); | |
7a31f6f4 | 999 | } |
89184651 | 1000 | } |
7a31f6f4 | 1001 | |
d1313e78 TR |
1002 | static int tegra_smmu_swgroups_show(struct seq_file *s, void *data) |
1003 | { | |
1004 | struct tegra_smmu *smmu = s->private; | |
1005 | unsigned int i; | |
1006 | u32 value; | |
1007 | ||
1008 | seq_printf(s, "swgroup enabled ASID\n"); | |
1009 | seq_printf(s, "------------------------\n"); | |
1010 | ||
1011 | for (i = 0; i < smmu->soc->num_swgroups; i++) { | |
1012 | const struct tegra_smmu_swgroup *group = &smmu->soc->swgroups[i]; | |
1013 | const char *status; | |
1014 | unsigned int asid; | |
1015 | ||
1016 | value = smmu_readl(smmu, group->reg); | |
1017 | ||
1018 | if (value & SMMU_ASID_ENABLE) | |
1019 | status = "yes"; | |
1020 | else | |
1021 | status = "no"; | |
1022 | ||
1023 | asid = value & SMMU_ASID_MASK; | |
1024 | ||
1025 | seq_printf(s, "%-9s %-7s %#04x\n", group->name, status, | |
1026 | asid); | |
1027 | } | |
1028 | ||
1029 | return 0; | |
1030 | } | |
1031 | ||
062e52a5 | 1032 | DEFINE_SHOW_ATTRIBUTE(tegra_smmu_swgroups); |
d1313e78 TR |
1033 | |
1034 | static int tegra_smmu_clients_show(struct seq_file *s, void *data) | |
1035 | { | |
1036 | struct tegra_smmu *smmu = s->private; | |
1037 | unsigned int i; | |
1038 | u32 value; | |
1039 | ||
1040 | seq_printf(s, "client enabled\n"); | |
1041 | seq_printf(s, "--------------------\n"); | |
1042 | ||
1043 | for (i = 0; i < smmu->soc->num_clients; i++) { | |
1044 | const struct tegra_mc_client *client = &smmu->soc->clients[i]; | |
1045 | const char *status; | |
1046 | ||
4f1ac76e | 1047 | value = smmu_readl(smmu, client->regs.smmu.reg); |
d1313e78 | 1048 | |
4f1ac76e | 1049 | if (value & BIT(client->regs.smmu.bit)) |
d1313e78 TR |
1050 | status = "yes"; |
1051 | else | |
1052 | status = "no"; | |
1053 | ||
1054 | seq_printf(s, "%-12s %s\n", client->name, status); | |
1055 | } | |
1056 | ||
1057 | return 0; | |
1058 | } | |
1059 | ||
062e52a5 | 1060 | DEFINE_SHOW_ATTRIBUTE(tegra_smmu_clients); |
d1313e78 TR |
1061 | |
1062 | static void tegra_smmu_debugfs_init(struct tegra_smmu *smmu) | |
1063 | { | |
1064 | smmu->debugfs = debugfs_create_dir("smmu", NULL); | |
1065 | if (!smmu->debugfs) | |
1066 | return; | |
1067 | ||
1068 | debugfs_create_file("swgroups", S_IRUGO, smmu->debugfs, smmu, | |
1069 | &tegra_smmu_swgroups_fops); | |
1070 | debugfs_create_file("clients", S_IRUGO, smmu->debugfs, smmu, | |
1071 | &tegra_smmu_clients_fops); | |
1072 | } | |
1073 | ||
1074 | static void tegra_smmu_debugfs_exit(struct tegra_smmu *smmu) | |
1075 | { | |
1076 | debugfs_remove_recursive(smmu->debugfs); | |
1077 | } | |
1078 | ||
89184651 TR |
1079 | struct tegra_smmu *tegra_smmu_probe(struct device *dev, |
1080 | const struct tegra_smmu_soc *soc, | |
1081 | struct tegra_mc *mc) | |
1082 | { | |
1083 | struct tegra_smmu *smmu; | |
1084 | size_t size; | |
1085 | u32 value; | |
1086 | int err; | |
7a31f6f4 | 1087 | |
89184651 TR |
1088 | smmu = devm_kzalloc(dev, sizeof(*smmu), GFP_KERNEL); |
1089 | if (!smmu) | |
1090 | return ERR_PTR(-ENOMEM); | |
0760e8fa | 1091 | |
765a9d1d NC |
1092 | /* |
1093 | * This is a bit of a hack. Ideally we'd want to simply return this | |
1094 | * value. However the IOMMU registration process will attempt to add | |
1095 | * all devices to the IOMMU when bus_set_iommu() is called. In order | |
1096 | * not to rely on global variables to track the IOMMU instance, we | |
1097 | * set it here so that it can be looked up from the .probe_device() | |
1098 | * callback via the IOMMU device's .drvdata field. | |
1099 | */ | |
1100 | mc->smmu = smmu; | |
1101 | ||
89184651 | 1102 | size = BITS_TO_LONGS(soc->num_asids) * sizeof(long); |
0760e8fa | 1103 | |
89184651 TR |
1104 | smmu->asids = devm_kzalloc(dev, size, GFP_KERNEL); |
1105 | if (!smmu->asids) | |
1106 | return ERR_PTR(-ENOMEM); | |
7a31f6f4 | 1107 | |
7f4c9176 | 1108 | INIT_LIST_HEAD(&smmu->groups); |
89184651 | 1109 | mutex_init(&smmu->lock); |
7a31f6f4 | 1110 | |
89184651 TR |
1111 | smmu->regs = mc->regs; |
1112 | smmu->soc = soc; | |
1113 | smmu->dev = dev; | |
1114 | smmu->mc = mc; | |
7a31f6f4 | 1115 | |
82fa58e8 NC |
1116 | smmu->pfn_mask = |
1117 | BIT_MASK(mc->soc->num_address_bits - SMMU_PTE_SHIFT) - 1; | |
804cb54c TR |
1118 | dev_dbg(dev, "address bits: %u, PFN mask: %#lx\n", |
1119 | mc->soc->num_address_bits, smmu->pfn_mask); | |
d5c152c3 | 1120 | smmu->tlb_mask = (1 << fls(smmu->soc->num_tlb_lines)) - 1; |
11cec15b TR |
1121 | dev_dbg(dev, "TLB lines: %u, mask: %#lx\n", smmu->soc->num_tlb_lines, |
1122 | smmu->tlb_mask); | |
804cb54c | 1123 | |
89184651 | 1124 | value = SMMU_PTC_CONFIG_ENABLE | SMMU_PTC_CONFIG_INDEX_MAP(0x3f); |
7a31f6f4 | 1125 | |
89184651 TR |
1126 | if (soc->supports_request_limit) |
1127 | value |= SMMU_PTC_CONFIG_REQ_LIMIT(8); | |
39abf8aa | 1128 | |
89184651 | 1129 | smmu_writel(smmu, value, SMMU_PTC_CONFIG); |
7a31f6f4 | 1130 | |
89184651 | 1131 | value = SMMU_TLB_CONFIG_HIT_UNDER_MISS | |
11cec15b | 1132 | SMMU_TLB_CONFIG_ACTIVE_LINES(smmu); |
7a31f6f4 | 1133 | |
89184651 TR |
1134 | if (soc->supports_round_robin_arbitration) |
1135 | value |= SMMU_TLB_CONFIG_ROUND_ROBIN_ARBITRATION; | |
7a31f6f4 | 1136 | |
89184651 | 1137 | smmu_writel(smmu, value, SMMU_TLB_CONFIG); |
7a31f6f4 | 1138 | |
b8fe0382 | 1139 | smmu_flush_ptc_all(smmu); |
89184651 TR |
1140 | smmu_flush_tlb(smmu); |
1141 | smmu_writel(smmu, SMMU_CONFIG_ENABLE, SMMU_CONFIG); | |
1142 | smmu_flush(smmu); | |
1143 | ||
1144 | tegra_smmu_ahb_enable(); | |
7a31f6f4 | 1145 | |
0b480e44 JR |
1146 | err = iommu_device_sysfs_add(&smmu->iommu, dev, NULL, dev_name(dev)); |
1147 | if (err) | |
1148 | return ERR_PTR(err); | |
1149 | ||
2d471b20 | 1150 | err = iommu_device_register(&smmu->iommu, &tegra_smmu_ops, dev); |
541f29bb NC |
1151 | if (err) |
1152 | goto remove_sysfs; | |
0b480e44 | 1153 | |
96302d89 | 1154 | err = bus_set_iommu(&platform_bus_type, &tegra_smmu_ops); |
541f29bb NC |
1155 | if (err < 0) |
1156 | goto unregister; | |
1157 | ||
1158 | #ifdef CONFIG_PCI | |
1159 | err = bus_set_iommu(&pci_bus_type, &tegra_smmu_ops); | |
1160 | if (err < 0) | |
1161 | goto unset_platform_bus; | |
1162 | #endif | |
96302d89 | 1163 | |
d1313e78 TR |
1164 | if (IS_ENABLED(CONFIG_DEBUG_FS)) |
1165 | tegra_smmu_debugfs_init(smmu); | |
1166 | ||
89184651 | 1167 | return smmu; |
541f29bb NC |
1168 | |
1169 | unset_platform_bus: __maybe_unused; | |
1170 | bus_set_iommu(&platform_bus_type, NULL); | |
1171 | unregister: | |
1172 | iommu_device_unregister(&smmu->iommu); | |
1173 | remove_sysfs: | |
1174 | iommu_device_sysfs_remove(&smmu->iommu); | |
1175 | ||
1176 | return ERR_PTR(err); | |
89184651 | 1177 | } |
d1313e78 TR |
1178 | |
1179 | void tegra_smmu_remove(struct tegra_smmu *smmu) | |
1180 | { | |
0b480e44 JR |
1181 | iommu_device_unregister(&smmu->iommu); |
1182 | iommu_device_sysfs_remove(&smmu->iommu); | |
1183 | ||
d1313e78 TR |
1184 | if (IS_ENABLED(CONFIG_DEBUG_FS)) |
1185 | tegra_smmu_debugfs_exit(smmu); | |
1186 | } |