]> git.proxmox.com Git - mirror_ubuntu-jammy-kernel.git/blame - drivers/irqchip/Kconfig
Merge tag 'qcom-fixes-for-5.0-rc3' of git://git.kernel.org/pub/scm/linux/kernel/git...
[mirror_ubuntu-jammy-kernel.git] / drivers / irqchip / Kconfig
CommitLineData
c94fb639
RD
1menu "IRQ chip support"
2
f6e916b8
TP
3config IRQCHIP
4 def_bool y
5 depends on OF_IRQ
6
81243e44
RH
7config ARM_GIC
8 bool
9 select IRQ_DOMAIN
9a1091ef 10 select IRQ_DOMAIN_HIERARCHY
4f7799d9 11 select GENERIC_IRQ_MULTI_HANDLER
0c9e4982 12 select GENERIC_IRQ_EFFECTIVE_AFF_MASK
81243e44 13
9c8edddf
JH
14config ARM_GIC_PM
15 bool
16 depends on PM
17 select ARM_GIC
18 select PM_CLK
19
a27d21e0
LW
20config ARM_GIC_MAX_NR
21 int
22 default 2 if ARCH_REALVIEW
23 default 1
24
853a33ce
SS
25config ARM_GIC_V2M
26 bool
3ee80364
AB
27 depends on PCI
28 select ARM_GIC
29 select PCI_MSI
853a33ce 30
81243e44
RH
31config GIC_NON_BANKED
32 bool
33
021f6537
MZ
34config ARM_GIC_V3
35 bool
36 select IRQ_DOMAIN
4f7799d9 37 select GENERIC_IRQ_MULTI_HANDLER
443acc4f 38 select IRQ_DOMAIN_HIERARCHY
e3825ba1 39 select PARTITION_PERCPU
956ae91a 40 select GENERIC_IRQ_EFFECTIVE_AFF_MASK
021f6537 41
19812729
MZ
42config ARM_GIC_V3_ITS
43 bool
29f41139
MZ
44 select GENERIC_MSI_IRQ_DOMAIN
45 default ARM_GIC_V3
46
47config ARM_GIC_V3_ITS_PCI
48 bool
49 depends on ARM_GIC_V3_ITS
3ee80364
AB
50 depends on PCI
51 depends on PCI_MSI
29f41139 52 default ARM_GIC_V3_ITS
021f6537 53
7afe031c
BP
54config ARM_GIC_V3_ITS_FSL_MC
55 bool
56 depends on ARM_GIC_V3_ITS
57 depends on FSL_MC_BUS
58 default ARM_GIC_V3_ITS
59
292ec080
UKK
60config ARM_NVIC
61 bool
62 select IRQ_DOMAIN
2d9f59f7 63 select IRQ_DOMAIN_HIERARCHY
292ec080
UKK
64 select GENERIC_IRQ_CHIP
65
44430ec0
RH
66config ARM_VIC
67 bool
68 select IRQ_DOMAIN
4f7799d9 69 select GENERIC_IRQ_MULTI_HANDLER
44430ec0
RH
70
71config ARM_VIC_NR
72 int
73 default 4 if ARCH_S5PV210
44430ec0
RH
74 default 2
75 depends on ARM_VIC
76 help
77 The maximum number of VICs available in the system, for
78 power management.
79
fed6d336
TP
80config ARMADA_370_XP_IRQ
81 bool
fed6d336 82 select GENERIC_IRQ_CHIP
3ee80364 83 select PCI_MSI if PCI
e31793a3 84 select GENERIC_IRQ_EFFECTIVE_AFF_MASK
fed6d336 85
e6b78f2c
AT
86config ALPINE_MSI
87 bool
3ee80364
AB
88 depends on PCI
89 select PCI_MSI
e6b78f2c 90 select GENERIC_IRQ_CHIP
e6b78f2c 91
b1479ebb
BB
92config ATMEL_AIC_IRQ
93 bool
94 select GENERIC_IRQ_CHIP
95 select IRQ_DOMAIN
4f7799d9 96 select GENERIC_IRQ_MULTI_HANDLER
b1479ebb
BB
97 select SPARSE_IRQ
98
99config ATMEL_AIC5_IRQ
100 bool
101 select GENERIC_IRQ_CHIP
102 select IRQ_DOMAIN
4f7799d9 103 select GENERIC_IRQ_MULTI_HANDLER
b1479ebb
BB
104 select SPARSE_IRQ
105
0509cfde
RB
106config I8259
107 bool
108 select IRQ_DOMAIN
109
c7c42ec2
SA
110config BCM6345_L1_IRQ
111 bool
112 select GENERIC_IRQ_CHIP
113 select IRQ_DOMAIN
d0ed5e8e 114 select GENERIC_IRQ_EFFECTIVE_AFF_MASK
c7c42ec2 115
5f7f0317
KC
116config BCM7038_L1_IRQ
117 bool
118 select GENERIC_IRQ_CHIP
119 select IRQ_DOMAIN
b8d9884a 120 select GENERIC_IRQ_EFFECTIVE_AFF_MASK
5f7f0317 121
a4fcbb86
KC
122config BCM7120_L2_IRQ
123 bool
124 select GENERIC_IRQ_CHIP
125 select IRQ_DOMAIN
126
7f646e92
FF
127config BRCMSTB_L2_IRQ
128 bool
7f646e92
FF
129 select GENERIC_IRQ_CHIP
130 select IRQ_DOMAIN
131
350d71b9
SH
132config DW_APB_ICTL
133 bool
e1588490 134 select GENERIC_IRQ_CHIP
350d71b9
SH
135 select IRQ_DOMAIN
136
6ee532e2
LW
137config FARADAY_FTINTC010
138 bool
139 select IRQ_DOMAIN
4f7799d9 140 select GENERIC_IRQ_MULTI_HANDLER
6ee532e2
LW
141 select SPARSE_IRQ
142
9a7c4abd
M
143config HISILICON_IRQ_MBIGEN
144 bool
145 select ARM_GIC_V3
146 select ARM_GIC_V3_ITS
9a7c4abd 147
b6ef9161
JH
148config IMGPDC_IRQ
149 bool
150 select GENERIC_IRQ_CHIP
151 select IRQ_DOMAIN
152
da0abe1a
RF
153config MADERA_IRQ
154 tristate
155
67e38cf2
RB
156config IRQ_MIPS_CPU
157 bool
158 select GENERIC_IRQ_CHIP
3838a547 159 select GENERIC_IRQ_IPI if SYS_SUPPORTS_MULTITHREADING
67e38cf2 160 select IRQ_DOMAIN
3838a547 161 select IRQ_DOMAIN_HIERARCHY if GENERIC_IRQ_IPI
18416e45 162 select GENERIC_IRQ_EFFECTIVE_AFF_MASK
67e38cf2 163
afc98d90
AS
164config CLPS711X_IRQCHIP
165 bool
166 depends on ARCH_CLPS711X
167 select IRQ_DOMAIN
4f7799d9 168 select GENERIC_IRQ_MULTI_HANDLER
afc98d90
AS
169 select SPARSE_IRQ
170 default y
171
9b54470a
SH
172config OMPIC
173 bool
174
4db8e6d2
SK
175config OR1K_PIC
176 bool
177 select IRQ_DOMAIN
178
8598066c
FB
179config OMAP_IRQCHIP
180 bool
181 select GENERIC_IRQ_CHIP
182 select IRQ_DOMAIN
183
9dbd90f1
SH
184config ORION_IRQCHIP
185 bool
186 select IRQ_DOMAIN
4f7799d9 187 select GENERIC_IRQ_MULTI_HANDLER
9dbd90f1 188
aaa8666a
CB
189config PIC32_EVIC
190 bool
191 select GENERIC_IRQ_CHIP
192 select IRQ_DOMAIN
193
981b58f6 194config JCORE_AIC
3602ffde
RF
195 bool "J-Core integrated AIC" if COMPILE_TEST
196 depends on OF
981b58f6
RF
197 select IRQ_DOMAIN
198 help
199 Support for the J-Core integrated AIC.
200
d852e62a
MS
201config RDA_INTC
202 bool
203 select IRQ_DOMAIN
204
44358048
MD
205config RENESAS_INTC_IRQPIN
206 bool
207 select IRQ_DOMAIN
208
fbc83b7f
MD
209config RENESAS_IRQC
210 bool
99c221df 211 select GENERIC_IRQ_CHIP
fbc83b7f
MD
212 select IRQ_DOMAIN
213
07088484
LJ
214config ST_IRQCHIP
215 bool
216 select REGMAP
217 select MFD_SYSCON
218 help
219 Enables SysCfg Controlled IRQs on STi based platforms.
220
4bba6689
MR
221config TANGO_IRQ
222 bool
223 select IRQ_DOMAIN
224 select GENERIC_IRQ_CHIP
225
b06eb017
CR
226config TB10X_IRQC
227 bool
228 select IRQ_DOMAIN
229 select GENERIC_IRQ_CHIP
230
d01f8633
DR
231config TS4800_IRQ
232 tristate "TS-4800 IRQ controller"
233 select IRQ_DOMAIN
0df337cf 234 depends on HAS_IOMEM
d2b383dc 235 depends on SOC_IMX51 || COMPILE_TEST
d01f8633
DR
236 help
237 Support for the TS-4800 FPGA IRQ controller
238
2389d501
LW
239config VERSATILE_FPGA_IRQ
240 bool
241 select IRQ_DOMAIN
242
243config VERSATILE_FPGA_IRQ_NR
244 int
245 default 4
246 depends on VERSATILE_FPGA_IRQ
26a8e96a
MF
247
248config XTENSA_MX
249 bool
250 select IRQ_DOMAIN
50091212 251 select GENERIC_IRQ_EFFECTIVE_AFF_MASK
96ca848e 252
0547dc78
ZLK
253config XILINX_INTC
254 bool
255 select IRQ_DOMAIN
256
96ca848e
S
257config IRQ_CROSSBAR
258 bool
259 help
f54619f2 260 Support for a CROSSBAR ip that precedes the main interrupt controller.
96ca848e
S
261 The primary irqchip invokes the crossbar's callback which inturn allocates
262 a free irq and configures the IP. Thus the peripheral interrupts are
263 routed to one of the free irqchip interrupt lines.
89323f8c
GS
264
265config KEYSTONE_IRQ
266 tristate "Keystone 2 IRQ controller IP"
267 depends on ARCH_KEYSTONE
268 help
269 Support for Texas Instruments Keystone 2 IRQ controller IP which
270 is part of the Keystone 2 IPC mechanism
8a19b8f1
AB
271
272config MIPS_GIC
273 bool
bb11cff3 274 select GENERIC_IRQ_IPI
2af70a96 275 select IRQ_DOMAIN_HIERARCHY
8a19b8f1 276 select MIPS_CM
8a764482 277
44e08e70
PB
278config INGENIC_IRQ
279 bool
280 depends on MACH_INGENIC
281 default y
78c10e55 282
8a764482
YS
283config RENESAS_H8300H_INTC
284 bool
285 select IRQ_DOMAIN
286
287config RENESAS_H8S_INTC
288 bool
78c10e55 289 select IRQ_DOMAIN
e324c4dc
SW
290
291config IMX_GPCV2
292 bool
293 select IRQ_DOMAIN
294 help
295 Enables the wakeup IRQs for IMX platforms with GPCv2 block
7e4ac676
OR
296
297config IRQ_MXS
298 def_bool y if MACH_ASM9260 || ARCH_MXS
299 select IRQ_DOMAIN
300 select STMP_DEVICE
c27f29bb 301
19d99164
AB
302config MSCC_OCELOT_IRQ
303 bool
304 select IRQ_DOMAIN
305 select GENERIC_IRQ_CHIP
306
a68a63cb
TP
307config MVEBU_GICP
308 bool
309
e0de91a9
TP
310config MVEBU_ICU
311 bool
312
c27f29bb
TP
313config MVEBU_ODMI
314 bool
fa23b9d1 315 select GENERIC_MSI_IRQ_DOMAIN
9e2c986c 316
a109893b
TP
317config MVEBU_PIC
318 bool
319
61ce8d8d
MR
320config MVEBU_SEI
321 bool
322
b8f3ebe6
ML
323config LS_SCFG_MSI
324 def_bool y if SOC_LS1021A || ARCH_LAYERSCAPE
325 depends on PCI && PCI_MSI
b8f3ebe6 326
9e2c986c
MZ
327config PARTITION_PERCPU
328 bool
0efacbba 329
44df427c
NC
330config EZNPS_GIC
331 bool "NPS400 Global Interrupt Manager (GIM)"
ffd565e3 332 depends on ARC || (COMPILE_TEST && !64BIT)
44df427c
NC
333 select IRQ_DOMAIN
334 help
335 Support the EZchip NPS400 global interrupt controller
e0720416
AT
336
337config STM32_EXTI
338 bool
339 select IRQ_DOMAIN
0e7d7807 340 select GENERIC_IRQ_CHIP
f20cc9b0
AVF
341
342config QCOM_IRQ_COMBINER
343 bool "QCOM IRQ combiner support"
344 depends on ARCH_QCOM && ACPI
345 select IRQ_DOMAIN
346 select IRQ_DOMAIN_HIERARCHY
347 help
348 Say yes here to add support for the IRQ combiner devices embedded
349 in Qualcomm Technologies chips.
5ed34d3a
MY
350
351config IRQ_UNIPHIER_AIDET
352 bool "UniPhier AIDET support" if COMPILE_TEST
353 depends on ARCH_UNIPHIER || COMPILE_TEST
354 default ARCH_UNIPHIER
355 select IRQ_DOMAIN_HIERARCHY
356 help
357 Support for the UniPhier AIDET (ARM Interrupt Detector).
c94fb639 358
215f4cc0
JB
359config MESON_IRQ_GPIO
360 bool "Meson GPIO Interrupt Multiplexer"
d9ee91c1 361 depends on ARCH_MESON
215f4cc0
JB
362 select IRQ_DOMAIN
363 select IRQ_DOMAIN_HIERARCHY
364 help
365 Support Meson SoC Family GPIO Interrupt Multiplexer
366
4235ff50
MD
367config GOLDFISH_PIC
368 bool "Goldfish programmable interrupt controller"
369 depends on MIPS && (GOLDFISH || COMPILE_TEST)
370 select IRQ_DOMAIN
371 help
372 Say yes here to enable Goldfish interrupt controller driver used
373 for Goldfish based virtual platforms.
374
f55c73ae
AS
375config QCOM_PDC
376 bool "QCOM PDC"
377 depends on ARCH_QCOM
378 select IRQ_DOMAIN
379 select IRQ_DOMAIN_HIERARCHY
380 help
381 Power Domain Controller driver to manage and configure wakeup
382 IRQs for Qualcomm Technologies Inc (QTI) mobile chips.
383
d8a5f5f7
GR
384config CSKY_MPINTC
385 bool "C-SKY Multi Processor Interrupt Controller"
386 depends on CSKY
387 help
388 Say yes here to enable C-SKY SMP interrupt controller driver used
389 for C-SKY SMP system.
390 In fact it's not mmio map in hw and it use ld/st to visit the
391 controller's register inside CPU.
392
edff1b48
GR
393config CSKY_APB_INTC
394 bool "C-SKY APB Interrupt Controller"
395 depends on CSKY
396 help
397 Say yes here to enable C-SKY APB interrupt controller driver used
398 by C-SKY single core SOC system. It use mmio map apb-bus to visit
399 the controller's register.
400
0136afa0
LS
401config IMX_IRQSTEER
402 bool "i.MX IRQSTEER support"
403 depends on ARCH_MXC || COMPILE_TEST
404 default ARCH_MXC
405 select IRQ_DOMAIN
406 help
407 Support for the i.MX IRQSTEER interrupt multiplexer/remapper.
408
c94fb639 409endmenu
8237f8bc
CH
410
411config SIFIVE_PLIC
412 bool "SiFive Platform-Level Interrupt Controller"
413 depends on RISCV
414 help
415 This enables support for the PLIC chip found in SiFive (and
416 potentially other) RISC-V systems. The PLIC controls devices
417 interrupts and connects them to each core's local interrupt
418 controller. Aside from timer and software interrupts, all other
419 interrupt sources are subordinate to the PLIC.
420
421 If you don't know what to do here, say Y.