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f6e916b8
TP
1config IRQCHIP
2 def_bool y
3 depends on OF_IRQ
4
81243e44
RH
5config ARM_GIC
6 bool
7 select IRQ_DOMAIN
9a1091ef 8 select IRQ_DOMAIN_HIERARCHY
81243e44
RH
9 select MULTI_IRQ_HANDLER
10
9c8edddf
JH
11config ARM_GIC_PM
12 bool
13 depends on PM
14 select ARM_GIC
15 select PM_CLK
16
a27d21e0
LW
17config ARM_GIC_MAX_NR
18 int
19 default 2 if ARCH_REALVIEW
20 default 1
21
853a33ce
SS
22config ARM_GIC_V2M
23 bool
3ee80364
AB
24 depends on PCI
25 select ARM_GIC
26 select PCI_MSI
853a33ce 27
81243e44
RH
28config GIC_NON_BANKED
29 bool
30
021f6537
MZ
31config ARM_GIC_V3
32 bool
33 select IRQ_DOMAIN
34 select MULTI_IRQ_HANDLER
443acc4f 35 select IRQ_DOMAIN_HIERARCHY
e3825ba1 36 select PARTITION_PERCPU
021f6537 37
19812729
MZ
38config ARM_GIC_V3_ITS
39 bool
3ee80364
AB
40 depends on PCI
41 depends on PCI_MSI
021f6537 42
292ec080
UKK
43config ARM_NVIC
44 bool
45 select IRQ_DOMAIN
2d9f59f7 46 select IRQ_DOMAIN_HIERARCHY
292ec080
UKK
47 select GENERIC_IRQ_CHIP
48
44430ec0
RH
49config ARM_VIC
50 bool
51 select IRQ_DOMAIN
52 select MULTI_IRQ_HANDLER
53
54config ARM_VIC_NR
55 int
56 default 4 if ARCH_S5PV210
44430ec0
RH
57 default 2
58 depends on ARM_VIC
59 help
60 The maximum number of VICs available in the system, for
61 power management.
62
fed6d336
TP
63config ARMADA_370_XP_IRQ
64 bool
fed6d336 65 select GENERIC_IRQ_CHIP
3ee80364 66 select PCI_MSI if PCI
fed6d336 67
e6b78f2c
AT
68config ALPINE_MSI
69 bool
3ee80364
AB
70 depends on PCI
71 select PCI_MSI
e6b78f2c 72 select GENERIC_IRQ_CHIP
e6b78f2c 73
b1479ebb
BB
74config ATMEL_AIC_IRQ
75 bool
76 select GENERIC_IRQ_CHIP
77 select IRQ_DOMAIN
78 select MULTI_IRQ_HANDLER
79 select SPARSE_IRQ
80
81config ATMEL_AIC5_IRQ
82 bool
83 select GENERIC_IRQ_CHIP
84 select IRQ_DOMAIN
85 select MULTI_IRQ_HANDLER
86 select SPARSE_IRQ
87
0509cfde
RB
88config I8259
89 bool
90 select IRQ_DOMAIN
91
c7c42ec2
SA
92config BCM6345_L1_IRQ
93 bool
94 select GENERIC_IRQ_CHIP
95 select IRQ_DOMAIN
96
5f7f0317
KC
97config BCM7038_L1_IRQ
98 bool
99 select GENERIC_IRQ_CHIP
100 select IRQ_DOMAIN
101
a4fcbb86
KC
102config BCM7120_L2_IRQ
103 bool
104 select GENERIC_IRQ_CHIP
105 select IRQ_DOMAIN
106
7f646e92
FF
107config BRCMSTB_L2_IRQ
108 bool
7f646e92
FF
109 select GENERIC_IRQ_CHIP
110 select IRQ_DOMAIN
111
350d71b9
SH
112config DW_APB_ICTL
113 bool
e1588490 114 select GENERIC_IRQ_CHIP
350d71b9
SH
115 select IRQ_DOMAIN
116
6ee532e2
LW
117config FARADAY_FTINTC010
118 bool
119 select IRQ_DOMAIN
120 select MULTI_IRQ_HANDLER
121 select SPARSE_IRQ
122
9a7c4abd
M
123config HISILICON_IRQ_MBIGEN
124 bool
125 select ARM_GIC_V3
126 select ARM_GIC_V3_ITS
9a7c4abd 127
b6ef9161
JH
128config IMGPDC_IRQ
129 bool
130 select GENERIC_IRQ_CHIP
131 select IRQ_DOMAIN
132
67e38cf2
RB
133config IRQ_MIPS_CPU
134 bool
135 select GENERIC_IRQ_CHIP
3838a547 136 select GENERIC_IRQ_IPI if SYS_SUPPORTS_MULTITHREADING
67e38cf2 137 select IRQ_DOMAIN
3838a547 138 select IRQ_DOMAIN_HIERARCHY if GENERIC_IRQ_IPI
67e38cf2 139
afc98d90
AS
140config CLPS711X_IRQCHIP
141 bool
142 depends on ARCH_CLPS711X
143 select IRQ_DOMAIN
144 select MULTI_IRQ_HANDLER
145 select SPARSE_IRQ
146 default y
147
4db8e6d2
SK
148config OR1K_PIC
149 bool
150 select IRQ_DOMAIN
151
8598066c
FB
152config OMAP_IRQCHIP
153 bool
154 select GENERIC_IRQ_CHIP
155 select IRQ_DOMAIN
156
9dbd90f1
SH
157config ORION_IRQCHIP
158 bool
159 select IRQ_DOMAIN
160 select MULTI_IRQ_HANDLER
161
aaa8666a
CB
162config PIC32_EVIC
163 bool
164 select GENERIC_IRQ_CHIP
165 select IRQ_DOMAIN
166
981b58f6 167config JCORE_AIC
3602ffde
RF
168 bool "J-Core integrated AIC" if COMPILE_TEST
169 depends on OF
981b58f6
RF
170 select IRQ_DOMAIN
171 help
172 Support for the J-Core integrated AIC.
173
44358048
MD
174config RENESAS_INTC_IRQPIN
175 bool
176 select IRQ_DOMAIN
177
fbc83b7f
MD
178config RENESAS_IRQC
179 bool
99c221df 180 select GENERIC_IRQ_CHIP
fbc83b7f
MD
181 select IRQ_DOMAIN
182
07088484
LJ
183config ST_IRQCHIP
184 bool
185 select REGMAP
186 select MFD_SYSCON
187 help
188 Enables SysCfg Controlled IRQs on STi based platforms.
189
4bba6689
MR
190config TANGO_IRQ
191 bool
192 select IRQ_DOMAIN
193 select GENERIC_IRQ_CHIP
194
b06eb017
CR
195config TB10X_IRQC
196 bool
197 select IRQ_DOMAIN
198 select GENERIC_IRQ_CHIP
199
d01f8633
DR
200config TS4800_IRQ
201 tristate "TS-4800 IRQ controller"
202 select IRQ_DOMAIN
0df337cf 203 depends on HAS_IOMEM
d2b383dc 204 depends on SOC_IMX51 || COMPILE_TEST
d01f8633
DR
205 help
206 Support for the TS-4800 FPGA IRQ controller
207
2389d501
LW
208config VERSATILE_FPGA_IRQ
209 bool
210 select IRQ_DOMAIN
211
212config VERSATILE_FPGA_IRQ_NR
213 int
214 default 4
215 depends on VERSATILE_FPGA_IRQ
26a8e96a
MF
216
217config XTENSA_MX
218 bool
219 select IRQ_DOMAIN
96ca848e 220
0547dc78
ZLK
221config XILINX_INTC
222 bool
223 select IRQ_DOMAIN
224
96ca848e
S
225config IRQ_CROSSBAR
226 bool
227 help
f54619f2 228 Support for a CROSSBAR ip that precedes the main interrupt controller.
96ca848e
S
229 The primary irqchip invokes the crossbar's callback which inturn allocates
230 a free irq and configures the IP. Thus the peripheral interrupts are
231 routed to one of the free irqchip interrupt lines.
89323f8c
GS
232
233config KEYSTONE_IRQ
234 tristate "Keystone 2 IRQ controller IP"
235 depends on ARCH_KEYSTONE
236 help
237 Support for Texas Instruments Keystone 2 IRQ controller IP which
238 is part of the Keystone 2 IPC mechanism
8a19b8f1
AB
239
240config MIPS_GIC
241 bool
bb11cff3 242 select GENERIC_IRQ_IPI
2af70a96 243 select IRQ_DOMAIN_HIERARCHY
8a19b8f1 244 select MIPS_CM
8a764482 245
44e08e70
PB
246config INGENIC_IRQ
247 bool
248 depends on MACH_INGENIC
249 default y
78c10e55 250
8a764482
YS
251config RENESAS_H8300H_INTC
252 bool
253 select IRQ_DOMAIN
254
255config RENESAS_H8S_INTC
256 bool
78c10e55 257 select IRQ_DOMAIN
e324c4dc
SW
258
259config IMX_GPCV2
260 bool
261 select IRQ_DOMAIN
262 help
263 Enables the wakeup IRQs for IMX platforms with GPCv2 block
7e4ac676
OR
264
265config IRQ_MXS
266 def_bool y if MACH_ASM9260 || ARCH_MXS
267 select IRQ_DOMAIN
268 select STMP_DEVICE
c27f29bb 269
a68a63cb
TP
270config MVEBU_GICP
271 bool
272
e0de91a9
TP
273config MVEBU_ICU
274 bool
275
c27f29bb
TP
276config MVEBU_ODMI
277 bool
fa23b9d1 278 select GENERIC_MSI_IRQ_DOMAIN
9e2c986c 279
a109893b
TP
280config MVEBU_PIC
281 bool
282
b8f3ebe6
ML
283config LS_SCFG_MSI
284 def_bool y if SOC_LS1021A || ARCH_LAYERSCAPE
285 depends on PCI && PCI_MSI
b8f3ebe6 286
9e2c986c
MZ
287config PARTITION_PERCPU
288 bool
0efacbba 289
44df427c
NC
290config EZNPS_GIC
291 bool "NPS400 Global Interrupt Manager (GIM)"
ffd565e3 292 depends on ARC || (COMPILE_TEST && !64BIT)
44df427c
NC
293 select IRQ_DOMAIN
294 help
295 Support the EZchip NPS400 global interrupt controller
e0720416
AT
296
297config STM32_EXTI
298 bool
299 select IRQ_DOMAIN
f20cc9b0
AVF
300
301config QCOM_IRQ_COMBINER
302 bool "QCOM IRQ combiner support"
303 depends on ARCH_QCOM && ACPI
304 select IRQ_DOMAIN
305 select IRQ_DOMAIN_HIERARCHY
306 help
307 Say yes here to add support for the IRQ combiner devices embedded
308 in Qualcomm Technologies chips.