[mirror_ubuntu-jammy-kernel.git] / drivers / irqchip / Kconfig

config IRQCHIP
	def_bool y
	depends on OF_IRQ

config ARM_GIC
	bool
	select IRQ_DOMAIN
	select MULTI_IRQ_HANDLER

config GIC_NON_BANKED
	bool

config ARM_NVIC
	bool
	select IRQ_DOMAIN
	select GENERIC_IRQ_CHIP

config ARM_VIC
	bool
	select IRQ_DOMAIN
	select MULTI_IRQ_HANDLER

config ARM_VIC_NR
	int
	default 4 if ARCH_S5PV210
	default 3 if ARCH_S5PC100
	default 2
	depends on ARM_VIC
	help
	  The maximum number of VICs available in the system, for
	  power management.

config BRCMSTB_L2_IRQ
	bool
	depends on ARM
	select GENERIC_IRQ_CHIP
	select IRQ_DOMAIN

config DW_APB_ICTL
	bool
	select IRQ_DOMAIN

config IMGPDC_IRQ
	bool
	select GENERIC_IRQ_CHIP
	select IRQ_DOMAIN

config CLPS711X_IRQCHIP
	bool
	depends on ARCH_CLPS711X
	select IRQ_DOMAIN
	select MULTI_IRQ_HANDLER
	select SPARSE_IRQ
	default y

config ORION_IRQCHIP
	bool
	select IRQ_DOMAIN
	select MULTI_IRQ_HANDLER

config RENESAS_INTC_IRQPIN
	bool
	select IRQ_DOMAIN

config RENESAS_IRQC
	bool
	select IRQ_DOMAIN

config TB10X_IRQC
	bool
	select IRQ_DOMAIN
	select GENERIC_IRQ_CHIP

config VERSATILE_FPGA_IRQ
	bool
	select IRQ_DOMAIN

config VERSATILE_FPGA_IRQ_NR
       int
       default 4
       depends on VERSATILE_FPGA_IRQ

config XTENSA_MX
	bool
	select IRQ_DOMAIN

config IRQ_CROSSBAR
	bool
	help
	  Support for a CROSSBAR ip that preceeds the main interrupt controller.
	  The primary irqchip invokes the crossbar's callback which inturn allocates
	  a free irq and configures the IP. Thus the peripheral interrupts are
	  routed to one of the free irqchip interrupt lines.
Commit	Line	Data
f6e916b8 TP	1	config IRQCHIP
	2	def_bool y
	3	depends on OF_IRQ
	4
81243e44 RH	5	config ARM_GIC
	6	bool
	7	select IRQ_DOMAIN
	8	select MULTI_IRQ_HANDLER
	9
	10	config GIC_NON_BANKED
	11	bool
	12
292ec080 UKK	13	config ARM_NVIC
	14	bool
	15	select IRQ_DOMAIN
	16	select GENERIC_IRQ_CHIP
	17
44430ec0 RH	18	config ARM_VIC
	19	bool
	20	select IRQ_DOMAIN
	21	select MULTI_IRQ_HANDLER
	22
	23	config ARM_VIC_NR
	24	int
	25	default 4 if ARCH_S5PV210
	26	default 3 if ARCH_S5PC100
	27	default 2
	28	depends on ARM_VIC
	29	help
	30	The maximum number of VICs available in the system, for
	31	power management.
	32
7f646e92 FF	33	config BRCMSTB_L2_IRQ
	34	bool
	35	depends on ARM
	36	select GENERIC_IRQ_CHIP
	37	select IRQ_DOMAIN
	38
350d71b9 SH	39	config DW_APB_ICTL
	40	bool
	41	select IRQ_DOMAIN
	42
b6ef9161 JH	43	config IMGPDC_IRQ
	44	bool
	45	select GENERIC_IRQ_CHIP
	46	select IRQ_DOMAIN
	47
afc98d90 AS	48	config CLPS711X_IRQCHIP
	49	bool
	50	depends on ARCH_CLPS711X
	51	select IRQ_DOMAIN
	52	select MULTI_IRQ_HANDLER
	53	select SPARSE_IRQ
	54	default y
	55
9dbd90f1 SH	56	config ORION_IRQCHIP
	57	bool
	58	select IRQ_DOMAIN
	59	select MULTI_IRQ_HANDLER
	60
44358048 MD	61	config RENESAS_INTC_IRQPIN
	62	bool
	63	select IRQ_DOMAIN
	64
fbc83b7f MD	65	config RENESAS_IRQC
	66	bool
	67	select IRQ_DOMAIN
	68
b06eb017 CR	69	config TB10X_IRQC
	70	bool
	71	select IRQ_DOMAIN
	72	select GENERIC_IRQ_CHIP
	73
2389d501 LW	74	config VERSATILE_FPGA_IRQ
	75	bool
	76	select IRQ_DOMAIN
	77
	78	config VERSATILE_FPGA_IRQ_NR
	79	int
	80	default 4
	81	depends on VERSATILE_FPGA_IRQ
26a8e96a MF	82
	83	config XTENSA_MX
	84	bool
	85	select IRQ_DOMAIN
96ca848e S	86
	87	config IRQ_CROSSBAR
	88	bool
	89	help
	90	Support for a CROSSBAR ip that preceeds the main interrupt controller.
	91	The primary irqchip invokes the crossbar's callback which inturn allocates
	92	a free irq and configures the IP. Thus the peripheral interrupts are
	93	routed to one of the free irqchip interrupt lines.