[mirror_ubuntu-bionic-kernel.git] / drivers / irqchip / Kconfig

config IRQCHIP
	def_bool y
	depends on OF_IRQ

config ARM_GIC
	bool
	select IRQ_DOMAIN
	select IRQ_DOMAIN_HIERARCHY
	select MULTI_IRQ_HANDLER

config ARM_GIC_PM
	bool
	depends on PM
	select ARM_GIC
	select PM_CLK

config ARM_GIC_MAX_NR
	int
	default 2 if ARCH_REALVIEW
	default 1

config ARM_GIC_V2M
	bool
	depends on PCI
	select ARM_GIC
	select PCI_MSI

config GIC_NON_BANKED
	bool

config ARM_GIC_V3
	bool
	select IRQ_DOMAIN
	select MULTI_IRQ_HANDLER
	select IRQ_DOMAIN_HIERARCHY
	select PARTITION_PERCPU

config ARM_GIC_V3_ITS
	bool
	depends on PCI
	depends on PCI_MSI
	select ACPI_IORT if ACPI

config ARM_NVIC
	bool
	select IRQ_DOMAIN
	select IRQ_DOMAIN_HIERARCHY
	select GENERIC_IRQ_CHIP

config ARM_VIC
	bool
	select IRQ_DOMAIN
	select MULTI_IRQ_HANDLER

config ARM_VIC_NR
	int
	default 4 if ARCH_S5PV210
	default 2
	depends on ARM_VIC
	help
	  The maximum number of VICs available in the system, for
	  power management.

config ARMADA_370_XP_IRQ
	bool
	select GENERIC_IRQ_CHIP
	select PCI_MSI if PCI

config ALPINE_MSI
	bool
	depends on PCI
	select PCI_MSI
	select GENERIC_IRQ_CHIP

config ATMEL_AIC_IRQ
	bool
	select GENERIC_IRQ_CHIP
	select IRQ_DOMAIN
	select MULTI_IRQ_HANDLER
	select SPARSE_IRQ

config ATMEL_AIC5_IRQ
	bool
	select GENERIC_IRQ_CHIP
	select IRQ_DOMAIN
	select MULTI_IRQ_HANDLER
	select SPARSE_IRQ

config I8259
	bool
	select IRQ_DOMAIN

config BCM6345_L1_IRQ
	bool
	select GENERIC_IRQ_CHIP
	select IRQ_DOMAIN

config BCM7038_L1_IRQ
	bool
	select GENERIC_IRQ_CHIP
	select IRQ_DOMAIN

config BCM7120_L2_IRQ
	bool
	select GENERIC_IRQ_CHIP
	select IRQ_DOMAIN

config BRCMSTB_L2_IRQ
	bool
	select GENERIC_IRQ_CHIP
	select IRQ_DOMAIN

config DW_APB_ICTL
	bool
	select GENERIC_IRQ_CHIP
	select IRQ_DOMAIN

config HISILICON_IRQ_MBIGEN
	bool
	select ARM_GIC_V3
	select ARM_GIC_V3_ITS

config IMGPDC_IRQ
	bool
	select GENERIC_IRQ_CHIP
	select IRQ_DOMAIN

config IRQ_MIPS_CPU
	bool
	select GENERIC_IRQ_CHIP
	select IRQ_DOMAIN

config CLPS711X_IRQCHIP
	bool
	depends on ARCH_CLPS711X
	select IRQ_DOMAIN
	select MULTI_IRQ_HANDLER
	select SPARSE_IRQ
	default y

config OR1K_PIC
	bool
	select IRQ_DOMAIN

config OMAP_IRQCHIP
	bool
	select GENERIC_IRQ_CHIP
	select IRQ_DOMAIN

config ORION_IRQCHIP
	bool
	select IRQ_DOMAIN
	select MULTI_IRQ_HANDLER

config PIC32_EVIC
	bool
	select GENERIC_IRQ_CHIP
	select IRQ_DOMAIN

config JCORE_AIC
	bool "J-Core integrated AIC" if COMPILE_TEST
	depends on OF
	select IRQ_DOMAIN
	help
	  Support for the J-Core integrated AIC.

config RENESAS_INTC_IRQPIN
	bool
	select IRQ_DOMAIN

config RENESAS_IRQC
	bool
	select GENERIC_IRQ_CHIP
	select IRQ_DOMAIN

config ST_IRQCHIP
	bool
	select REGMAP
	select MFD_SYSCON
	help
	  Enables SysCfg Controlled IRQs on STi based platforms.

config TANGO_IRQ
	bool
	select IRQ_DOMAIN
	select GENERIC_IRQ_CHIP

config TB10X_IRQC
	bool
	select IRQ_DOMAIN
	select GENERIC_IRQ_CHIP

config TS4800_IRQ
	tristate "TS-4800 IRQ controller"
	select IRQ_DOMAIN
	depends on HAS_IOMEM
	depends on SOC_IMX51 || COMPILE_TEST
	help
	  Support for the TS-4800 FPGA IRQ controller

config VERSATILE_FPGA_IRQ
	bool
	select IRQ_DOMAIN

config VERSATILE_FPGA_IRQ_NR
       int
       default 4
       depends on VERSATILE_FPGA_IRQ

config XTENSA_MX
	bool
	select IRQ_DOMAIN

config XILINX_INTC
	bool
	select IRQ_DOMAIN

config IRQ_CROSSBAR
	bool
	help
	  Support for a CROSSBAR ip that precedes the main interrupt controller.
	  The primary irqchip invokes the crossbar's callback which inturn allocates
	  a free irq and configures the IP. Thus the peripheral interrupts are
	  routed to one of the free irqchip interrupt lines.

config KEYSTONE_IRQ
	tristate "Keystone 2 IRQ controller IP"
	depends on ARCH_KEYSTONE
	help
		Support for Texas Instruments Keystone 2 IRQ controller IP which
		is part of the Keystone 2 IPC mechanism

config MIPS_GIC
	bool
	select GENERIC_IRQ_IPI
	select IRQ_DOMAIN_HIERARCHY
	select MIPS_CM

config INGENIC_IRQ
	bool
	depends on MACH_INGENIC
	default y

config RENESAS_H8300H_INTC
        bool
	select IRQ_DOMAIN

config RENESAS_H8S_INTC
        bool
	select IRQ_DOMAIN

config IMX_GPCV2
	bool
	select IRQ_DOMAIN
	help
	  Enables the wakeup IRQs for IMX platforms with GPCv2 block

config IRQ_MXS
	def_bool y if MACH_ASM9260 || ARCH_MXS
	select IRQ_DOMAIN
	select STMP_DEVICE

config MVEBU_ODMI
	bool
	select GENERIC_MSI_IRQ_DOMAIN

config MVEBU_PIC
	bool

config LS_SCFG_MSI
	def_bool y if SOC_LS1021A || ARCH_LAYERSCAPE
	depends on PCI && PCI_MSI

config PARTITION_PERCPU
	bool

config EZNPS_GIC
	bool "NPS400 Global Interrupt Manager (GIM)"
	depends on ARC || (COMPILE_TEST && !64BIT)
	select IRQ_DOMAIN
	help
	  Support the EZchip NPS400 global interrupt controller

config STM32_EXTI
	bool
	select IRQ_DOMAIN

config QCOM_IRQ_COMBINER
	bool "QCOM IRQ combiner support"
	depends on ARCH_QCOM && ACPI
	select IRQ_DOMAIN
	select IRQ_DOMAIN_HIERARCHY
	help
	  Say yes here to add support for the IRQ combiner devices embedded
	  in Qualcomm Technologies chips.
Commit	Line	Data
f6e916b8 TP	1	config IRQCHIP
	2	def_bool y
	3	depends on OF_IRQ
	4
81243e44 RH	5	config ARM_GIC
	6	bool
	7	select IRQ_DOMAIN
9a1091ef	8	select IRQ_DOMAIN_HIERARCHY
81243e44 RH	9	select MULTI_IRQ_HANDLER
81243e44 RH	10
9c8edddf JH	11	config ARM_GIC_PM
	12	bool
	13	depends on PM
	14	select ARM_GIC
	15	select PM_CLK
	16
a27d21e0 LW	17	config ARM_GIC_MAX_NR
	18	int
	19	default 2 if ARCH_REALVIEW
	20	default 1
	21
853a33ce SS	22	config ARM_GIC_V2M
853a33ce SS	23	bool
3ee80364 AB	24	depends on PCI
	25	select ARM_GIC
	26	select PCI_MSI
853a33ce	27
81243e44 RH	28	config GIC_NON_BANKED
	29	bool
	30
021f6537 MZ	31	config ARM_GIC_V3
	32	bool
	33	select IRQ_DOMAIN
	34	select MULTI_IRQ_HANDLER
443acc4f	35	select IRQ_DOMAIN_HIERARCHY
e3825ba1	36	select PARTITION_PERCPU
021f6537	37
19812729 MZ	38	config ARM_GIC_V3_ITS
19812729 MZ	39	bool
3ee80364 AB	40	depends on PCI
3ee80364 AB	41	depends on PCI_MSI
3f010cf1	42	select ACPI_IORT if ACPI
021f6537	43
292ec080 UKK	44	config ARM_NVIC
	45	bool
	46	select IRQ_DOMAIN
2d9f59f7	47	select IRQ_DOMAIN_HIERARCHY
292ec080 UKK	48	select GENERIC_IRQ_CHIP
292ec080 UKK	49
44430ec0 RH	50	config ARM_VIC
	51	bool
	52	select IRQ_DOMAIN
	53	select MULTI_IRQ_HANDLER
	54
	55	config ARM_VIC_NR
	56	int
	57	default 4 if ARCH_S5PV210
44430ec0 RH	58	default 2
	59	depends on ARM_VIC
	60	help
	61	The maximum number of VICs available in the system, for
	62	power management.
	63
fed6d336 TP	64	config ARMADA_370_XP_IRQ
fed6d336 TP	65	bool
fed6d336	66	select GENERIC_IRQ_CHIP
3ee80364	67	select PCI_MSI if PCI
fed6d336	68
e6b78f2c AT	69	config ALPINE_MSI
e6b78f2c AT	70	bool
3ee80364 AB	71	depends on PCI
3ee80364 AB	72	select PCI_MSI
e6b78f2c	73	select GENERIC_IRQ_CHIP
e6b78f2c	74
b1479ebb BB	75	config ATMEL_AIC_IRQ
	76	bool
	77	select GENERIC_IRQ_CHIP
	78	select IRQ_DOMAIN
	79	select MULTI_IRQ_HANDLER
	80	select SPARSE_IRQ
	81
	82	config ATMEL_AIC5_IRQ
	83	bool
	84	select GENERIC_IRQ_CHIP
	85	select IRQ_DOMAIN
	86	select MULTI_IRQ_HANDLER
	87	select SPARSE_IRQ
	88
0509cfde RB	89	config I8259
	90	bool
	91	select IRQ_DOMAIN
	92
c7c42ec2 SA	93	config BCM6345_L1_IRQ
	94	bool
	95	select GENERIC_IRQ_CHIP
	96	select IRQ_DOMAIN
	97
5f7f0317 KC	98	config BCM7038_L1_IRQ
	99	bool
	100	select GENERIC_IRQ_CHIP
	101	select IRQ_DOMAIN
	102
a4fcbb86 KC	103	config BCM7120_L2_IRQ
	104	bool
	105	select GENERIC_IRQ_CHIP
	106	select IRQ_DOMAIN
	107
7f646e92 FF	108	config BRCMSTB_L2_IRQ
7f646e92 FF	109	bool
7f646e92 FF	110	select GENERIC_IRQ_CHIP
	111	select IRQ_DOMAIN
	112
350d71b9 SH	113	config DW_APB_ICTL
350d71b9 SH	114	bool
e1588490	115	select GENERIC_IRQ_CHIP
350d71b9 SH	116	select IRQ_DOMAIN
350d71b9 SH	117
9a7c4abd M	118	config HISILICON_IRQ_MBIGEN
	119	bool
	120	select ARM_GIC_V3
	121	select ARM_GIC_V3_ITS
9a7c4abd	122
b6ef9161 JH	123	config IMGPDC_IRQ
	124	bool
	125	select GENERIC_IRQ_CHIP
	126	select IRQ_DOMAIN
	127
67e38cf2 RB	128	config IRQ_MIPS_CPU
	129	bool
	130	select GENERIC_IRQ_CHIP
	131	select IRQ_DOMAIN
	132
afc98d90 AS	133	config CLPS711X_IRQCHIP
	134	bool
	135	depends on ARCH_CLPS711X
	136	select IRQ_DOMAIN
	137	select MULTI_IRQ_HANDLER
	138	select SPARSE_IRQ
	139	default y
	140
4db8e6d2 SK	141	config OR1K_PIC
	142	bool
	143	select IRQ_DOMAIN
	144
8598066c FB	145	config OMAP_IRQCHIP
	146	bool
	147	select GENERIC_IRQ_CHIP
	148	select IRQ_DOMAIN
	149
9dbd90f1 SH	150	config ORION_IRQCHIP
	151	bool
	152	select IRQ_DOMAIN
	153	select MULTI_IRQ_HANDLER
	154
aaa8666a CB	155	config PIC32_EVIC
	156	bool
	157	select GENERIC_IRQ_CHIP
	158	select IRQ_DOMAIN
	159
981b58f6	160	config JCORE_AIC
3602ffde RF	161	bool "J-Core integrated AIC" if COMPILE_TEST
3602ffde RF	162	depends on OF
981b58f6 RF	163	select IRQ_DOMAIN
	164	help
	165	Support for the J-Core integrated AIC.
	166
44358048 MD	167	config RENESAS_INTC_IRQPIN
	168	bool
	169	select IRQ_DOMAIN
	170
fbc83b7f MD	171	config RENESAS_IRQC
fbc83b7f MD	172	bool
99c221df	173	select GENERIC_IRQ_CHIP
fbc83b7f MD	174	select IRQ_DOMAIN
fbc83b7f MD	175
07088484 LJ	176	config ST_IRQCHIP
	177	bool
	178	select REGMAP
	179	select MFD_SYSCON
	180	help
	181	Enables SysCfg Controlled IRQs on STi based platforms.
	182
4bba6689 MR	183	config TANGO_IRQ
	184	bool
	185	select IRQ_DOMAIN
	186	select GENERIC_IRQ_CHIP
	187
b06eb017 CR	188	config TB10X_IRQC
	189	bool
	190	select IRQ_DOMAIN
	191	select GENERIC_IRQ_CHIP
	192
d01f8633 DR	193	config TS4800_IRQ
	194	tristate "TS-4800 IRQ controller"
	195	select IRQ_DOMAIN
0df337cf	196	depends on HAS_IOMEM
d2b383dc	197	depends on SOC_IMX51 \|\| COMPILE_TEST
d01f8633 DR	198	help
	199	Support for the TS-4800 FPGA IRQ controller
	200
2389d501 LW	201	config VERSATILE_FPGA_IRQ
	202	bool
	203	select IRQ_DOMAIN
	204
	205	config VERSATILE_FPGA_IRQ_NR
	206	int
	207	default 4
	208	depends on VERSATILE_FPGA_IRQ
26a8e96a MF	209
	210	config XTENSA_MX
	211	bool
	212	select IRQ_DOMAIN
96ca848e	213
0547dc78 ZLK	214	config XILINX_INTC
	215	bool
	216	select IRQ_DOMAIN
	217
96ca848e S	218	config IRQ_CROSSBAR
	219	bool
	220	help
f54619f2	221	Support for a CROSSBAR ip that precedes the main interrupt controller.
96ca848e S	222	The primary irqchip invokes the crossbar's callback which inturn allocates
	223	a free irq and configures the IP. Thus the peripheral interrupts are
	224	routed to one of the free irqchip interrupt lines.
89323f8c GS	225
	226	config KEYSTONE_IRQ
	227	tristate "Keystone 2 IRQ controller IP"
	228	depends on ARCH_KEYSTONE
	229	help
	230	Support for Texas Instruments Keystone 2 IRQ controller IP which
	231	is part of the Keystone 2 IPC mechanism
8a19b8f1 AB	232
	233	config MIPS_GIC
	234	bool
bb11cff3	235	select GENERIC_IRQ_IPI
2af70a96	236	select IRQ_DOMAIN_HIERARCHY
8a19b8f1	237	select MIPS_CM
8a764482	238
44e08e70 PB	239	config INGENIC_IRQ
	240	bool
	241	depends on MACH_INGENIC
	242	default y
78c10e55	243
8a764482 YS	244	config RENESAS_H8300H_INTC
	245	bool
	246	select IRQ_DOMAIN
	247
	248	config RENESAS_H8S_INTC
	249	bool
78c10e55	250	select IRQ_DOMAIN
e324c4dc SW	251
	252	config IMX_GPCV2
	253	bool
	254	select IRQ_DOMAIN
	255	help
	256	Enables the wakeup IRQs for IMX platforms with GPCv2 block
7e4ac676 OR	257
	258	config IRQ_MXS
	259	def_bool y if MACH_ASM9260 \|\| ARCH_MXS
	260	select IRQ_DOMAIN
	261	select STMP_DEVICE
c27f29bb TP	262
	263	config MVEBU_ODMI
	264	bool
fa23b9d1	265	select GENERIC_MSI_IRQ_DOMAIN
9e2c986c	266
a109893b TP	267	config MVEBU_PIC
	268	bool
	269
b8f3ebe6 ML	270	config LS_SCFG_MSI
	271	def_bool y if SOC_LS1021A \|\| ARCH_LAYERSCAPE
	272	depends on PCI && PCI_MSI
b8f3ebe6	273
9e2c986c MZ	274	config PARTITION_PERCPU
9e2c986c MZ	275	bool
0efacbba	276
44df427c NC	277	config EZNPS_GIC
44df427c NC	278	bool "NPS400 Global Interrupt Manager (GIM)"
ffd565e3	279	depends on ARC \|\| (COMPILE_TEST && !64BIT)
44df427c NC	280	select IRQ_DOMAIN
	281	help
	282	Support the EZchip NPS400 global interrupt controller
e0720416 AT	283
	284	config STM32_EXTI
	285	bool
	286	select IRQ_DOMAIN
f20cc9b0 AVF	287
	288	config QCOM_IRQ_COMBINER
	289	bool "QCOM IRQ combiner support"
	290	depends on ARCH_QCOM && ACPI
	291	select IRQ_DOMAIN
	292	select IRQ_DOMAIN_HIERARCHY
	293	help
	294	Say yes here to add support for the IRQ combiner devices embedded
	295	in Qualcomm Technologies chips.