[mirror_ubuntu-bionic-kernel.git] / drivers / irqchip / Kconfig

menu "IRQ chip support"

config IRQCHIP
	def_bool y
	depends on OF_IRQ

config ARM_GIC
	bool
	select IRQ_DOMAIN
	select IRQ_DOMAIN_HIERARCHY
	select MULTI_IRQ_HANDLER
	select GENERIC_IRQ_EFFECTIVE_AFF_MASK

config ARM_GIC_PM
	bool
	depends on PM
	select ARM_GIC
	select PM_CLK

config ARM_GIC_MAX_NR
	int
	default 2 if ARCH_REALVIEW
	default 1

config ARM_GIC_V2M
	bool
	depends on PCI
	select ARM_GIC
	select PCI_MSI

config GIC_NON_BANKED
	bool

config ARM_GIC_V3
	bool
	select IRQ_DOMAIN
	select MULTI_IRQ_HANDLER
	select IRQ_DOMAIN_HIERARCHY
	select PARTITION_PERCPU
	select GENERIC_IRQ_EFFECTIVE_AFF_MASK

config ARM_GIC_V3_ITS
	bool
	select GENERIC_MSI_IRQ_DOMAIN
	default ARM_GIC_V3

config ARM_GIC_V3_ITS_PCI
	bool
	depends on ARM_GIC_V3_ITS
	depends on PCI
	depends on PCI_MSI
	default ARM_GIC_V3_ITS

config ARM_NVIC
	bool
	select IRQ_DOMAIN
	select IRQ_DOMAIN_HIERARCHY
	select GENERIC_IRQ_CHIP

config ARM_VIC
	bool
	select IRQ_DOMAIN
	select MULTI_IRQ_HANDLER

config ARM_VIC_NR
	int
	default 4 if ARCH_S5PV210
	default 2
	depends on ARM_VIC
	help
	  The maximum number of VICs available in the system, for
	  power management.

config ARMADA_370_XP_IRQ
	bool
	select GENERIC_IRQ_CHIP
	select PCI_MSI if PCI
	select GENERIC_IRQ_EFFECTIVE_AFF_MASK

config ALPINE_MSI
	bool
	depends on PCI
	select PCI_MSI
	select GENERIC_IRQ_CHIP

config ATMEL_AIC_IRQ
	bool
	select GENERIC_IRQ_CHIP
	select IRQ_DOMAIN
	select MULTI_IRQ_HANDLER
	select SPARSE_IRQ

config ATMEL_AIC5_IRQ
	bool
	select GENERIC_IRQ_CHIP
	select IRQ_DOMAIN
	select MULTI_IRQ_HANDLER
	select SPARSE_IRQ

config I8259
	bool
	select IRQ_DOMAIN

config BCM6345_L1_IRQ
	bool
	select GENERIC_IRQ_CHIP
	select IRQ_DOMAIN
	select GENERIC_IRQ_EFFECTIVE_AFF_MASK

config BCM7038_L1_IRQ
	bool
	select GENERIC_IRQ_CHIP
	select IRQ_DOMAIN
	select GENERIC_IRQ_EFFECTIVE_AFF_MASK

config BCM7120_L2_IRQ
	bool
	select GENERIC_IRQ_CHIP
	select IRQ_DOMAIN

config BRCMSTB_L2_IRQ
	bool
	select GENERIC_IRQ_CHIP
	select IRQ_DOMAIN

config DW_APB_ICTL
	bool
	select GENERIC_IRQ_CHIP
	select IRQ_DOMAIN

config FARADAY_FTINTC010
	bool
	select IRQ_DOMAIN
	select MULTI_IRQ_HANDLER
	select SPARSE_IRQ

config HISILICON_IRQ_MBIGEN
	bool
	select ARM_GIC_V3
	select ARM_GIC_V3_ITS

config IMGPDC_IRQ
	bool
	select GENERIC_IRQ_CHIP
	select IRQ_DOMAIN

config IRQ_MIPS_CPU
	bool
	select GENERIC_IRQ_CHIP
	select GENERIC_IRQ_IPI if SYS_SUPPORTS_MULTITHREADING
	select IRQ_DOMAIN
	select IRQ_DOMAIN_HIERARCHY if GENERIC_IRQ_IPI
	select GENERIC_IRQ_EFFECTIVE_AFF_MASK

config CLPS711X_IRQCHIP
	bool
	depends on ARCH_CLPS711X
	select IRQ_DOMAIN
	select MULTI_IRQ_HANDLER
	select SPARSE_IRQ
	default y

config OMPIC
	bool

config OR1K_PIC
	bool
	select IRQ_DOMAIN

config OMAP_IRQCHIP
	bool
	select GENERIC_IRQ_CHIP
	select IRQ_DOMAIN

config ORION_IRQCHIP
	bool
	select IRQ_DOMAIN
	select MULTI_IRQ_HANDLER

config PIC32_EVIC
	bool
	select GENERIC_IRQ_CHIP
	select IRQ_DOMAIN

config JCORE_AIC
	bool "J-Core integrated AIC" if COMPILE_TEST
	depends on OF
	select IRQ_DOMAIN
	help
	  Support for the J-Core integrated AIC.

config RENESAS_INTC_IRQPIN
	bool
	select IRQ_DOMAIN

config RENESAS_IRQC
	bool
	select GENERIC_IRQ_CHIP
	select IRQ_DOMAIN

config ST_IRQCHIP
	bool
	select REGMAP
	select MFD_SYSCON
	help
	  Enables SysCfg Controlled IRQs on STi based platforms.

config TANGO_IRQ
	bool
	select IRQ_DOMAIN
	select GENERIC_IRQ_CHIP

config TB10X_IRQC
	bool
	select IRQ_DOMAIN
	select GENERIC_IRQ_CHIP

config TS4800_IRQ
	tristate "TS-4800 IRQ controller"
	select IRQ_DOMAIN
	depends on HAS_IOMEM
	depends on SOC_IMX51 || COMPILE_TEST
	help
	  Support for the TS-4800 FPGA IRQ controller

config VERSATILE_FPGA_IRQ
	bool
	select IRQ_DOMAIN

config VERSATILE_FPGA_IRQ_NR
       int
       default 4
       depends on VERSATILE_FPGA_IRQ

config XTENSA_MX
	bool
	select IRQ_DOMAIN
	select GENERIC_IRQ_EFFECTIVE_AFF_MASK

config XILINX_INTC
	bool
	select IRQ_DOMAIN

config IRQ_CROSSBAR
	bool
	help
	  Support for a CROSSBAR ip that precedes the main interrupt controller.
	  The primary irqchip invokes the crossbar's callback which inturn allocates
	  a free irq and configures the IP. Thus the peripheral interrupts are
	  routed to one of the free irqchip interrupt lines.

config KEYSTONE_IRQ
	tristate "Keystone 2 IRQ controller IP"
	depends on ARCH_KEYSTONE
	help
		Support for Texas Instruments Keystone 2 IRQ controller IP which
		is part of the Keystone 2 IPC mechanism

config MIPS_GIC
	bool
	select GENERIC_IRQ_IPI
	select IRQ_DOMAIN_HIERARCHY
	select MIPS_CM

config INGENIC_IRQ
	bool
	depends on MACH_INGENIC
	default y

config RENESAS_H8300H_INTC
        bool
	select IRQ_DOMAIN

config RENESAS_H8S_INTC
        bool
	select IRQ_DOMAIN

config IMX_GPCV2
	bool
	select IRQ_DOMAIN
	help
	  Enables the wakeup IRQs for IMX platforms with GPCv2 block

config IRQ_MXS
	def_bool y if MACH_ASM9260 || ARCH_MXS
	select IRQ_DOMAIN
	select STMP_DEVICE

config MVEBU_GICP
	bool

config MVEBU_ICU
	bool

config MVEBU_ODMI
	bool
	select GENERIC_MSI_IRQ_DOMAIN

config MVEBU_PIC
	bool

config LS_SCFG_MSI
	def_bool y if SOC_LS1021A || ARCH_LAYERSCAPE
	depends on PCI && PCI_MSI

config PARTITION_PERCPU
	bool

config EZNPS_GIC
	bool "NPS400 Global Interrupt Manager (GIM)"
	depends on ARC || (COMPILE_TEST && !64BIT)
	select IRQ_DOMAIN
	help
	  Support the EZchip NPS400 global interrupt controller

config STM32_EXTI
	bool
	select IRQ_DOMAIN
	select GENERIC_IRQ_CHIP

config QCOM_IRQ_COMBINER
	bool "QCOM IRQ combiner support"
	depends on ARCH_QCOM && ACPI
	select IRQ_DOMAIN
	select IRQ_DOMAIN_HIERARCHY
	help
	  Say yes here to add support for the IRQ combiner devices embedded
	  in Qualcomm Technologies chips.

config IRQ_UNIPHIER_AIDET
	bool "UniPhier AIDET support" if COMPILE_TEST
	depends on ARCH_UNIPHIER || COMPILE_TEST
	default ARCH_UNIPHIER
	select IRQ_DOMAIN_HIERARCHY
	help
	  Support for the UniPhier AIDET (ARM Interrupt Detector).

config MESON_IRQ_GPIO
       bool "Meson GPIO Interrupt Multiplexer"
       depends on ARCH_MESON
       select IRQ_DOMAIN
       select IRQ_DOMAIN_HIERARCHY
       help
         Support Meson SoC Family GPIO Interrupt Multiplexer

endmenu
Commit	Line	Data
c94fb639 RD	1	menu "IRQ chip support"
c94fb639 RD	2
f6e916b8 TP	3	config IRQCHIP
	4	def_bool y
	5	depends on OF_IRQ
	6
81243e44 RH	7	config ARM_GIC
	8	bool
	9	select IRQ_DOMAIN
9a1091ef	10	select IRQ_DOMAIN_HIERARCHY
81243e44	11	select MULTI_IRQ_HANDLER
0c9e4982	12	select GENERIC_IRQ_EFFECTIVE_AFF_MASK
81243e44	13
9c8edddf JH	14	config ARM_GIC_PM
	15	bool
	16	depends on PM
	17	select ARM_GIC
	18	select PM_CLK
	19
a27d21e0 LW	20	config ARM_GIC_MAX_NR
	21	int
	22	default 2 if ARCH_REALVIEW
	23	default 1
	24
853a33ce SS	25	config ARM_GIC_V2M
853a33ce SS	26	bool
3ee80364 AB	27	depends on PCI
	28	select ARM_GIC
	29	select PCI_MSI
853a33ce	30
81243e44 RH	31	config GIC_NON_BANKED
	32	bool
	33
021f6537 MZ	34	config ARM_GIC_V3
	35	bool
	36	select IRQ_DOMAIN
	37	select MULTI_IRQ_HANDLER
443acc4f	38	select IRQ_DOMAIN_HIERARCHY
e3825ba1	39	select PARTITION_PERCPU
956ae91a	40	select GENERIC_IRQ_EFFECTIVE_AFF_MASK
021f6537	41
19812729 MZ	42	config ARM_GIC_V3_ITS
19812729 MZ	43	bool
29f41139 MZ	44	select GENERIC_MSI_IRQ_DOMAIN
	45	default ARM_GIC_V3
	46
	47	config ARM_GIC_V3_ITS_PCI
	48	bool
	49	depends on ARM_GIC_V3_ITS
3ee80364 AB	50	depends on PCI
3ee80364 AB	51	depends on PCI_MSI
29f41139	52	default ARM_GIC_V3_ITS
021f6537	53
292ec080 UKK	54	config ARM_NVIC
	55	bool
	56	select IRQ_DOMAIN
2d9f59f7	57	select IRQ_DOMAIN_HIERARCHY
292ec080 UKK	58	select GENERIC_IRQ_CHIP
292ec080 UKK	59
44430ec0 RH	60	config ARM_VIC
	61	bool
	62	select IRQ_DOMAIN
	63	select MULTI_IRQ_HANDLER
	64
	65	config ARM_VIC_NR
	66	int
	67	default 4 if ARCH_S5PV210
44430ec0 RH	68	default 2
	69	depends on ARM_VIC
	70	help
	71	The maximum number of VICs available in the system, for
	72	power management.
	73
fed6d336 TP	74	config ARMADA_370_XP_IRQ
fed6d336 TP	75	bool
fed6d336	76	select GENERIC_IRQ_CHIP
3ee80364	77	select PCI_MSI if PCI
e31793a3	78	select GENERIC_IRQ_EFFECTIVE_AFF_MASK
fed6d336	79
e6b78f2c AT	80	config ALPINE_MSI
e6b78f2c AT	81	bool
3ee80364 AB	82	depends on PCI
3ee80364 AB	83	select PCI_MSI
e6b78f2c	84	select GENERIC_IRQ_CHIP
e6b78f2c	85
b1479ebb BB	86	config ATMEL_AIC_IRQ
	87	bool
	88	select GENERIC_IRQ_CHIP
	89	select IRQ_DOMAIN
	90	select MULTI_IRQ_HANDLER
	91	select SPARSE_IRQ
	92
	93	config ATMEL_AIC5_IRQ
	94	bool
	95	select GENERIC_IRQ_CHIP
	96	select IRQ_DOMAIN
	97	select MULTI_IRQ_HANDLER
	98	select SPARSE_IRQ
	99
0509cfde RB	100	config I8259
	101	bool
	102	select IRQ_DOMAIN
	103
c7c42ec2 SA	104	config BCM6345_L1_IRQ
	105	bool
	106	select GENERIC_IRQ_CHIP
	107	select IRQ_DOMAIN
d0ed5e8e	108	select GENERIC_IRQ_EFFECTIVE_AFF_MASK
c7c42ec2	109
5f7f0317 KC	110	config BCM7038_L1_IRQ
	111	bool
	112	select GENERIC_IRQ_CHIP
	113	select IRQ_DOMAIN
b8d9884a	114	select GENERIC_IRQ_EFFECTIVE_AFF_MASK
5f7f0317	115
a4fcbb86 KC	116	config BCM7120_L2_IRQ
	117	bool
	118	select GENERIC_IRQ_CHIP
	119	select IRQ_DOMAIN
	120
7f646e92 FF	121	config BRCMSTB_L2_IRQ
7f646e92 FF	122	bool
7f646e92 FF	123	select GENERIC_IRQ_CHIP
	124	select IRQ_DOMAIN
	125
350d71b9 SH	126	config DW_APB_ICTL
350d71b9 SH	127	bool
e1588490	128	select GENERIC_IRQ_CHIP
350d71b9 SH	129	select IRQ_DOMAIN
350d71b9 SH	130
6ee532e2 LW	131	config FARADAY_FTINTC010
	132	bool
	133	select IRQ_DOMAIN
	134	select MULTI_IRQ_HANDLER
	135	select SPARSE_IRQ
	136
9a7c4abd M	137	config HISILICON_IRQ_MBIGEN
	138	bool
	139	select ARM_GIC_V3
	140	select ARM_GIC_V3_ITS
9a7c4abd	141
b6ef9161 JH	142	config IMGPDC_IRQ
	143	bool
	144	select GENERIC_IRQ_CHIP
	145	select IRQ_DOMAIN
	146
67e38cf2 RB	147	config IRQ_MIPS_CPU
	148	bool
	149	select GENERIC_IRQ_CHIP
3838a547	150	select GENERIC_IRQ_IPI if SYS_SUPPORTS_MULTITHREADING
67e38cf2	151	select IRQ_DOMAIN
3838a547	152	select IRQ_DOMAIN_HIERARCHY if GENERIC_IRQ_IPI
18416e45	153	select GENERIC_IRQ_EFFECTIVE_AFF_MASK
67e38cf2	154
afc98d90 AS	155	config CLPS711X_IRQCHIP
	156	bool
	157	depends on ARCH_CLPS711X
	158	select IRQ_DOMAIN
	159	select MULTI_IRQ_HANDLER
	160	select SPARSE_IRQ
	161	default y
	162
9b54470a SH	163	config OMPIC
	164	bool
	165
4db8e6d2 SK	166	config OR1K_PIC
	167	bool
	168	select IRQ_DOMAIN
	169
8598066c FB	170	config OMAP_IRQCHIP
	171	bool
	172	select GENERIC_IRQ_CHIP
	173	select IRQ_DOMAIN
	174
9dbd90f1 SH	175	config ORION_IRQCHIP
	176	bool
	177	select IRQ_DOMAIN
	178	select MULTI_IRQ_HANDLER
	179
aaa8666a CB	180	config PIC32_EVIC
	181	bool
	182	select GENERIC_IRQ_CHIP
	183	select IRQ_DOMAIN
	184
981b58f6	185	config JCORE_AIC
3602ffde RF	186	bool "J-Core integrated AIC" if COMPILE_TEST
3602ffde RF	187	depends on OF
981b58f6 RF	188	select IRQ_DOMAIN
	189	help
	190	Support for the J-Core integrated AIC.
	191
44358048 MD	192	config RENESAS_INTC_IRQPIN
	193	bool
	194	select IRQ_DOMAIN
	195
fbc83b7f MD	196	config RENESAS_IRQC
fbc83b7f MD	197	bool
99c221df	198	select GENERIC_IRQ_CHIP
fbc83b7f MD	199	select IRQ_DOMAIN
fbc83b7f MD	200
07088484 LJ	201	config ST_IRQCHIP
	202	bool
	203	select REGMAP
	204	select MFD_SYSCON
	205	help
	206	Enables SysCfg Controlled IRQs on STi based platforms.
	207
4bba6689 MR	208	config TANGO_IRQ
	209	bool
	210	select IRQ_DOMAIN
	211	select GENERIC_IRQ_CHIP
	212
b06eb017 CR	213	config TB10X_IRQC
	214	bool
	215	select IRQ_DOMAIN
	216	select GENERIC_IRQ_CHIP
	217
d01f8633 DR	218	config TS4800_IRQ
	219	tristate "TS-4800 IRQ controller"
	220	select IRQ_DOMAIN
0df337cf	221	depends on HAS_IOMEM
d2b383dc	222	depends on SOC_IMX51 \|\| COMPILE_TEST
d01f8633 DR	223	help
	224	Support for the TS-4800 FPGA IRQ controller
	225
2389d501 LW	226	config VERSATILE_FPGA_IRQ
	227	bool
	228	select IRQ_DOMAIN
	229
	230	config VERSATILE_FPGA_IRQ_NR
	231	int
	232	default 4
	233	depends on VERSATILE_FPGA_IRQ
26a8e96a MF	234
	235	config XTENSA_MX
	236	bool
	237	select IRQ_DOMAIN
50091212	238	select GENERIC_IRQ_EFFECTIVE_AFF_MASK
96ca848e	239
0547dc78 ZLK	240	config XILINX_INTC
	241	bool
	242	select IRQ_DOMAIN
	243
96ca848e S	244	config IRQ_CROSSBAR
	245	bool
	246	help
f54619f2	247	Support for a CROSSBAR ip that precedes the main interrupt controller.
96ca848e S	248	The primary irqchip invokes the crossbar's callback which inturn allocates
	249	a free irq and configures the IP. Thus the peripheral interrupts are
	250	routed to one of the free irqchip interrupt lines.
89323f8c GS	251
	252	config KEYSTONE_IRQ
	253	tristate "Keystone 2 IRQ controller IP"
	254	depends on ARCH_KEYSTONE
	255	help
	256	Support for Texas Instruments Keystone 2 IRQ controller IP which
	257	is part of the Keystone 2 IPC mechanism
8a19b8f1 AB	258
	259	config MIPS_GIC
	260	bool
bb11cff3	261	select GENERIC_IRQ_IPI
2af70a96	262	select IRQ_DOMAIN_HIERARCHY
8a19b8f1	263	select MIPS_CM
8a764482	264
44e08e70 PB	265	config INGENIC_IRQ
	266	bool
	267	depends on MACH_INGENIC
	268	default y
78c10e55	269
8a764482 YS	270	config RENESAS_H8300H_INTC
	271	bool
	272	select IRQ_DOMAIN
	273
	274	config RENESAS_H8S_INTC
	275	bool
78c10e55	276	select IRQ_DOMAIN
e324c4dc SW	277
	278	config IMX_GPCV2
	279	bool
	280	select IRQ_DOMAIN
	281	help
	282	Enables the wakeup IRQs for IMX platforms with GPCv2 block
7e4ac676 OR	283
	284	config IRQ_MXS
	285	def_bool y if MACH_ASM9260 \|\| ARCH_MXS
	286	select IRQ_DOMAIN
	287	select STMP_DEVICE
c27f29bb	288
a68a63cb TP	289	config MVEBU_GICP
	290	bool
	291
e0de91a9 TP	292	config MVEBU_ICU
	293	bool
	294
c27f29bb TP	295	config MVEBU_ODMI
c27f29bb TP	296	bool
fa23b9d1	297	select GENERIC_MSI_IRQ_DOMAIN
9e2c986c	298
a109893b TP	299	config MVEBU_PIC
	300	bool
	301
b8f3ebe6 ML	302	config LS_SCFG_MSI
	303	def_bool y if SOC_LS1021A \|\| ARCH_LAYERSCAPE
	304	depends on PCI && PCI_MSI
b8f3ebe6	305
9e2c986c MZ	306	config PARTITION_PERCPU
9e2c986c MZ	307	bool
0efacbba	308
44df427c NC	309	config EZNPS_GIC
44df427c NC	310	bool "NPS400 Global Interrupt Manager (GIM)"
ffd565e3	311	depends on ARC \|\| (COMPILE_TEST && !64BIT)
44df427c NC	312	select IRQ_DOMAIN
	313	help
	314	Support the EZchip NPS400 global interrupt controller
e0720416 AT	315
	316	config STM32_EXTI
	317	bool
	318	select IRQ_DOMAIN
0e7d7807	319	select GENERIC_IRQ_CHIP
f20cc9b0 AVF	320
	321	config QCOM_IRQ_COMBINER
	322	bool "QCOM IRQ combiner support"
	323	depends on ARCH_QCOM && ACPI
	324	select IRQ_DOMAIN
	325	select IRQ_DOMAIN_HIERARCHY
	326	help
	327	Say yes here to add support for the IRQ combiner devices embedded
	328	in Qualcomm Technologies chips.
5ed34d3a MY	329
	330	config IRQ_UNIPHIER_AIDET
	331	bool "UniPhier AIDET support" if COMPILE_TEST
	332	depends on ARCH_UNIPHIER \|\| COMPILE_TEST
	333	default ARCH_UNIPHIER
	334	select IRQ_DOMAIN_HIERARCHY
	335	help
	336	Support for the UniPhier AIDET (ARM Interrupt Detector).
c94fb639	337
215f4cc0 JB	338	config MESON_IRQ_GPIO
215f4cc0 JB	339	bool "Meson GPIO Interrupt Multiplexer"
d9ee91c1	340	depends on ARCH_MESON
215f4cc0 JB	341	select IRQ_DOMAIN
	342	select IRQ_DOMAIN_HIERARCHY
	343	help
	344	Support Meson SoC Family GPIO Interrupt Multiplexer
	345
c94fb639	346	endmenu