[mirror_ubuntu-bionic-kernel.git] / drivers / irqchip / Kconfig

config IRQCHIP
	def_bool y
	depends on OF_IRQ

config ARM_GIC
	bool
	select IRQ_DOMAIN
	select IRQ_DOMAIN_HIERARCHY
	select MULTI_IRQ_HANDLER

config ARM_GIC_MAX_NR
	int
	default 2 if ARCH_REALVIEW
	default 1

config ARM_GIC_V2M
	bool
	depends on ARM_GIC
	depends on PCI && PCI_MSI
	select PCI_MSI_IRQ_DOMAIN

config GIC_NON_BANKED
	bool

config ARM_GIC_V3
	bool
	select IRQ_DOMAIN
	select MULTI_IRQ_HANDLER
	select IRQ_DOMAIN_HIERARCHY

config ARM_GIC_V3_ITS
	bool
	select PCI_MSI_IRQ_DOMAIN

config HISILICON_IRQ_MBIGEN
	bool "Support mbigen interrupt controller"
	default n
	depends on ARM_GIC_V3 && ARM_GIC_V3_ITS && GENERIC_MSI_IRQ_DOMAIN
	help
	 Enable the mbigen interrupt controller used on
	 Hisilicon platform.

config ARM_NVIC
	bool
	select IRQ_DOMAIN
	select IRQ_DOMAIN_HIERARCHY
	select GENERIC_IRQ_CHIP

config ARM_VIC
	bool
	select IRQ_DOMAIN
	select MULTI_IRQ_HANDLER

config ARM_VIC_NR
	int
	default 4 if ARCH_S5PV210
	default 2
	depends on ARM_VIC
	help
	  The maximum number of VICs available in the system, for
	  power management.

config ATMEL_AIC_IRQ
	bool
	select GENERIC_IRQ_CHIP
	select IRQ_DOMAIN
	select MULTI_IRQ_HANDLER
	select SPARSE_IRQ

config ATMEL_AIC5_IRQ
	bool
	select GENERIC_IRQ_CHIP
	select IRQ_DOMAIN
	select MULTI_IRQ_HANDLER
	select SPARSE_IRQ

config I8259
	bool
	select IRQ_DOMAIN

config BCM7038_L1_IRQ
	bool
	select GENERIC_IRQ_CHIP
	select IRQ_DOMAIN

config BCM7120_L2_IRQ
	bool
	select GENERIC_IRQ_CHIP
	select IRQ_DOMAIN

config BRCMSTB_L2_IRQ
	bool
	select GENERIC_IRQ_CHIP
	select IRQ_DOMAIN

config DW_APB_ICTL
	bool
	select GENERIC_IRQ_CHIP
	select IRQ_DOMAIN

config IMGPDC_IRQ
	bool
	select GENERIC_IRQ_CHIP
	select IRQ_DOMAIN

config IRQ_MIPS_CPU
	bool
	select GENERIC_IRQ_CHIP
	select IRQ_DOMAIN

config CLPS711X_IRQCHIP
	bool
	depends on ARCH_CLPS711X
	select IRQ_DOMAIN
	select MULTI_IRQ_HANDLER
	select SPARSE_IRQ
	default y

config OR1K_PIC
	bool
	select IRQ_DOMAIN

config OMAP_IRQCHIP
	bool
	select GENERIC_IRQ_CHIP
	select IRQ_DOMAIN

config ORION_IRQCHIP
	bool
	select IRQ_DOMAIN
	select MULTI_IRQ_HANDLER

config PIC32_EVIC
	bool
	select GENERIC_IRQ_CHIP
	select IRQ_DOMAIN

config RENESAS_INTC_IRQPIN
	bool
	select IRQ_DOMAIN

config RENESAS_IRQC
	bool
	select GENERIC_IRQ_CHIP
	select IRQ_DOMAIN

config ST_IRQCHIP
	bool
	select REGMAP
	select MFD_SYSCON
	help
	  Enables SysCfg Controlled IRQs on STi based platforms.

config TB10X_IRQC
	bool
	select IRQ_DOMAIN
	select GENERIC_IRQ_CHIP

config TS4800_IRQ
	tristate "TS-4800 IRQ controller"
	select IRQ_DOMAIN
	depends on HAS_IOMEM
	help
	  Support for the TS-4800 FPGA IRQ controller

config VERSATILE_FPGA_IRQ
	bool
	select IRQ_DOMAIN

config VERSATILE_FPGA_IRQ_NR
       int
       default 4
       depends on VERSATILE_FPGA_IRQ

config XTENSA_MX
	bool
	select IRQ_DOMAIN

config IRQ_CROSSBAR
	bool
	help
	  Support for a CROSSBAR ip that precedes the main interrupt controller.
	  The primary irqchip invokes the crossbar's callback which inturn allocates
	  a free irq and configures the IP. Thus the peripheral interrupts are
	  routed to one of the free irqchip interrupt lines.

config KEYSTONE_IRQ
	tristate "Keystone 2 IRQ controller IP"
	depends on ARCH_KEYSTONE
	help
		Support for Texas Instruments Keystone 2 IRQ controller IP which
		is part of the Keystone 2 IPC mechanism

config MIPS_GIC
	bool
	select MIPS_CM

config INGENIC_IRQ
	bool
	depends on MACH_INGENIC
	default y

config RENESAS_H8300H_INTC
        bool
	select IRQ_DOMAIN

config RENESAS_H8S_INTC
        bool
	select IRQ_DOMAIN

config IMX_GPCV2
	bool
	select IRQ_DOMAIN
	help
	  Enables the wakeup IRQs for IMX platforms with GPCv2 block

config IRQ_MXS
	def_bool y if MACH_ASM9260 || ARCH_MXS
	select IRQ_DOMAIN
	select STMP_DEVICE
Commit	Line	Data
f6e916b8 TP	1	config IRQCHIP
	2	def_bool y
	3	depends on OF_IRQ
	4
81243e44 RH	5	config ARM_GIC
	6	bool
	7	select IRQ_DOMAIN
9a1091ef	8	select IRQ_DOMAIN_HIERARCHY
81243e44 RH	9	select MULTI_IRQ_HANDLER
81243e44 RH	10
a27d21e0 LW	11	config ARM_GIC_MAX_NR
	12	int
	13	default 2 if ARCH_REALVIEW
	14	default 1
	15
853a33ce SS	16	config ARM_GIC_V2M
	17	bool
	18	depends on ARM_GIC
	19	depends on PCI && PCI_MSI
	20	select PCI_MSI_IRQ_DOMAIN
	21
81243e44 RH	22	config GIC_NON_BANKED
	23	bool
	24
021f6537 MZ	25	config ARM_GIC_V3
	26	bool
	27	select IRQ_DOMAIN
	28	select MULTI_IRQ_HANDLER
443acc4f	29	select IRQ_DOMAIN_HIERARCHY
021f6537	30
19812729 MZ	31	config ARM_GIC_V3_ITS
	32	bool
	33	select PCI_MSI_IRQ_DOMAIN
021f6537	34
717c3dbc MJ	35	config HISILICON_IRQ_MBIGEN
	36	bool "Support mbigen interrupt controller"
	37	default n
	38	depends on ARM_GIC_V3 && ARM_GIC_V3_ITS && GENERIC_MSI_IRQ_DOMAIN
	39	help
	40	Enable the mbigen interrupt controller used on
	41	Hisilicon platform.
	42
292ec080 UKK	43	config ARM_NVIC
	44	bool
	45	select IRQ_DOMAIN
2d9f59f7	46	select IRQ_DOMAIN_HIERARCHY
292ec080 UKK	47	select GENERIC_IRQ_CHIP
292ec080 UKK	48
44430ec0 RH	49	config ARM_VIC
	50	bool
	51	select IRQ_DOMAIN
	52	select MULTI_IRQ_HANDLER
	53
	54	config ARM_VIC_NR
	55	int
	56	default 4 if ARCH_S5PV210
44430ec0 RH	57	default 2
	58	depends on ARM_VIC
	59	help
	60	The maximum number of VICs available in the system, for
	61	power management.
	62
b1479ebb BB	63	config ATMEL_AIC_IRQ
	64	bool
	65	select GENERIC_IRQ_CHIP
	66	select IRQ_DOMAIN
	67	select MULTI_IRQ_HANDLER
	68	select SPARSE_IRQ
	69
	70	config ATMEL_AIC5_IRQ
	71	bool
	72	select GENERIC_IRQ_CHIP
	73	select IRQ_DOMAIN
	74	select MULTI_IRQ_HANDLER
	75	select SPARSE_IRQ
	76
0509cfde RB	77	config I8259
	78	bool
	79	select IRQ_DOMAIN
	80
5f7f0317 KC	81	config BCM7038_L1_IRQ
	82	bool
	83	select GENERIC_IRQ_CHIP
	84	select IRQ_DOMAIN
	85
a4fcbb86 KC	86	config BCM7120_L2_IRQ
	87	bool
	88	select GENERIC_IRQ_CHIP
	89	select IRQ_DOMAIN
	90
7f646e92 FF	91	config BRCMSTB_L2_IRQ
7f646e92 FF	92	bool
7f646e92 FF	93	select GENERIC_IRQ_CHIP
	94	select IRQ_DOMAIN
	95
350d71b9 SH	96	config DW_APB_ICTL
350d71b9 SH	97	bool
e1588490	98	select GENERIC_IRQ_CHIP
350d71b9 SH	99	select IRQ_DOMAIN
350d71b9 SH	100
b6ef9161 JH	101	config IMGPDC_IRQ
	102	bool
	103	select GENERIC_IRQ_CHIP
	104	select IRQ_DOMAIN
	105
67e38cf2 RB	106	config IRQ_MIPS_CPU
	107	bool
	108	select GENERIC_IRQ_CHIP
	109	select IRQ_DOMAIN
	110
afc98d90 AS	111	config CLPS711X_IRQCHIP
	112	bool
	113	depends on ARCH_CLPS711X
	114	select IRQ_DOMAIN
	115	select MULTI_IRQ_HANDLER
	116	select SPARSE_IRQ
	117	default y
	118
4db8e6d2 SK	119	config OR1K_PIC
	120	bool
	121	select IRQ_DOMAIN
	122
8598066c FB	123	config OMAP_IRQCHIP
	124	bool
	125	select GENERIC_IRQ_CHIP
	126	select IRQ_DOMAIN
	127
9dbd90f1 SH	128	config ORION_IRQCHIP
	129	bool
	130	select IRQ_DOMAIN
	131	select MULTI_IRQ_HANDLER
	132
aaa8666a CB	133	config PIC32_EVIC
	134	bool
	135	select GENERIC_IRQ_CHIP
	136	select IRQ_DOMAIN
	137
44358048 MD	138	config RENESAS_INTC_IRQPIN
	139	bool
	140	select IRQ_DOMAIN
	141
fbc83b7f MD	142	config RENESAS_IRQC
fbc83b7f MD	143	bool
99c221df	144	select GENERIC_IRQ_CHIP
fbc83b7f MD	145	select IRQ_DOMAIN
fbc83b7f MD	146
07088484 LJ	147	config ST_IRQCHIP
	148	bool
	149	select REGMAP
	150	select MFD_SYSCON
	151	help
	152	Enables SysCfg Controlled IRQs on STi based platforms.
	153
b06eb017 CR	154	config TB10X_IRQC
	155	bool
	156	select IRQ_DOMAIN
	157	select GENERIC_IRQ_CHIP
	158
d01f8633 DR	159	config TS4800_IRQ
	160	tristate "TS-4800 IRQ controller"
	161	select IRQ_DOMAIN
0df337cf	162	depends on HAS_IOMEM
d01f8633 DR	163	help
	164	Support for the TS-4800 FPGA IRQ controller
	165
2389d501 LW	166	config VERSATILE_FPGA_IRQ
	167	bool
	168	select IRQ_DOMAIN
	169
	170	config VERSATILE_FPGA_IRQ_NR
	171	int
	172	default 4
	173	depends on VERSATILE_FPGA_IRQ
26a8e96a MF	174
	175	config XTENSA_MX
	176	bool
	177	select IRQ_DOMAIN
96ca848e S	178
	179	config IRQ_CROSSBAR
	180	bool
	181	help
f54619f2	182	Support for a CROSSBAR ip that precedes the main interrupt controller.
96ca848e S	183	The primary irqchip invokes the crossbar's callback which inturn allocates
	184	a free irq and configures the IP. Thus the peripheral interrupts are
	185	routed to one of the free irqchip interrupt lines.
89323f8c GS	186
	187	config KEYSTONE_IRQ
	188	tristate "Keystone 2 IRQ controller IP"
	189	depends on ARCH_KEYSTONE
	190	help
	191	Support for Texas Instruments Keystone 2 IRQ controller IP which
	192	is part of the Keystone 2 IPC mechanism
8a19b8f1 AB	193
	194	config MIPS_GIC
	195	bool
	196	select MIPS_CM
8a764482	197
44e08e70 PB	198	config INGENIC_IRQ
	199	bool
	200	depends on MACH_INGENIC
	201	default y
78c10e55	202
8a764482 YS	203	config RENESAS_H8300H_INTC
	204	bool
	205	select IRQ_DOMAIN
	206
	207	config RENESAS_H8S_INTC
	208	bool
78c10e55	209	select IRQ_DOMAIN
e324c4dc SW	210
	211	config IMX_GPCV2
	212	bool
	213	select IRQ_DOMAIN
	214	help
	215	Enables the wakeup IRQs for IMX platforms with GPCv2 block
7e4ac676 OR	216
	217	config IRQ_MXS
	218	def_bool y if MACH_ASM9260 \|\| ARCH_MXS
	219	select IRQ_DOMAIN
	220	select STMP_DEVICE