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Merge branch 'akpm' (patches from Andrew)
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ec8f24b7 1# SPDX-License-Identifier: GPL-2.0-only
c94fb639
RD
2menu "IRQ chip support"
3
f6e916b8
TP
4config IRQCHIP
5 def_bool y
6 depends on OF_IRQ
7
81243e44
RH
8config ARM_GIC
9 bool
9a1091ef 10 select IRQ_DOMAIN_HIERARCHY
4f7799d9 11 select GENERIC_IRQ_MULTI_HANDLER
0c9e4982 12 select GENERIC_IRQ_EFFECTIVE_AFF_MASK
81243e44 13
9c8edddf
JH
14config ARM_GIC_PM
15 bool
16 depends on PM
17 select ARM_GIC
9c8edddf 18
a27d21e0
LW
19config ARM_GIC_MAX_NR
20 int
70265523 21 depends on ARM_GIC
a27d21e0
LW
22 default 2 if ARCH_REALVIEW
23 default 1
24
853a33ce
SS
25config ARM_GIC_V2M
26 bool
3ee80364
AB
27 depends on PCI
28 select ARM_GIC
29 select PCI_MSI
853a33ce 30
81243e44
RH
31config GIC_NON_BANKED
32 bool
33
021f6537
MZ
34config ARM_GIC_V3
35 bool
4f7799d9 36 select GENERIC_IRQ_MULTI_HANDLER
443acc4f 37 select IRQ_DOMAIN_HIERARCHY
e3825ba1 38 select PARTITION_PERCPU
956ae91a 39 select GENERIC_IRQ_EFFECTIVE_AFF_MASK
021f6537 40
19812729
MZ
41config ARM_GIC_V3_ITS
42 bool
29f41139
MZ
43 select GENERIC_MSI_IRQ_DOMAIN
44 default ARM_GIC_V3
45
46config ARM_GIC_V3_ITS_PCI
47 bool
48 depends on ARM_GIC_V3_ITS
3ee80364
AB
49 depends on PCI
50 depends on PCI_MSI
29f41139 51 default ARM_GIC_V3_ITS
021f6537 52
7afe031c
BP
53config ARM_GIC_V3_ITS_FSL_MC
54 bool
55 depends on ARM_GIC_V3_ITS
56 depends on FSL_MC_BUS
57 default ARM_GIC_V3_ITS
58
292ec080
UKK
59config ARM_NVIC
60 bool
2d9f59f7 61 select IRQ_DOMAIN_HIERARCHY
292ec080
UKK
62 select GENERIC_IRQ_CHIP
63
44430ec0
RH
64config ARM_VIC
65 bool
66 select IRQ_DOMAIN
4f7799d9 67 select GENERIC_IRQ_MULTI_HANDLER
44430ec0
RH
68
69config ARM_VIC_NR
70 int
71 default 4 if ARCH_S5PV210
44430ec0
RH
72 default 2
73 depends on ARM_VIC
74 help
75 The maximum number of VICs available in the system, for
76 power management.
77
fed6d336
TP
78config ARMADA_370_XP_IRQ
79 bool
fed6d336 80 select GENERIC_IRQ_CHIP
3ee80364 81 select PCI_MSI if PCI
e31793a3 82 select GENERIC_IRQ_EFFECTIVE_AFF_MASK
fed6d336 83
e6b78f2c
AT
84config ALPINE_MSI
85 bool
3ee80364
AB
86 depends on PCI
87 select PCI_MSI
e6b78f2c 88 select GENERIC_IRQ_CHIP
e6b78f2c 89
1eb77c3b
TS
90config AL_FIC
91 bool "Amazon's Annapurna Labs Fabric Interrupt Controller"
92 depends on OF || COMPILE_TEST
93 select GENERIC_IRQ_CHIP
94 select IRQ_DOMAIN
95 help
96 Support Amazon's Annapurna Labs Fabric Interrupt Controller.
97
b1479ebb
BB
98config ATMEL_AIC_IRQ
99 bool
100 select GENERIC_IRQ_CHIP
101 select IRQ_DOMAIN
4f7799d9 102 select GENERIC_IRQ_MULTI_HANDLER
b1479ebb
BB
103 select SPARSE_IRQ
104
105config ATMEL_AIC5_IRQ
106 bool
107 select GENERIC_IRQ_CHIP
108 select IRQ_DOMAIN
4f7799d9 109 select GENERIC_IRQ_MULTI_HANDLER
b1479ebb
BB
110 select SPARSE_IRQ
111
0509cfde
RB
112config I8259
113 bool
114 select IRQ_DOMAIN
115
c7c42ec2
SA
116config BCM6345_L1_IRQ
117 bool
118 select GENERIC_IRQ_CHIP
119 select IRQ_DOMAIN
d0ed5e8e 120 select GENERIC_IRQ_EFFECTIVE_AFF_MASK
c7c42ec2 121
5f7f0317
KC
122config BCM7038_L1_IRQ
123 bool
124 select GENERIC_IRQ_CHIP
125 select IRQ_DOMAIN
b8d9884a 126 select GENERIC_IRQ_EFFECTIVE_AFF_MASK
5f7f0317 127
a4fcbb86
KC
128config BCM7120_L2_IRQ
129 bool
130 select GENERIC_IRQ_CHIP
131 select IRQ_DOMAIN
132
7f646e92
FF
133config BRCMSTB_L2_IRQ
134 bool
7f646e92
FF
135 select GENERIC_IRQ_CHIP
136 select IRQ_DOMAIN
137
0145beed
BG
138config DAVINCI_AINTC
139 bool
140 select GENERIC_IRQ_CHIP
141 select IRQ_DOMAIN
142
0fc3d74c
BG
143config DAVINCI_CP_INTC
144 bool
145 select GENERIC_IRQ_CHIP
146 select IRQ_DOMAIN
147
350d71b9
SH
148config DW_APB_ICTL
149 bool
e1588490 150 select GENERIC_IRQ_CHIP
54a38440 151 select IRQ_DOMAIN_HIERARCHY
350d71b9 152
6ee532e2
LW
153config FARADAY_FTINTC010
154 bool
155 select IRQ_DOMAIN
4f7799d9 156 select GENERIC_IRQ_MULTI_HANDLER
6ee532e2
LW
157 select SPARSE_IRQ
158
9a7c4abd
M
159config HISILICON_IRQ_MBIGEN
160 bool
161 select ARM_GIC_V3
162 select ARM_GIC_V3_ITS
9a7c4abd 163
b6ef9161
JH
164config IMGPDC_IRQ
165 bool
166 select GENERIC_IRQ_CHIP
167 select IRQ_DOMAIN
168
5b978c10
LW
169config IXP4XX_IRQ
170 bool
171 select IRQ_DOMAIN
172 select GENERIC_IRQ_MULTI_HANDLER
173 select SPARSE_IRQ
174
da0abe1a
RF
175config MADERA_IRQ
176 tristate
177
67e38cf2
RB
178config IRQ_MIPS_CPU
179 bool
180 select GENERIC_IRQ_CHIP
3838a547 181 select GENERIC_IRQ_IPI if SYS_SUPPORTS_MULTITHREADING
67e38cf2 182 select IRQ_DOMAIN
18416e45 183 select GENERIC_IRQ_EFFECTIVE_AFF_MASK
67e38cf2 184
afc98d90
AS
185config CLPS711X_IRQCHIP
186 bool
187 depends on ARCH_CLPS711X
188 select IRQ_DOMAIN
4f7799d9 189 select GENERIC_IRQ_MULTI_HANDLER
afc98d90
AS
190 select SPARSE_IRQ
191 default y
192
9b54470a
SH
193config OMPIC
194 bool
195
4db8e6d2
SK
196config OR1K_PIC
197 bool
198 select IRQ_DOMAIN
199
8598066c
FB
200config OMAP_IRQCHIP
201 bool
202 select GENERIC_IRQ_CHIP
203 select IRQ_DOMAIN
204
9dbd90f1
SH
205config ORION_IRQCHIP
206 bool
207 select IRQ_DOMAIN
4f7799d9 208 select GENERIC_IRQ_MULTI_HANDLER
9dbd90f1 209
aaa8666a
CB
210config PIC32_EVIC
211 bool
212 select GENERIC_IRQ_CHIP
213 select IRQ_DOMAIN
214
981b58f6 215config JCORE_AIC
3602ffde
RF
216 bool "J-Core integrated AIC" if COMPILE_TEST
217 depends on OF
981b58f6
RF
218 select IRQ_DOMAIN
219 help
220 Support for the J-Core integrated AIC.
221
d852e62a
MS
222config RDA_INTC
223 bool
224 select IRQ_DOMAIN
225
44358048 226config RENESAS_INTC_IRQPIN
02d7e041 227 bool "Renesas INTC External IRQ Pin Support" if COMPILE_TEST
44358048 228 select IRQ_DOMAIN
02d7e041
GU
229 help
230 Enable support for the Renesas Interrupt Controller for external
231 interrupt pins, as found on SH/R-Mobile and R-Car Gen1 SoCs.
44358048 232
fbc83b7f 233config RENESAS_IRQC
72d44c0c 234 bool "Renesas R-Mobile APE6, R-Car Gen{2,3} and RZ/G{1,2} IRQC support" if COMPILE_TEST
99c221df 235 select GENERIC_IRQ_CHIP
fbc83b7f 236 select IRQ_DOMAIN
02d7e041
GU
237 help
238 Enable support for the Renesas Interrupt Controller for external
72d44c0c 239 devices, as found on R-Mobile APE6, R-Car Gen{2,3} and RZ/G{1,2} SoCs.
fbc83b7f 240
a644ccb8 241config RENESAS_RZA1_IRQC
02d7e041 242 bool "Renesas RZ/A1 IRQC support" if COMPILE_TEST
a644ccb8 243 select IRQ_DOMAIN_HIERARCHY
02d7e041
GU
244 help
245 Enable support for the Renesas RZ/A1 Interrupt Controller, to use up
246 to 8 external interrupts with configurable sense select.
a644ccb8 247
03ac990e
MW
248config SL28CPLD_INTC
249 bool "Kontron sl28cpld IRQ controller"
250 depends on MFD_SL28CPLD=y || COMPILE_TEST
251 select REGMAP_IRQ
252 help
253 Interrupt controller driver for the board management controller
254 found on the Kontron sl28 CPLD.
255
07088484
LJ
256config ST_IRQCHIP
257 bool
258 select REGMAP
259 select MFD_SYSCON
260 help
261 Enables SysCfg Controlled IRQs on STi based platforms.
262
4bba6689
MR
263config TANGO_IRQ
264 bool
265 select IRQ_DOMAIN
266 select GENERIC_IRQ_CHIP
267
b06eb017
CR
268config TB10X_IRQC
269 bool
270 select IRQ_DOMAIN
271 select GENERIC_IRQ_CHIP
272
d01f8633
DR
273config TS4800_IRQ
274 tristate "TS-4800 IRQ controller"
275 select IRQ_DOMAIN
0df337cf 276 depends on HAS_IOMEM
d2b383dc 277 depends on SOC_IMX51 || COMPILE_TEST
d01f8633
DR
278 help
279 Support for the TS-4800 FPGA IRQ controller
280
2389d501
LW
281config VERSATILE_FPGA_IRQ
282 bool
283 select IRQ_DOMAIN
284
285config VERSATILE_FPGA_IRQ_NR
286 int
287 default 4
288 depends on VERSATILE_FPGA_IRQ
26a8e96a
MF
289
290config XTENSA_MX
291 bool
292 select IRQ_DOMAIN
50091212 293 select GENERIC_IRQ_EFFECTIVE_AFF_MASK
96ca848e 294
0547dc78
ZLK
295config XILINX_INTC
296 bool
297 select IRQ_DOMAIN
298
96ca848e
S
299config IRQ_CROSSBAR
300 bool
301 help
f54619f2 302 Support for a CROSSBAR ip that precedes the main interrupt controller.
96ca848e
S
303 The primary irqchip invokes the crossbar's callback which inturn allocates
304 a free irq and configures the IP. Thus the peripheral interrupts are
305 routed to one of the free irqchip interrupt lines.
89323f8c
GS
306
307config KEYSTONE_IRQ
308 tristate "Keystone 2 IRQ controller IP"
309 depends on ARCH_KEYSTONE
310 help
311 Support for Texas Instruments Keystone 2 IRQ controller IP which
312 is part of the Keystone 2 IPC mechanism
8a19b8f1
AB
313
314config MIPS_GIC
315 bool
bb11cff3 316 select GENERIC_IRQ_IPI
8a19b8f1 317 select MIPS_CM
8a764482 318
44e08e70
PB
319config INGENIC_IRQ
320 bool
321 depends on MACH_INGENIC
322 default y
78c10e55 323
9536eba0
PC
324config INGENIC_TCU_IRQ
325 bool "Ingenic JZ47xx TCU interrupt controller"
326 default MACH_INGENIC
327 depends on MIPS || COMPILE_TEST
328 select MFD_SYSCON
8084499b 329 select GENERIC_IRQ_CHIP
9536eba0
PC
330 help
331 Support for interrupts in the Timer/Counter Unit (TCU) of the Ingenic
332 JZ47xx SoCs.
333
334 If unsure, say N.
335
8a764482
YS
336config RENESAS_H8300H_INTC
337 bool
338 select IRQ_DOMAIN
339
340config RENESAS_H8S_INTC
02d7e041 341 bool "Renesas H8S Interrupt Controller Support" if COMPILE_TEST
78c10e55 342 select IRQ_DOMAIN
02d7e041
GU
343 help
344 Enable support for the Renesas H8/300 Interrupt Controller, as found
345 on Renesas H8S SoCs.
e324c4dc
SW
346
347config IMX_GPCV2
348 bool
349 select IRQ_DOMAIN
350 help
351 Enables the wakeup IRQs for IMX platforms with GPCv2 block
7e4ac676
OR
352
353config IRQ_MXS
354 def_bool y if MACH_ASM9260 || ARCH_MXS
355 select IRQ_DOMAIN
356 select STMP_DEVICE
c27f29bb 357
19d99164
AB
358config MSCC_OCELOT_IRQ
359 bool
360 select IRQ_DOMAIN
361 select GENERIC_IRQ_CHIP
362
a68a63cb
TP
363config MVEBU_GICP
364 bool
365
e0de91a9
TP
366config MVEBU_ICU
367 bool
368
c27f29bb
TP
369config MVEBU_ODMI
370 bool
fa23b9d1 371 select GENERIC_MSI_IRQ_DOMAIN
9e2c986c 372
a109893b
TP
373config MVEBU_PIC
374 bool
375
61ce8d8d
MR
376config MVEBU_SEI
377 bool
378
0dcd9f87
RV
379config LS_EXTIRQ
380 def_bool y if SOC_LS1021A || ARCH_LAYERSCAPE
381 select MFD_SYSCON
382
b8f3ebe6
ML
383config LS_SCFG_MSI
384 def_bool y if SOC_LS1021A || ARCH_LAYERSCAPE
385 depends on PCI && PCI_MSI
b8f3ebe6 386
9e2c986c
MZ
387config PARTITION_PERCPU
388 bool
0efacbba 389
e0720416
AT
390config STM32_EXTI
391 bool
392 select IRQ_DOMAIN
0e7d7807 393 select GENERIC_IRQ_CHIP
f20cc9b0
AVF
394
395config QCOM_IRQ_COMBINER
396 bool "QCOM IRQ combiner support"
397 depends on ARCH_QCOM && ACPI
f20cc9b0
AVF
398 select IRQ_DOMAIN_HIERARCHY
399 help
400 Say yes here to add support for the IRQ combiner devices embedded
401 in Qualcomm Technologies chips.
5ed34d3a
MY
402
403config IRQ_UNIPHIER_AIDET
404 bool "UniPhier AIDET support" if COMPILE_TEST
405 depends on ARCH_UNIPHIER || COMPILE_TEST
406 default ARCH_UNIPHIER
407 select IRQ_DOMAIN_HIERARCHY
408 help
409 Support for the UniPhier AIDET (ARM Interrupt Detector).
c94fb639 410
215f4cc0
JB
411config MESON_IRQ_GPIO
412 bool "Meson GPIO Interrupt Multiplexer"
d9ee91c1 413 depends on ARCH_MESON
215f4cc0
JB
414 select IRQ_DOMAIN_HIERARCHY
415 help
416 Support Meson SoC Family GPIO Interrupt Multiplexer
417
4235ff50
MD
418config GOLDFISH_PIC
419 bool "Goldfish programmable interrupt controller"
420 depends on MIPS && (GOLDFISH || COMPILE_TEST)
421 select IRQ_DOMAIN
422 help
423 Say yes here to enable Goldfish interrupt controller driver used
424 for Goldfish based virtual platforms.
425
f55c73ae 426config QCOM_PDC
a150dac5 427 bool "QCOM PDC"
f55c73ae 428 depends on ARCH_QCOM
f55c73ae
AS
429 select IRQ_DOMAIN_HIERARCHY
430 help
431 Power Domain Controller driver to manage and configure wakeup
432 IRQs for Qualcomm Technologies Inc (QTI) mobile chips.
433
d8a5f5f7
GR
434config CSKY_MPINTC
435 bool "C-SKY Multi Processor Interrupt Controller"
436 depends on CSKY
437 help
438 Say yes here to enable C-SKY SMP interrupt controller driver used
439 for C-SKY SMP system.
656b42de 440 In fact it's not mmio map in hardware and it uses ld/st to visit the
d8a5f5f7
GR
441 controller's register inside CPU.
442
edff1b48
GR
443config CSKY_APB_INTC
444 bool "C-SKY APB Interrupt Controller"
445 depends on CSKY
446 help
447 Say yes here to enable C-SKY APB interrupt controller driver used
656b42de 448 by C-SKY single core SOC system. It uses mmio map apb-bus to visit
edff1b48
GR
449 the controller's register.
450
0136afa0
LS
451config IMX_IRQSTEER
452 bool "i.MX IRQSTEER support"
453 depends on ARCH_MXC || COMPILE_TEST
454 default ARCH_MXC
455 select IRQ_DOMAIN
456 help
457 Support for the i.MX IRQSTEER interrupt multiplexer/remapper.
458
2fbb1396 459config IMX_INTMUX
66968d7d 460 def_bool y if ARCH_MXC || COMPILE_TEST
2fbb1396
JZ
461 select IRQ_DOMAIN
462 help
463 Support for the i.MX INTMUX interrupt multiplexer.
464
9e543e22
JY
465config LS1X_IRQ
466 bool "Loongson-1 Interrupt Controller"
467 depends on MACH_LOONGSON32
468 default y
469 select IRQ_DOMAIN
470 select GENERIC_IRQ_CHIP
471 help
472 Support for the Loongson-1 platform Interrupt Controller.
473
cd844b07
LV
474config TI_SCI_INTR_IRQCHIP
475 bool
476 depends on TI_SCI_PROTOCOL
477 select IRQ_DOMAIN_HIERARCHY
478 help
479 This enables the irqchip driver support for K3 Interrupt router
480 over TI System Control Interface available on some new TI's SoCs.
481 If you wish to use interrupt router irq resources managed by the
482 TI System Controller, say Y here. Otherwise, say N.
483
9f1463b8
LV
484config TI_SCI_INTA_IRQCHIP
485 bool
486 depends on TI_SCI_PROTOCOL
487 select IRQ_DOMAIN_HIERARCHY
f011df61 488 select TI_SCI_INTA_MSI_DOMAIN
9f1463b8
LV
489 help
490 This enables the irqchip driver support for K3 Interrupt aggregator
491 over TI System Control Interface available on some new TI's SoCs.
492 If you wish to use interrupt aggregator irq resources managed by the
493 TI System Controller, say Y here. Otherwise, say N.
494
04e2d1e0 495config TI_PRUSS_INTC
b8e594fa
SA
496 tristate
497 depends on TI_PRUSS
498 default TI_PRUSS
04e2d1e0
GJ
499 select IRQ_DOMAIN
500 help
501 This enables support for the PRU-ICSS Local Interrupt Controller
502 present within a PRU-ICSS subsystem present on various TI SoCs.
503 The PRUSS INTC enables various interrupts to be routed to multiple
504 different processors within the SoC.
505
6b7ce892
AP
506config RISCV_INTC
507 bool "RISC-V Local Interrupt Controller"
508 depends on RISCV
509 default y
510 help
511 This enables support for the per-HART local interrupt controller
512 found in standard RISC-V systems. The per-HART local interrupt
513 controller handles timer interrupts, software interrupts, and
514 hardware interrupts. Without a per-HART local interrupt controller,
515 a RISC-V system will be unable to handle any interrupts.
516
517 If you don't know what to do here, say Y.
518
8237f8bc
CH
519config SIFIVE_PLIC
520 bool "SiFive Platform-Level Interrupt Controller"
521 depends on RISCV
466008f9 522 select IRQ_DOMAIN_HIERARCHY
8237f8bc
CH
523 help
524 This enables support for the PLIC chip found in SiFive (and
525 potentially other) RISC-V systems. The PLIC controls devices
526 interrupts and connects them to each core's local interrupt
527 controller. Aside from timer and software interrupts, all other
528 interrupt sources are subordinate to the PLIC.
529
530 If you don't know what to do here, say Y.
01493855 531
b74416db
HK
532config EXYNOS_IRQ_COMBINER
533 bool "Samsung Exynos IRQ combiner support" if COMPILE_TEST
534 depends on (ARCH_EXYNOS && ARM) || COMPILE_TEST
535 help
536 Say yes here to add support for the IRQ combiner devices embedded
537 in Samsung Exynos chips.
538
dbb15226
JY
539config LOONGSON_LIOINTC
540 bool "Loongson Local I/O Interrupt Controller"
541 depends on MACH_LOONGSON64
542 default y
543 select IRQ_DOMAIN
544 select GENERIC_IRQ_CHIP
545 help
546 Support for the Loongson Local I/O Interrupt Controller.
547
a93f1d90
JY
548config LOONGSON_HTPIC
549 bool "Loongson3 HyperTransport PIC Controller"
550 depends on MACH_LOONGSON64
551 default y
552 select IRQ_DOMAIN
553 select GENERIC_IRQ_CHIP
a93f1d90
JY
554 help
555 Support for the Loongson-3 HyperTransport PIC Controller.
556
818e915f
JY
557config LOONGSON_HTVEC
558 bool "Loongson3 HyperTransport Interrupt Vector Controller"
d77aeb5d 559 depends on MACH_LOONGSON64
818e915f
JY
560 default MACH_LOONGSON64
561 select IRQ_DOMAIN_HIERARCHY
562 help
563 Support for the Loongson3 HyperTransport Interrupt Vector Controller.
564
ef8c01eb
JY
565config LOONGSON_PCH_PIC
566 bool "Loongson PCH PIC Controller"
567 depends on MACH_LOONGSON64 || COMPILE_TEST
568 default MACH_LOONGSON64
569 select IRQ_DOMAIN_HIERARCHY
570 select IRQ_FASTEOI_HIERARCHY_HANDLERS
571 help
572 Support for the Loongson PCH PIC Controller.
573
632dcc2c 574config LOONGSON_PCH_MSI
a23df9a4 575 bool "Loongson PCH MSI Controller"
632dcc2c
JY
576 depends on MACH_LOONGSON64 || COMPILE_TEST
577 depends on PCI
578 default MACH_LOONGSON64
579 select IRQ_DOMAIN_HIERARCHY
580 select PCI_MSI
581 help
582 Support for the Loongson PCH MSI Controller.
583
ad4c938c
MPT
584config MST_IRQ
585 bool "MStar Interrupt Controller"
61b0648d 586 depends on ARCH_MEDIATEK || ARCH_MSTARV7 || COMPILE_TEST
ad4c938c
MPT
587 default ARCH_MEDIATEK
588 select IRQ_DOMAIN
589 select IRQ_DOMAIN_HIERARCHY
590 help
591 Support MStar Interrupt Controller.
592
01493855 593endmenu