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Commit | Line | Data |
---|---|---|
c94fb639 RD |
1 | menu "IRQ chip support" |
2 | ||
f6e916b8 TP |
3 | config IRQCHIP |
4 | def_bool y | |
5 | depends on OF_IRQ | |
6 | ||
81243e44 RH |
7 | config ARM_GIC |
8 | bool | |
9 | select IRQ_DOMAIN | |
9a1091ef | 10 | select IRQ_DOMAIN_HIERARCHY |
4f7799d9 | 11 | select GENERIC_IRQ_MULTI_HANDLER |
0c9e4982 | 12 | select GENERIC_IRQ_EFFECTIVE_AFF_MASK |
81243e44 | 13 | |
9c8edddf JH |
14 | config ARM_GIC_PM |
15 | bool | |
16 | depends on PM | |
17 | select ARM_GIC | |
18 | select PM_CLK | |
19 | ||
a27d21e0 LW |
20 | config ARM_GIC_MAX_NR |
21 | int | |
22 | default 2 if ARCH_REALVIEW | |
23 | default 1 | |
24 | ||
853a33ce SS |
25 | config ARM_GIC_V2M |
26 | bool | |
3ee80364 AB |
27 | depends on PCI |
28 | select ARM_GIC | |
29 | select PCI_MSI | |
853a33ce | 30 | |
81243e44 RH |
31 | config GIC_NON_BANKED |
32 | bool | |
33 | ||
021f6537 MZ |
34 | config ARM_GIC_V3 |
35 | bool | |
36 | select IRQ_DOMAIN | |
4f7799d9 | 37 | select GENERIC_IRQ_MULTI_HANDLER |
443acc4f | 38 | select IRQ_DOMAIN_HIERARCHY |
e3825ba1 | 39 | select PARTITION_PERCPU |
956ae91a | 40 | select GENERIC_IRQ_EFFECTIVE_AFF_MASK |
021f6537 | 41 | |
19812729 MZ |
42 | config ARM_GIC_V3_ITS |
43 | bool | |
29f41139 MZ |
44 | select GENERIC_MSI_IRQ_DOMAIN |
45 | default ARM_GIC_V3 | |
46 | ||
47 | config ARM_GIC_V3_ITS_PCI | |
48 | bool | |
49 | depends on ARM_GIC_V3_ITS | |
3ee80364 AB |
50 | depends on PCI |
51 | depends on PCI_MSI | |
29f41139 | 52 | default ARM_GIC_V3_ITS |
021f6537 | 53 | |
7afe031c BP |
54 | config ARM_GIC_V3_ITS_FSL_MC |
55 | bool | |
56 | depends on ARM_GIC_V3_ITS | |
57 | depends on FSL_MC_BUS | |
58 | default ARM_GIC_V3_ITS | |
59 | ||
292ec080 UKK |
60 | config ARM_NVIC |
61 | bool | |
62 | select IRQ_DOMAIN | |
2d9f59f7 | 63 | select IRQ_DOMAIN_HIERARCHY |
292ec080 UKK |
64 | select GENERIC_IRQ_CHIP |
65 | ||
44430ec0 RH |
66 | config ARM_VIC |
67 | bool | |
68 | select IRQ_DOMAIN | |
4f7799d9 | 69 | select GENERIC_IRQ_MULTI_HANDLER |
44430ec0 RH |
70 | |
71 | config ARM_VIC_NR | |
72 | int | |
73 | default 4 if ARCH_S5PV210 | |
44430ec0 RH |
74 | default 2 |
75 | depends on ARM_VIC | |
76 | help | |
77 | The maximum number of VICs available in the system, for | |
78 | power management. | |
79 | ||
fed6d336 TP |
80 | config ARMADA_370_XP_IRQ |
81 | bool | |
fed6d336 | 82 | select GENERIC_IRQ_CHIP |
3ee80364 | 83 | select PCI_MSI if PCI |
e31793a3 | 84 | select GENERIC_IRQ_EFFECTIVE_AFF_MASK |
fed6d336 | 85 | |
e6b78f2c AT |
86 | config ALPINE_MSI |
87 | bool | |
3ee80364 AB |
88 | depends on PCI |
89 | select PCI_MSI | |
e6b78f2c | 90 | select GENERIC_IRQ_CHIP |
e6b78f2c | 91 | |
b1479ebb BB |
92 | config ATMEL_AIC_IRQ |
93 | bool | |
94 | select GENERIC_IRQ_CHIP | |
95 | select IRQ_DOMAIN | |
4f7799d9 | 96 | select GENERIC_IRQ_MULTI_HANDLER |
b1479ebb BB |
97 | select SPARSE_IRQ |
98 | ||
99 | config ATMEL_AIC5_IRQ | |
100 | bool | |
101 | select GENERIC_IRQ_CHIP | |
102 | select IRQ_DOMAIN | |
4f7799d9 | 103 | select GENERIC_IRQ_MULTI_HANDLER |
b1479ebb BB |
104 | select SPARSE_IRQ |
105 | ||
0509cfde RB |
106 | config I8259 |
107 | bool | |
108 | select IRQ_DOMAIN | |
109 | ||
c7c42ec2 SA |
110 | config BCM6345_L1_IRQ |
111 | bool | |
112 | select GENERIC_IRQ_CHIP | |
113 | select IRQ_DOMAIN | |
d0ed5e8e | 114 | select GENERIC_IRQ_EFFECTIVE_AFF_MASK |
c7c42ec2 | 115 | |
5f7f0317 KC |
116 | config BCM7038_L1_IRQ |
117 | bool | |
118 | select GENERIC_IRQ_CHIP | |
119 | select IRQ_DOMAIN | |
b8d9884a | 120 | select GENERIC_IRQ_EFFECTIVE_AFF_MASK |
5f7f0317 | 121 | |
a4fcbb86 KC |
122 | config BCM7120_L2_IRQ |
123 | bool | |
124 | select GENERIC_IRQ_CHIP | |
125 | select IRQ_DOMAIN | |
126 | ||
7f646e92 FF |
127 | config BRCMSTB_L2_IRQ |
128 | bool | |
7f646e92 FF |
129 | select GENERIC_IRQ_CHIP |
130 | select IRQ_DOMAIN | |
131 | ||
350d71b9 SH |
132 | config DW_APB_ICTL |
133 | bool | |
e1588490 | 134 | select GENERIC_IRQ_CHIP |
350d71b9 SH |
135 | select IRQ_DOMAIN |
136 | ||
6ee532e2 LW |
137 | config FARADAY_FTINTC010 |
138 | bool | |
139 | select IRQ_DOMAIN | |
4f7799d9 | 140 | select GENERIC_IRQ_MULTI_HANDLER |
6ee532e2 LW |
141 | select SPARSE_IRQ |
142 | ||
9a7c4abd M |
143 | config HISILICON_IRQ_MBIGEN |
144 | bool | |
145 | select ARM_GIC_V3 | |
146 | select ARM_GIC_V3_ITS | |
9a7c4abd | 147 | |
b6ef9161 JH |
148 | config IMGPDC_IRQ |
149 | bool | |
150 | select GENERIC_IRQ_CHIP | |
151 | select IRQ_DOMAIN | |
152 | ||
67e38cf2 RB |
153 | config IRQ_MIPS_CPU |
154 | bool | |
155 | select GENERIC_IRQ_CHIP | |
3838a547 | 156 | select GENERIC_IRQ_IPI if SYS_SUPPORTS_MULTITHREADING |
67e38cf2 | 157 | select IRQ_DOMAIN |
3838a547 | 158 | select IRQ_DOMAIN_HIERARCHY if GENERIC_IRQ_IPI |
18416e45 | 159 | select GENERIC_IRQ_EFFECTIVE_AFF_MASK |
67e38cf2 | 160 | |
afc98d90 AS |
161 | config CLPS711X_IRQCHIP |
162 | bool | |
163 | depends on ARCH_CLPS711X | |
164 | select IRQ_DOMAIN | |
4f7799d9 | 165 | select GENERIC_IRQ_MULTI_HANDLER |
afc98d90 AS |
166 | select SPARSE_IRQ |
167 | default y | |
168 | ||
9b54470a SH |
169 | config OMPIC |
170 | bool | |
171 | ||
4db8e6d2 SK |
172 | config OR1K_PIC |
173 | bool | |
174 | select IRQ_DOMAIN | |
175 | ||
8598066c FB |
176 | config OMAP_IRQCHIP |
177 | bool | |
178 | select GENERIC_IRQ_CHIP | |
179 | select IRQ_DOMAIN | |
180 | ||
9dbd90f1 SH |
181 | config ORION_IRQCHIP |
182 | bool | |
183 | select IRQ_DOMAIN | |
4f7799d9 | 184 | select GENERIC_IRQ_MULTI_HANDLER |
9dbd90f1 | 185 | |
aaa8666a CB |
186 | config PIC32_EVIC |
187 | bool | |
188 | select GENERIC_IRQ_CHIP | |
189 | select IRQ_DOMAIN | |
190 | ||
981b58f6 | 191 | config JCORE_AIC |
3602ffde RF |
192 | bool "J-Core integrated AIC" if COMPILE_TEST |
193 | depends on OF | |
981b58f6 RF |
194 | select IRQ_DOMAIN |
195 | help | |
196 | Support for the J-Core integrated AIC. | |
197 | ||
44358048 MD |
198 | config RENESAS_INTC_IRQPIN |
199 | bool | |
200 | select IRQ_DOMAIN | |
201 | ||
fbc83b7f MD |
202 | config RENESAS_IRQC |
203 | bool | |
99c221df | 204 | select GENERIC_IRQ_CHIP |
fbc83b7f MD |
205 | select IRQ_DOMAIN |
206 | ||
07088484 LJ |
207 | config ST_IRQCHIP |
208 | bool | |
209 | select REGMAP | |
210 | select MFD_SYSCON | |
211 | help | |
212 | Enables SysCfg Controlled IRQs on STi based platforms. | |
213 | ||
4bba6689 MR |
214 | config TANGO_IRQ |
215 | bool | |
216 | select IRQ_DOMAIN | |
217 | select GENERIC_IRQ_CHIP | |
218 | ||
b06eb017 CR |
219 | config TB10X_IRQC |
220 | bool | |
221 | select IRQ_DOMAIN | |
222 | select GENERIC_IRQ_CHIP | |
223 | ||
d01f8633 DR |
224 | config TS4800_IRQ |
225 | tristate "TS-4800 IRQ controller" | |
226 | select IRQ_DOMAIN | |
0df337cf | 227 | depends on HAS_IOMEM |
d2b383dc | 228 | depends on SOC_IMX51 || COMPILE_TEST |
d01f8633 DR |
229 | help |
230 | Support for the TS-4800 FPGA IRQ controller | |
231 | ||
2389d501 LW |
232 | config VERSATILE_FPGA_IRQ |
233 | bool | |
234 | select IRQ_DOMAIN | |
235 | ||
236 | config VERSATILE_FPGA_IRQ_NR | |
237 | int | |
238 | default 4 | |
239 | depends on VERSATILE_FPGA_IRQ | |
26a8e96a MF |
240 | |
241 | config XTENSA_MX | |
242 | bool | |
243 | select IRQ_DOMAIN | |
50091212 | 244 | select GENERIC_IRQ_EFFECTIVE_AFF_MASK |
96ca848e | 245 | |
0547dc78 ZLK |
246 | config XILINX_INTC |
247 | bool | |
248 | select IRQ_DOMAIN | |
249 | ||
96ca848e S |
250 | config IRQ_CROSSBAR |
251 | bool | |
252 | help | |
f54619f2 | 253 | Support for a CROSSBAR ip that precedes the main interrupt controller. |
96ca848e S |
254 | The primary irqchip invokes the crossbar's callback which inturn allocates |
255 | a free irq and configures the IP. Thus the peripheral interrupts are | |
256 | routed to one of the free irqchip interrupt lines. | |
89323f8c GS |
257 | |
258 | config KEYSTONE_IRQ | |
259 | tristate "Keystone 2 IRQ controller IP" | |
260 | depends on ARCH_KEYSTONE | |
261 | help | |
262 | Support for Texas Instruments Keystone 2 IRQ controller IP which | |
263 | is part of the Keystone 2 IPC mechanism | |
8a19b8f1 AB |
264 | |
265 | config MIPS_GIC | |
266 | bool | |
bb11cff3 | 267 | select GENERIC_IRQ_IPI |
2af70a96 | 268 | select IRQ_DOMAIN_HIERARCHY |
8a19b8f1 | 269 | select MIPS_CM |
8a764482 | 270 | |
44e08e70 PB |
271 | config INGENIC_IRQ |
272 | bool | |
273 | depends on MACH_INGENIC | |
274 | default y | |
78c10e55 | 275 | |
8a764482 YS |
276 | config RENESAS_H8300H_INTC |
277 | bool | |
278 | select IRQ_DOMAIN | |
279 | ||
280 | config RENESAS_H8S_INTC | |
281 | bool | |
78c10e55 | 282 | select IRQ_DOMAIN |
e324c4dc SW |
283 | |
284 | config IMX_GPCV2 | |
285 | bool | |
286 | select IRQ_DOMAIN | |
287 | help | |
288 | Enables the wakeup IRQs for IMX platforms with GPCv2 block | |
7e4ac676 OR |
289 | |
290 | config IRQ_MXS | |
291 | def_bool y if MACH_ASM9260 || ARCH_MXS | |
292 | select IRQ_DOMAIN | |
293 | select STMP_DEVICE | |
c27f29bb | 294 | |
19d99164 AB |
295 | config MSCC_OCELOT_IRQ |
296 | bool | |
297 | select IRQ_DOMAIN | |
298 | select GENERIC_IRQ_CHIP | |
299 | ||
a68a63cb TP |
300 | config MVEBU_GICP |
301 | bool | |
302 | ||
e0de91a9 TP |
303 | config MVEBU_ICU |
304 | bool | |
305 | ||
c27f29bb TP |
306 | config MVEBU_ODMI |
307 | bool | |
fa23b9d1 | 308 | select GENERIC_MSI_IRQ_DOMAIN |
9e2c986c | 309 | |
a109893b TP |
310 | config MVEBU_PIC |
311 | bool | |
312 | ||
61ce8d8d MR |
313 | config MVEBU_SEI |
314 | bool | |
315 | ||
b8f3ebe6 ML |
316 | config LS_SCFG_MSI |
317 | def_bool y if SOC_LS1021A || ARCH_LAYERSCAPE | |
318 | depends on PCI && PCI_MSI | |
b8f3ebe6 | 319 | |
9e2c986c MZ |
320 | config PARTITION_PERCPU |
321 | bool | |
0efacbba | 322 | |
44df427c NC |
323 | config EZNPS_GIC |
324 | bool "NPS400 Global Interrupt Manager (GIM)" | |
ffd565e3 | 325 | depends on ARC || (COMPILE_TEST && !64BIT) |
44df427c NC |
326 | select IRQ_DOMAIN |
327 | help | |
328 | Support the EZchip NPS400 global interrupt controller | |
e0720416 AT |
329 | |
330 | config STM32_EXTI | |
331 | bool | |
332 | select IRQ_DOMAIN | |
0e7d7807 | 333 | select GENERIC_IRQ_CHIP |
f20cc9b0 AVF |
334 | |
335 | config QCOM_IRQ_COMBINER | |
336 | bool "QCOM IRQ combiner support" | |
337 | depends on ARCH_QCOM && ACPI | |
338 | select IRQ_DOMAIN | |
339 | select IRQ_DOMAIN_HIERARCHY | |
340 | help | |
341 | Say yes here to add support for the IRQ combiner devices embedded | |
342 | in Qualcomm Technologies chips. | |
5ed34d3a MY |
343 | |
344 | config IRQ_UNIPHIER_AIDET | |
345 | bool "UniPhier AIDET support" if COMPILE_TEST | |
346 | depends on ARCH_UNIPHIER || COMPILE_TEST | |
347 | default ARCH_UNIPHIER | |
348 | select IRQ_DOMAIN_HIERARCHY | |
349 | help | |
350 | Support for the UniPhier AIDET (ARM Interrupt Detector). | |
c94fb639 | 351 | |
215f4cc0 JB |
352 | config MESON_IRQ_GPIO |
353 | bool "Meson GPIO Interrupt Multiplexer" | |
d9ee91c1 | 354 | depends on ARCH_MESON |
215f4cc0 JB |
355 | select IRQ_DOMAIN |
356 | select IRQ_DOMAIN_HIERARCHY | |
357 | help | |
358 | Support Meson SoC Family GPIO Interrupt Multiplexer | |
359 | ||
4235ff50 MD |
360 | config GOLDFISH_PIC |
361 | bool "Goldfish programmable interrupt controller" | |
362 | depends on MIPS && (GOLDFISH || COMPILE_TEST) | |
363 | select IRQ_DOMAIN | |
364 | help | |
365 | Say yes here to enable Goldfish interrupt controller driver used | |
366 | for Goldfish based virtual platforms. | |
367 | ||
f55c73ae AS |
368 | config QCOM_PDC |
369 | bool "QCOM PDC" | |
370 | depends on ARCH_QCOM | |
371 | select IRQ_DOMAIN | |
372 | select IRQ_DOMAIN_HIERARCHY | |
373 | help | |
374 | Power Domain Controller driver to manage and configure wakeup | |
375 | IRQs for Qualcomm Technologies Inc (QTI) mobile chips. | |
376 | ||
d8a5f5f7 GR |
377 | config CSKY_MPINTC |
378 | bool "C-SKY Multi Processor Interrupt Controller" | |
379 | depends on CSKY | |
380 | help | |
381 | Say yes here to enable C-SKY SMP interrupt controller driver used | |
382 | for C-SKY SMP system. | |
383 | In fact it's not mmio map in hw and it use ld/st to visit the | |
384 | controller's register inside CPU. | |
385 | ||
edff1b48 GR |
386 | config CSKY_APB_INTC |
387 | bool "C-SKY APB Interrupt Controller" | |
388 | depends on CSKY | |
389 | help | |
390 | Say yes here to enable C-SKY APB interrupt controller driver used | |
391 | by C-SKY single core SOC system. It use mmio map apb-bus to visit | |
392 | the controller's register. | |
393 | ||
c94fb639 | 394 | endmenu |
8237f8bc CH |
395 | |
396 | config SIFIVE_PLIC | |
397 | bool "SiFive Platform-Level Interrupt Controller" | |
398 | depends on RISCV | |
399 | help | |
400 | This enables support for the PLIC chip found in SiFive (and | |
401 | potentially other) RISC-V systems. The PLIC controls devices | |
402 | interrupts and connects them to each core's local interrupt | |
403 | controller. Aside from timer and software interrupts, all other | |
404 | interrupt sources are subordinate to the PLIC. | |
405 | ||
406 | If you don't know what to do here, say Y. |