]>
Commit | Line | Data |
---|---|---|
a900e5d9 RH |
1 | /* |
2 | * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd. | |
3 | * http://www.samsung.com | |
4 | * | |
5 | * Combiner irqchip for EXYNOS | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License version 2 as | |
9 | * published by the Free Software Foundation. | |
10 | */ | |
11 | #include <linux/err.h> | |
12 | #include <linux/export.h> | |
13 | #include <linux/init.h> | |
14 | #include <linux/io.h> | |
d34f03d4 | 15 | #include <linux/slab.h> |
a900e5d9 RH |
16 | #include <linux/irqdomain.h> |
17 | #include <linux/of_address.h> | |
18 | #include <linux/of_irq.h> | |
19 | #include <asm/mach/irq.h> | |
20 | ||
92c8e496 | 21 | #ifdef CONFIG_EXYNOS_ATAGS |
a900e5d9 | 22 | #include <plat/cpu.h> |
92c8e496 | 23 | #endif |
a900e5d9 RH |
24 | |
25 | #include "irqchip.h" | |
26 | ||
27 | #define COMBINER_ENABLE_SET 0x0 | |
28 | #define COMBINER_ENABLE_CLEAR 0x4 | |
29 | #define COMBINER_INT_STATUS 0xC | |
30 | ||
6761dcfe AB |
31 | #define IRQ_IN_COMBINER 8 |
32 | ||
a900e5d9 RH |
33 | static DEFINE_SPINLOCK(irq_controller_lock); |
34 | ||
35 | struct combiner_chip_data { | |
36 | unsigned int irq_offset; | |
37 | unsigned int irq_mask; | |
38 | void __iomem *base; | |
df7ef462 | 39 | unsigned int parent_irq; |
a900e5d9 RH |
40 | }; |
41 | ||
42 | static struct irq_domain *combiner_irq_domain; | |
a900e5d9 RH |
43 | |
44 | static inline void __iomem *combiner_base(struct irq_data *data) | |
45 | { | |
46 | struct combiner_chip_data *combiner_data = | |
47 | irq_data_get_irq_chip_data(data); | |
48 | ||
49 | return combiner_data->base; | |
50 | } | |
51 | ||
52 | static void combiner_mask_irq(struct irq_data *data) | |
53 | { | |
54 | u32 mask = 1 << (data->hwirq % 32); | |
55 | ||
56 | __raw_writel(mask, combiner_base(data) + COMBINER_ENABLE_CLEAR); | |
57 | } | |
58 | ||
59 | static void combiner_unmask_irq(struct irq_data *data) | |
60 | { | |
61 | u32 mask = 1 << (data->hwirq % 32); | |
62 | ||
63 | __raw_writel(mask, combiner_base(data) + COMBINER_ENABLE_SET); | |
64 | } | |
65 | ||
66 | static void combiner_handle_cascade_irq(unsigned int irq, struct irq_desc *desc) | |
67 | { | |
68 | struct combiner_chip_data *chip_data = irq_get_handler_data(irq); | |
69 | struct irq_chip *chip = irq_get_chip(irq); | |
70 | unsigned int cascade_irq, combiner_irq; | |
71 | unsigned long status; | |
72 | ||
73 | chained_irq_enter(chip, desc); | |
74 | ||
75 | spin_lock(&irq_controller_lock); | |
76 | status = __raw_readl(chip_data->base + COMBINER_INT_STATUS); | |
77 | spin_unlock(&irq_controller_lock); | |
78 | status &= chip_data->irq_mask; | |
79 | ||
80 | if (status == 0) | |
81 | goto out; | |
82 | ||
83 | combiner_irq = __ffs(status); | |
84 | ||
85 | cascade_irq = combiner_irq + (chip_data->irq_offset & ~31); | |
86 | if (unlikely(cascade_irq >= NR_IRQS)) | |
87 | do_bad_IRQ(cascade_irq, desc); | |
88 | else | |
89 | generic_handle_irq(cascade_irq); | |
90 | ||
91 | out: | |
92 | chained_irq_exit(chip, desc); | |
93 | } | |
94 | ||
df7ef462 CP |
95 | #ifdef CONFIG_SMP |
96 | static int combiner_set_affinity(struct irq_data *d, | |
97 | const struct cpumask *mask_val, bool force) | |
98 | { | |
99 | struct combiner_chip_data *chip_data = irq_data_get_irq_chip_data(d); | |
100 | struct irq_chip *chip = irq_get_chip(chip_data->parent_irq); | |
101 | struct irq_data *data = irq_get_irq_data(chip_data->parent_irq); | |
102 | ||
103 | if (chip && chip->irq_set_affinity) | |
104 | return chip->irq_set_affinity(data, mask_val, force); | |
105 | else | |
106 | return -EINVAL; | |
107 | } | |
108 | #endif | |
109 | ||
a900e5d9 | 110 | static struct irq_chip combiner_chip = { |
df7ef462 CP |
111 | .name = "COMBINER", |
112 | .irq_mask = combiner_mask_irq, | |
113 | .irq_unmask = combiner_unmask_irq, | |
114 | #ifdef CONFIG_SMP | |
115 | .irq_set_affinity = combiner_set_affinity, | |
116 | #endif | |
a900e5d9 RH |
117 | }; |
118 | ||
d34f03d4 | 119 | static void __init combiner_cascade_irq(struct combiner_chip_data *combiner_data, |
4e164dc5 CP |
120 | unsigned int irq) |
121 | { | |
d34f03d4 | 122 | if (irq_set_handler_data(irq, combiner_data) != 0) |
a900e5d9 RH |
123 | BUG(); |
124 | irq_set_chained_handler(irq, combiner_handle_cascade_irq); | |
125 | } | |
126 | ||
d34f03d4 AB |
127 | static void __init combiner_init_one(struct combiner_chip_data *combiner_data, |
128 | unsigned int combiner_nr, | |
df7ef462 | 129 | void __iomem *base, unsigned int irq) |
a900e5d9 | 130 | { |
d34f03d4 AB |
131 | combiner_data->base = base; |
132 | combiner_data->irq_offset = irq_find_mapping( | |
6761dcfe | 133 | combiner_irq_domain, combiner_nr * IRQ_IN_COMBINER); |
d34f03d4 AB |
134 | combiner_data->irq_mask = 0xff << ((combiner_nr % 4) << 3); |
135 | combiner_data->parent_irq = irq; | |
a900e5d9 RH |
136 | |
137 | /* Disable all interrupts */ | |
d34f03d4 | 138 | __raw_writel(combiner_data->irq_mask, base + COMBINER_ENABLE_CLEAR); |
a900e5d9 RH |
139 | } |
140 | ||
141 | #ifdef CONFIG_OF | |
142 | static int combiner_irq_domain_xlate(struct irq_domain *d, | |
143 | struct device_node *controller, | |
144 | const u32 *intspec, unsigned int intsize, | |
145 | unsigned long *out_hwirq, | |
146 | unsigned int *out_type) | |
147 | { | |
148 | if (d->of_node != controller) | |
149 | return -EINVAL; | |
150 | ||
151 | if (intsize < 2) | |
152 | return -EINVAL; | |
153 | ||
6761dcfe | 154 | *out_hwirq = intspec[0] * IRQ_IN_COMBINER + intspec[1]; |
a900e5d9 RH |
155 | *out_type = 0; |
156 | ||
157 | return 0; | |
158 | } | |
159 | #else | |
160 | static int combiner_irq_domain_xlate(struct irq_domain *d, | |
161 | struct device_node *controller, | |
162 | const u32 *intspec, unsigned int intsize, | |
163 | unsigned long *out_hwirq, | |
164 | unsigned int *out_type) | |
165 | { | |
166 | return -EINVAL; | |
167 | } | |
168 | #endif | |
169 | ||
170 | static int combiner_irq_domain_map(struct irq_domain *d, unsigned int irq, | |
171 | irq_hw_number_t hw) | |
172 | { | |
d34f03d4 AB |
173 | struct combiner_chip_data *combiner_data = d->host_data; |
174 | ||
a900e5d9 RH |
175 | irq_set_chip_and_handler(irq, &combiner_chip, handle_level_irq); |
176 | irq_set_chip_data(irq, &combiner_data[hw >> 3]); | |
177 | set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); | |
178 | ||
179 | return 0; | |
180 | } | |
181 | ||
182 | static struct irq_domain_ops combiner_irq_domain_ops = { | |
183 | .xlate = combiner_irq_domain_xlate, | |
184 | .map = combiner_irq_domain_map, | |
185 | }; | |
186 | ||
92c8e496 | 187 | static unsigned int combiner_lookup_irq(int group) |
4e164dc5 | 188 | { |
92c8e496 AB |
189 | #ifdef CONFIG_EXYNOS_ATAGS |
190 | if (group < EXYNOS4210_MAX_COMBINER_NR || soc_is_exynos5250()) | |
191 | return IRQ_SPI(group); | |
192 | ||
4e164dc5 CP |
193 | switch (group) { |
194 | case 16: | |
195 | return IRQ_SPI(107); | |
196 | case 17: | |
197 | return IRQ_SPI(108); | |
198 | case 18: | |
199 | return IRQ_SPI(48); | |
200 | case 19: | |
201 | return IRQ_SPI(42); | |
4e164dc5 | 202 | } |
92c8e496 AB |
203 | #endif |
204 | return 0; | |
4e164dc5 CP |
205 | } |
206 | ||
a900e5d9 | 207 | void __init combiner_init(void __iomem *combiner_base, |
6761dcfe | 208 | struct device_node *np, |
863a08dc AB |
209 | unsigned int max_nr, |
210 | int irq_base) | |
a900e5d9 | 211 | { |
863a08dc | 212 | int i, irq; |
6761dcfe | 213 | unsigned int nr_irq; |
d34f03d4 | 214 | struct combiner_chip_data *combiner_data; |
a900e5d9 | 215 | |
6761dcfe | 216 | nr_irq = max_nr * IRQ_IN_COMBINER; |
a900e5d9 | 217 | |
d34f03d4 AB |
218 | combiner_data = kcalloc(max_nr, sizeof (*combiner_data), GFP_KERNEL); |
219 | if (!combiner_data) { | |
220 | pr_warning("%s: could not allocate combiner data\n", __func__); | |
221 | return; | |
222 | } | |
223 | ||
863a08dc | 224 | combiner_irq_domain = irq_domain_add_simple(np, nr_irq, irq_base, |
d34f03d4 | 225 | &combiner_irq_domain_ops, combiner_data); |
a900e5d9 RH |
226 | if (WARN_ON(!combiner_irq_domain)) { |
227 | pr_warning("%s: irq domain init failed\n", __func__); | |
228 | return; | |
229 | } | |
230 | ||
231 | for (i = 0; i < max_nr; i++) { | |
a900e5d9 RH |
232 | #ifdef CONFIG_OF |
233 | if (np) | |
234 | irq = irq_of_parse_and_map(np, i); | |
92c8e496 | 235 | else |
a900e5d9 | 236 | #endif |
92c8e496 AB |
237 | irq = combiner_lookup_irq(i); |
238 | ||
d34f03d4 AB |
239 | combiner_init_one(&combiner_data[i], i, |
240 | combiner_base + (i >> 2) * 0x10, irq); | |
241 | combiner_cascade_irq(&combiner_data[i], irq); | |
a900e5d9 RH |
242 | } |
243 | } | |
244 | ||
245 | #ifdef CONFIG_OF | |
246 | static int __init combiner_of_init(struct device_node *np, | |
247 | struct device_node *parent) | |
248 | { | |
249 | void __iomem *combiner_base; | |
6761dcfe | 250 | unsigned int max_nr = 20; |
863a08dc | 251 | int irq_base = -1; |
a900e5d9 RH |
252 | |
253 | combiner_base = of_iomap(np, 0); | |
254 | if (!combiner_base) { | |
255 | pr_err("%s: failed to map combiner registers\n", __func__); | |
256 | return -ENXIO; | |
257 | } | |
258 | ||
6761dcfe AB |
259 | if (of_property_read_u32(np, "samsung,combiner-nr", &max_nr)) { |
260 | pr_info("%s: number of combiners not specified, " | |
261 | "setting default as %d.\n", | |
262 | __func__, max_nr); | |
263 | } | |
264 | ||
863a08dc AB |
265 | /* |
266 | * FIXME: This is a hardwired COMBINER_IRQ(0,0). Once all devices | |
267 | * get their IRQ from DT, remove this in order to get dynamic | |
268 | * allocation. | |
269 | */ | |
270 | irq_base = 160; | |
271 | ||
272 | combiner_init(combiner_base, np, max_nr, irq_base); | |
a900e5d9 RH |
273 | |
274 | return 0; | |
275 | } | |
276 | IRQCHIP_DECLARE(exynos4210_combiner, "samsung,exynos4210-combiner", | |
277 | combiner_of_init); | |
278 | #endif |