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a900e5d9 RH |
1 | /* |
2 | * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd. | |
3 | * http://www.samsung.com | |
4 | * | |
5 | * Combiner irqchip for EXYNOS | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License version 2 as | |
9 | * published by the Free Software Foundation. | |
10 | */ | |
11 | #include <linux/err.h> | |
12 | #include <linux/export.h> | |
13 | #include <linux/init.h> | |
14 | #include <linux/io.h> | |
15 | #include <linux/irqdomain.h> | |
de88cbb7 | 16 | #include <linux/irqchip/chained_irq.h> |
a900e5d9 RH |
17 | #include <linux/of_address.h> |
18 | #include <linux/of_irq.h> | |
19 | #include <asm/mach/irq.h> | |
20 | ||
21 | #include <plat/cpu.h> | |
22 | ||
23 | #include "irqchip.h" | |
24 | ||
25 | #define COMBINER_ENABLE_SET 0x0 | |
26 | #define COMBINER_ENABLE_CLEAR 0x4 | |
27 | #define COMBINER_INT_STATUS 0xC | |
28 | ||
29 | static DEFINE_SPINLOCK(irq_controller_lock); | |
30 | ||
31 | struct combiner_chip_data { | |
32 | unsigned int irq_offset; | |
33 | unsigned int irq_mask; | |
34 | void __iomem *base; | |
35 | }; | |
36 | ||
37 | static struct irq_domain *combiner_irq_domain; | |
38 | static struct combiner_chip_data combiner_data[MAX_COMBINER_NR]; | |
39 | ||
40 | static inline void __iomem *combiner_base(struct irq_data *data) | |
41 | { | |
42 | struct combiner_chip_data *combiner_data = | |
43 | irq_data_get_irq_chip_data(data); | |
44 | ||
45 | return combiner_data->base; | |
46 | } | |
47 | ||
48 | static void combiner_mask_irq(struct irq_data *data) | |
49 | { | |
50 | u32 mask = 1 << (data->hwirq % 32); | |
51 | ||
52 | __raw_writel(mask, combiner_base(data) + COMBINER_ENABLE_CLEAR); | |
53 | } | |
54 | ||
55 | static void combiner_unmask_irq(struct irq_data *data) | |
56 | { | |
57 | u32 mask = 1 << (data->hwirq % 32); | |
58 | ||
59 | __raw_writel(mask, combiner_base(data) + COMBINER_ENABLE_SET); | |
60 | } | |
61 | ||
62 | static void combiner_handle_cascade_irq(unsigned int irq, struct irq_desc *desc) | |
63 | { | |
64 | struct combiner_chip_data *chip_data = irq_get_handler_data(irq); | |
65 | struct irq_chip *chip = irq_get_chip(irq); | |
66 | unsigned int cascade_irq, combiner_irq; | |
67 | unsigned long status; | |
68 | ||
69 | chained_irq_enter(chip, desc); | |
70 | ||
71 | spin_lock(&irq_controller_lock); | |
72 | status = __raw_readl(chip_data->base + COMBINER_INT_STATUS); | |
73 | spin_unlock(&irq_controller_lock); | |
74 | status &= chip_data->irq_mask; | |
75 | ||
76 | if (status == 0) | |
77 | goto out; | |
78 | ||
79 | combiner_irq = __ffs(status); | |
80 | ||
81 | cascade_irq = combiner_irq + (chip_data->irq_offset & ~31); | |
82 | if (unlikely(cascade_irq >= NR_IRQS)) | |
83 | do_bad_IRQ(cascade_irq, desc); | |
84 | else | |
85 | generic_handle_irq(cascade_irq); | |
86 | ||
87 | out: | |
88 | chained_irq_exit(chip, desc); | |
89 | } | |
90 | ||
91 | static struct irq_chip combiner_chip = { | |
92 | .name = "COMBINER", | |
93 | .irq_mask = combiner_mask_irq, | |
94 | .irq_unmask = combiner_unmask_irq, | |
95 | }; | |
96 | ||
97 | static void __init combiner_cascade_irq(unsigned int combiner_nr, unsigned int irq) | |
98 | { | |
99 | unsigned int max_nr; | |
100 | ||
101 | if (soc_is_exynos5250()) | |
102 | max_nr = EXYNOS5_MAX_COMBINER_NR; | |
103 | else | |
104 | max_nr = EXYNOS4_MAX_COMBINER_NR; | |
105 | ||
106 | if (combiner_nr >= max_nr) | |
107 | BUG(); | |
108 | if (irq_set_handler_data(irq, &combiner_data[combiner_nr]) != 0) | |
109 | BUG(); | |
110 | irq_set_chained_handler(irq, combiner_handle_cascade_irq); | |
111 | } | |
112 | ||
113 | static void __init combiner_init_one(unsigned int combiner_nr, | |
114 | void __iomem *base) | |
115 | { | |
116 | combiner_data[combiner_nr].base = base; | |
117 | combiner_data[combiner_nr].irq_offset = irq_find_mapping( | |
118 | combiner_irq_domain, combiner_nr * MAX_IRQ_IN_COMBINER); | |
119 | combiner_data[combiner_nr].irq_mask = 0xff << ((combiner_nr % 4) << 3); | |
120 | ||
121 | /* Disable all interrupts */ | |
122 | __raw_writel(combiner_data[combiner_nr].irq_mask, | |
123 | base + COMBINER_ENABLE_CLEAR); | |
124 | } | |
125 | ||
126 | #ifdef CONFIG_OF | |
127 | static int combiner_irq_domain_xlate(struct irq_domain *d, | |
128 | struct device_node *controller, | |
129 | const u32 *intspec, unsigned int intsize, | |
130 | unsigned long *out_hwirq, | |
131 | unsigned int *out_type) | |
132 | { | |
133 | if (d->of_node != controller) | |
134 | return -EINVAL; | |
135 | ||
136 | if (intsize < 2) | |
137 | return -EINVAL; | |
138 | ||
139 | *out_hwirq = intspec[0] * MAX_IRQ_IN_COMBINER + intspec[1]; | |
140 | *out_type = 0; | |
141 | ||
142 | return 0; | |
143 | } | |
144 | #else | |
145 | static int combiner_irq_domain_xlate(struct irq_domain *d, | |
146 | struct device_node *controller, | |
147 | const u32 *intspec, unsigned int intsize, | |
148 | unsigned long *out_hwirq, | |
149 | unsigned int *out_type) | |
150 | { | |
151 | return -EINVAL; | |
152 | } | |
153 | #endif | |
154 | ||
155 | static int combiner_irq_domain_map(struct irq_domain *d, unsigned int irq, | |
156 | irq_hw_number_t hw) | |
157 | { | |
158 | irq_set_chip_and_handler(irq, &combiner_chip, handle_level_irq); | |
159 | irq_set_chip_data(irq, &combiner_data[hw >> 3]); | |
160 | set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); | |
161 | ||
162 | return 0; | |
163 | } | |
164 | ||
165 | static struct irq_domain_ops combiner_irq_domain_ops = { | |
166 | .xlate = combiner_irq_domain_xlate, | |
167 | .map = combiner_irq_domain_map, | |
168 | }; | |
169 | ||
170 | void __init combiner_init(void __iomem *combiner_base, | |
171 | struct device_node *np) | |
172 | { | |
173 | int i, irq, irq_base; | |
174 | unsigned int max_nr, nr_irq; | |
175 | ||
176 | if (np) { | |
177 | if (of_property_read_u32(np, "samsung,combiner-nr", &max_nr)) { | |
178 | pr_warning("%s: number of combiners not specified, " | |
179 | "setting default as %d.\n", | |
180 | __func__, EXYNOS4_MAX_COMBINER_NR); | |
181 | max_nr = EXYNOS4_MAX_COMBINER_NR; | |
182 | } | |
183 | } else { | |
184 | max_nr = soc_is_exynos5250() ? EXYNOS5_MAX_COMBINER_NR : | |
185 | EXYNOS4_MAX_COMBINER_NR; | |
186 | } | |
187 | nr_irq = max_nr * MAX_IRQ_IN_COMBINER; | |
188 | ||
189 | irq_base = irq_alloc_descs(COMBINER_IRQ(0, 0), 1, nr_irq, 0); | |
190 | if (IS_ERR_VALUE(irq_base)) { | |
191 | irq_base = COMBINER_IRQ(0, 0); | |
192 | pr_warning("%s: irq desc alloc failed. Continuing with %d as linux irq base\n", __func__, irq_base); | |
193 | } | |
194 | ||
195 | combiner_irq_domain = irq_domain_add_legacy(np, nr_irq, irq_base, 0, | |
196 | &combiner_irq_domain_ops, &combiner_data); | |
197 | if (WARN_ON(!combiner_irq_domain)) { | |
198 | pr_warning("%s: irq domain init failed\n", __func__); | |
199 | return; | |
200 | } | |
201 | ||
202 | for (i = 0; i < max_nr; i++) { | |
203 | combiner_init_one(i, combiner_base + (i >> 2) * 0x10); | |
204 | irq = IRQ_SPI(i); | |
205 | #ifdef CONFIG_OF | |
206 | if (np) | |
207 | irq = irq_of_parse_and_map(np, i); | |
208 | #endif | |
209 | combiner_cascade_irq(i, irq); | |
210 | } | |
211 | } | |
212 | ||
213 | #ifdef CONFIG_OF | |
214 | static int __init combiner_of_init(struct device_node *np, | |
215 | struct device_node *parent) | |
216 | { | |
217 | void __iomem *combiner_base; | |
218 | ||
219 | combiner_base = of_iomap(np, 0); | |
220 | if (!combiner_base) { | |
221 | pr_err("%s: failed to map combiner registers\n", __func__); | |
222 | return -ENXIO; | |
223 | } | |
224 | ||
225 | combiner_init(combiner_base, np); | |
226 | ||
227 | return 0; | |
228 | } | |
229 | IRQCHIP_DECLARE(exynos4210_combiner, "samsung,exynos4210-combiner", | |
230 | combiner_of_init); | |
231 | #endif |