[mirror_ubuntu-artful-kernel.git] / drivers / irqchip / irq-armada-370-xp.c

/*
 * Marvell Armada 370 and Armada XP SoC IRQ handling
 *
 * Copyright (C) 2012 Marvell
 *
 * Lior Amsalem <alior@marvell.com>
 * Gregory CLEMENT <gregory.clement@free-electrons.com>
 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
 * Ben Dooks <ben.dooks@codethink.co.uk>
 *
 * This file is licensed under the terms of the GNU General Public
 * License version 2.  This program is licensed "as is" without any
 * warranty of any kind, whether express or implied.
 */

#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/init.h>
#include <linux/irq.h>
#include <linux/interrupt.h>
#include <linux/irqchip/chained_irq.h>
#include <linux/cpu.h>
#include <linux/io.h>
#include <linux/of_address.h>
#include <linux/of_irq.h>
#include <linux/of_pci.h>
#include <linux/irqdomain.h>
#include <linux/slab.h>
#include <linux/msi.h>
#include <asm/mach/arch.h>
#include <asm/exception.h>
#include <asm/smp_plat.h>
#include <asm/mach/irq.h>

#include "irqchip.h"

/* Interrupt Controller Registers Map */
#define ARMADA_370_XP_INT_SET_MASK_OFFS		(0x48)
#define ARMADA_370_XP_INT_CLEAR_MASK_OFFS	(0x4C)

#define ARMADA_370_XP_INT_CONTROL		(0x00)
#define ARMADA_370_XP_INT_SET_ENABLE_OFFS	(0x30)
#define ARMADA_370_XP_INT_CLEAR_ENABLE_OFFS	(0x34)
#define ARMADA_370_XP_INT_SOURCE_CTL(irq)	(0x100 + irq*4)
#define ARMADA_370_XP_INT_SOURCE_CPU_MASK	0xF

#define ARMADA_370_XP_CPU_INTACK_OFFS		(0x44)
#define ARMADA_375_PPI_CAUSE			(0x10)

#define ARMADA_370_XP_SW_TRIG_INT_OFFS           (0x4)
#define ARMADA_370_XP_IN_DRBEL_MSK_OFFS          (0xc)
#define ARMADA_370_XP_IN_DRBEL_CAUSE_OFFS        (0x8)

#define ARMADA_370_XP_MAX_PER_CPU_IRQS		(28)

#define ARMADA_370_XP_TIMER0_PER_CPU_IRQ	(5)

#define IPI_DOORBELL_START                      (0)
#define IPI_DOORBELL_END                        (8)
#define IPI_DOORBELL_MASK                       0xFF
#define PCI_MSI_DOORBELL_START                  (16)
#define PCI_MSI_DOORBELL_NR                     (16)
#define PCI_MSI_DOORBELL_END                    (32)
#define PCI_MSI_DOORBELL_MASK                   0xFFFF0000

static void __iomem *per_cpu_int_base;
static void __iomem *main_int_base;
static struct irq_domain *armada_370_xp_mpic_domain;
#ifdef CONFIG_PCI_MSI
static struct irq_domain *armada_370_xp_msi_domain;
static DECLARE_BITMAP(msi_used, PCI_MSI_DOORBELL_NR);
static DEFINE_MUTEX(msi_used_lock);
static phys_addr_t msi_doorbell_addr;
#endif

/*
 * In SMP mode:
 * For shared global interrupts, mask/unmask global enable bit
 * For CPU interrupts, mask/unmask the calling CPU's bit
 */
static void armada_370_xp_irq_mask(struct irq_data *d)
{
	irq_hw_number_t hwirq = irqd_to_hwirq(d);

	if (hwirq != ARMADA_370_XP_TIMER0_PER_CPU_IRQ)
		writel(hwirq, main_int_base +
				ARMADA_370_XP_INT_CLEAR_ENABLE_OFFS);
	else
		writel(hwirq, per_cpu_int_base +
				ARMADA_370_XP_INT_SET_MASK_OFFS);
}

static void armada_370_xp_irq_unmask(struct irq_data *d)
{
	irq_hw_number_t hwirq = irqd_to_hwirq(d);

	if (hwirq != ARMADA_370_XP_TIMER0_PER_CPU_IRQ)
		writel(hwirq, main_int_base +
				ARMADA_370_XP_INT_SET_ENABLE_OFFS);
	else
		writel(hwirq, per_cpu_int_base +
				ARMADA_370_XP_INT_CLEAR_MASK_OFFS);
}

#ifdef CONFIG_PCI_MSI

static int armada_370_xp_alloc_msi(void)
{
	int hwirq;

	mutex_lock(&msi_used_lock);
	hwirq = find_first_zero_bit(&msi_used, PCI_MSI_DOORBELL_NR);
	if (hwirq >= PCI_MSI_DOORBELL_NR)
		hwirq = -ENOSPC;
	else
		set_bit(hwirq, msi_used);
	mutex_unlock(&msi_used_lock);

	return hwirq;
}

static void armada_370_xp_free_msi(int hwirq)
{
	mutex_lock(&msi_used_lock);
	if (!test_bit(hwirq, msi_used))
		pr_err("trying to free unused MSI#%d\n", hwirq);
	else
		clear_bit(hwirq, msi_used);
	mutex_unlock(&msi_used_lock);
}

static int armada_370_xp_setup_msi_irq(struct msi_chip *chip,
				       struct pci_dev *pdev,
				       struct msi_desc *desc)
{
	struct msi_msg msg;
	int virq, hwirq;

	hwirq = armada_370_xp_alloc_msi();
	if (hwirq < 0)
		return hwirq;

	virq = irq_create_mapping(armada_370_xp_msi_domain, hwirq);
	if (!virq) {
		armada_370_xp_free_msi(hwirq);
		return -EINVAL;
	}

	irq_set_msi_desc(virq, desc);

	msg.address_lo = msi_doorbell_addr;
	msg.address_hi = 0;
	msg.data = 0xf00 | (hwirq + 16);

	write_msi_msg(virq, &msg);
	return 0;
}

static void armada_370_xp_teardown_msi_irq(struct msi_chip *chip,
					   unsigned int irq)
{
	struct irq_data *d = irq_get_irq_data(irq);
	unsigned long hwirq = d->hwirq;

	irq_dispose_mapping(irq);
	armada_370_xp_free_msi(hwirq);
}

static int armada_370_xp_check_msi_device(struct msi_chip *chip, struct pci_dev *dev,
					  int nvec, int type)
{
	/* We support MSI, but not MSI-X */
	if (type == PCI_CAP_ID_MSI)
		return 0;
	return -EINVAL;
}

static struct irq_chip armada_370_xp_msi_irq_chip = {
	.name = "armada_370_xp_msi_irq",
	.irq_enable = unmask_msi_irq,
	.irq_disable = mask_msi_irq,
	.irq_mask = mask_msi_irq,
	.irq_unmask = unmask_msi_irq,
};

static int armada_370_xp_msi_map(struct irq_domain *domain, unsigned int virq,
				 irq_hw_number_t hw)
{
	irq_set_chip_and_handler(virq, &armada_370_xp_msi_irq_chip,
				 handle_simple_irq);
	set_irq_flags(virq, IRQF_VALID);

	return 0;
}

static const struct irq_domain_ops armada_370_xp_msi_irq_ops = {
	.map = armada_370_xp_msi_map,
};

static int armada_370_xp_msi_init(struct device_node *node,
				  phys_addr_t main_int_phys_base)
{
	struct msi_chip *msi_chip;
	u32 reg;
	int ret;

	msi_doorbell_addr = main_int_phys_base +
		ARMADA_370_XP_SW_TRIG_INT_OFFS;

	msi_chip = kzalloc(sizeof(*msi_chip), GFP_KERNEL);
	if (!msi_chip)
		return -ENOMEM;

	msi_chip->setup_irq = armada_370_xp_setup_msi_irq;
	msi_chip->teardown_irq = armada_370_xp_teardown_msi_irq;
	msi_chip->check_device = armada_370_xp_check_msi_device;
	msi_chip->of_node = node;

	armada_370_xp_msi_domain =
		irq_domain_add_linear(NULL, PCI_MSI_DOORBELL_NR,
				      &armada_370_xp_msi_irq_ops,
				      NULL);
	if (!armada_370_xp_msi_domain) {
		kfree(msi_chip);
		return -ENOMEM;
	}

	ret = of_pci_msi_chip_add(msi_chip);
	if (ret < 0) {
		irq_domain_remove(armada_370_xp_msi_domain);
		kfree(msi_chip);
		return ret;
	}

	reg = readl(per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_MSK_OFFS)
		| PCI_MSI_DOORBELL_MASK;

	writel(reg, per_cpu_int_base +
	       ARMADA_370_XP_IN_DRBEL_MSK_OFFS);

	/* Unmask IPI interrupt */
	writel(1, per_cpu_int_base + ARMADA_370_XP_INT_CLEAR_MASK_OFFS);

	return 0;
}
#else
static inline int armada_370_xp_msi_init(struct device_node *node,
					 phys_addr_t main_int_phys_base)
{
	return 0;
}
#endif

#ifdef CONFIG_SMP
static DEFINE_RAW_SPINLOCK(irq_controller_lock);

static int armada_xp_set_affinity(struct irq_data *d,
				  const struct cpumask *mask_val, bool force)
{
	irq_hw_number_t hwirq = irqd_to_hwirq(d);
	unsigned long reg, mask;
	int cpu;

	/* Select a single core from the affinity mask which is online */
	cpu = cpumask_any_and(mask_val, cpu_online_mask);
	mask = 1UL << cpu_logical_map(cpu);

	raw_spin_lock(&irq_controller_lock);
	reg = readl(main_int_base + ARMADA_370_XP_INT_SOURCE_CTL(hwirq));
	reg = (reg & (~ARMADA_370_XP_INT_SOURCE_CPU_MASK)) | mask;
	writel(reg, main_int_base + ARMADA_370_XP_INT_SOURCE_CTL(hwirq));
	raw_spin_unlock(&irq_controller_lock);

	return 0;
}
#endif

static struct irq_chip armada_370_xp_irq_chip = {
	.name		= "armada_370_xp_irq",
	.irq_mask       = armada_370_xp_irq_mask,
	.irq_mask_ack   = armada_370_xp_irq_mask,
	.irq_unmask     = armada_370_xp_irq_unmask,
#ifdef CONFIG_SMP
	.irq_set_affinity = armada_xp_set_affinity,
#endif
};

static int armada_370_xp_mpic_irq_map(struct irq_domain *h,
				      unsigned int virq, irq_hw_number_t hw)
{
	armada_370_xp_irq_mask(irq_get_irq_data(virq));
	if (hw != ARMADA_370_XP_TIMER0_PER_CPU_IRQ)
		writel(hw, per_cpu_int_base +
			ARMADA_370_XP_INT_CLEAR_MASK_OFFS);
	else
		writel(hw, main_int_base + ARMADA_370_XP_INT_SET_ENABLE_OFFS);
	irq_set_status_flags(virq, IRQ_LEVEL);

	if (hw == ARMADA_370_XP_TIMER0_PER_CPU_IRQ) {
		irq_set_percpu_devid(virq);
		irq_set_chip_and_handler(virq, &armada_370_xp_irq_chip,
					handle_percpu_devid_irq);

	} else {
		irq_set_chip_and_handler(virq, &armada_370_xp_irq_chip,
					handle_level_irq);
	}
	set_irq_flags(virq, IRQF_VALID | IRQF_PROBE);

	return 0;
}

#ifdef CONFIG_SMP
static void armada_mpic_send_doorbell(const struct cpumask *mask,
				      unsigned int irq)
{
	int cpu;
	unsigned long map = 0;

	/* Convert our logical CPU mask into a physical one. */
	for_each_cpu(cpu, mask)
		map |= 1 << cpu_logical_map(cpu);

	/*
	 * Ensure that stores to Normal memory are visible to the
	 * other CPUs before issuing the IPI.
	 */
	dsb();

	/* submit softirq */
	writel((map << 8) | irq, main_int_base +
		ARMADA_370_XP_SW_TRIG_INT_OFFS);
}

static void armada_xp_mpic_smp_cpu_init(void)
{
	u32 control;
	int nr_irqs, i;

	control = readl(main_int_base + ARMADA_370_XP_INT_CONTROL);
	nr_irqs = (control >> 2) & 0x3ff;

	for (i = 0; i < nr_irqs; i++)
		writel(i, per_cpu_int_base + ARMADA_370_XP_INT_SET_MASK_OFFS);

	/* Clear pending IPIs */
	writel(0, per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_CAUSE_OFFS);

	/* Enable first 8 IPIs */
	writel(IPI_DOORBELL_MASK, per_cpu_int_base +
		ARMADA_370_XP_IN_DRBEL_MSK_OFFS);

	/* Unmask IPI interrupt */
	writel(0, per_cpu_int_base + ARMADA_370_XP_INT_CLEAR_MASK_OFFS);
}

static int armada_xp_mpic_secondary_init(struct notifier_block *nfb,
					 unsigned long action, void *hcpu)
{
	if (action == CPU_STARTING || action == CPU_STARTING_FROZEN)
		armada_xp_mpic_smp_cpu_init();
	return NOTIFY_OK;
}

static struct notifier_block armada_370_xp_mpic_cpu_notifier = {
	.notifier_call = armada_xp_mpic_secondary_init,
	.priority = 100,
};

#endif /* CONFIG_SMP */

static struct irq_domain_ops armada_370_xp_mpic_irq_ops = {
	.map = armada_370_xp_mpic_irq_map,
	.xlate = irq_domain_xlate_onecell,
};

#ifdef CONFIG_PCI_MSI
static void armada_370_xp_handle_msi_irq(struct pt_regs *regs, bool is_chained)
{
	u32 msimask, msinr;

	msimask = readl_relaxed(per_cpu_int_base +
				ARMADA_370_XP_IN_DRBEL_CAUSE_OFFS)
		& PCI_MSI_DOORBELL_MASK;

	writel(~msimask, per_cpu_int_base +
	       ARMADA_370_XP_IN_DRBEL_CAUSE_OFFS);

	for (msinr = PCI_MSI_DOORBELL_START;
	     msinr < PCI_MSI_DOORBELL_END; msinr++) {
		int irq;

		if (!(msimask & BIT(msinr)))
			continue;

		irq = irq_find_mapping(armada_370_xp_msi_domain,
				       msinr - 16);

		if (is_chained)
			generic_handle_irq(irq);
		else
			handle_IRQ(irq, regs);
	}
}
#else
static void armada_370_xp_handle_msi_irq(struct pt_regs *r, bool b) {}
#endif

static void armada_370_xp_mpic_handle_cascade_irq(unsigned int irq,
						  struct irq_desc *desc)
{
	struct irq_chip *chip = irq_get_chip(irq);
	unsigned long irqmap, irqn;
	unsigned int cascade_irq;

	chained_irq_enter(chip, desc);

	irqmap = readl_relaxed(per_cpu_int_base + ARMADA_375_PPI_CAUSE);

	if (irqmap & BIT(0)) {
		armada_370_xp_handle_msi_irq(NULL, true);
		irqmap &= ~BIT(0);
	}

	for_each_set_bit(irqn, &irqmap, BITS_PER_LONG) {
		cascade_irq = irq_find_mapping(armada_370_xp_mpic_domain, irqn);
		generic_handle_irq(cascade_irq);
	}

	chained_irq_exit(chip, desc);
}

static void __exception_irq_entry
armada_370_xp_handle_irq(struct pt_regs *regs)
{
	u32 irqstat, irqnr;

	do {
		irqstat = readl_relaxed(per_cpu_int_base +
					ARMADA_370_XP_CPU_INTACK_OFFS);
		irqnr = irqstat & 0x3FF;

		if (irqnr > 1022)
			break;

		if (irqnr > 1) {
			irqnr =	irq_find_mapping(armada_370_xp_mpic_domain,
					irqnr);
			handle_IRQ(irqnr, regs);
			continue;
		}

		/* MSI handling */
		if (irqnr == 1)
			armada_370_xp_handle_msi_irq(regs, false);

#ifdef CONFIG_SMP
		/* IPI Handling */
		if (irqnr == 0) {
			u32 ipimask, ipinr;

			ipimask = readl_relaxed(per_cpu_int_base +
						ARMADA_370_XP_IN_DRBEL_CAUSE_OFFS)
				& IPI_DOORBELL_MASK;

			writel(~ipimask, per_cpu_int_base +
				ARMADA_370_XP_IN_DRBEL_CAUSE_OFFS);

			/* Handle all pending doorbells */
			for (ipinr = IPI_DOORBELL_START;
			     ipinr < IPI_DOORBELL_END; ipinr++) {
				if (ipimask & (0x1 << ipinr))
					handle_IPI(ipinr, regs);
			}
			continue;
		}
#endif

	} while (1);
}

static int __init armada_370_xp_mpic_of_init(struct device_node *node,
					     struct device_node *parent)
{
	struct resource main_int_res, per_cpu_int_res;
	int parent_irq, nr_irqs, i;
	u32 control;

	BUG_ON(of_address_to_resource(node, 0, &main_int_res));
	BUG_ON(of_address_to_resource(node, 1, &per_cpu_int_res));

	BUG_ON(!request_mem_region(main_int_res.start,
				   resource_size(&main_int_res),
				   node->full_name));
	BUG_ON(!request_mem_region(per_cpu_int_res.start,
				   resource_size(&per_cpu_int_res),
				   node->full_name));

	main_int_base = ioremap(main_int_res.start,
				resource_size(&main_int_res));
	BUG_ON(!main_int_base);

	per_cpu_int_base = ioremap(per_cpu_int_res.start,
				   resource_size(&per_cpu_int_res));
	BUG_ON(!per_cpu_int_base);

	control = readl(main_int_base + ARMADA_370_XP_INT_CONTROL);
	nr_irqs = (control >> 2) & 0x3ff;

	for (i = 0; i < nr_irqs; i++)
		writel(i, main_int_base + ARMADA_370_XP_INT_CLEAR_ENABLE_OFFS);

	armada_370_xp_mpic_domain =
		irq_domain_add_linear(node, nr_irqs,
				&armada_370_xp_mpic_irq_ops, NULL);

	BUG_ON(!armada_370_xp_mpic_domain);

#ifdef CONFIG_SMP
	armada_xp_mpic_smp_cpu_init();
#endif

	armada_370_xp_msi_init(node, main_int_res.start);

	parent_irq = irq_of_parse_and_map(node, 0);
	if (parent_irq <= 0) {
		irq_set_default_host(armada_370_xp_mpic_domain);
		set_handle_irq(armada_370_xp_handle_irq);
#ifdef CONFIG_SMP
		set_smp_cross_call(armada_mpic_send_doorbell);
		register_cpu_notifier(&armada_370_xp_mpic_cpu_notifier);
#endif
	} else {
		irq_set_chained_handler(parent_irq,
					armada_370_xp_mpic_handle_cascade_irq);
	}

	return 0;
}

IRQCHIP_DECLARE(armada_370_xp_mpic, "marvell,mpic", armada_370_xp_mpic_of_init);
Commit	Line	Data
9ae6f740 TP	1	/*
	2	* Marvell Armada 370 and Armada XP SoC IRQ handling
	3	*
	4	* Copyright (C) 2012 Marvell
	5	*
	6	* Lior Amsalem <alior@marvell.com>
	7	* Gregory CLEMENT <gregory.clement@free-electrons.com>
	8	* Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
	9	* Ben Dooks <ben.dooks@codethink.co.uk>
	10	*
	11	* This file is licensed under the terms of the GNU General Public
	12	* License version 2. This program is licensed "as is" without any
	13	* warranty of any kind, whether express or implied.
	14	*/
	15
	16	#include <linux/kernel.h>
	17	#include <linux/module.h>
	18	#include <linux/init.h>
	19	#include <linux/irq.h>
	20	#include <linux/interrupt.h>
bc69b8ad	21	#include <linux/irqchip/chained_irq.h>
d7df84b3	22	#include <linux/cpu.h>
9ae6f740 TP	23	#include <linux/io.h>
	24	#include <linux/of_address.h>
	25	#include <linux/of_irq.h>
31f614ed	26	#include <linux/of_pci.h>
9ae6f740	27	#include <linux/irqdomain.h>
31f614ed TP	28	#include <linux/slab.h>
31f614ed TP	29	#include <linux/msi.h>
9ae6f740 TP	30	#include <asm/mach/arch.h>
9ae6f740 TP	31	#include <asm/exception.h>
344e873e	32	#include <asm/smp_plat.h>
9339d432 TP	33	#include <asm/mach/irq.h>
	34
	35	#include "irqchip.h"
9ae6f740 TP	36
	37	/* Interrupt Controller Registers Map */
	38	#define ARMADA_370_XP_INT_SET_MASK_OFFS (0x48)
	39	#define ARMADA_370_XP_INT_CLEAR_MASK_OFFS (0x4C)
	40
f3e16ccd	41	#define ARMADA_370_XP_INT_CONTROL (0x00)
9ae6f740 TP	42	#define ARMADA_370_XP_INT_SET_ENABLE_OFFS (0x30)
9ae6f740 TP	43	#define ARMADA_370_XP_INT_CLEAR_ENABLE_OFFS (0x34)
3202bf01	44	#define ARMADA_370_XP_INT_SOURCE_CTL(irq) (0x100 + irq*4)
8cc3cfc5	45	#define ARMADA_370_XP_INT_SOURCE_CPU_MASK 0xF
9ae6f740 TP	46
9ae6f740 TP	47	#define ARMADA_370_XP_CPU_INTACK_OFFS (0x44)
bc69b8ad	48	#define ARMADA_375_PPI_CAUSE (0x10)
9ae6f740	49
344e873e GC	50	#define ARMADA_370_XP_SW_TRIG_INT_OFFS (0x4)
	51	#define ARMADA_370_XP_IN_DRBEL_MSK_OFFS (0xc)
	52	#define ARMADA_370_XP_IN_DRBEL_CAUSE_OFFS (0x8)
	53
3202bf01 GC	54	#define ARMADA_370_XP_MAX_PER_CPU_IRQS (28)
3202bf01 GC	55
7f23f62f GC	56	#define ARMADA_370_XP_TIMER0_PER_CPU_IRQ (5)
7f23f62f GC	57
5ec69017 TP	58	#define IPI_DOORBELL_START (0)
	59	#define IPI_DOORBELL_END (8)
	60	#define IPI_DOORBELL_MASK 0xFF
31f614ed TP	61	#define PCI_MSI_DOORBELL_START (16)
	62	#define PCI_MSI_DOORBELL_NR (16)
	63	#define PCI_MSI_DOORBELL_END (32)
	64	#define PCI_MSI_DOORBELL_MASK 0xFFFF0000
344e873e	65
9ae6f740 TP	66	static void __iomem *per_cpu_int_base;
	67	static void __iomem *main_int_base;
	68	static struct irq_domain *armada_370_xp_mpic_domain;
31f614ed TP	69	#ifdef CONFIG_PCI_MSI
	70	static struct irq_domain *armada_370_xp_msi_domain;
	71	static DECLARE_BITMAP(msi_used, PCI_MSI_DOORBELL_NR);
	72	static DEFINE_MUTEX(msi_used_lock);
	73	static phys_addr_t msi_doorbell_addr;
	74	#endif
9ae6f740	75
3202bf01 GC	76	/*
	77	* In SMP mode:
	78	* For shared global interrupts, mask/unmask global enable bit
097ef18d	79	* For CPU interrupts, mask/unmask the calling CPU's bit
3202bf01	80	*/
9ae6f740 TP	81	static void armada_370_xp_irq_mask(struct irq_data *d)
9ae6f740 TP	82	{
3202bf01 GC	83	irq_hw_number_t hwirq = irqd_to_hwirq(d);
3202bf01 GC	84
7f23f62f	85	if (hwirq != ARMADA_370_XP_TIMER0_PER_CPU_IRQ)
3202bf01 GC	86	writel(hwirq, main_int_base +
	87	ARMADA_370_XP_INT_CLEAR_ENABLE_OFFS);
	88	else
	89	writel(hwirq, per_cpu_int_base +
	90	ARMADA_370_XP_INT_SET_MASK_OFFS);
9ae6f740 TP	91	}
	92
	93	static void armada_370_xp_irq_unmask(struct irq_data *d)
	94	{
3202bf01 GC	95	irq_hw_number_t hwirq = irqd_to_hwirq(d);
3202bf01 GC	96
7f23f62f	97	if (hwirq != ARMADA_370_XP_TIMER0_PER_CPU_IRQ)
3202bf01 GC	98	writel(hwirq, main_int_base +
	99	ARMADA_370_XP_INT_SET_ENABLE_OFFS);
	100	else
	101	writel(hwirq, per_cpu_int_base +
	102	ARMADA_370_XP_INT_CLEAR_MASK_OFFS);
9ae6f740 TP	103	}
9ae6f740 TP	104
31f614ed TP	105	#ifdef CONFIG_PCI_MSI
	106
	107	static int armada_370_xp_alloc_msi(void)
	108	{
	109	int hwirq;
	110
	111	mutex_lock(&msi_used_lock);
	112	hwirq = find_first_zero_bit(&msi_used, PCI_MSI_DOORBELL_NR);
	113	if (hwirq >= PCI_MSI_DOORBELL_NR)
	114	hwirq = -ENOSPC;
	115	else
	116	set_bit(hwirq, msi_used);
	117	mutex_unlock(&msi_used_lock);
	118
	119	return hwirq;
	120	}
	121
	122	static void armada_370_xp_free_msi(int hwirq)
	123	{
	124	mutex_lock(&msi_used_lock);
	125	if (!test_bit(hwirq, msi_used))
	126	pr_err("trying to free unused MSI#%d\n", hwirq);
	127	else
	128	clear_bit(hwirq, msi_used);
	129	mutex_unlock(&msi_used_lock);
	130	}
	131
	132	static int armada_370_xp_setup_msi_irq(struct msi_chip *chip,
	133	struct pci_dev *pdev,
	134	struct msi_desc *desc)
	135	{
	136	struct msi_msg msg;
da343fc7	137	int virq, hwirq;
31f614ed TP	138
	139	hwirq = armada_370_xp_alloc_msi();
	140	if (hwirq < 0)
	141	return hwirq;
	142
	143	virq = irq_create_mapping(armada_370_xp_msi_domain, hwirq);
	144	if (!virq) {
	145	armada_370_xp_free_msi(hwirq);
	146	return -EINVAL;
	147	}
	148
	149	irq_set_msi_desc(virq, desc);
	150
	151	msg.address_lo = msi_doorbell_addr;
	152	msg.address_hi = 0;
	153	msg.data = 0xf00 \| (hwirq + 16);
	154
	155	write_msi_msg(virq, &msg);
	156	return 0;
	157	}
	158
	159	static void armada_370_xp_teardown_msi_irq(struct msi_chip *chip,
	160	unsigned int irq)
	161	{
	162	struct irq_data *d = irq_get_irq_data(irq);
ff3c6645 NG	163	unsigned long hwirq = d->hwirq;
ff3c6645 NG	164
31f614ed	165	irq_dispose_mapping(irq);
ff3c6645	166	armada_370_xp_free_msi(hwirq);
31f614ed TP	167	}
31f614ed TP	168
830cbe4b TP	169	static int armada_370_xp_check_msi_device(struct msi_chip chip, struct pci_dev dev,
	170	int nvec, int type)
	171	{
	172	/* We support MSI, but not MSI-X */
	173	if (type == PCI_CAP_ID_MSI)
	174	return 0;
	175	return -EINVAL;
31f614ed TP	176	}
	177
	178	static struct irq_chip armada_370_xp_msi_irq_chip = {
	179	.name = "armada_370_xp_msi_irq",
	180	.irq_enable = unmask_msi_irq,
	181	.irq_disable = mask_msi_irq,
	182	.irq_mask = mask_msi_irq,
	183	.irq_unmask = unmask_msi_irq,
	184	};
	185
	186	static int armada_370_xp_msi_map(struct irq_domain *domain, unsigned int virq,
	187	irq_hw_number_t hw)
	188	{
	189	irq_set_chip_and_handler(virq, &armada_370_xp_msi_irq_chip,
	190	handle_simple_irq);
	191	set_irq_flags(virq, IRQF_VALID);
	192
	193	return 0;
	194	}
	195
	196	static const struct irq_domain_ops armada_370_xp_msi_irq_ops = {
	197	.map = armada_370_xp_msi_map,
	198	};
	199
	200	static int armada_370_xp_msi_init(struct device_node *node,
	201	phys_addr_t main_int_phys_base)
	202	{
	203	struct msi_chip *msi_chip;
	204	u32 reg;
	205	int ret;
	206
	207	msi_doorbell_addr = main_int_phys_base +
	208	ARMADA_370_XP_SW_TRIG_INT_OFFS;
	209
	210	msi_chip = kzalloc(sizeof(*msi_chip), GFP_KERNEL);
	211	if (!msi_chip)
	212	return -ENOMEM;
	213
	214	msi_chip->setup_irq = armada_370_xp_setup_msi_irq;
	215	msi_chip->teardown_irq = armada_370_xp_teardown_msi_irq;
830cbe4b	216	msi_chip->check_device = armada_370_xp_check_msi_device;
31f614ed TP	217	msi_chip->of_node = node;
	218
	219	armada_370_xp_msi_domain =
	220	irq_domain_add_linear(NULL, PCI_MSI_DOORBELL_NR,
	221	&armada_370_xp_msi_irq_ops,
	222	NULL);
	223	if (!armada_370_xp_msi_domain) {
	224	kfree(msi_chip);
	225	return -ENOMEM;
	226	}
	227
	228	ret = of_pci_msi_chip_add(msi_chip);
	229	if (ret < 0) {
	230	irq_domain_remove(armada_370_xp_msi_domain);
	231	kfree(msi_chip);
	232	return ret;
	233	}
	234
	235	reg = readl(per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_MSK_OFFS)
	236	\| PCI_MSI_DOORBELL_MASK;
	237
	238	writel(reg, per_cpu_int_base +
	239	ARMADA_370_XP_IN_DRBEL_MSK_OFFS);
	240
	241	/* Unmask IPI interrupt */
	242	writel(1, per_cpu_int_base + ARMADA_370_XP_INT_CLEAR_MASK_OFFS);
	243
	244	return 0;
	245	}
	246	#else
	247	static inline int armada_370_xp_msi_init(struct device_node *node,
	248	phys_addr_t main_int_phys_base)
	249	{
	250	return 0;
	251	}
	252	#endif
	253
344e873e	254	#ifdef CONFIG_SMP
19e61d41 AE	255	static DEFINE_RAW_SPINLOCK(irq_controller_lock);
19e61d41 AE	256
344e873e GC	257	static int armada_xp_set_affinity(struct irq_data *d,
	258	const struct cpumask *mask_val, bool force)
	259	{
3202bf01	260	irq_hw_number_t hwirq = irqd_to_hwirq(d);
8cc3cfc5	261	unsigned long reg, mask;
3202bf01 GC	262	int cpu;
3202bf01 GC	263
8cc3cfc5 TG	264	/* Select a single core from the affinity mask which is online */
	265	cpu = cpumask_any_and(mask_val, cpu_online_mask);
	266	mask = 1UL << cpu_logical_map(cpu);
3202bf01 GC	267
3202bf01 GC	268	raw_spin_lock(&irq_controller_lock);
3202bf01	269	reg = readl(main_int_base + ARMADA_370_XP_INT_SOURCE_CTL(hwirq));
8cc3cfc5	270	reg = (reg & (~ARMADA_370_XP_INT_SOURCE_CPU_MASK)) \| mask;
3202bf01	271	writel(reg, main_int_base + ARMADA_370_XP_INT_SOURCE_CTL(hwirq));
3202bf01 GC	272	raw_spin_unlock(&irq_controller_lock);
3202bf01 GC	273
344e873e GC	274	return 0;
	275	}
	276	#endif
	277
9ae6f740 TP	278	static struct irq_chip armada_370_xp_irq_chip = {
	279	.name = "armada_370_xp_irq",
	280	.irq_mask = armada_370_xp_irq_mask,
	281	.irq_mask_ack = armada_370_xp_irq_mask,
	282	.irq_unmask = armada_370_xp_irq_unmask,
344e873e GC	283	#ifdef CONFIG_SMP
	284	.irq_set_affinity = armada_xp_set_affinity,
	285	#endif
9ae6f740 TP	286	};
	287
	288	static int armada_370_xp_mpic_irq_map(struct irq_domain *h,
	289	unsigned int virq, irq_hw_number_t hw)
	290	{
	291	armada_370_xp_irq_mask(irq_get_irq_data(virq));
600468d0 GC	292	if (hw != ARMADA_370_XP_TIMER0_PER_CPU_IRQ)
	293	writel(hw, per_cpu_int_base +
	294	ARMADA_370_XP_INT_CLEAR_MASK_OFFS);
	295	else
	296	writel(hw, main_int_base + ARMADA_370_XP_INT_SET_ENABLE_OFFS);
9ae6f740	297	irq_set_status_flags(virq, IRQ_LEVEL);
3a6f08a3	298
7f23f62f	299	if (hw == ARMADA_370_XP_TIMER0_PER_CPU_IRQ) {
3a6f08a3 GC	300	irq_set_percpu_devid(virq);
	301	irq_set_chip_and_handler(virq, &armada_370_xp_irq_chip,
	302	handle_percpu_devid_irq);
	303
	304	} else {
	305	irq_set_chip_and_handler(virq, &armada_370_xp_irq_chip,
	306	handle_level_irq);
	307	}
9ae6f740 TP	308	set_irq_flags(virq, IRQF_VALID \| IRQF_PROBE);
	309
	310	return 0;
	311	}
	312
344e873e	313	#ifdef CONFIG_SMP
ef37d337 TP	314	static void armada_mpic_send_doorbell(const struct cpumask *mask,
ef37d337 TP	315	unsigned int irq)
344e873e GC	316	{
	317	int cpu;
	318	unsigned long map = 0;
	319
	320	/* Convert our logical CPU mask into a physical one. */
	321	for_each_cpu(cpu, mask)
	322	map \|= 1 << cpu_logical_map(cpu);
	323
	324	/*
	325	* Ensure that stores to Normal memory are visible to the
	326	* other CPUs before issuing the IPI.
	327	*/
	328	dsb();
	329
	330	/* submit softirq */
	331	writel((map << 8) \| irq, main_int_base +
	332	ARMADA_370_XP_SW_TRIG_INT_OFFS);
	333	}
	334
d7df84b3	335	static void armada_xp_mpic_smp_cpu_init(void)
344e873e	336	{
b73842b7 TP	337	u32 control;
	338	int nr_irqs, i;
	339
	340	control = readl(main_int_base + ARMADA_370_XP_INT_CONTROL);
	341	nr_irqs = (control >> 2) & 0x3ff;
	342
	343	for (i = 0; i < nr_irqs; i++)
	344	writel(i, per_cpu_int_base + ARMADA_370_XP_INT_SET_MASK_OFFS);
	345
344e873e GC	346	/* Clear pending IPIs */
	347	writel(0, per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_CAUSE_OFFS);
	348
	349	/* Enable first 8 IPIs */
5ec69017	350	writel(IPI_DOORBELL_MASK, per_cpu_int_base +
344e873e GC	351	ARMADA_370_XP_IN_DRBEL_MSK_OFFS);
	352
	353	/* Unmask IPI interrupt */
	354	writel(0, per_cpu_int_base + ARMADA_370_XP_INT_CLEAR_MASK_OFFS);
	355	}
d7df84b3 TP	356
	357	static int armada_xp_mpic_secondary_init(struct notifier_block *nfb,
	358	unsigned long action, void *hcpu)
	359	{
	360	if (action == CPU_STARTING \|\| action == CPU_STARTING_FROZEN)
	361	armada_xp_mpic_smp_cpu_init();
	362	return NOTIFY_OK;
	363	}
	364
	365	static struct notifier_block armada_370_xp_mpic_cpu_notifier = {
	366	.notifier_call = armada_xp_mpic_secondary_init,
	367	.priority = 100,
	368	};
	369
344e873e GC	370	#endif /* CONFIG_SMP */
344e873e GC	371
9ae6f740 TP	372	static struct irq_domain_ops armada_370_xp_mpic_irq_ops = {
	373	.map = armada_370_xp_mpic_irq_map,
	374	.xlate = irq_domain_xlate_onecell,
	375	};
	376
9b8cf779	377	#ifdef CONFIG_PCI_MSI
bc69b8ad	378	static void armada_370_xp_handle_msi_irq(struct pt_regs *regs, bool is_chained)
9b8cf779 EG	379	{
	380	u32 msimask, msinr;
	381
	382	msimask = readl_relaxed(per_cpu_int_base +
	383	ARMADA_370_XP_IN_DRBEL_CAUSE_OFFS)
	384	& PCI_MSI_DOORBELL_MASK;
	385
	386	writel(~msimask, per_cpu_int_base +
	387	ARMADA_370_XP_IN_DRBEL_CAUSE_OFFS);
	388
	389	for (msinr = PCI_MSI_DOORBELL_START;
	390	msinr < PCI_MSI_DOORBELL_END; msinr++) {
	391	int irq;
	392
	393	if (!(msimask & BIT(msinr)))
	394	continue;
	395
	396	irq = irq_find_mapping(armada_370_xp_msi_domain,
	397	msinr - 16);
bc69b8ad EG	398
	399	if (is_chained)
	400	generic_handle_irq(irq);
	401	else
	402	handle_IRQ(irq, regs);
9b8cf779 EG	403	}
	404	}
	405	#else
bc69b8ad	406	static void armada_370_xp_handle_msi_irq(struct pt_regs *r, bool b) {}
9b8cf779 EG	407	#endif
9b8cf779 EG	408
bc69b8ad EG	409	static void armada_370_xp_mpic_handle_cascade_irq(unsigned int irq,
	410	struct irq_desc *desc)
	411	{
	412	struct irq_chip *chip = irq_get_chip(irq);
	413	unsigned long irqmap, irqn;
	414	unsigned int cascade_irq;
	415
	416	chained_irq_enter(chip, desc);
	417
	418	irqmap = readl_relaxed(per_cpu_int_base + ARMADA_375_PPI_CAUSE);
	419
	420	if (irqmap & BIT(0)) {
	421	armada_370_xp_handle_msi_irq(NULL, true);
	422	irqmap &= ~BIT(0);
	423	}
	424
	425	for_each_set_bit(irqn, &irqmap, BITS_PER_LONG) {
	426	cascade_irq = irq_find_mapping(armada_370_xp_mpic_domain, irqn);
	427	generic_handle_irq(cascade_irq);
	428	}
	429
	430	chained_irq_exit(chip, desc);
	431	}
	432
8783dd3a	433	static void __exception_irq_entry
9339d432	434	armada_370_xp_handle_irq(struct pt_regs *regs)
9ae6f740 TP	435	{
	436	u32 irqstat, irqnr;
	437
	438	do {
	439	irqstat = readl_relaxed(per_cpu_int_base +
	440	ARMADA_370_XP_CPU_INTACK_OFFS);
	441	irqnr = irqstat & 0x3FF;
	442
344e873e GC	443	if (irqnr > 1022)
	444	break;
	445
31f614ed	446	if (irqnr > 1) {
344e873e GC	447	irqnr = irq_find_mapping(armada_370_xp_mpic_domain,
344e873e GC	448	irqnr);
9ae6f740 TP	449	handle_IRQ(irqnr, regs);
	450	continue;
	451	}
31f614ed	452
31f614ed	453	/* MSI handling */
9b8cf779	454	if (irqnr == 1)
bc69b8ad	455	armada_370_xp_handle_msi_irq(regs, false);
31f614ed	456
344e873e GC	457	#ifdef CONFIG_SMP
	458	/* IPI Handling */
	459	if (irqnr == 0) {
	460	u32 ipimask, ipinr;
	461
	462	ipimask = readl_relaxed(per_cpu_int_base +
	463	ARMADA_370_XP_IN_DRBEL_CAUSE_OFFS)
5ec69017	464	& IPI_DOORBELL_MASK;
344e873e	465
a6f089e9	466	writel(~ipimask, per_cpu_int_base +
344e873e GC	467	ARMADA_370_XP_IN_DRBEL_CAUSE_OFFS);
	468
	469	/* Handle all pending doorbells */
5ec69017 TP	470	for (ipinr = IPI_DOORBELL_START;
5ec69017 TP	471	ipinr < IPI_DOORBELL_END; ipinr++) {
344e873e GC	472	if (ipimask & (0x1 << ipinr))
	473	handle_IPI(ipinr, regs);
	474	}
	475	continue;
	476	}
	477	#endif
9ae6f740	478
9ae6f740 TP	479	} while (1);
	480	}
	481
b313ada8 TP	482	static int __init armada_370_xp_mpic_of_init(struct device_node *node,
b313ada8 TP	483	struct device_node *parent)
9ae6f740	484	{
627dfcc2	485	struct resource main_int_res, per_cpu_int_res;
b73842b7	486	int parent_irq, nr_irqs, i;
b313ada8 TP	487	u32 control;
b313ada8 TP	488
627dfcc2 TP	489	BUG_ON(of_address_to_resource(node, 0, &main_int_res));
627dfcc2 TP	490	BUG_ON(of_address_to_resource(node, 1, &per_cpu_int_res));
b313ada8	491
627dfcc2 TP	492	BUG_ON(!request_mem_region(main_int_res.start,
	493	resource_size(&main_int_res),
	494	node->full_name));
	495	BUG_ON(!request_mem_region(per_cpu_int_res.start,
	496	resource_size(&per_cpu_int_res),
	497	node->full_name));
	498
	499	main_int_base = ioremap(main_int_res.start,
	500	resource_size(&main_int_res));
b313ada8	501	BUG_ON(!main_int_base);
627dfcc2 TP	502
	503	per_cpu_int_base = ioremap(per_cpu_int_res.start,
	504	resource_size(&per_cpu_int_res));
b313ada8 TP	505	BUG_ON(!per_cpu_int_base);
	506
	507	control = readl(main_int_base + ARMADA_370_XP_INT_CONTROL);
b73842b7 TP	508	nr_irqs = (control >> 2) & 0x3ff;
	509
	510	for (i = 0; i < nr_irqs; i++)
	511	writel(i, main_int_base + ARMADA_370_XP_INT_CLEAR_ENABLE_OFFS);
b313ada8 TP	512
b313ada8 TP	513	armada_370_xp_mpic_domain =
b73842b7	514	irq_domain_add_linear(node, nr_irqs,
b313ada8 TP	515	&armada_370_xp_mpic_irq_ops, NULL);
b313ada8 TP	516
627dfcc2	517	BUG_ON(!armada_370_xp_mpic_domain);
b313ada8	518
b313ada8 TP	519	#ifdef CONFIG_SMP
b313ada8 TP	520	armada_xp_mpic_smp_cpu_init();
d792b1e9	521	#endif
b313ada8	522
31f614ed TP	523	armada_370_xp_msi_init(node, main_int_res.start);
31f614ed TP	524
bc69b8ad EG	525	parent_irq = irq_of_parse_and_map(node, 0);
	526	if (parent_irq <= 0) {
	527	irq_set_default_host(armada_370_xp_mpic_domain);
	528	set_handle_irq(armada_370_xp_handle_irq);
ef37d337 TP	529	#ifdef CONFIG_SMP
ef37d337 TP	530	set_smp_cross_call(armada_mpic_send_doorbell);
d7df84b3	531	register_cpu_notifier(&armada_370_xp_mpic_cpu_notifier);
ef37d337	532	#endif
bc69b8ad EG	533	} else {
	534	irq_set_chained_handler(parent_irq,
	535	armada_370_xp_mpic_handle_cascade_irq);
	536	}
b313ada8 TP	537
b313ada8 TP	538	return 0;
9ae6f740	539	}
b313ada8	540
9339d432	541	IRQCHIP_DECLARE(armada_370_xp_mpic, "marvell,mpic", armada_370_xp_mpic_of_init);