[mirror_ubuntu-zesty-kernel.git] / drivers / irqchip / irq-bcm2835.c

/*
 * Copyright 2010 Broadcom
 * Copyright 2012 Simon Arlott, Chris Boot, Stephen Warren
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * Quirk 1: Shortcut interrupts don't set the bank 1/2 register pending bits
 *
 * If an interrupt fires on bank 1 that isn't in the shortcuts list, bit 8
 * on bank 0 is set to signify that an interrupt in bank 1 has fired, and
 * to look in the bank 1 status register for more information.
 *
 * If an interrupt fires on bank 1 that _is_ in the shortcuts list, its
 * shortcut bit in bank 0 is set as well as its interrupt bit in the bank 1
 * status register, but bank 0 bit 8 is _not_ set.
 *
 * Quirk 2: You can't mask the register 1/2 pending interrupts
 *
 * In a proper cascaded interrupt controller, the interrupt lines with
 * cascaded interrupt controllers on them are just normal interrupt lines.
 * You can mask the interrupts and get on with things. With this controller
 * you can't do that.
 *
 * Quirk 3: The shortcut interrupts can't be (un)masked in bank 0
 *
 * Those interrupts that have shortcuts can only be masked/unmasked in
 * their respective banks' enable/disable registers. Doing so in the bank 0
 * enable/disable registers has no effect.
 *
 * The FIQ control register:
 *  Bits 0-6: IRQ (index in order of interrupts from banks 1, 2, then 0)
 *  Bit    7: Enable FIQ generation
 *  Bits  8+: Unused
 *
 * An interrupt must be disabled before configuring it for FIQ generation
 * otherwise both handlers will fire at the same time!
 */

#include <linux/io.h>
#include <linux/slab.h>
#include <linux/of_address.h>
#include <linux/of_irq.h>
#include <linux/irqchip.h>
#include <linux/irqdomain.h>

#include <asm/exception.h>

/* Put the bank and irq (32 bits) into the hwirq */
#define MAKE_HWIRQ(b, n)	(((b) << 5) | (n))
#define HWIRQ_BANK(i)		(i >> 5)
#define HWIRQ_BIT(i)		BIT(i & 0x1f)

#define NR_IRQS_BANK0		8
#define BANK0_HWIRQ_MASK	0xff
/* Shortcuts can't be disabled so any unknown new ones need to be masked */
#define SHORTCUT1_MASK		0x00007c00
#define SHORTCUT2_MASK		0x001f8000
#define SHORTCUT_SHIFT		10
#define BANK1_HWIRQ		BIT(8)
#define BANK2_HWIRQ		BIT(9)
#define BANK0_VALID_MASK	(BANK0_HWIRQ_MASK | BANK1_HWIRQ | BANK2_HWIRQ \
					| SHORTCUT1_MASK | SHORTCUT2_MASK)

#define REG_FIQ_CONTROL		0x0c
#define REG_FIQ_ENABLE		0x80
#define REG_FIQ_DISABLE		0

#define NR_BANKS		3
#define IRQS_PER_BANK		32
#define NUMBER_IRQS		MAKE_HWIRQ(NR_BANKS, 0)
#define FIQ_START		(NR_IRQS_BANK0 + MAKE_HWIRQ(NR_BANKS - 1, 0))

static const int reg_pending[] __initconst = { 0x00, 0x04, 0x08 };
static const int reg_enable[] __initconst = { 0x18, 0x10, 0x14 };
static const int reg_disable[] __initconst = { 0x24, 0x1c, 0x20 };
static const int bank_irqs[] __initconst = { 8, 32, 32 };

static const int shortcuts[] = {
	7, 9, 10, 18, 19,		/* Bank 1 */
	21, 22, 23, 24, 25, 30		/* Bank 2 */
};

struct armctrl_ic {
	void __iomem *base;
	void __iomem *pending[NR_BANKS];
	void __iomem *enable[NR_BANKS];
	void __iomem *disable[NR_BANKS];
	struct irq_domain *domain;
};

static struct armctrl_ic intc __read_mostly;
static void __exception_irq_entry bcm2835_handle_irq(
	struct pt_regs *regs);
static void bcm2836_chained_handle_irq(struct irq_desc *desc);

static inline unsigned int hwirq_to_fiq(unsigned long hwirq)
{
	hwirq -= NUMBER_IRQS;
	/*
	 * The hwirq numbering used in this driver is:
	 *   BASE (0-7) GPU1 (32-63) GPU2 (64-95).
	 * This differ from the one used in the FIQ register:
	 *   GPU1 (0-31) GPU2 (32-63) BASE (64-71)
	 */
	if (hwirq >= 32)
		return hwirq - 32;

	return hwirq + 64;
}

static void armctrl_mask_irq(struct irq_data *d)
{
	if (d->hwirq >= NUMBER_IRQS)
		writel_relaxed(REG_FIQ_DISABLE, intc.base + REG_FIQ_CONTROL);
	else
		writel_relaxed(HWIRQ_BIT(d->hwirq),
			       intc.disable[HWIRQ_BANK(d->hwirq)]);
}

static void armctrl_unmask_irq(struct irq_data *d)
{
	if (d->hwirq >= NUMBER_IRQS)
		writel_relaxed(REG_FIQ_ENABLE | hwirq_to_fiq(d->hwirq),
			       intc.base + REG_FIQ_CONTROL);
	else
		writel_relaxed(HWIRQ_BIT(d->hwirq),
			       intc.enable[HWIRQ_BANK(d->hwirq)]);
}

static struct irq_chip armctrl_chip = {
	.name = "ARMCTRL-level",
	.irq_mask = armctrl_mask_irq,
	.irq_unmask = armctrl_unmask_irq
};

static int armctrl_xlate(struct irq_domain *d, struct device_node *ctrlr,
	const u32 *intspec, unsigned int intsize,
	unsigned long *out_hwirq, unsigned int *out_type)
{
	if (WARN_ON(intsize != 2))
		return -EINVAL;

	if (WARN_ON(intspec[0] >= NR_BANKS))
		return -EINVAL;

	if (WARN_ON(intspec[1] >= IRQS_PER_BANK))
		return -EINVAL;

	if (WARN_ON(intspec[0] == 0 && intspec[1] >= NR_IRQS_BANK0))
		return -EINVAL;

	*out_hwirq = MAKE_HWIRQ(intspec[0], intspec[1]);
	*out_type = IRQ_TYPE_NONE;
	return 0;
}

static const struct irq_domain_ops armctrl_ops = {
	.xlate = armctrl_xlate
};

static int __init armctrl_of_init(struct device_node *node,
				  struct device_node *parent,
				  bool is_2836)
{
	void __iomem *base;
	int irq, b, i;

	base = of_iomap(node, 0);
	if (!base)
		panic("%s: unable to map IC registers\n",
			node->full_name);

	intc.base = base;
	intc.domain = irq_domain_add_linear(node, NUMBER_IRQS * 2,
					    &armctrl_ops, NULL);
	if (!intc.domain)
		panic("%s: unable to create IRQ domain\n", node->full_name);

	for (b = 0; b < NR_BANKS; b++) {
		intc.pending[b] = base + reg_pending[b];
		intc.enable[b] = base + reg_enable[b];
		intc.disable[b] = base + reg_disable[b];

		for (i = 0; i < bank_irqs[b]; i++) {
			irq = irq_create_mapping(intc.domain, MAKE_HWIRQ(b, i));
			BUG_ON(irq <= 0);
			irq_set_chip_and_handler(irq, &armctrl_chip,
				handle_level_irq);
			irq_set_probe(irq);
		}
	}

	if (is_2836) {
		int parent_irq = irq_of_parse_and_map(node, 0);

		if (!parent_irq) {
			panic("%s: unable to get parent interrupt.\n",
			      node->full_name);
		}
		irq_set_chained_handler(parent_irq, bcm2836_chained_handle_irq);
	} else {
		set_handle_irq(bcm2835_handle_irq);
	}

	/* Make a duplicate irq range which is used to enable FIQ */
	for (b = 0; b < NR_BANKS; b++) {
		for (i = 0; i < bank_irqs[b]; i++) {
			irq = irq_create_mapping(intc.domain,
					MAKE_HWIRQ(b, i) + NUMBER_IRQS);
			BUG_ON(irq <= 0);
			irq_set_chip(irq, &armctrl_chip);
			set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
		}
	}
	init_FIQ(FIQ_START);

	return 0;
}

static int __init bcm2835_armctrl_of_init(struct device_node *node,
					  struct device_node *parent)
{
	return armctrl_of_init(node, parent, false);
}

static int __init bcm2836_armctrl_of_init(struct device_node *node,
					  struct device_node *parent)
{
	return armctrl_of_init(node, parent, true);
}


/*
 * Handle each interrupt across the entire interrupt controller.  This reads the
 * status register before handling each interrupt, which is necessary given that
 * handle_IRQ may briefly re-enable interrupts for soft IRQ handling.
 */

static u32 armctrl_translate_bank(int bank)
{
	u32 stat = readl_relaxed(intc.pending[bank]);

	return MAKE_HWIRQ(bank, ffs(stat) - 1);
}

static u32 armctrl_translate_shortcut(int bank, u32 stat)
{
	return MAKE_HWIRQ(bank, shortcuts[ffs(stat >> SHORTCUT_SHIFT) - 1]);
}

static u32 get_next_armctrl_hwirq(void)
{
	u32 stat = readl_relaxed(intc.pending[0]) & BANK0_VALID_MASK;

	if (stat == 0)
		return ~0;
	else if (stat & BANK0_HWIRQ_MASK)
		return MAKE_HWIRQ(0, ffs(stat & BANK0_HWIRQ_MASK) - 1);
	else if (stat & SHORTCUT1_MASK)
		return armctrl_translate_shortcut(1, stat & SHORTCUT1_MASK);
	else if (stat & SHORTCUT2_MASK)
		return armctrl_translate_shortcut(2, stat & SHORTCUT2_MASK);
	else if (stat & BANK1_HWIRQ)
		return armctrl_translate_bank(1);
	else if (stat & BANK2_HWIRQ)
		return armctrl_translate_bank(2);
	else
		BUG();
}

static void __exception_irq_entry bcm2835_handle_irq(
	struct pt_regs *regs)
{
	u32 hwirq;

	while ((hwirq = get_next_armctrl_hwirq()) != ~0)
		handle_domain_irq(intc.domain, hwirq, regs);
}

static void bcm2836_chained_handle_irq(struct irq_desc *desc)
{
	u32 hwirq;

	while ((hwirq = get_next_armctrl_hwirq()) != ~0)
		generic_handle_irq(irq_linear_revmap(intc.domain, hwirq));
}

IRQCHIP_DECLARE(bcm2835_armctrl_ic, "brcm,bcm2835-armctrl-ic",
		bcm2835_armctrl_of_init);
IRQCHIP_DECLARE(bcm2836_armctrl_ic, "brcm,bcm2836-armctrl-ic",
		bcm2836_armctrl_of_init);
Commit	Line	Data
89214f00 SA	1	/*
	2	* Copyright 2010 Broadcom
	3	* Copyright 2012 Simon Arlott, Chris Boot, Stephen Warren
	4	*
	5	* This program is free software; you can redistribute it and/or modify
	6	* it under the terms of the GNU General Public License as published by
	7	* the Free Software Foundation; either version 2 of the License, or
	8	* (at your option) any later version.
	9	*
	10	* This program is distributed in the hope that it will be useful,
	11	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	12	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	13	* GNU General Public License for more details.
	14	*
	15	* Quirk 1: Shortcut interrupts don't set the bank 1/2 register pending bits
	16	*
	17	* If an interrupt fires on bank 1 that isn't in the shortcuts list, bit 8
	18	* on bank 0 is set to signify that an interrupt in bank 1 has fired, and
	19	* to look in the bank 1 status register for more information.
	20	*
	21	* If an interrupt fires on bank 1 that _is_ in the shortcuts list, its
	22	* shortcut bit in bank 0 is set as well as its interrupt bit in the bank 1
	23	* status register, but bank 0 bit 8 is _not_ set.
	24	*
	25	* Quirk 2: You can't mask the register 1/2 pending interrupts
	26	*
	27	* In a proper cascaded interrupt controller, the interrupt lines with
	28	* cascaded interrupt controllers on them are just normal interrupt lines.
	29	* You can mask the interrupts and get on with things. With this controller
	30	* you can't do that.
	31	*
	32	* Quirk 3: The shortcut interrupts can't be (un)masked in bank 0
	33	*
	34	* Those interrupts that have shortcuts can only be masked/unmasked in
	35	* their respective banks' enable/disable registers. Doing so in the bank 0
	36	* enable/disable registers has no effect.
	37	*
	38	* The FIQ control register:
	39	* Bits 0-6: IRQ (index in order of interrupts from banks 1, 2, then 0)
	40	* Bit 7: Enable FIQ generation
	41	* Bits 8+: Unused
	42	*
	43	* An interrupt must be disabled before configuring it for FIQ generation
	44	* otherwise both handlers will fire at the same time!
	45	*/
	46
	47	#include <linux/io.h>
	48	#include <linux/slab.h>
	49	#include <linux/of_address.h>
	50	#include <linux/of_irq.h>
41a83e06	51	#include <linux/irqchip.h>
89214f00	52	#include <linux/irqdomain.h>
89214f00 SA	53
89214f00 SA	54	#include <asm/exception.h>
5702941e	55
89214f00	56	/* Put the bank and irq (32 bits) into the hwirq */
a3372999	57	#define MAKE_HWIRQ(b, n) (((b) << 5) \| (n))
89214f00 SA	58	#define HWIRQ_BANK(i) (i >> 5)
	59	#define HWIRQ_BIT(i) BIT(i & 0x1f)
	60
	61	#define NR_IRQS_BANK0 8
	62	#define BANK0_HWIRQ_MASK 0xff
	63	/* Shortcuts can't be disabled so any unknown new ones need to be masked */
	64	#define SHORTCUT1_MASK 0x00007c00
	65	#define SHORTCUT2_MASK 0x001f8000
	66	#define SHORTCUT_SHIFT 10
	67	#define BANK1_HWIRQ BIT(8)
	68	#define BANK2_HWIRQ BIT(9)
	69	#define BANK0_VALID_MASK (BANK0_HWIRQ_MASK \| BANK1_HWIRQ \| BANK2_HWIRQ \
	70	\| SHORTCUT1_MASK \| SHORTCUT2_MASK)
	71
	72	#define REG_FIQ_CONTROL 0x0c
a3372999 NT	73	#define REG_FIQ_ENABLE 0x80
a3372999 NT	74	#define REG_FIQ_DISABLE 0
89214f00 SA	75
	76	#define NR_BANKS 3
	77	#define IRQS_PER_BANK 32
a3372999 NT	78	#define NUMBER_IRQS MAKE_HWIRQ(NR_BANKS, 0)
a3372999 NT	79	#define FIQ_START (NR_IRQS_BANK0 + MAKE_HWIRQ(NR_BANKS - 1, 0))
89214f00	80
c376023b NP	81	static const int reg_pending[] __initconst = { 0x00, 0x04, 0x08 };
	82	static const int reg_enable[] __initconst = { 0x18, 0x10, 0x14 };
	83	static const int reg_disable[] __initconst = { 0x24, 0x1c, 0x20 };
	84	static const int bank_irqs[] __initconst = { 8, 32, 32 };
89214f00 SA	85
	86	static const int shortcuts[] = {
	87	7, 9, 10, 18, 19, /* Bank 1 */
	88	21, 22, 23, 24, 25, 30 /* Bank 2 */
	89	};
	90
	91	struct armctrl_ic {
	92	void __iomem *base;
	93	void __iomem *pending[NR_BANKS];
	94	void __iomem *enable[NR_BANKS];
	95	void __iomem *disable[NR_BANKS];
	96	struct irq_domain *domain;
	97	};
	98
	99	static struct armctrl_ic intc __read_mostly;
8783dd3a	100	static void __exception_irq_entry bcm2835_handle_irq(
5702941e	101	struct pt_regs *regs);
bd0b9ac4	102	static void bcm2836_chained_handle_irq(struct irq_desc *desc);
89214f00	103
a3372999 NT	104	static inline unsigned int hwirq_to_fiq(unsigned long hwirq)
	105	{
	106	hwirq -= NUMBER_IRQS;
	107	/*
	108	* The hwirq numbering used in this driver is:
	109	* BASE (0-7) GPU1 (32-63) GPU2 (64-95).
	110	* This differ from the one used in the FIQ register:
	111	* GPU1 (0-31) GPU2 (32-63) BASE (64-71)
	112	*/
	113	if (hwirq >= 32)
	114	return hwirq - 32;
	115
	116	return hwirq + 64;
	117	}
	118
89214f00 SA	119	static void armctrl_mask_irq(struct irq_data *d)
89214f00 SA	120	{
a3372999 NT	121	if (d->hwirq >= NUMBER_IRQS)
	122	writel_relaxed(REG_FIQ_DISABLE, intc.base + REG_FIQ_CONTROL);
	123	else
	124	writel_relaxed(HWIRQ_BIT(d->hwirq),
	125	intc.disable[HWIRQ_BANK(d->hwirq)]);
89214f00 SA	126	}
	127
	128	static void armctrl_unmask_irq(struct irq_data *d)
	129	{
a3372999 NT	130	if (d->hwirq >= NUMBER_IRQS)
	131	writel_relaxed(REG_FIQ_ENABLE \| hwirq_to_fiq(d->hwirq),
	132	intc.base + REG_FIQ_CONTROL);
	133	else
	134	writel_relaxed(HWIRQ_BIT(d->hwirq),
	135	intc.enable[HWIRQ_BANK(d->hwirq)]);
89214f00 SA	136	}
	137
	138	static struct irq_chip armctrl_chip = {
	139	.name = "ARMCTRL-level",
	140	.irq_mask = armctrl_mask_irq,
	141	.irq_unmask = armctrl_unmask_irq
	142	};
	143
	144	static int armctrl_xlate(struct irq_domain d, struct device_node ctrlr,
	145	const u32 *intspec, unsigned int intsize,
	146	unsigned long out_hwirq, unsigned int out_type)
	147	{
	148	if (WARN_ON(intsize != 2))
	149	return -EINVAL;
	150
	151	if (WARN_ON(intspec[0] >= NR_BANKS))
	152	return -EINVAL;
	153
	154	if (WARN_ON(intspec[1] >= IRQS_PER_BANK))
	155	return -EINVAL;
	156
	157	if (WARN_ON(intspec[0] == 0 && intspec[1] >= NR_IRQS_BANK0))
	158	return -EINVAL;
	159
	160	*out_hwirq = MAKE_HWIRQ(intspec[0], intspec[1]);
	161	*out_type = IRQ_TYPE_NONE;
	162	return 0;
	163	}
	164
96009736	165	static const struct irq_domain_ops armctrl_ops = {
89214f00 SA	166	.xlate = armctrl_xlate
	167	};
	168
	169	static int __init armctrl_of_init(struct device_node *node,
a493f339 EA	170	struct device_node *parent,
a493f339 EA	171	bool is_2836)
89214f00 SA	172	{
	173	void __iomem *base;
	174	int irq, b, i;
	175
	176	base = of_iomap(node, 0);
	177	if (!base)
	178	panic("%s: unable to map IC registers\n",
	179	node->full_name);
	180
a3372999 NT	181	intc.base = base;
	182	intc.domain = irq_domain_add_linear(node, NUMBER_IRQS * 2,
	183	&armctrl_ops, NULL);
89214f00 SA	184	if (!intc.domain)
	185	panic("%s: unable to create IRQ domain\n", node->full_name);
	186
	187	for (b = 0; b < NR_BANKS; b++) {
	188	intc.pending[b] = base + reg_pending[b];
	189	intc.enable[b] = base + reg_enable[b];
	190	intc.disable[b] = base + reg_disable[b];
	191
	192	for (i = 0; i < bank_irqs[b]; i++) {
	193	irq = irq_create_mapping(intc.domain, MAKE_HWIRQ(b, i));
	194	BUG_ON(irq <= 0);
	195	irq_set_chip_and_handler(irq, &armctrl_chip,
	196	handle_level_irq);
d17cab44	197	irq_set_probe(irq);
89214f00 SA	198	}
89214f00 SA	199	}
89214f00	200
a493f339 EA	201	if (is_2836) {
	202	int parent_irq = irq_of_parse_and_map(node, 0);
	203
	204	if (!parent_irq) {
	205	panic("%s: unable to get parent interrupt.\n",
	206	node->full_name);
	207	}
	208	irq_set_chained_handler(parent_irq, bcm2836_chained_handle_irq);
	209	} else {
	210	set_handle_irq(bcm2835_handle_irq);
	211	}
	212
a3372999 NT	213	/* Make a duplicate irq range which is used to enable FIQ */
	214	for (b = 0; b < NR_BANKS; b++) {
	215	for (i = 0; i < bank_irqs[b]; i++) {
	216	irq = irq_create_mapping(intc.domain,
	217	MAKE_HWIRQ(b, i) + NUMBER_IRQS);
	218	BUG_ON(irq <= 0);
	219	irq_set_chip(irq, &armctrl_chip);
	220	set_irq_flags(irq, IRQF_VALID \| IRQF_PROBE);
	221	}
	222	}
	223	init_FIQ(FIQ_START);
	224
5702941e	225	return 0;
89214f00 SA	226	}
89214f00 SA	227
a493f339 EA	228	static int __init bcm2835_armctrl_of_init(struct device_node *node,
	229	struct device_node *parent)
	230	{
	231	return armctrl_of_init(node, parent, false);
	232	}
	233
	234	static int __init bcm2836_armctrl_of_init(struct device_node *node,
	235	struct device_node *parent)
	236	{
	237	return armctrl_of_init(node, parent, true);
	238	}
	239
	240
89214f00 SA	241	/*
	242	* Handle each interrupt across the entire interrupt controller. This reads the
	243	* status register before handling each interrupt, which is necessary given that
	244	* handle_IRQ may briefly re-enable interrupts for soft IRQ handling.
	245	*/
	246
de58e52f	247	static u32 armctrl_translate_bank(int bank)
89214f00	248	{
de58e52f	249	u32 stat = readl_relaxed(intc.pending[bank]);
89214f00	250
de58e52f EA	251	return MAKE_HWIRQ(bank, ffs(stat) - 1);
	252	}
	253
	254	static u32 armctrl_translate_shortcut(int bank, u32 stat)
	255	{
	256	return MAKE_HWIRQ(bank, shortcuts[ffs(stat >> SHORTCUT_SHIFT) - 1]);
89214f00 SA	257	}
89214f00 SA	258
de58e52f	259	static u32 get_next_armctrl_hwirq(void)
89214f00	260	{
de58e52f EA	261	u32 stat = readl_relaxed(intc.pending[0]) & BANK0_VALID_MASK;
	262
	263	if (stat == 0)
	264	return ~0;
	265	else if (stat & BANK0_HWIRQ_MASK)
	266	return MAKE_HWIRQ(0, ffs(stat & BANK0_HWIRQ_MASK) - 1);
	267	else if (stat & SHORTCUT1_MASK)
	268	return armctrl_translate_shortcut(1, stat & SHORTCUT1_MASK);
	269	else if (stat & SHORTCUT2_MASK)
	270	return armctrl_translate_shortcut(2, stat & SHORTCUT2_MASK);
	271	else if (stat & BANK1_HWIRQ)
	272	return armctrl_translate_bank(1);
	273	else if (stat & BANK2_HWIRQ)
	274	return armctrl_translate_bank(2);
	275	else
	276	BUG();
89214f00 SA	277	}
89214f00 SA	278
8783dd3a	279	static void __exception_irq_entry bcm2835_handle_irq(
89214f00 SA	280	struct pt_regs *regs)
89214f00 SA	281	{
de58e52f EA	282	u32 hwirq;
	283
	284	while ((hwirq = get_next_armctrl_hwirq()) != ~0)
d7e3528e	285	handle_domain_irq(intc.domain, hwirq, regs);
89214f00	286	}
5702941e	287
bd0b9ac4	288	static void bcm2836_chained_handle_irq(struct irq_desc *desc)
a493f339 EA	289	{
	290	u32 hwirq;
	291
	292	while ((hwirq = get_next_armctrl_hwirq()) != ~0)
	293	generic_handle_irq(irq_linear_revmap(intc.domain, hwirq));
	294	}
	295
	296	IRQCHIP_DECLARE(bcm2835_armctrl_ic, "brcm,bcm2835-armctrl-ic",
	297	bcm2835_armctrl_of_init);
	298	IRQCHIP_DECLARE(bcm2836_armctrl_ic, "brcm,bcm2836-armctrl-ic",
	299	bcm2836_armctrl_of_init);