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c7c42ec2 SA |
1 | /* |
2 | * Broadcom BCM6345 style Level 1 interrupt controller driver | |
3 | * | |
4 | * Copyright (C) 2014 Broadcom Corporation | |
5 | * Copyright 2015 Simon Arlott | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License version 2 as | |
9 | * published by the Free Software Foundation. | |
10 | * | |
11 | * This is based on the BCM7038 (which supports SMP) but with a single | |
12 | * enable register instead of separate mask/set/clear registers. | |
13 | * | |
14 | * The BCM3380 has a similar mask/status register layout, but each pair | |
15 | * of words is at separate locations (and SMP is not supported). | |
16 | * | |
17 | * ENABLE/STATUS words are packed next to each other for each CPU: | |
18 | * | |
19 | * BCM6368: | |
20 | * 0x1000_0020: CPU0_W0_ENABLE | |
21 | * 0x1000_0024: CPU0_W1_ENABLE | |
22 | * 0x1000_0028: CPU0_W0_STATUS IRQs 31-63 | |
23 | * 0x1000_002c: CPU0_W1_STATUS IRQs 0-31 | |
24 | * 0x1000_0030: CPU1_W0_ENABLE | |
25 | * 0x1000_0034: CPU1_W1_ENABLE | |
26 | * 0x1000_0038: CPU1_W0_STATUS IRQs 31-63 | |
27 | * 0x1000_003c: CPU1_W1_STATUS IRQs 0-31 | |
28 | * | |
29 | * BCM63168: | |
30 | * 0x1000_0020: CPU0_W0_ENABLE | |
31 | * 0x1000_0024: CPU0_W1_ENABLE | |
32 | * 0x1000_0028: CPU0_W2_ENABLE | |
33 | * 0x1000_002c: CPU0_W3_ENABLE | |
34 | * 0x1000_0030: CPU0_W0_STATUS IRQs 96-127 | |
35 | * 0x1000_0034: CPU0_W1_STATUS IRQs 64-95 | |
36 | * 0x1000_0038: CPU0_W2_STATUS IRQs 32-63 | |
37 | * 0x1000_003c: CPU0_W3_STATUS IRQs 0-31 | |
38 | * 0x1000_0040: CPU1_W0_ENABLE | |
39 | * 0x1000_0044: CPU1_W1_ENABLE | |
40 | * 0x1000_0048: CPU1_W2_ENABLE | |
41 | * 0x1000_004c: CPU1_W3_ENABLE | |
42 | * 0x1000_0050: CPU1_W0_STATUS IRQs 96-127 | |
43 | * 0x1000_0054: CPU1_W1_STATUS IRQs 64-95 | |
44 | * 0x1000_0058: CPU1_W2_STATUS IRQs 32-63 | |
45 | * 0x1000_005c: CPU1_W3_STATUS IRQs 0-31 | |
46 | * | |
47 | * IRQs are numbered in CPU native endian order | |
48 | * (which is big-endian in these examples) | |
49 | */ | |
50 | ||
51 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt | |
52 | ||
53 | #include <linux/bitops.h> | |
54 | #include <linux/cpumask.h> | |
c7c42ec2 SA |
55 | #include <linux/kernel.h> |
56 | #include <linux/init.h> | |
57 | #include <linux/interrupt.h> | |
58 | #include <linux/io.h> | |
59 | #include <linux/ioport.h> | |
60 | #include <linux/irq.h> | |
61 | #include <linux/irqdomain.h> | |
62 | #include <linux/module.h> | |
63 | #include <linux/of.h> | |
64 | #include <linux/of_irq.h> | |
65 | #include <linux/of_address.h> | |
66 | #include <linux/of_platform.h> | |
67 | #include <linux/platform_device.h> | |
68 | #include <linux/slab.h> | |
69 | #include <linux/smp.h> | |
70 | #include <linux/types.h> | |
71 | #include <linux/irqchip.h> | |
72 | #include <linux/irqchip/chained_irq.h> | |
73 | ||
74 | #define IRQS_PER_WORD 32 | |
75 | #define REG_BYTES_PER_IRQ_WORD (sizeof(u32) * 2) | |
76 | ||
77 | struct bcm6345_l1_cpu; | |
78 | ||
79 | struct bcm6345_l1_chip { | |
80 | raw_spinlock_t lock; | |
81 | unsigned int n_words; | |
82 | struct irq_domain *domain; | |
83 | struct cpumask cpumask; | |
84 | struct bcm6345_l1_cpu *cpus[NR_CPUS]; | |
85 | }; | |
86 | ||
87 | struct bcm6345_l1_cpu { | |
88 | void __iomem *map_base; | |
89 | unsigned int parent_irq; | |
90 | u32 enable_cache[]; | |
91 | }; | |
92 | ||
93 | static inline unsigned int reg_enable(struct bcm6345_l1_chip *intc, | |
94 | unsigned int word) | |
95 | { | |
96 | #ifdef __BIG_ENDIAN | |
97 | return (1 * intc->n_words - word - 1) * sizeof(u32); | |
98 | #else | |
99 | return (0 * intc->n_words + word) * sizeof(u32); | |
100 | #endif | |
101 | } | |
102 | ||
103 | static inline unsigned int reg_status(struct bcm6345_l1_chip *intc, | |
104 | unsigned int word) | |
105 | { | |
106 | #ifdef __BIG_ENDIAN | |
107 | return (2 * intc->n_words - word - 1) * sizeof(u32); | |
108 | #else | |
109 | return (1 * intc->n_words + word) * sizeof(u32); | |
110 | #endif | |
111 | } | |
112 | ||
113 | static inline unsigned int cpu_for_irq(struct bcm6345_l1_chip *intc, | |
114 | struct irq_data *d) | |
115 | { | |
116 | return cpumask_first_and(&intc->cpumask, irq_data_get_affinity_mask(d)); | |
117 | } | |
118 | ||
119 | static void bcm6345_l1_irq_handle(struct irq_desc *desc) | |
120 | { | |
121 | struct bcm6345_l1_chip *intc = irq_desc_get_handler_data(desc); | |
122 | struct bcm6345_l1_cpu *cpu; | |
123 | struct irq_chip *chip = irq_desc_get_chip(desc); | |
124 | unsigned int idx; | |
125 | ||
126 | #ifdef CONFIG_SMP | |
127 | cpu = intc->cpus[cpu_logical_map(smp_processor_id())]; | |
128 | #else | |
129 | cpu = intc->cpus[0]; | |
130 | #endif | |
131 | ||
132 | chained_irq_enter(chip, desc); | |
133 | ||
134 | for (idx = 0; idx < intc->n_words; idx++) { | |
135 | int base = idx * IRQS_PER_WORD; | |
136 | unsigned long pending; | |
137 | irq_hw_number_t hwirq; | |
138 | unsigned int irq; | |
139 | ||
140 | pending = __raw_readl(cpu->map_base + reg_status(intc, idx)); | |
141 | pending &= __raw_readl(cpu->map_base + reg_enable(intc, idx)); | |
142 | ||
143 | for_each_set_bit(hwirq, &pending, IRQS_PER_WORD) { | |
144 | irq = irq_linear_revmap(intc->domain, base + hwirq); | |
145 | if (irq) | |
146 | do_IRQ(irq); | |
147 | else | |
148 | spurious_interrupt(); | |
149 | } | |
150 | } | |
151 | ||
152 | chained_irq_exit(chip, desc); | |
153 | } | |
154 | ||
155 | static inline void __bcm6345_l1_unmask(struct irq_data *d) | |
156 | { | |
157 | struct bcm6345_l1_chip *intc = irq_data_get_irq_chip_data(d); | |
158 | u32 word = d->hwirq / IRQS_PER_WORD; | |
159 | u32 mask = BIT(d->hwirq % IRQS_PER_WORD); | |
160 | unsigned int cpu_idx = cpu_for_irq(intc, d); | |
161 | ||
162 | intc->cpus[cpu_idx]->enable_cache[word] |= mask; | |
163 | __raw_writel(intc->cpus[cpu_idx]->enable_cache[word], | |
164 | intc->cpus[cpu_idx]->map_base + reg_enable(intc, word)); | |
165 | } | |
166 | ||
167 | static inline void __bcm6345_l1_mask(struct irq_data *d) | |
168 | { | |
169 | struct bcm6345_l1_chip *intc = irq_data_get_irq_chip_data(d); | |
170 | u32 word = d->hwirq / IRQS_PER_WORD; | |
171 | u32 mask = BIT(d->hwirq % IRQS_PER_WORD); | |
172 | unsigned int cpu_idx = cpu_for_irq(intc, d); | |
173 | ||
174 | intc->cpus[cpu_idx]->enable_cache[word] &= ~mask; | |
175 | __raw_writel(intc->cpus[cpu_idx]->enable_cache[word], | |
176 | intc->cpus[cpu_idx]->map_base + reg_enable(intc, word)); | |
177 | } | |
178 | ||
179 | static void bcm6345_l1_unmask(struct irq_data *d) | |
180 | { | |
181 | struct bcm6345_l1_chip *intc = irq_data_get_irq_chip_data(d); | |
182 | unsigned long flags; | |
183 | ||
184 | raw_spin_lock_irqsave(&intc->lock, flags); | |
185 | __bcm6345_l1_unmask(d); | |
186 | raw_spin_unlock_irqrestore(&intc->lock, flags); | |
187 | } | |
188 | ||
189 | static void bcm6345_l1_mask(struct irq_data *d) | |
190 | { | |
191 | struct bcm6345_l1_chip *intc = irq_data_get_irq_chip_data(d); | |
192 | unsigned long flags; | |
193 | ||
194 | raw_spin_lock_irqsave(&intc->lock, flags); | |
195 | __bcm6345_l1_mask(d); | |
196 | raw_spin_unlock_irqrestore(&intc->lock, flags); | |
197 | } | |
198 | ||
199 | static int bcm6345_l1_set_affinity(struct irq_data *d, | |
200 | const struct cpumask *dest, | |
201 | bool force) | |
202 | { | |
203 | struct bcm6345_l1_chip *intc = irq_data_get_irq_chip_data(d); | |
204 | u32 word = d->hwirq / IRQS_PER_WORD; | |
205 | u32 mask = BIT(d->hwirq % IRQS_PER_WORD); | |
206 | unsigned int old_cpu = cpu_for_irq(intc, d); | |
207 | unsigned int new_cpu; | |
208 | struct cpumask valid; | |
209 | unsigned long flags; | |
210 | bool enabled; | |
211 | ||
212 | if (!cpumask_and(&valid, &intc->cpumask, dest)) | |
213 | return -EINVAL; | |
214 | ||
215 | new_cpu = cpumask_any_and(&valid, cpu_online_mask); | |
216 | if (new_cpu >= nr_cpu_ids) | |
217 | return -EINVAL; | |
218 | ||
219 | dest = cpumask_of(new_cpu); | |
220 | ||
221 | raw_spin_lock_irqsave(&intc->lock, flags); | |
222 | if (old_cpu != new_cpu) { | |
223 | enabled = intc->cpus[old_cpu]->enable_cache[word] & mask; | |
224 | if (enabled) | |
225 | __bcm6345_l1_mask(d); | |
226 | cpumask_copy(irq_data_get_affinity_mask(d), dest); | |
227 | if (enabled) | |
228 | __bcm6345_l1_unmask(d); | |
229 | } else { | |
230 | cpumask_copy(irq_data_get_affinity_mask(d), dest); | |
231 | } | |
232 | raw_spin_unlock_irqrestore(&intc->lock, flags); | |
233 | ||
234 | return IRQ_SET_MASK_OK_NOCOPY; | |
235 | } | |
236 | ||
237 | static int __init bcm6345_l1_init_one(struct device_node *dn, | |
238 | unsigned int idx, | |
239 | struct bcm6345_l1_chip *intc) | |
240 | { | |
241 | struct resource res; | |
242 | resource_size_t sz; | |
243 | struct bcm6345_l1_cpu *cpu; | |
244 | unsigned int i, n_words; | |
245 | ||
246 | if (of_address_to_resource(dn, idx, &res)) | |
247 | return -EINVAL; | |
248 | sz = resource_size(&res); | |
249 | n_words = sz / REG_BYTES_PER_IRQ_WORD; | |
250 | ||
251 | if (!intc->n_words) | |
252 | intc->n_words = n_words; | |
253 | else if (intc->n_words != n_words) | |
254 | return -EINVAL; | |
255 | ||
256 | cpu = intc->cpus[idx] = kzalloc(sizeof(*cpu) + n_words * sizeof(u32), | |
257 | GFP_KERNEL); | |
258 | if (!cpu) | |
259 | return -ENOMEM; | |
260 | ||
261 | cpu->map_base = ioremap(res.start, sz); | |
262 | if (!cpu->map_base) | |
263 | return -ENOMEM; | |
264 | ||
265 | for (i = 0; i < n_words; i++) { | |
266 | cpu->enable_cache[i] = 0; | |
267 | __raw_writel(0, cpu->map_base + reg_enable(intc, i)); | |
268 | } | |
269 | ||
270 | cpu->parent_irq = irq_of_parse_and_map(dn, idx); | |
271 | if (!cpu->parent_irq) { | |
272 | pr_err("failed to map parent interrupt %d\n", cpu->parent_irq); | |
273 | return -EINVAL; | |
274 | } | |
275 | irq_set_chained_handler_and_data(cpu->parent_irq, | |
276 | bcm6345_l1_irq_handle, intc); | |
277 | ||
278 | return 0; | |
279 | } | |
280 | ||
281 | static struct irq_chip bcm6345_l1_irq_chip = { | |
282 | .name = "bcm6345-l1", | |
283 | .irq_mask = bcm6345_l1_mask, | |
284 | .irq_unmask = bcm6345_l1_unmask, | |
285 | .irq_set_affinity = bcm6345_l1_set_affinity, | |
286 | }; | |
287 | ||
288 | static int bcm6345_l1_map(struct irq_domain *d, unsigned int virq, | |
289 | irq_hw_number_t hw_irq) | |
290 | { | |
291 | irq_set_chip_and_handler(virq, | |
292 | &bcm6345_l1_irq_chip, handle_percpu_irq); | |
293 | irq_set_chip_data(virq, d->host_data); | |
294 | return 0; | |
295 | } | |
296 | ||
297 | static const struct irq_domain_ops bcm6345_l1_domain_ops = { | |
298 | .xlate = irq_domain_xlate_onecell, | |
299 | .map = bcm6345_l1_map, | |
300 | }; | |
301 | ||
302 | static int __init bcm6345_l1_of_init(struct device_node *dn, | |
303 | struct device_node *parent) | |
304 | { | |
305 | struct bcm6345_l1_chip *intc; | |
306 | unsigned int idx; | |
307 | int ret; | |
308 | ||
309 | intc = kzalloc(sizeof(*intc), GFP_KERNEL); | |
310 | if (!intc) | |
311 | return -ENOMEM; | |
312 | ||
313 | for_each_possible_cpu(idx) { | |
314 | ret = bcm6345_l1_init_one(dn, idx, intc); | |
315 | if (ret) | |
316 | pr_err("failed to init intc L1 for cpu %d: %d\n", | |
317 | idx, ret); | |
318 | else | |
319 | cpumask_set_cpu(idx, &intc->cpumask); | |
320 | } | |
321 | ||
322 | if (!cpumask_weight(&intc->cpumask)) { | |
323 | ret = -ENODEV; | |
324 | goto out_free; | |
325 | } | |
326 | ||
327 | raw_spin_lock_init(&intc->lock); | |
328 | ||
329 | intc->domain = irq_domain_add_linear(dn, IRQS_PER_WORD * intc->n_words, | |
330 | &bcm6345_l1_domain_ops, | |
331 | intc); | |
332 | if (!intc->domain) { | |
333 | ret = -ENOMEM; | |
334 | goto out_unmap; | |
335 | } | |
336 | ||
337 | pr_info("registered BCM6345 L1 intc (IRQs: %d)\n", | |
338 | IRQS_PER_WORD * intc->n_words); | |
339 | for_each_cpu(idx, &intc->cpumask) { | |
340 | struct bcm6345_l1_cpu *cpu = intc->cpus[idx]; | |
341 | ||
342 | pr_info(" CPU%u at MMIO 0x%p (irq = %d)\n", idx, | |
343 | cpu->map_base, cpu->parent_irq); | |
344 | } | |
345 | ||
346 | return 0; | |
347 | ||
348 | out_unmap: | |
349 | for_each_possible_cpu(idx) { | |
350 | struct bcm6345_l1_cpu *cpu = intc->cpus[idx]; | |
351 | ||
352 | if (cpu) { | |
353 | if (cpu->map_base) | |
354 | iounmap(cpu->map_base); | |
355 | kfree(cpu); | |
356 | } | |
357 | } | |
358 | out_free: | |
359 | kfree(intc); | |
360 | return ret; | |
361 | } | |
362 | ||
363 | IRQCHIP_DECLARE(bcm6345_l1, "brcm,bcm6345-l1-intc", bcm6345_l1_of_init); |