[mirror_ubuntu-bionic-kernel.git] / drivers / irqchip / irq-bcm7120-l2.c

/*
 * Broadcom BCM7120 style Level 2 interrupt controller driver
 *
 * Copyright (C) 2014 Broadcom Corporation
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

#define pr_fmt(fmt)	KBUILD_MODNAME	": " fmt

#include <linux/init.h>
#include <linux/slab.h>
#include <linux/module.h>
#include <linux/kconfig.h>
#include <linux/kernel.h>
#include <linux/platform_device.h>
#include <linux/of.h>
#include <linux/of_irq.h>
#include <linux/of_address.h>
#include <linux/of_platform.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/io.h>
#include <linux/irqdomain.h>
#include <linux/reboot.h>
#include <linux/bitops.h>
#include <linux/irqchip/chained_irq.h>

#include "irqchip.h"

/* Register offset in the L2 interrupt controller */
#define IRQEN		0x00
#define IRQSTAT		0x04

#define MAX_WORDS	4
#define MAX_MAPPINGS	(MAX_WORDS * 2)
#define IRQS_PER_WORD	32

struct bcm7120_l2_intc_data {
	unsigned int n_words;
	void __iomem *map_base[MAX_MAPPINGS];
	void __iomem *pair_base[MAX_WORDS];
	int en_offset[MAX_WORDS];
	int stat_offset[MAX_WORDS];
	struct irq_domain *domain;
	bool can_wake;
	u32 irq_fwd_mask[MAX_WORDS];
	u32 irq_map_mask[MAX_WORDS];
	int num_parent_irqs;
	const __be32 *map_mask_prop;
};

static void bcm7120_l2_intc_irq_handle(unsigned int irq, struct irq_desc *desc)
{
	struct bcm7120_l2_intc_data *b = irq_desc_get_handler_data(desc);
	struct irq_chip *chip = irq_desc_get_chip(desc);
	unsigned int idx;

	chained_irq_enter(chip, desc);

	for (idx = 0; idx < b->n_words; idx++) {
		int base = idx * IRQS_PER_WORD;
		struct irq_chip_generic *gc =
			irq_get_domain_generic_chip(b->domain, base);
		unsigned long pending;
		int hwirq;

		irq_gc_lock(gc);
		pending = irq_reg_readl(gc, b->stat_offset[idx]) &
					    gc->mask_cache;
		irq_gc_unlock(gc);

		for_each_set_bit(hwirq, &pending, IRQS_PER_WORD) {
			generic_handle_irq(irq_find_mapping(b->domain,
					   base + hwirq));
		}
	}

	chained_irq_exit(chip, desc);
}

static void bcm7120_l2_intc_suspend(struct irq_data *d)
{
	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
	struct irq_chip_type *ct = irq_data_get_chip_type(d);
	struct bcm7120_l2_intc_data *b = gc->private;

	irq_gc_lock(gc);
	if (b->can_wake)
		irq_reg_writel(gc, gc->mask_cache | gc->wake_active,
			       ct->regs.mask);
	irq_gc_unlock(gc);
}

static void bcm7120_l2_intc_resume(struct irq_data *d)
{
	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
	struct irq_chip_type *ct = irq_data_get_chip_type(d);

	/* Restore the saved mask */
	irq_gc_lock(gc);
	irq_reg_writel(gc, gc->mask_cache, ct->regs.mask);
	irq_gc_unlock(gc);
}

static int bcm7120_l2_intc_init_one(struct device_node *dn,
					struct bcm7120_l2_intc_data *data,
					int irq)
{
	int parent_irq;
	unsigned int idx;

	parent_irq = irq_of_parse_and_map(dn, irq);
	if (!parent_irq) {
		pr_err("failed to map interrupt %d\n", irq);
		return -EINVAL;
	}

	/* For multiple parent IRQs with multiple words, this looks like:
	 * <irq0_w0 irq0_w1 irq1_w0 irq1_w1 ...>
	 */
	for (idx = 0; idx < data->n_words; idx++) {
		if (data->map_mask_prop) {
			data->irq_map_mask[idx] |=
				be32_to_cpup(data->map_mask_prop +
					     irq * data->n_words + idx);
		} else {
			data->irq_map_mask[idx] = 0xffffffff;
		}
	}

	irq_set_handler_data(parent_irq, data);
	irq_set_chained_handler(parent_irq, bcm7120_l2_intc_irq_handle);

	return 0;
}

static int __init bcm7120_l2_intc_iomap_7120(struct device_node *dn,
					     struct bcm7120_l2_intc_data *data)
{
	int ret;

	data->map_base[0] = of_iomap(dn, 0);
	if (!data->map_base[0]) {
		pr_err("unable to map registers\n");
		return -ENOMEM;
	}

	data->pair_base[0] = data->map_base[0];
	data->en_offset[0] = IRQEN;
	data->stat_offset[0] = IRQSTAT;
	data->n_words = 1;

	ret = of_property_read_u32_array(dn, "brcm,int-fwd-mask",
					 data->irq_fwd_mask, data->n_words);
	if (ret != 0 && ret != -EINVAL) {
		/* property exists but has the wrong number of words */
		pr_err("invalid brcm,int-fwd-mask property\n");
		return -EINVAL;
	}

	data->map_mask_prop = of_get_property(dn, "brcm,int-map-mask", &ret);
	if (!data->map_mask_prop ||
	    (ret != (sizeof(__be32) * data->num_parent_irqs * data->n_words))) {
		pr_err("invalid brcm,int-map-mask property\n");
		return -EINVAL;
	}

	return 0;
}

static int __init bcm7120_l2_intc_iomap_3380(struct device_node *dn,
					     struct bcm7120_l2_intc_data *data)
{
	unsigned int gc_idx;

	for (gc_idx = 0; gc_idx < MAX_WORDS; gc_idx++) {
		unsigned int map_idx = gc_idx * 2;
		void __iomem *en = of_iomap(dn, map_idx + 0);
		void __iomem *stat = of_iomap(dn, map_idx + 1);
		void __iomem *base = min(en, stat);

		data->map_base[map_idx + 0] = en;
		data->map_base[map_idx + 1] = stat;

		if (!base)
			break;

		data->pair_base[gc_idx] = base;
		data->en_offset[gc_idx] = en - base;
		data->stat_offset[gc_idx] = stat - base;
	}

	if (!gc_idx) {
		pr_err("unable to map registers\n");
		return -EINVAL;
	}

	data->n_words = gc_idx;
	return 0;
}

int __init bcm7120_l2_intc_probe(struct device_node *dn,
				 struct device_node *parent,
				 int (*iomap_regs_fn)(struct device_node *,
					struct bcm7120_l2_intc_data *),
				 const char *intc_name)
{
	unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN;
	struct bcm7120_l2_intc_data *data;
	struct irq_chip_generic *gc;
	struct irq_chip_type *ct;
	int ret = 0;
	unsigned int idx, irq, flags;

	data = kzalloc(sizeof(*data), GFP_KERNEL);
	if (!data)
		return -ENOMEM;

	data->num_parent_irqs = of_irq_count(dn);
	if (data->num_parent_irqs <= 0) {
		pr_err("invalid number of parent interrupts\n");
		ret = -ENOMEM;
		goto out_unmap;
	}

	ret = iomap_regs_fn(dn, data);
	if (ret < 0)
		goto out_unmap;

	for (idx = 0; idx < data->n_words; idx++) {
		__raw_writel(data->irq_fwd_mask[idx],
			     data->pair_base[idx] +
			     data->en_offset[idx]);
	}

	for (irq = 0; irq < data->num_parent_irqs; irq++) {
		ret = bcm7120_l2_intc_init_one(dn, data, irq);
		if (ret)
			goto out_unmap;
	}

	data->domain = irq_domain_add_linear(dn, IRQS_PER_WORD * data->n_words,
					     &irq_generic_chip_ops, NULL);
	if (!data->domain) {
		ret = -ENOMEM;
		goto out_unmap;
	}

	/* MIPS chips strapped for BE will automagically configure the
	 * peripheral registers for CPU-native byte order.
	 */
	flags = IRQ_GC_INIT_MASK_CACHE;
	if (IS_ENABLED(CONFIG_MIPS) && IS_ENABLED(CONFIG_CPU_BIG_ENDIAN))
		flags |= IRQ_GC_BE_IO;

	ret = irq_alloc_domain_generic_chips(data->domain, IRQS_PER_WORD, 1,
				dn->full_name, handle_level_irq, clr, 0, flags);
	if (ret) {
		pr_err("failed to allocate generic irq chip\n");
		goto out_free_domain;
	}

	if (of_property_read_bool(dn, "brcm,irq-can-wake"))
		data->can_wake = true;

	for (idx = 0; idx < data->n_words; idx++) {
		irq = idx * IRQS_PER_WORD;
		gc = irq_get_domain_generic_chip(data->domain, irq);

		gc->unused = 0xffffffff & ~data->irq_map_mask[idx];
		gc->private = data;
		ct = gc->chip_types;

		gc->reg_base = data->pair_base[idx];
		ct->regs.mask = data->en_offset[idx];

		ct->chip.irq_mask = irq_gc_mask_clr_bit;
		ct->chip.irq_unmask = irq_gc_mask_set_bit;
		ct->chip.irq_ack = irq_gc_noop;
		ct->chip.irq_suspend = bcm7120_l2_intc_suspend;
		ct->chip.irq_resume = bcm7120_l2_intc_resume;

		if (data->can_wake) {
			/* This IRQ chip can wake the system, set all
			 * relevant child interupts in wake_enabled mask
			 */
			gc->wake_enabled = 0xffffffff;
			gc->wake_enabled &= ~gc->unused;
			ct->chip.irq_set_wake = irq_gc_set_wake;
		}
	}

	pr_info("registered %s intc (mem: 0x%p, parent IRQ(s): %d)\n",
			intc_name, data->map_base[0], data->num_parent_irqs);

	return 0;

out_free_domain:
	irq_domain_remove(data->domain);
out_unmap:
	for (idx = 0; idx < MAX_MAPPINGS; idx++) {
		if (data->map_base[idx])
			iounmap(data->map_base[idx]);
	}
	kfree(data);
	return ret;
}

int __init bcm7120_l2_intc_probe_7120(struct device_node *dn,
				      struct device_node *parent)
{
	return bcm7120_l2_intc_probe(dn, parent, bcm7120_l2_intc_iomap_7120,
				     "BCM7120 L2");
}

int __init bcm7120_l2_intc_probe_3380(struct device_node *dn,
				      struct device_node *parent)
{
	return bcm7120_l2_intc_probe(dn, parent, bcm7120_l2_intc_iomap_3380,
				     "BCM3380 L2");
}

IRQCHIP_DECLARE(bcm7120_l2_intc, "brcm,bcm7120-l2-intc",
		bcm7120_l2_intc_probe_7120);

IRQCHIP_DECLARE(bcm3380_l2_intc, "brcm,bcm3380-l2-intc",
		bcm7120_l2_intc_probe_3380);
Commit	Line	Data
a5042de2 FF	1	/*
	2	* Broadcom BCM7120 style Level 2 interrupt controller driver
	3	*
	4	* Copyright (C) 2014 Broadcom Corporation
	5	*
	6	* This program is free software; you can redistribute it and/or modify
	7	* it under the terms of the GNU General Public License version 2 as
	8	* published by the Free Software Foundation.
	9	*/
	10
	11	#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
	12
	13	#include <linux/init.h>
	14	#include <linux/slab.h>
	15	#include <linux/module.h>
c17261fa	16	#include <linux/kconfig.h>
7b7230e7	17	#include <linux/kernel.h>
a5042de2 FF	18	#include <linux/platform_device.h>
	19	#include <linux/of.h>
	20	#include <linux/of_irq.h>
	21	#include <linux/of_address.h>
	22	#include <linux/of_platform.h>
	23	#include <linux/interrupt.h>
	24	#include <linux/irq.h>
	25	#include <linux/io.h>
	26	#include <linux/irqdomain.h>
	27	#include <linux/reboot.h>
c76acf4d	28	#include <linux/bitops.h>
a5042de2 FF	29	#include <linux/irqchip/chained_irq.h>
	30
	31	#include "irqchip.h"
	32
a5042de2 FF	33	/* Register offset in the L2 interrupt controller */
	34	#define IRQEN 0x00
	35	#define IRQSTAT 0x04
	36
c76acf4d	37	#define MAX_WORDS 4
ca40f1b2	38	#define MAX_MAPPINGS (MAX_WORDS * 2)
c76acf4d KC	39	#define IRQS_PER_WORD 32
c76acf4d KC	40
a5042de2	41	struct bcm7120_l2_intc_data {
c76acf4d	42	unsigned int n_words;
5b5468cf KC	43	void __iomem *map_base[MAX_MAPPINGS];
	44	void __iomem *pair_base[MAX_WORDS];
	45	int en_offset[MAX_WORDS];
	46	int stat_offset[MAX_WORDS];
a5042de2 FF	47	struct irq_domain *domain;
a5042de2 FF	48	bool can_wake;
c76acf4d KC	49	u32 irq_fwd_mask[MAX_WORDS];
c76acf4d KC	50	u32 irq_map_mask[MAX_WORDS];
ca40f1b2 KC	51	int num_parent_irqs;
ca40f1b2 KC	52	const __be32 *map_mask_prop;
a5042de2 FF	53	};
	54
	55	static void bcm7120_l2_intc_irq_handle(unsigned int irq, struct irq_desc *desc)
	56	{
	57	struct bcm7120_l2_intc_data *b = irq_desc_get_handler_data(desc);
	58	struct irq_chip *chip = irq_desc_get_chip(desc);
c76acf4d	59	unsigned int idx;
a5042de2 FF	60
	61	chained_irq_enter(chip, desc);
	62
c76acf4d KC	63	for (idx = 0; idx < b->n_words; idx++) {
	64	int base = idx * IRQS_PER_WORD;
	65	struct irq_chip_generic *gc =
	66	irq_get_domain_generic_chip(b->domain, base);
	67	unsigned long pending;
	68	int hwirq;
	69
	70	irq_gc_lock(gc);
5b5468cf KC	71	pending = irq_reg_readl(gc, b->stat_offset[idx]) &
5b5468cf KC	72	gc->mask_cache;
c76acf4d KC	73	irq_gc_unlock(gc);
	74
	75	for_each_set_bit(hwirq, &pending, IRQS_PER_WORD) {
	76	generic_handle_irq(irq_find_mapping(b->domain,
	77	base + hwirq));
	78	}
a5042de2 FF	79	}
a5042de2 FF	80
a5042de2 FF	81	chained_irq_exit(chip, desc);
	82	}
	83
	84	static void bcm7120_l2_intc_suspend(struct irq_data *d)
	85	{
	86	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
5b5468cf	87	struct irq_chip_type *ct = irq_data_get_chip_type(d);
a5042de2	88	struct bcm7120_l2_intc_data *b = gc->private;
a5042de2 FF	89
a5042de2 FF	90	irq_gc_lock(gc);
c17261fa	91	if (b->can_wake)
5b5468cf KC	92	irq_reg_writel(gc, gc->mask_cache \| gc->wake_active,
5b5468cf KC	93	ct->regs.mask);
a5042de2 FF	94	irq_gc_unlock(gc);
	95	}
	96
	97	static void bcm7120_l2_intc_resume(struct irq_data *d)
	98	{
	99	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
5b5468cf	100	struct irq_chip_type *ct = irq_data_get_chip_type(d);
a5042de2 FF	101
	102	/* Restore the saved mask */
	103	irq_gc_lock(gc);
5b5468cf	104	irq_reg_writel(gc, gc->mask_cache, ct->regs.mask);
a5042de2 FF	105	irq_gc_unlock(gc);
	106	}
	107
	108	static int bcm7120_l2_intc_init_one(struct device_node *dn,
	109	struct bcm7120_l2_intc_data *data,
ca40f1b2	110	int irq)
a5042de2 FF	111	{
a5042de2 FF	112	int parent_irq;
c76acf4d	113	unsigned int idx;
a5042de2 FF	114
a5042de2 FF	115	parent_irq = irq_of_parse_and_map(dn, irq);
714710e1	116	if (!parent_irq) {
a5042de2	117	pr_err("failed to map interrupt %d\n", irq);
714710e1	118	return -EINVAL;
a5042de2 FF	119	}
a5042de2 FF	120
c76acf4d KC	121	/* For multiple parent IRQs with multiple words, this looks like:
	122	* <irq0_w0 irq0_w1 irq1_w0 irq1_w1 ...>
	123	*/
7b7230e7 KC	124	for (idx = 0; idx < data->n_words; idx++) {
	125	if (data->map_mask_prop) {
	126	data->irq_map_mask[idx] \|=
	127	be32_to_cpup(data->map_mask_prop +
	128	irq * data->n_words + idx);
	129	} else {
	130	data->irq_map_mask[idx] = 0xffffffff;
	131	}
	132	}
a5042de2 FF	133
	134	irq_set_handler_data(parent_irq, data);
	135	irq_set_chained_handler(parent_irq, bcm7120_l2_intc_irq_handle);
	136
	137	return 0;
	138	}
	139
ca40f1b2 KC	140	static int __init bcm7120_l2_intc_iomap_7120(struct device_node *dn,
	141	struct bcm7120_l2_intc_data *data)
	142	{
	143	int ret;
	144
	145	data->map_base[0] = of_iomap(dn, 0);
	146	if (!data->map_base[0]) {
	147	pr_err("unable to map registers\n");
	148	return -ENOMEM;
	149	}
	150
	151	data->pair_base[0] = data->map_base[0];
	152	data->en_offset[0] = IRQEN;
	153	data->stat_offset[0] = IRQSTAT;
	154	data->n_words = 1;
	155
	156	ret = of_property_read_u32_array(dn, "brcm,int-fwd-mask",
	157	data->irq_fwd_mask, data->n_words);
	158	if (ret != 0 && ret != -EINVAL) {
	159	/* property exists but has the wrong number of words */
	160	pr_err("invalid brcm,int-fwd-mask property\n");
	161	return -EINVAL;
	162	}
	163
	164	data->map_mask_prop = of_get_property(dn, "brcm,int-map-mask", &ret);
	165	if (!data->map_mask_prop \|\|
	166	(ret != (sizeof(__be32) * data->num_parent_irqs * data->n_words))) {
	167	pr_err("invalid brcm,int-map-mask property\n");
	168	return -EINVAL;
	169	}
	170
	171	return 0;
	172	}
	173
7b7230e7 KC	174	static int __init bcm7120_l2_intc_iomap_3380(struct device_node *dn,
	175	struct bcm7120_l2_intc_data *data)
	176	{
	177	unsigned int gc_idx;
	178
	179	for (gc_idx = 0; gc_idx < MAX_WORDS; gc_idx++) {
	180	unsigned int map_idx = gc_idx * 2;
	181	void __iomem *en = of_iomap(dn, map_idx + 0);
	182	void __iomem *stat = of_iomap(dn, map_idx + 1);
	183	void __iomem *base = min(en, stat);
	184
	185	data->map_base[map_idx + 0] = en;
	186	data->map_base[map_idx + 1] = stat;
	187
	188	if (!base)
	189	break;
	190
	191	data->pair_base[gc_idx] = base;
	192	data->en_offset[gc_idx] = en - base;
	193	data->stat_offset[gc_idx] = stat - base;
	194	}
	195
	196	if (!gc_idx) {
	197	pr_err("unable to map registers\n");
	198	return -EINVAL;
	199	}
	200
	201	data->n_words = gc_idx;
	202	return 0;
	203	}
	204
ca40f1b2 KC	205	int __init bcm7120_l2_intc_probe(struct device_node *dn,
	206	struct device_node *parent,
	207	int (iomap_regs_fn)(struct device_node ,
	208	struct bcm7120_l2_intc_data *),
	209	const char *intc_name)
a5042de2 FF	210	{
	211	unsigned int clr = IRQ_NOREQUEST \| IRQ_NOPROBE \| IRQ_NOAUTOEN;
	212	struct bcm7120_l2_intc_data *data;
	213	struct irq_chip_generic *gc;
	214	struct irq_chip_type *ct;
ca40f1b2	215	int ret = 0;
c17261fa	216	unsigned int idx, irq, flags;
a5042de2 FF	217
	218	data = kzalloc(sizeof(*data), GFP_KERNEL);
	219	if (!data)
	220	return -ENOMEM;
	221
ca40f1b2 KC	222	data->num_parent_irqs = of_irq_count(dn);
ca40f1b2 KC	223	if (data->num_parent_irqs <= 0) {
a5042de2 FF	224	pr_err("invalid number of parent interrupts\n");
	225	ret = -ENOMEM;
	226	goto out_unmap;
	227	}
	228
ca40f1b2 KC	229	ret = iomap_regs_fn(dn, data);
ca40f1b2 KC	230	if (ret < 0)
a5042de2	231	goto out_unmap;
ca40f1b2 KC	232
	233	for (idx = 0; idx < data->n_words; idx++) {
	234	__raw_writel(data->irq_fwd_mask[idx],
	235	data->pair_base[idx] +
	236	data->en_offset[idx]);
a5042de2 FF	237	}
a5042de2 FF	238
ca40f1b2 KC	239	for (irq = 0; irq < data->num_parent_irqs; irq++) {
ca40f1b2 KC	240	ret = bcm7120_l2_intc_init_one(dn, data, irq);
a5042de2 FF	241	if (ret)
	242	goto out_unmap;
	243	}
	244
c76acf4d KC	245	data->domain = irq_domain_add_linear(dn, IRQS_PER_WORD * data->n_words,
c76acf4d KC	246	&irq_generic_chip_ops, NULL);
a5042de2 FF	247	if (!data->domain) {
	248	ret = -ENOMEM;
	249	goto out_unmap;
	250	}
	251
c17261fa KC	252	/* MIPS chips strapped for BE will automagically configure the
	253	* peripheral registers for CPU-native byte order.
	254	*/
	255	flags = IRQ_GC_INIT_MASK_CACHE;
	256	if (IS_ENABLED(CONFIG_MIPS) && IS_ENABLED(CONFIG_CPU_BIG_ENDIAN))
	257	flags \|= IRQ_GC_BE_IO;
	258
c76acf4d	259	ret = irq_alloc_domain_generic_chips(data->domain, IRQS_PER_WORD, 1,
c17261fa	260	dn->full_name, handle_level_irq, clr, 0, flags);
a5042de2 FF	261	if (ret) {
	262	pr_err("failed to allocate generic irq chip\n");
	263	goto out_free_domain;
	264	}
	265
c76acf4d	266	if (of_property_read_bool(dn, "brcm,irq-can-wake"))
a5042de2	267	data->can_wake = true;
c76acf4d KC	268
	269	for (idx = 0; idx < data->n_words; idx++) {
	270	irq = idx * IRQS_PER_WORD;
	271	gc = irq_get_domain_generic_chip(data->domain, irq);
	272
	273	gc->unused = 0xffffffff & ~data->irq_map_mask[idx];
c76acf4d KC	274	gc->private = data;
	275	ct = gc->chip_types;
	276
5b5468cf KC	277	gc->reg_base = data->pair_base[idx];
	278	ct->regs.mask = data->en_offset[idx];
	279
c76acf4d KC	280	ct->chip.irq_mask = irq_gc_mask_clr_bit;
	281	ct->chip.irq_unmask = irq_gc_mask_set_bit;
	282	ct->chip.irq_ack = irq_gc_noop;
	283	ct->chip.irq_suspend = bcm7120_l2_intc_suspend;
	284	ct->chip.irq_resume = bcm7120_l2_intc_resume;
	285
	286	if (data->can_wake) {
	287	/* This IRQ chip can wake the system, set all
	288	* relevant child interupts in wake_enabled mask
	289	*/
	290	gc->wake_enabled = 0xffffffff;
	291	gc->wake_enabled &= ~gc->unused;
	292	ct->chip.irq_set_wake = irq_gc_set_wake;
	293	}
a5042de2 FF	294	}
a5042de2 FF	295
ca40f1b2 KC	296	pr_info("registered %s intc (mem: 0x%p, parent IRQ(s): %d)\n",
ca40f1b2 KC	297	intc_name, data->map_base[0], data->num_parent_irqs);
a5042de2 FF	298
	299	return 0;
	300
	301	out_free_domain:
	302	irq_domain_remove(data->domain);
	303	out_unmap:
5b5468cf KC	304	for (idx = 0; idx < MAX_MAPPINGS; idx++) {
	305	if (data->map_base[idx])
	306	iounmap(data->map_base[idx]);
c76acf4d	307	}
a5042de2 FF	308	kfree(data);
	309	return ret;
	310	}
ca40f1b2 KC	311
	312	int __init bcm7120_l2_intc_probe_7120(struct device_node *dn,
	313	struct device_node *parent)
	314	{
	315	return bcm7120_l2_intc_probe(dn, parent, bcm7120_l2_intc_iomap_7120,
	316	"BCM7120 L2");
	317	}
	318
7b7230e7 KC	319	int __init bcm7120_l2_intc_probe_3380(struct device_node *dn,
	320	struct device_node *parent)
	321	{
	322	return bcm7120_l2_intc_probe(dn, parent, bcm7120_l2_intc_iomap_3380,
	323	"BCM3380 L2");
	324	}
	325
a4fcbb86	326	IRQCHIP_DECLARE(bcm7120_l2_intc, "brcm,bcm7120-l2-intc",
ca40f1b2	327	bcm7120_l2_intc_probe_7120);
7b7230e7 KC	328
	329	IRQCHIP_DECLARE(bcm3380_l2_intc, "brcm,bcm3380-l2-intc",
	330	bcm7120_l2_intc_probe_3380);