[mirror_ubuntu-zesty-kernel.git] / drivers / irqchip / irq-bcm7120-l2.c

/*
 * Broadcom BCM7120 style Level 2 interrupt controller driver
 *
 * Copyright (C) 2014 Broadcom Corporation
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

#define pr_fmt(fmt)	KBUILD_MODNAME	": " fmt

#include <linux/init.h>
#include <linux/slab.h>
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/platform_device.h>
#include <linux/of.h>
#include <linux/of_irq.h>
#include <linux/of_address.h>
#include <linux/of_platform.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/io.h>
#include <linux/irqdomain.h>
#include <linux/reboot.h>
#include <linux/bitops.h>
#include <linux/irqchip.h>
#include <linux/irqchip/chained_irq.h>

/* Register offset in the L2 interrupt controller */
#define IRQEN		0x00
#define IRQSTAT		0x04

#define MAX_WORDS	4
#define MAX_MAPPINGS	(MAX_WORDS * 2)
#define IRQS_PER_WORD	32

struct bcm7120_l1_intc_data {
	struct bcm7120_l2_intc_data *b;
	u32 irq_map_mask[MAX_WORDS];
};

struct bcm7120_l2_intc_data {
	unsigned int n_words;
	void __iomem *map_base[MAX_MAPPINGS];
	void __iomem *pair_base[MAX_WORDS];
	int en_offset[MAX_WORDS];
	int stat_offset[MAX_WORDS];
	struct irq_domain *domain;
	bool can_wake;
	u32 irq_fwd_mask[MAX_WORDS];
	struct bcm7120_l1_intc_data *l1_data;
	int num_parent_irqs;
	const __be32 *map_mask_prop;
};

static void bcm7120_l2_intc_irq_handle(struct irq_desc *desc)
{
	struct bcm7120_l1_intc_data *data = irq_desc_get_handler_data(desc);
	struct bcm7120_l2_intc_data *b = data->b;
	struct irq_chip *chip = irq_desc_get_chip(desc);
	unsigned int idx;

	chained_irq_enter(chip, desc);

	for (idx = 0; idx < b->n_words; idx++) {
		int base = idx * IRQS_PER_WORD;
		struct irq_chip_generic *gc =
			irq_get_domain_generic_chip(b->domain, base);
		unsigned long pending;
		int hwirq;

		irq_gc_lock(gc);
		pending = irq_reg_readl(gc, b->stat_offset[idx]) &
					    gc->mask_cache &
					    data->irq_map_mask[idx];
		irq_gc_unlock(gc);

		for_each_set_bit(hwirq, &pending, IRQS_PER_WORD) {
			generic_handle_irq(irq_find_mapping(b->domain,
					   base + hwirq));
		}
	}

	chained_irq_exit(chip, desc);
}

static void bcm7120_l2_intc_suspend(struct irq_chip_generic *gc)
{
	struct bcm7120_l2_intc_data *b = gc->private;
	struct irq_chip_type *ct = gc->chip_types;

	irq_gc_lock(gc);
	if (b->can_wake)
		irq_reg_writel(gc, gc->mask_cache | gc->wake_active,
			       ct->regs.mask);
	irq_gc_unlock(gc);
}

static void bcm7120_l2_intc_resume(struct irq_chip_generic *gc)
{
	struct irq_chip_type *ct = gc->chip_types;

	/* Restore the saved mask */
	irq_gc_lock(gc);
	irq_reg_writel(gc, gc->mask_cache, ct->regs.mask);
	irq_gc_unlock(gc);
}

static int bcm7120_l2_intc_init_one(struct device_node *dn,
					struct bcm7120_l2_intc_data *data,
					int irq, u32 *valid_mask)
{
	struct bcm7120_l1_intc_data *l1_data = &data->l1_data[irq];
	int parent_irq;
	unsigned int idx;

	parent_irq = irq_of_parse_and_map(dn, irq);
	if (!parent_irq) {
		pr_err("failed to map interrupt %d\n", irq);
		return -EINVAL;
	}

	/* For multiple parent IRQs with multiple words, this looks like:
	 * <irq0_w0 irq0_w1 irq1_w0 irq1_w1 ...>
	 *
	 * We need to associate a given parent interrupt with its corresponding
	 * map_mask in order to mask the status register with it because we
	 * have the same handler being called for multiple parent interrupts.
	 *
	 * This is typically something needed on BCM7xxx (STB chips).
	 */
	for (idx = 0; idx < data->n_words; idx++) {
		if (data->map_mask_prop) {
			l1_data->irq_map_mask[idx] |=
				be32_to_cpup(data->map_mask_prop +
					     irq * data->n_words + idx);
		} else {
			l1_data->irq_map_mask[idx] = 0xffffffff;
		}
		valid_mask[idx] |= l1_data->irq_map_mask[idx];
	}

	l1_data->b = data;

	irq_set_chained_handler_and_data(parent_irq,
					 bcm7120_l2_intc_irq_handle, l1_data);
	return 0;
}

static int __init bcm7120_l2_intc_iomap_7120(struct device_node *dn,
					     struct bcm7120_l2_intc_data *data)
{
	int ret;

	data->map_base[0] = of_iomap(dn, 0);
	if (!data->map_base[0]) {
		pr_err("unable to map registers\n");
		return -ENOMEM;
	}

	data->pair_base[0] = data->map_base[0];
	data->en_offset[0] = IRQEN;
	data->stat_offset[0] = IRQSTAT;
	data->n_words = 1;

	ret = of_property_read_u32_array(dn, "brcm,int-fwd-mask",
					 data->irq_fwd_mask, data->n_words);
	if (ret != 0 && ret != -EINVAL) {
		/* property exists but has the wrong number of words */
		pr_err("invalid brcm,int-fwd-mask property\n");
		return -EINVAL;
	}

	data->map_mask_prop = of_get_property(dn, "brcm,int-map-mask", &ret);
	if (!data->map_mask_prop ||
	    (ret != (sizeof(__be32) * data->num_parent_irqs * data->n_words))) {
		pr_err("invalid brcm,int-map-mask property\n");
		return -EINVAL;
	}

	return 0;
}

static int __init bcm7120_l2_intc_iomap_3380(struct device_node *dn,
					     struct bcm7120_l2_intc_data *data)
{
	unsigned int gc_idx;

	for (gc_idx = 0; gc_idx < MAX_WORDS; gc_idx++) {
		unsigned int map_idx = gc_idx * 2;
		void __iomem *en = of_iomap(dn, map_idx + 0);
		void __iomem *stat = of_iomap(dn, map_idx + 1);
		void __iomem *base = min(en, stat);

		data->map_base[map_idx + 0] = en;
		data->map_base[map_idx + 1] = stat;

		if (!base)
			break;

		data->pair_base[gc_idx] = base;
		data->en_offset[gc_idx] = en - base;
		data->stat_offset[gc_idx] = stat - base;
	}

	if (!gc_idx) {
		pr_err("unable to map registers\n");
		return -EINVAL;
	}

	data->n_words = gc_idx;
	return 0;
}

static int __init bcm7120_l2_intc_probe(struct device_node *dn,
				 struct device_node *parent,
				 int (*iomap_regs_fn)(struct device_node *,
					struct bcm7120_l2_intc_data *),
				 const char *intc_name)
{
	unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN;
	struct bcm7120_l2_intc_data *data;
	struct irq_chip_generic *gc;
	struct irq_chip_type *ct;
	int ret = 0;
	unsigned int idx, irq, flags;
	u32 valid_mask[MAX_WORDS] = { };

	data = kzalloc(sizeof(*data), GFP_KERNEL);
	if (!data)
		return -ENOMEM;

	data->num_parent_irqs = of_irq_count(dn);
	if (data->num_parent_irqs <= 0) {
		pr_err("invalid number of parent interrupts\n");
		ret = -ENOMEM;
		goto out_unmap;
	}

	data->l1_data = kcalloc(data->num_parent_irqs, sizeof(*data->l1_data),
				GFP_KERNEL);
	if (!data->l1_data) {
		ret = -ENOMEM;
		goto out_free_l1_data;
	}

	ret = iomap_regs_fn(dn, data);
	if (ret < 0)
		goto out_free_l1_data;

	for (idx = 0; idx < data->n_words; idx++) {
		__raw_writel(data->irq_fwd_mask[idx],
			     data->pair_base[idx] +
			     data->en_offset[idx]);
	}

	for (irq = 0; irq < data->num_parent_irqs; irq++) {
		ret = bcm7120_l2_intc_init_one(dn, data, irq, valid_mask);
		if (ret)
			goto out_free_l1_data;
	}

	data->domain = irq_domain_add_linear(dn, IRQS_PER_WORD * data->n_words,
					     &irq_generic_chip_ops, NULL);
	if (!data->domain) {
		ret = -ENOMEM;
		goto out_free_l1_data;
	}

	/* MIPS chips strapped for BE will automagically configure the
	 * peripheral registers for CPU-native byte order.
	 */
	flags = IRQ_GC_INIT_MASK_CACHE;
	if (IS_ENABLED(CONFIG_MIPS) && IS_ENABLED(CONFIG_CPU_BIG_ENDIAN))
		flags |= IRQ_GC_BE_IO;

	ret = irq_alloc_domain_generic_chips(data->domain, IRQS_PER_WORD, 1,
				dn->full_name, handle_level_irq, clr, 0, flags);
	if (ret) {
		pr_err("failed to allocate generic irq chip\n");
		goto out_free_domain;
	}

	if (of_property_read_bool(dn, "brcm,irq-can-wake"))
		data->can_wake = true;

	for (idx = 0; idx < data->n_words; idx++) {
		irq = idx * IRQS_PER_WORD;
		gc = irq_get_domain_generic_chip(data->domain, irq);

		gc->unused = 0xffffffff & ~valid_mask[idx];
		gc->private = data;
		ct = gc->chip_types;

		gc->reg_base = data->pair_base[idx];
		ct->regs.mask = data->en_offset[idx];

		ct->chip.irq_mask = irq_gc_mask_clr_bit;
		ct->chip.irq_unmask = irq_gc_mask_set_bit;
		ct->chip.irq_ack = irq_gc_noop;
		gc->suspend = bcm7120_l2_intc_suspend;
		gc->resume = bcm7120_l2_intc_resume;

		/*
		 * Initialize mask-cache, in case we need it for
		 * saving/restoring fwd mask even w/o any child interrupts
		 * installed
		 */
		gc->mask_cache = irq_reg_readl(gc, ct->regs.mask);

		if (data->can_wake) {
			/* This IRQ chip can wake the system, set all
			 * relevant child interupts in wake_enabled mask
			 */
			gc->wake_enabled = 0xffffffff;
			gc->wake_enabled &= ~gc->unused;
			ct->chip.irq_set_wake = irq_gc_set_wake;
		}
	}

	pr_info("registered %s intc (mem: 0x%p, parent IRQ(s): %d)\n",
			intc_name, data->map_base[0], data->num_parent_irqs);

	return 0;

out_free_domain:
	irq_domain_remove(data->domain);
out_free_l1_data:
	kfree(data->l1_data);
out_unmap:
	for (idx = 0; idx < MAX_MAPPINGS; idx++) {
		if (data->map_base[idx])
			iounmap(data->map_base[idx]);
	}
	kfree(data);
	return ret;
}

static int __init bcm7120_l2_intc_probe_7120(struct device_node *dn,
					     struct device_node *parent)
{
	return bcm7120_l2_intc_probe(dn, parent, bcm7120_l2_intc_iomap_7120,
				     "BCM7120 L2");
}

static int __init bcm7120_l2_intc_probe_3380(struct device_node *dn,
					     struct device_node *parent)
{
	return bcm7120_l2_intc_probe(dn, parent, bcm7120_l2_intc_iomap_3380,
				     "BCM3380 L2");
}

IRQCHIP_DECLARE(bcm7120_l2_intc, "brcm,bcm7120-l2-intc",
		bcm7120_l2_intc_probe_7120);

IRQCHIP_DECLARE(bcm3380_l2_intc, "brcm,bcm3380-l2-intc",
		bcm7120_l2_intc_probe_3380);
Commit	Line	Data
a5042de2 FF	1	/*
	2	* Broadcom BCM7120 style Level 2 interrupt controller driver
	3	*
	4	* Copyright (C) 2014 Broadcom Corporation
	5	*
	6	* This program is free software; you can redistribute it and/or modify
	7	* it under the terms of the GNU General Public License version 2 as
	8	* published by the Free Software Foundation.
	9	*/
	10
	11	#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
	12
	13	#include <linux/init.h>
	14	#include <linux/slab.h>
	15	#include <linux/module.h>
7b7230e7	16	#include <linux/kernel.h>
a5042de2 FF	17	#include <linux/platform_device.h>
	18	#include <linux/of.h>
	19	#include <linux/of_irq.h>
	20	#include <linux/of_address.h>
	21	#include <linux/of_platform.h>
	22	#include <linux/interrupt.h>
	23	#include <linux/irq.h>
	24	#include <linux/io.h>
	25	#include <linux/irqdomain.h>
	26	#include <linux/reboot.h>
c76acf4d	27	#include <linux/bitops.h>
41a83e06	28	#include <linux/irqchip.h>
a5042de2 FF	29	#include <linux/irqchip/chained_irq.h>
a5042de2 FF	30
a5042de2 FF	31	/* Register offset in the L2 interrupt controller */
	32	#define IRQEN 0x00
	33	#define IRQSTAT 0x04
	34
c76acf4d	35	#define MAX_WORDS 4
ca40f1b2	36	#define MAX_MAPPINGS (MAX_WORDS * 2)
c76acf4d KC	37	#define IRQS_PER_WORD 32
c76acf4d KC	38
0aef3997 FF	39	struct bcm7120_l1_intc_data {
	40	struct bcm7120_l2_intc_data *b;
	41	u32 irq_map_mask[MAX_WORDS];
	42	};
	43
a5042de2	44	struct bcm7120_l2_intc_data {
c76acf4d	45	unsigned int n_words;
5b5468cf KC	46	void __iomem *map_base[MAX_MAPPINGS];
	47	void __iomem *pair_base[MAX_WORDS];
	48	int en_offset[MAX_WORDS];
	49	int stat_offset[MAX_WORDS];
a5042de2 FF	50	struct irq_domain *domain;
a5042de2 FF	51	bool can_wake;
c76acf4d	52	u32 irq_fwd_mask[MAX_WORDS];
0aef3997	53	struct bcm7120_l1_intc_data *l1_data;
ca40f1b2 KC	54	int num_parent_irqs;
ca40f1b2 KC	55	const __be32 *map_mask_prop;
a5042de2 FF	56	};
a5042de2 FF	57
bd0b9ac4	58	static void bcm7120_l2_intc_irq_handle(struct irq_desc *desc)
a5042de2	59	{
0aef3997 FF	60	struct bcm7120_l1_intc_data *data = irq_desc_get_handler_data(desc);
0aef3997 FF	61	struct bcm7120_l2_intc_data *b = data->b;
a5042de2	62	struct irq_chip *chip = irq_desc_get_chip(desc);
c76acf4d	63	unsigned int idx;
a5042de2 FF	64
	65	chained_irq_enter(chip, desc);
	66
c76acf4d KC	67	for (idx = 0; idx < b->n_words; idx++) {
	68	int base = idx * IRQS_PER_WORD;
	69	struct irq_chip_generic *gc =
	70	irq_get_domain_generic_chip(b->domain, base);
	71	unsigned long pending;
	72	int hwirq;
	73
	74	irq_gc_lock(gc);
5b5468cf	75	pending = irq_reg_readl(gc, b->stat_offset[idx]) &
0aef3997 FF	76	gc->mask_cache &
0aef3997 FF	77	data->irq_map_mask[idx];
c76acf4d KC	78	irq_gc_unlock(gc);
	79
	80	for_each_set_bit(hwirq, &pending, IRQS_PER_WORD) {
	81	generic_handle_irq(irq_find_mapping(b->domain,
	82	base + hwirq));
	83	}
a5042de2 FF	84	}
a5042de2 FF	85
a5042de2 FF	86	chained_irq_exit(chip, desc);
	87	}
	88
fd537766	89	static void bcm7120_l2_intc_suspend(struct irq_chip_generic *gc)
a5042de2	90	{
a5042de2	91	struct bcm7120_l2_intc_data *b = gc->private;
fd537766	92	struct irq_chip_type *ct = gc->chip_types;
a5042de2 FF	93
a5042de2 FF	94	irq_gc_lock(gc);
c17261fa	95	if (b->can_wake)
5b5468cf KC	96	irq_reg_writel(gc, gc->mask_cache \| gc->wake_active,
5b5468cf KC	97	ct->regs.mask);
a5042de2 FF	98	irq_gc_unlock(gc);
	99	}
	100
fd537766	101	static void bcm7120_l2_intc_resume(struct irq_chip_generic *gc)
a5042de2	102	{
fd537766	103	struct irq_chip_type *ct = gc->chip_types;
a5042de2 FF	104
	105	/* Restore the saved mask */
	106	irq_gc_lock(gc);
5b5468cf	107	irq_reg_writel(gc, gc->mask_cache, ct->regs.mask);
a5042de2 FF	108	irq_gc_unlock(gc);
	109	}
	110
	111	static int bcm7120_l2_intc_init_one(struct device_node *dn,
	112	struct bcm7120_l2_intc_data *data,
0aef3997	113	int irq, u32 *valid_mask)
a5042de2	114	{
0aef3997	115	struct bcm7120_l1_intc_data *l1_data = &data->l1_data[irq];
a5042de2	116	int parent_irq;
c76acf4d	117	unsigned int idx;
a5042de2 FF	118
a5042de2 FF	119	parent_irq = irq_of_parse_and_map(dn, irq);
714710e1	120	if (!parent_irq) {
a5042de2	121	pr_err("failed to map interrupt %d\n", irq);
714710e1	122	return -EINVAL;
a5042de2 FF	123	}
a5042de2 FF	124
c76acf4d KC	125	/* For multiple parent IRQs with multiple words, this looks like:
c76acf4d KC	126	* <irq0_w0 irq0_w1 irq1_w0 irq1_w1 ...>
0aef3997 FF	127	*
	128	* We need to associate a given parent interrupt with its corresponding
	129	* map_mask in order to mask the status register with it because we
	130	* have the same handler being called for multiple parent interrupts.
	131	*
	132	* This is typically something needed on BCM7xxx (STB chips).
c76acf4d	133	*/
7b7230e7 KC	134	for (idx = 0; idx < data->n_words; idx++) {
7b7230e7 KC	135	if (data->map_mask_prop) {
0aef3997	136	l1_data->irq_map_mask[idx] \|=
7b7230e7 KC	137	be32_to_cpup(data->map_mask_prop +
	138	irq * data->n_words + idx);
	139	} else {
0aef3997	140	l1_data->irq_map_mask[idx] = 0xffffffff;
7b7230e7	141	}
0aef3997	142	valid_mask[idx] \|= l1_data->irq_map_mask[idx];
7b7230e7	143	}
a5042de2	144
0aef3997	145	l1_data->b = data;
a5042de2	146
0aef3997 FF	147	irq_set_chained_handler_and_data(parent_irq,
0aef3997 FF	148	bcm7120_l2_intc_irq_handle, l1_data);
a5042de2 FF	149	return 0;
	150	}
	151
ca40f1b2 KC	152	static int __init bcm7120_l2_intc_iomap_7120(struct device_node *dn,
	153	struct bcm7120_l2_intc_data *data)
	154	{
	155	int ret;
	156
	157	data->map_base[0] = of_iomap(dn, 0);
	158	if (!data->map_base[0]) {
	159	pr_err("unable to map registers\n");
	160	return -ENOMEM;
	161	}
	162
	163	data->pair_base[0] = data->map_base[0];
	164	data->en_offset[0] = IRQEN;
	165	data->stat_offset[0] = IRQSTAT;
	166	data->n_words = 1;
	167
	168	ret = of_property_read_u32_array(dn, "brcm,int-fwd-mask",
	169	data->irq_fwd_mask, data->n_words);
	170	if (ret != 0 && ret != -EINVAL) {
	171	/* property exists but has the wrong number of words */
	172	pr_err("invalid brcm,int-fwd-mask property\n");
	173	return -EINVAL;
	174	}
	175
	176	data->map_mask_prop = of_get_property(dn, "brcm,int-map-mask", &ret);
	177	if (!data->map_mask_prop \|\|
	178	(ret != (sizeof(__be32) * data->num_parent_irqs * data->n_words))) {
	179	pr_err("invalid brcm,int-map-mask property\n");
	180	return -EINVAL;
	181	}
	182
	183	return 0;
	184	}
	185
7b7230e7 KC	186	static int __init bcm7120_l2_intc_iomap_3380(struct device_node *dn,
	187	struct bcm7120_l2_intc_data *data)
	188	{
	189	unsigned int gc_idx;
	190
	191	for (gc_idx = 0; gc_idx < MAX_WORDS; gc_idx++) {
	192	unsigned int map_idx = gc_idx * 2;
	193	void __iomem *en = of_iomap(dn, map_idx + 0);
	194	void __iomem *stat = of_iomap(dn, map_idx + 1);
	195	void __iomem *base = min(en, stat);
	196
	197	data->map_base[map_idx + 0] = en;
	198	data->map_base[map_idx + 1] = stat;
	199
	200	if (!base)
	201	break;
	202
	203	data->pair_base[gc_idx] = base;
	204	data->en_offset[gc_idx] = en - base;
	205	data->stat_offset[gc_idx] = stat - base;
	206	}
	207
	208	if (!gc_idx) {
	209	pr_err("unable to map registers\n");
	210	return -EINVAL;
	211	}
	212
	213	data->n_words = gc_idx;
	214	return 0;
	215	}
	216
dde7e6d1	217	static int __init bcm7120_l2_intc_probe(struct device_node *dn,
ca40f1b2 KC	218	struct device_node *parent,
	219	int (iomap_regs_fn)(struct device_node ,
	220	struct bcm7120_l2_intc_data *),
	221	const char *intc_name)
a5042de2 FF	222	{
	223	unsigned int clr = IRQ_NOREQUEST \| IRQ_NOPROBE \| IRQ_NOAUTOEN;
	224	struct bcm7120_l2_intc_data *data;
	225	struct irq_chip_generic *gc;
	226	struct irq_chip_type *ct;
ca40f1b2	227	int ret = 0;
c17261fa	228	unsigned int idx, irq, flags;
0aef3997	229	u32 valid_mask[MAX_WORDS] = { };
a5042de2 FF	230
	231	data = kzalloc(sizeof(*data), GFP_KERNEL);
	232	if (!data)
	233	return -ENOMEM;
	234
ca40f1b2 KC	235	data->num_parent_irqs = of_irq_count(dn);
ca40f1b2 KC	236	if (data->num_parent_irqs <= 0) {
a5042de2 FF	237	pr_err("invalid number of parent interrupts\n");
	238	ret = -ENOMEM;
	239	goto out_unmap;
	240	}
	241
0aef3997 FF	242	data->l1_data = kcalloc(data->num_parent_irqs, sizeof(*data->l1_data),
	243	GFP_KERNEL);
	244	if (!data->l1_data) {
	245	ret = -ENOMEM;
	246	goto out_free_l1_data;
	247	}
	248
ca40f1b2 KC	249	ret = iomap_regs_fn(dn, data);
ca40f1b2 KC	250	if (ret < 0)
0aef3997	251	goto out_free_l1_data;
ca40f1b2 KC	252
	253	for (idx = 0; idx < data->n_words; idx++) {
	254	__raw_writel(data->irq_fwd_mask[idx],
	255	data->pair_base[idx] +
	256	data->en_offset[idx]);
a5042de2 FF	257	}
a5042de2 FF	258
ca40f1b2	259	for (irq = 0; irq < data->num_parent_irqs; irq++) {
0aef3997	260	ret = bcm7120_l2_intc_init_one(dn, data, irq, valid_mask);
a5042de2	261	if (ret)
0aef3997	262	goto out_free_l1_data;
a5042de2 FF	263	}
a5042de2 FF	264
c76acf4d KC	265	data->domain = irq_domain_add_linear(dn, IRQS_PER_WORD * data->n_words,
c76acf4d KC	266	&irq_generic_chip_ops, NULL);
a5042de2 FF	267	if (!data->domain) {
a5042de2 FF	268	ret = -ENOMEM;
0aef3997	269	goto out_free_l1_data;
a5042de2 FF	270	}
a5042de2 FF	271
c17261fa KC	272	/* MIPS chips strapped for BE will automagically configure the
	273	* peripheral registers for CPU-native byte order.
	274	*/
	275	flags = IRQ_GC_INIT_MASK_CACHE;
	276	if (IS_ENABLED(CONFIG_MIPS) && IS_ENABLED(CONFIG_CPU_BIG_ENDIAN))
	277	flags \|= IRQ_GC_BE_IO;
	278
c76acf4d	279	ret = irq_alloc_domain_generic_chips(data->domain, IRQS_PER_WORD, 1,
c17261fa	280	dn->full_name, handle_level_irq, clr, 0, flags);
a5042de2 FF	281	if (ret) {
	282	pr_err("failed to allocate generic irq chip\n");
	283	goto out_free_domain;
	284	}
	285
c76acf4d	286	if (of_property_read_bool(dn, "brcm,irq-can-wake"))
a5042de2	287	data->can_wake = true;
c76acf4d KC	288
	289	for (idx = 0; idx < data->n_words; idx++) {
	290	irq = idx * IRQS_PER_WORD;
	291	gc = irq_get_domain_generic_chip(data->domain, irq);
	292
0aef3997	293	gc->unused = 0xffffffff & ~valid_mask[idx];
c76acf4d KC	294	gc->private = data;
	295	ct = gc->chip_types;
	296
5b5468cf KC	297	gc->reg_base = data->pair_base[idx];
	298	ct->regs.mask = data->en_offset[idx];
	299
c76acf4d KC	300	ct->chip.irq_mask = irq_gc_mask_clr_bit;
	301	ct->chip.irq_unmask = irq_gc_mask_set_bit;
	302	ct->chip.irq_ack = irq_gc_noop;
fd537766 BN	303	gc->suspend = bcm7120_l2_intc_suspend;
	304	gc->resume = bcm7120_l2_intc_resume;
	305
	306	/*
	307	* Initialize mask-cache, in case we need it for
	308	* saving/restoring fwd mask even w/o any child interrupts
	309	* installed
	310	*/
	311	gc->mask_cache = irq_reg_readl(gc, ct->regs.mask);
c76acf4d KC	312
	313	if (data->can_wake) {
	314	/* This IRQ chip can wake the system, set all
	315	* relevant child interupts in wake_enabled mask
	316	*/
	317	gc->wake_enabled = 0xffffffff;
	318	gc->wake_enabled &= ~gc->unused;
	319	ct->chip.irq_set_wake = irq_gc_set_wake;
	320	}
a5042de2 FF	321	}
a5042de2 FF	322
ca40f1b2 KC	323	pr_info("registered %s intc (mem: 0x%p, parent IRQ(s): %d)\n",
ca40f1b2 KC	324	intc_name, data->map_base[0], data->num_parent_irqs);
a5042de2 FF	325
	326	return 0;
	327
	328	out_free_domain:
	329	irq_domain_remove(data->domain);
0aef3997 FF	330	out_free_l1_data:
0aef3997 FF	331	kfree(data->l1_data);
a5042de2	332	out_unmap:
5b5468cf KC	333	for (idx = 0; idx < MAX_MAPPINGS; idx++) {
	334	if (data->map_base[idx])
	335	iounmap(data->map_base[idx]);
c76acf4d	336	}
a5042de2 FF	337	kfree(data);
	338	return ret;
	339	}
ca40f1b2	340
dde7e6d1 BD	341	static int __init bcm7120_l2_intc_probe_7120(struct device_node *dn,
dde7e6d1 BD	342	struct device_node *parent)
ca40f1b2 KC	343	{
	344	return bcm7120_l2_intc_probe(dn, parent, bcm7120_l2_intc_iomap_7120,
	345	"BCM7120 L2");
	346	}
	347
dde7e6d1 BD	348	static int __init bcm7120_l2_intc_probe_3380(struct device_node *dn,
dde7e6d1 BD	349	struct device_node *parent)
7b7230e7 KC	350	{
	351	return bcm7120_l2_intc_probe(dn, parent, bcm7120_l2_intc_iomap_3380,
	352	"BCM3380 L2");
	353	}
	354
a4fcbb86	355	IRQCHIP_DECLARE(bcm7120_l2_intc, "brcm,bcm7120-l2-intc",
ca40f1b2	356	bcm7120_l2_intc_probe_7120);
7b7230e7 KC	357
	358	IRQCHIP_DECLARE(bcm3380_l2_intc, "brcm,bcm3380-l2-intc",
	359	bcm7120_l2_intc_probe_3380);