[mirror_ubuntu-jammy-kernel.git] / drivers / irqchip / irq-brcmstb-l2.c

/*
 * Generic Broadcom Set Top Box Level 2 Interrupt controller driver
 *
 * Copyright (C) 2014-2017 Broadcom
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
 * GNU General Public License for more details.
 */

#define pr_fmt(fmt)	KBUILD_MODNAME	": " fmt

#include <linux/init.h>
#include <linux/slab.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/spinlock.h>
#include <linux/of.h>
#include <linux/of_irq.h>
#include <linux/of_address.h>
#include <linux/of_platform.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/io.h>
#include <linux/irqdomain.h>
#include <linux/irqchip.h>
#include <linux/irqchip/chained_irq.h>

struct brcmstb_intc_init_params {
	irq_flow_handler_t handler;
	int cpu_status;
	int cpu_clear;
	int cpu_mask_status;
	int cpu_mask_set;
	int cpu_mask_clear;
};

/* Register offsets in the L2 latched interrupt controller */
static const struct brcmstb_intc_init_params l2_edge_intc_init = {
	.handler		= handle_edge_irq,
	.cpu_status		= 0x00,
	.cpu_clear		= 0x08,
	.cpu_mask_status	= 0x0c,
	.cpu_mask_set		= 0x10,
	.cpu_mask_clear		= 0x14
};

/* Register offsets in the L2 level interrupt controller */
static const struct brcmstb_intc_init_params l2_lvl_intc_init = {
	.handler		= handle_level_irq,
	.cpu_status		= 0x00,
	.cpu_clear		= -1, /* Register not present */
	.cpu_mask_status	= 0x04,
	.cpu_mask_set		= 0x08,
	.cpu_mask_clear		= 0x0C
};

/* L2 intc private data structure */
struct brcmstb_l2_intc_data {
	struct irq_domain *domain;
	struct irq_chip_generic *gc;
	int status_offset;
	int mask_offset;
	bool can_wake;
	u32 saved_mask; /* for suspend/resume */
};

/**
 * brcmstb_l2_mask_and_ack - Mask and ack pending interrupt
 * @d: irq_data
 *
 * Chip has separate enable/disable registers instead of a single mask
 * register and pending interrupt is acknowledged by setting a bit.
 *
 * Note: This function is generic and could easily be added to the
 * generic irqchip implementation if there ever becomes a will to do so.
 * Perhaps with a name like irq_gc_mask_disable_and_ack_set().
 *
 * e.g.: https://patchwork.kernel.org/patch/9831047/
 */
static void brcmstb_l2_mask_and_ack(struct irq_data *d)
{
	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
	struct irq_chip_type *ct = irq_data_get_chip_type(d);
	u32 mask = d->mask;

	irq_gc_lock(gc);
	irq_reg_writel(gc, mask, ct->regs.disable);
	*ct->mask_cache &= ~mask;
	irq_reg_writel(gc, mask, ct->regs.ack);
	irq_gc_unlock(gc);
}

static void brcmstb_l2_intc_irq_handle(struct irq_desc *desc)
{
	struct brcmstb_l2_intc_data *b = irq_desc_get_handler_data(desc);
	struct irq_chip *chip = irq_desc_get_chip(desc);
	unsigned int irq;
	u32 status;

	chained_irq_enter(chip, desc);

	status = irq_reg_readl(b->gc, b->status_offset) &
		~(irq_reg_readl(b->gc, b->mask_offset));

	if (status == 0) {
		raw_spin_lock(&desc->lock);
		handle_bad_irq(desc);
		raw_spin_unlock(&desc->lock);
		goto out;
	}

	do {
		irq = ffs(status) - 1;
		status &= ~(1 << irq);
		generic_handle_irq(irq_linear_revmap(b->domain, irq));
	} while (status);
out:
	chained_irq_exit(chip, desc);
}

static void brcmstb_l2_intc_suspend(struct irq_data *d)
{
	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
	struct irq_chip_type *ct = irq_data_get_chip_type(d);
	struct brcmstb_l2_intc_data *b = gc->private;

	irq_gc_lock(gc);
	/* Save the current mask */
	b->saved_mask = irq_reg_readl(gc, ct->regs.mask);

	if (b->can_wake) {
		/* Program the wakeup mask */
		irq_reg_writel(gc, ~gc->wake_active, ct->regs.disable);
		irq_reg_writel(gc, gc->wake_active, ct->regs.enable);
	}
	irq_gc_unlock(gc);
}

static void brcmstb_l2_intc_resume(struct irq_data *d)
{
	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
	struct irq_chip_type *ct = irq_data_get_chip_type(d);
	struct brcmstb_l2_intc_data *b = gc->private;

	irq_gc_lock(gc);
	if (ct->chip.irq_ack) {
		/* Clear unmasked non-wakeup interrupts */
		irq_reg_writel(gc, ~b->saved_mask & ~gc->wake_active,
				ct->regs.ack);
	}

	/* Restore the saved mask */
	irq_reg_writel(gc, b->saved_mask, ct->regs.disable);
	irq_reg_writel(gc, ~b->saved_mask, ct->regs.enable);
	irq_gc_unlock(gc);
}

static int __init brcmstb_l2_intc_of_init(struct device_node *np,
					  struct device_node *parent,
					  const struct brcmstb_intc_init_params
					  *init_params)
{
	unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN;
	struct brcmstb_l2_intc_data *data;
	struct irq_chip_type *ct;
	int ret;
	unsigned int flags;
	int parent_irq;
	void __iomem *base;

	data = kzalloc(sizeof(*data), GFP_KERNEL);
	if (!data)
		return -ENOMEM;

	base = of_iomap(np, 0);
	if (!base) {
		pr_err("failed to remap intc L2 registers\n");
		ret = -ENOMEM;
		goto out_free;
	}

	/* Disable all interrupts by default */
	writel(0xffffffff, base + init_params->cpu_mask_set);

	/* Wakeup interrupts may be retained from S5 (cold boot) */
	data->can_wake = of_property_read_bool(np, "brcm,irq-can-wake");
	if (!data->can_wake && (init_params->cpu_clear >= 0))
		writel(0xffffffff, base + init_params->cpu_clear);

	parent_irq = irq_of_parse_and_map(np, 0);
	if (!parent_irq) {
		pr_err("failed to find parent interrupt\n");
		ret = -EINVAL;
		goto out_unmap;
	}

	data->domain = irq_domain_add_linear(np, 32,
				&irq_generic_chip_ops, NULL);
	if (!data->domain) {
		ret = -ENOMEM;
		goto out_unmap;
	}

	/* MIPS chips strapped for BE will automagically configure the
	 * peripheral registers for CPU-native byte order.
	 */
	flags = 0;
	if (IS_ENABLED(CONFIG_MIPS) && IS_ENABLED(CONFIG_CPU_BIG_ENDIAN))
		flags |= IRQ_GC_BE_IO;

	/* Allocate a single Generic IRQ chip for this node */
	ret = irq_alloc_domain_generic_chips(data->domain, 32, 1,
			np->full_name, init_params->handler, clr, 0, flags);
	if (ret) {
		pr_err("failed to allocate generic irq chip\n");
		goto out_free_domain;
	}

	/* Set the IRQ chaining logic */
	irq_set_chained_handler_and_data(parent_irq,
					 brcmstb_l2_intc_irq_handle, data);

	data->gc = irq_get_domain_generic_chip(data->domain, 0);
	data->gc->reg_base = base;
	data->gc->private = data;
	data->status_offset = init_params->cpu_status;
	data->mask_offset = init_params->cpu_mask_status;

	ct = data->gc->chip_types;

	if (init_params->cpu_clear >= 0) {
		ct->regs.ack = init_params->cpu_clear;
		ct->chip.irq_ack = irq_gc_ack_set_bit;
		ct->chip.irq_mask_ack = brcmstb_l2_mask_and_ack;
	} else {
		/* No Ack - but still slightly more efficient to define this */
		ct->chip.irq_mask_ack = irq_gc_mask_disable_reg;
	}

	ct->chip.irq_mask = irq_gc_mask_disable_reg;
	ct->regs.disable = init_params->cpu_mask_set;
	ct->regs.mask = init_params->cpu_mask_status;

	ct->chip.irq_unmask = irq_gc_unmask_enable_reg;
	ct->regs.enable = init_params->cpu_mask_clear;

	ct->chip.irq_suspend = brcmstb_l2_intc_suspend;
	ct->chip.irq_resume = brcmstb_l2_intc_resume;
	ct->chip.irq_pm_shutdown = brcmstb_l2_intc_suspend;

	if (data->can_wake) {
		/* This IRQ chip can wake the system, set all child interrupts
		 * in wake_enabled mask
		 */
		data->gc->wake_enabled = 0xffffffff;
		ct->chip.irq_set_wake = irq_gc_set_wake;
	}

	return 0;

out_free_domain:
	irq_domain_remove(data->domain);
out_unmap:
	iounmap(base);
out_free:
	kfree(data);
	return ret;
}

int __init brcmstb_l2_edge_intc_of_init(struct device_node *np,
	struct device_node *parent)
{
	return brcmstb_l2_intc_of_init(np, parent, &l2_edge_intc_init);
}
IRQCHIP_DECLARE(brcmstb_l2_intc, "brcm,l2-intc", brcmstb_l2_edge_intc_of_init);

int __init brcmstb_l2_lvl_intc_of_init(struct device_node *np,
	struct device_node *parent)
{
	return brcmstb_l2_intc_of_init(np, parent, &l2_lvl_intc_init);
}
IRQCHIP_DECLARE(bcm7271_l2_intc, "brcm,bcm7271-l2-intc",
	brcmstb_l2_lvl_intc_of_init);
Commit	Line	Data
7f646e92 FF	1	/*
	2	* Generic Broadcom Set Top Box Level 2 Interrupt controller driver
	3	*
49aa6ef0	4	* Copyright (C) 2014-2017 Broadcom
7f646e92 FF	5	*
	6	* This program is free software; you can redistribute it and/or modify
	7	* it under the terms of the GNU General Public License version 2 as
	8	* published by the Free Software Foundation.
	9	*
	10	* This program is distributed in the hope that it will be useful,
	11	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	12	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	13	* GNU General Public License for more details.
	14	*/
	15
	16	#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
	17
	18	#include <linux/init.h>
	19	#include <linux/slab.h>
	20	#include <linux/module.h>
	21	#include <linux/platform_device.h>
05f12757	22	#include <linux/spinlock.h>
7f646e92 FF	23	#include <linux/of.h>
	24	#include <linux/of_irq.h>
	25	#include <linux/of_address.h>
	26	#include <linux/of_platform.h>
	27	#include <linux/interrupt.h>
	28	#include <linux/irq.h>
	29	#include <linux/io.h>
	30	#include <linux/irqdomain.h>
	31	#include <linux/irqchip.h>
	32	#include <linux/irqchip/chained_irq.h>
	33
c0ca7262 DB	34	struct brcmstb_intc_init_params {
	35	irq_flow_handler_t handler;
	36	int cpu_status;
	37	int cpu_clear;
	38	int cpu_mask_status;
	39	int cpu_mask_set;
	40	int cpu_mask_clear;
	41	};
	42
	43	/* Register offsets in the L2 latched interrupt controller */
	44	static const struct brcmstb_intc_init_params l2_edge_intc_init = {
	45	.handler = handle_edge_irq,
	46	.cpu_status = 0x00,
	47	.cpu_clear = 0x08,
	48	.cpu_mask_status = 0x0c,
	49	.cpu_mask_set = 0x10,
	50	.cpu_mask_clear = 0x14
	51	};
	52
	53	/* Register offsets in the L2 level interrupt controller */
	54	static const struct brcmstb_intc_init_params l2_lvl_intc_init = {
	55	.handler = handle_level_irq,
	56	.cpu_status = 0x00,
	57	.cpu_clear = -1, /* Register not present */
	58	.cpu_mask_status = 0x04,
	59	.cpu_mask_set = 0x08,
	60	.cpu_mask_clear = 0x0C
	61	};
7f646e92 FF	62
	63	/* L2 intc private data structure */
	64	struct brcmstb_l2_intc_data {
7f646e92	65	struct irq_domain *domain;
49aa6ef0	66	struct irq_chip_generic *gc;
8480ca47 DB	67	int status_offset;
8480ca47 DB	68	int mask_offset;
7f646e92 FF	69	bool can_wake;
	70	u32 saved_mask; /* for suspend/resume */
	71	};
	72
49aa6ef0 DB	73	/**
	74	* brcmstb_l2_mask_and_ack - Mask and ack pending interrupt
	75	* @d: irq_data
	76	*
	77	* Chip has separate enable/disable registers instead of a single mask
	78	* register and pending interrupt is acknowledged by setting a bit.
	79	*
	80	* Note: This function is generic and could easily be added to the
	81	* generic irqchip implementation if there ever becomes a will to do so.
	82	* Perhaps with a name like irq_gc_mask_disable_and_ack_set().
	83	*
	84	* e.g.: https://patchwork.kernel.org/patch/9831047/
	85	*/
	86	static void brcmstb_l2_mask_and_ack(struct irq_data *d)
	87	{
	88	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
	89	struct irq_chip_type *ct = irq_data_get_chip_type(d);
	90	u32 mask = d->mask;
	91
	92	irq_gc_lock(gc);
	93	irq_reg_writel(gc, mask, ct->regs.disable);
	94	*ct->mask_cache &= ~mask;
	95	irq_reg_writel(gc, mask, ct->regs.ack);
	96	irq_gc_unlock(gc);
	97	}
	98
bd0b9ac4	99	static void brcmstb_l2_intc_irq_handle(struct irq_desc *desc)
7f646e92 FF	100	{
	101	struct brcmstb_l2_intc_data *b = irq_desc_get_handler_data(desc);
	102	struct irq_chip *chip = irq_desc_get_chip(desc);
bd0b9ac4	103	unsigned int irq;
7f646e92 FF	104	u32 status;
	105
	106	chained_irq_enter(chip, desc);
	107
8480ca47 DB	108	status = irq_reg_readl(b->gc, b->status_offset) &
8480ca47 DB	109	~(irq_reg_readl(b->gc, b->mask_offset));
7f646e92 FF	110
7f646e92 FF	111	if (status == 0) {
05f12757	112	raw_spin_lock(&desc->lock);
bd0b9ac4	113	handle_bad_irq(desc);
05f12757	114	raw_spin_unlock(&desc->lock);
7f646e92 FF	115	goto out;
	116	}
	117
	118	do {
	119	irq = ffs(status) - 1;
7f646e92	120	status &= ~(1 << irq);
49aa6ef0	121	generic_handle_irq(irq_linear_revmap(b->domain, irq));
7f646e92 FF	122	} while (status);
	123	out:
	124	chained_irq_exit(chip, desc);
	125	}
	126
	127	static void brcmstb_l2_intc_suspend(struct irq_data *d)
	128	{
	129	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
8480ca47	130	struct irq_chip_type *ct = irq_data_get_chip_type(d);
7f646e92 FF	131	struct brcmstb_l2_intc_data *b = gc->private;
	132
	133	irq_gc_lock(gc);
	134	/* Save the current mask */
8480ca47	135	b->saved_mask = irq_reg_readl(gc, ct->regs.mask);
7f646e92 FF	136
	137	if (b->can_wake) {
	138	/* Program the wakeup mask */
8480ca47 DB	139	irq_reg_writel(gc, ~gc->wake_active, ct->regs.disable);
8480ca47 DB	140	irq_reg_writel(gc, gc->wake_active, ct->regs.enable);
7f646e92 FF	141	}
	142	irq_gc_unlock(gc);
	143	}
	144
	145	static void brcmstb_l2_intc_resume(struct irq_data *d)
	146	{
	147	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
8480ca47	148	struct irq_chip_type *ct = irq_data_get_chip_type(d);
7f646e92 FF	149	struct brcmstb_l2_intc_data *b = gc->private;
	150
	151	irq_gc_lock(gc);
c0ca7262	152	if (ct->chip.irq_ack) {
8480ca47 DB	153	/* Clear unmasked non-wakeup interrupts */
	154	irq_reg_writel(gc, ~b->saved_mask & ~gc->wake_active,
	155	ct->regs.ack);
	156	}
7f646e92 FF	157
7f646e92 FF	158	/* Restore the saved mask */
8480ca47 DB	159	irq_reg_writel(gc, b->saved_mask, ct->regs.disable);
8480ca47 DB	160	irq_reg_writel(gc, ~b->saved_mask, ct->regs.enable);
7f646e92 FF	161	irq_gc_unlock(gc);
	162	}
	163
2ae9add9	164	static int __init brcmstb_l2_intc_of_init(struct device_node *np,
c0ca7262 DB	165	struct device_node *parent,
	166	const struct brcmstb_intc_init_params
	167	*init_params)
7f646e92 FF	168	{
	169	unsigned int clr = IRQ_NOREQUEST \| IRQ_NOPROBE \| IRQ_NOAUTOEN;
	170	struct brcmstb_l2_intc_data *data;
7f646e92 FF	171	struct irq_chip_type *ct;
7f646e92 FF	172	int ret;
1abbdbac	173	unsigned int flags;
49aa6ef0 DB	174	int parent_irq;
49aa6ef0 DB	175	void __iomem *base;
7f646e92 FF	176
	177	data = kzalloc(sizeof(*data), GFP_KERNEL);
	178	if (!data)
	179	return -ENOMEM;
	180
49aa6ef0 DB	181	base = of_iomap(np, 0);
49aa6ef0 DB	182	if (!base) {
7f646e92 FF	183	pr_err("failed to remap intc L2 registers\n");
	184	ret = -ENOMEM;
	185	goto out_free;
	186	}
	187
	188	/* Disable all interrupts by default */
c0ca7262	189	writel(0xffffffff, base + init_params->cpu_mask_set);
c9ae71e0 BN	190
	191	/* Wakeup interrupts may be retained from S5 (cold boot) */
	192	data->can_wake = of_property_read_bool(np, "brcm,irq-can-wake");
c0ca7262 DB	193	if (!data->can_wake && (init_params->cpu_clear >= 0))
c0ca7262 DB	194	writel(0xffffffff, base + init_params->cpu_clear);
7f646e92	195
49aa6ef0 DB	196	parent_irq = irq_of_parse_and_map(np, 0);
49aa6ef0 DB	197	if (!parent_irq) {
7f646e92	198	pr_err("failed to find parent interrupt\n");
d99ba446	199	ret = -EINVAL;
7f646e92 FF	200	goto out_unmap;
	201	}
	202
	203	data->domain = irq_domain_add_linear(np, 32,
	204	&irq_generic_chip_ops, NULL);
	205	if (!data->domain) {
	206	ret = -ENOMEM;
	207	goto out_unmap;
	208	}
	209
1abbdbac KC	210	/* MIPS chips strapped for BE will automagically configure the
	211	* peripheral registers for CPU-native byte order.
	212	*/
	213	flags = 0;
	214	if (IS_ENABLED(CONFIG_MIPS) && IS_ENABLED(CONFIG_CPU_BIG_ENDIAN))
	215	flags \|= IRQ_GC_BE_IO;
	216
7f646e92 FF	217	/* Allocate a single Generic IRQ chip for this node */
7f646e92 FF	218	ret = irq_alloc_domain_generic_chips(data->domain, 32, 1,
c0ca7262	219	np->full_name, init_params->handler, clr, 0, flags);
7f646e92 FF	220	if (ret) {
	221	pr_err("failed to allocate generic irq chip\n");
	222	goto out_free_domain;
	223	}
	224
	225	/* Set the IRQ chaining logic */
49aa6ef0	226	irq_set_chained_handler_and_data(parent_irq,
f286c173	227	brcmstb_l2_intc_irq_handle, data);
7f646e92	228
49aa6ef0 DB	229	data->gc = irq_get_domain_generic_chip(data->domain, 0);
	230	data->gc->reg_base = base;
	231	data->gc->private = data;
c0ca7262 DB	232	data->status_offset = init_params->cpu_status;
c0ca7262 DB	233	data->mask_offset = init_params->cpu_mask_status;
8480ca47	234
49aa6ef0	235	ct = data->gc->chip_types;
7f646e92	236
c0ca7262 DB	237	if (init_params->cpu_clear >= 0) {
	238	ct->regs.ack = init_params->cpu_clear;
	239	ct->chip.irq_ack = irq_gc_ack_set_bit;
	240	ct->chip.irq_mask_ack = brcmstb_l2_mask_and_ack;
	241	} else {
	242	/* No Ack - but still slightly more efficient to define this */
	243	ct->chip.irq_mask_ack = irq_gc_mask_disable_reg;
	244	}
7f646e92 FF	245
7f646e92 FF	246	ct->chip.irq_mask = irq_gc_mask_disable_reg;
c0ca7262 DB	247	ct->regs.disable = init_params->cpu_mask_set;
c0ca7262 DB	248	ct->regs.mask = init_params->cpu_mask_status;
7f646e92 FF	249
7f646e92 FF	250	ct->chip.irq_unmask = irq_gc_unmask_enable_reg;
c0ca7262	251	ct->regs.enable = init_params->cpu_mask_clear;
7f646e92 FF	252
	253	ct->chip.irq_suspend = brcmstb_l2_intc_suspend;
	254	ct->chip.irq_resume = brcmstb_l2_intc_resume;
c017d211	255	ct->chip.irq_pm_shutdown = brcmstb_l2_intc_suspend;
7f646e92	256
c9ae71e0	257	if (data->can_wake) {
7f646e92 FF	258	/* This IRQ chip can wake the system, set all child interrupts
	259	* in wake_enabled mask
	260	*/
49aa6ef0	261	data->gc->wake_enabled = 0xffffffff;
7f646e92 FF	262	ct->chip.irq_set_wake = irq_gc_set_wake;
	263	}
	264
7f646e92 FF	265	return 0;
	266
	267	out_free_domain:
	268	irq_domain_remove(data->domain);
	269	out_unmap:
49aa6ef0	270	iounmap(base);
7f646e92 FF	271	out_free:
	272	kfree(data);
	273	return ret;
	274	}
c0ca7262 DB	275
	276	int __init brcmstb_l2_edge_intc_of_init(struct device_node *np,
	277	struct device_node *parent)
	278	{
	279	return brcmstb_l2_intc_of_init(np, parent, &l2_edge_intc_init);
	280	}
	281	IRQCHIP_DECLARE(brcmstb_l2_intc, "brcm,l2-intc", brcmstb_l2_edge_intc_of_init);
	282
	283	int __init brcmstb_l2_lvl_intc_of_init(struct device_node *np,
	284	struct device_node *parent)
	285	{
	286	return brcmstb_l2_intc_of_init(np, parent, &l2_lvl_intc_init);
	287	}
	288	IRQCHIP_DECLARE(bcm7271_l2_intc, "brcm,bcm7271-l2-intc",
	289	brcmstb_l2_lvl_intc_of_init);