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cc2d3216 MZ |
1 | /* |
2 | * Copyright (C) 2013, 2014 ARM Limited, All Rights Reserved. | |
3 | * Author: Marc Zyngier <marc.zyngier@arm.com> | |
4 | * | |
5 | * This program is free software; you can redistribute it and/or modify | |
6 | * it under the terms of the GNU General Public License version 2 as | |
7 | * published by the Free Software Foundation. | |
8 | * | |
9 | * This program is distributed in the hope that it will be useful, | |
10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
12 | * GNU General Public License for more details. | |
13 | * | |
14 | * You should have received a copy of the GNU General Public License | |
15 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | |
16 | */ | |
17 | ||
ab789c11 | 18 | #include <linux/acpi_iort.h> |
cc2d3216 MZ |
19 | #include <linux/bitmap.h> |
20 | #include <linux/cpu.h> | |
21 | #include <linux/delay.h> | |
44bb7e24 | 22 | #include <linux/dma-iommu.h> |
cc2d3216 | 23 | #include <linux/interrupt.h> |
3f010cf1 | 24 | #include <linux/irqdomain.h> |
cc2d3216 MZ |
25 | #include <linux/log2.h> |
26 | #include <linux/mm.h> | |
27 | #include <linux/msi.h> | |
28 | #include <linux/of.h> | |
29 | #include <linux/of_address.h> | |
30 | #include <linux/of_irq.h> | |
31 | #include <linux/of_pci.h> | |
32 | #include <linux/of_platform.h> | |
33 | #include <linux/percpu.h> | |
34 | #include <linux/slab.h> | |
35 | ||
41a83e06 | 36 | #include <linux/irqchip.h> |
cc2d3216 MZ |
37 | #include <linux/irqchip/arm-gic-v3.h> |
38 | ||
cc2d3216 MZ |
39 | #include <asm/cputype.h> |
40 | #include <asm/exception.h> | |
41 | ||
67510cca RR |
42 | #include "irq-gic-common.h" |
43 | ||
94100970 RR |
44 | #define ITS_FLAGS_CMDQ_NEEDS_FLUSHING (1ULL << 0) |
45 | #define ITS_FLAGS_WORKAROUND_CAVIUM_22375 (1ULL << 1) | |
fbf8f40e | 46 | #define ITS_FLAGS_WORKAROUND_CAVIUM_23144 (1ULL << 2) |
cc2d3216 | 47 | |
c48ed51c MZ |
48 | #define RDIST_FLAGS_PROPBASE_NEEDS_FLUSHING (1 << 0) |
49 | ||
cc2d3216 MZ |
50 | /* |
51 | * Collection structure - just an ID, and a redistributor address to | |
52 | * ping. We use one per CPU as a bag of interrupts assigned to this | |
53 | * CPU. | |
54 | */ | |
55 | struct its_collection { | |
56 | u64 target_address; | |
57 | u16 col_id; | |
58 | }; | |
59 | ||
466b7d16 | 60 | /* |
9347359a SD |
61 | * The ITS_BASER structure - contains memory information, cached |
62 | * value of BASER register configuration and ITS page size. | |
466b7d16 SD |
63 | */ |
64 | struct its_baser { | |
65 | void *base; | |
66 | u64 val; | |
67 | u32 order; | |
9347359a | 68 | u32 psz; |
466b7d16 SD |
69 | }; |
70 | ||
cc2d3216 MZ |
71 | /* |
72 | * The ITS structure - contains most of the infrastructure, with the | |
841514ab MZ |
73 | * top-level MSI domain, the command queue, the collections, and the |
74 | * list of devices writing to it. | |
cc2d3216 MZ |
75 | */ |
76 | struct its_node { | |
77 | raw_spinlock_t lock; | |
78 | struct list_head entry; | |
cc2d3216 | 79 | void __iomem *base; |
db40f0a7 | 80 | phys_addr_t phys_base; |
cc2d3216 MZ |
81 | struct its_cmd_block *cmd_base; |
82 | struct its_cmd_block *cmd_write; | |
466b7d16 | 83 | struct its_baser tables[GITS_BASER_NR_REGS]; |
cc2d3216 MZ |
84 | struct its_collection *collections; |
85 | struct list_head its_device_list; | |
86 | u64 flags; | |
87 | u32 ite_size; | |
466b7d16 | 88 | u32 device_ids; |
fbf8f40e | 89 | int numa_node; |
cc2d3216 MZ |
90 | }; |
91 | ||
92 | #define ITS_ITT_ALIGN SZ_256 | |
93 | ||
2eca0d6c SD |
94 | /* Convert page order to size in bytes */ |
95 | #define PAGE_ORDER_TO_SIZE(o) (PAGE_SIZE << (o)) | |
96 | ||
591e5bec MZ |
97 | struct event_lpi_map { |
98 | unsigned long *lpi_map; | |
99 | u16 *col_map; | |
100 | irq_hw_number_t lpi_base; | |
101 | int nr_lpis; | |
102 | }; | |
103 | ||
cc2d3216 MZ |
104 | /* |
105 | * The ITS view of a device - belongs to an ITS, a collection, owns an | |
106 | * interrupt translation table, and a list of interrupts. | |
107 | */ | |
108 | struct its_device { | |
109 | struct list_head entry; | |
110 | struct its_node *its; | |
591e5bec | 111 | struct event_lpi_map event_map; |
cc2d3216 | 112 | void *itt; |
cc2d3216 MZ |
113 | u32 nr_ites; |
114 | u32 device_id; | |
115 | }; | |
116 | ||
1ac19ca6 MZ |
117 | static LIST_HEAD(its_nodes); |
118 | static DEFINE_SPINLOCK(its_lock); | |
1ac19ca6 | 119 | static struct rdists *gic_rdists; |
db40f0a7 | 120 | static struct irq_domain *its_parent; |
1ac19ca6 MZ |
121 | |
122 | #define gic_data_rdist() (raw_cpu_ptr(gic_rdists->rdist)) | |
123 | #define gic_data_rdist_rd_base() (gic_data_rdist()->rd_base) | |
124 | ||
591e5bec MZ |
125 | static struct its_collection *dev_event_to_col(struct its_device *its_dev, |
126 | u32 event) | |
127 | { | |
128 | struct its_node *its = its_dev->its; | |
129 | ||
130 | return its->collections + its_dev->event_map.col_map[event]; | |
131 | } | |
132 | ||
cc2d3216 MZ |
133 | /* |
134 | * ITS command descriptors - parameters to be encoded in a command | |
135 | * block. | |
136 | */ | |
137 | struct its_cmd_desc { | |
138 | union { | |
139 | struct { | |
140 | struct its_device *dev; | |
141 | u32 event_id; | |
142 | } its_inv_cmd; | |
143 | ||
144 | struct { | |
145 | struct its_device *dev; | |
146 | u32 event_id; | |
147 | } its_int_cmd; | |
148 | ||
149 | struct { | |
150 | struct its_device *dev; | |
151 | int valid; | |
152 | } its_mapd_cmd; | |
153 | ||
154 | struct { | |
155 | struct its_collection *col; | |
156 | int valid; | |
157 | } its_mapc_cmd; | |
158 | ||
159 | struct { | |
160 | struct its_device *dev; | |
161 | u32 phys_id; | |
162 | u32 event_id; | |
163 | } its_mapvi_cmd; | |
164 | ||
165 | struct { | |
166 | struct its_device *dev; | |
167 | struct its_collection *col; | |
591e5bec | 168 | u32 event_id; |
cc2d3216 MZ |
169 | } its_movi_cmd; |
170 | ||
171 | struct { | |
172 | struct its_device *dev; | |
173 | u32 event_id; | |
174 | } its_discard_cmd; | |
175 | ||
176 | struct { | |
177 | struct its_collection *col; | |
178 | } its_invall_cmd; | |
179 | }; | |
180 | }; | |
181 | ||
182 | /* | |
183 | * The ITS command block, which is what the ITS actually parses. | |
184 | */ | |
185 | struct its_cmd_block { | |
186 | u64 raw_cmd[4]; | |
187 | }; | |
188 | ||
189 | #define ITS_CMD_QUEUE_SZ SZ_64K | |
190 | #define ITS_CMD_QUEUE_NR_ENTRIES (ITS_CMD_QUEUE_SZ / sizeof(struct its_cmd_block)) | |
191 | ||
192 | typedef struct its_collection *(*its_cmd_builder_t)(struct its_cmd_block *, | |
193 | struct its_cmd_desc *); | |
194 | ||
195 | static void its_encode_cmd(struct its_cmd_block *cmd, u8 cmd_nr) | |
196 | { | |
b11283eb | 197 | cmd->raw_cmd[0] &= ~0xffULL; |
cc2d3216 MZ |
198 | cmd->raw_cmd[0] |= cmd_nr; |
199 | } | |
200 | ||
201 | static void its_encode_devid(struct its_cmd_block *cmd, u32 devid) | |
202 | { | |
7e195ba0 | 203 | cmd->raw_cmd[0] &= BIT_ULL(32) - 1; |
cc2d3216 MZ |
204 | cmd->raw_cmd[0] |= ((u64)devid) << 32; |
205 | } | |
206 | ||
207 | static void its_encode_event_id(struct its_cmd_block *cmd, u32 id) | |
208 | { | |
b11283eb | 209 | cmd->raw_cmd[1] &= ~0xffffffffULL; |
cc2d3216 MZ |
210 | cmd->raw_cmd[1] |= id; |
211 | } | |
212 | ||
213 | static void its_encode_phys_id(struct its_cmd_block *cmd, u32 phys_id) | |
214 | { | |
b11283eb | 215 | cmd->raw_cmd[1] &= 0xffffffffULL; |
cc2d3216 MZ |
216 | cmd->raw_cmd[1] |= ((u64)phys_id) << 32; |
217 | } | |
218 | ||
219 | static void its_encode_size(struct its_cmd_block *cmd, u8 size) | |
220 | { | |
b11283eb | 221 | cmd->raw_cmd[1] &= ~0x1fULL; |
cc2d3216 MZ |
222 | cmd->raw_cmd[1] |= size & 0x1f; |
223 | } | |
224 | ||
225 | static void its_encode_itt(struct its_cmd_block *cmd, u64 itt_addr) | |
226 | { | |
b11283eb VM |
227 | cmd->raw_cmd[2] &= ~0xffffffffffffULL; |
228 | cmd->raw_cmd[2] |= itt_addr & 0xffffffffff00ULL; | |
cc2d3216 MZ |
229 | } |
230 | ||
231 | static void its_encode_valid(struct its_cmd_block *cmd, int valid) | |
232 | { | |
b11283eb | 233 | cmd->raw_cmd[2] &= ~(1ULL << 63); |
cc2d3216 MZ |
234 | cmd->raw_cmd[2] |= ((u64)!!valid) << 63; |
235 | } | |
236 | ||
237 | static void its_encode_target(struct its_cmd_block *cmd, u64 target_addr) | |
238 | { | |
b11283eb VM |
239 | cmd->raw_cmd[2] &= ~(0xffffffffULL << 16); |
240 | cmd->raw_cmd[2] |= (target_addr & (0xffffffffULL << 16)); | |
cc2d3216 MZ |
241 | } |
242 | ||
243 | static void its_encode_collection(struct its_cmd_block *cmd, u16 col) | |
244 | { | |
b11283eb | 245 | cmd->raw_cmd[2] &= ~0xffffULL; |
cc2d3216 MZ |
246 | cmd->raw_cmd[2] |= col; |
247 | } | |
248 | ||
249 | static inline void its_fixup_cmd(struct its_cmd_block *cmd) | |
250 | { | |
251 | /* Let's fixup BE commands */ | |
252 | cmd->raw_cmd[0] = cpu_to_le64(cmd->raw_cmd[0]); | |
253 | cmd->raw_cmd[1] = cpu_to_le64(cmd->raw_cmd[1]); | |
254 | cmd->raw_cmd[2] = cpu_to_le64(cmd->raw_cmd[2]); | |
255 | cmd->raw_cmd[3] = cpu_to_le64(cmd->raw_cmd[3]); | |
256 | } | |
257 | ||
258 | static struct its_collection *its_build_mapd_cmd(struct its_cmd_block *cmd, | |
259 | struct its_cmd_desc *desc) | |
260 | { | |
261 | unsigned long itt_addr; | |
c8481267 | 262 | u8 size = ilog2(desc->its_mapd_cmd.dev->nr_ites); |
cc2d3216 MZ |
263 | |
264 | itt_addr = virt_to_phys(desc->its_mapd_cmd.dev->itt); | |
265 | itt_addr = ALIGN(itt_addr, ITS_ITT_ALIGN); | |
266 | ||
267 | its_encode_cmd(cmd, GITS_CMD_MAPD); | |
268 | its_encode_devid(cmd, desc->its_mapd_cmd.dev->device_id); | |
269 | its_encode_size(cmd, size - 1); | |
270 | its_encode_itt(cmd, itt_addr); | |
271 | its_encode_valid(cmd, desc->its_mapd_cmd.valid); | |
272 | ||
273 | its_fixup_cmd(cmd); | |
274 | ||
591e5bec | 275 | return NULL; |
cc2d3216 MZ |
276 | } |
277 | ||
278 | static struct its_collection *its_build_mapc_cmd(struct its_cmd_block *cmd, | |
279 | struct its_cmd_desc *desc) | |
280 | { | |
281 | its_encode_cmd(cmd, GITS_CMD_MAPC); | |
282 | its_encode_collection(cmd, desc->its_mapc_cmd.col->col_id); | |
283 | its_encode_target(cmd, desc->its_mapc_cmd.col->target_address); | |
284 | its_encode_valid(cmd, desc->its_mapc_cmd.valid); | |
285 | ||
286 | its_fixup_cmd(cmd); | |
287 | ||
288 | return desc->its_mapc_cmd.col; | |
289 | } | |
290 | ||
291 | static struct its_collection *its_build_mapvi_cmd(struct its_cmd_block *cmd, | |
292 | struct its_cmd_desc *desc) | |
293 | { | |
591e5bec MZ |
294 | struct its_collection *col; |
295 | ||
296 | col = dev_event_to_col(desc->its_mapvi_cmd.dev, | |
297 | desc->its_mapvi_cmd.event_id); | |
298 | ||
cc2d3216 MZ |
299 | its_encode_cmd(cmd, GITS_CMD_MAPVI); |
300 | its_encode_devid(cmd, desc->its_mapvi_cmd.dev->device_id); | |
301 | its_encode_event_id(cmd, desc->its_mapvi_cmd.event_id); | |
302 | its_encode_phys_id(cmd, desc->its_mapvi_cmd.phys_id); | |
591e5bec | 303 | its_encode_collection(cmd, col->col_id); |
cc2d3216 MZ |
304 | |
305 | its_fixup_cmd(cmd); | |
306 | ||
591e5bec | 307 | return col; |
cc2d3216 MZ |
308 | } |
309 | ||
310 | static struct its_collection *its_build_movi_cmd(struct its_cmd_block *cmd, | |
311 | struct its_cmd_desc *desc) | |
312 | { | |
591e5bec MZ |
313 | struct its_collection *col; |
314 | ||
315 | col = dev_event_to_col(desc->its_movi_cmd.dev, | |
316 | desc->its_movi_cmd.event_id); | |
317 | ||
cc2d3216 MZ |
318 | its_encode_cmd(cmd, GITS_CMD_MOVI); |
319 | its_encode_devid(cmd, desc->its_movi_cmd.dev->device_id); | |
591e5bec | 320 | its_encode_event_id(cmd, desc->its_movi_cmd.event_id); |
cc2d3216 MZ |
321 | its_encode_collection(cmd, desc->its_movi_cmd.col->col_id); |
322 | ||
323 | its_fixup_cmd(cmd); | |
324 | ||
591e5bec | 325 | return col; |
cc2d3216 MZ |
326 | } |
327 | ||
328 | static struct its_collection *its_build_discard_cmd(struct its_cmd_block *cmd, | |
329 | struct its_cmd_desc *desc) | |
330 | { | |
591e5bec MZ |
331 | struct its_collection *col; |
332 | ||
333 | col = dev_event_to_col(desc->its_discard_cmd.dev, | |
334 | desc->its_discard_cmd.event_id); | |
335 | ||
cc2d3216 MZ |
336 | its_encode_cmd(cmd, GITS_CMD_DISCARD); |
337 | its_encode_devid(cmd, desc->its_discard_cmd.dev->device_id); | |
338 | its_encode_event_id(cmd, desc->its_discard_cmd.event_id); | |
339 | ||
340 | its_fixup_cmd(cmd); | |
341 | ||
591e5bec | 342 | return col; |
cc2d3216 MZ |
343 | } |
344 | ||
345 | static struct its_collection *its_build_inv_cmd(struct its_cmd_block *cmd, | |
346 | struct its_cmd_desc *desc) | |
347 | { | |
591e5bec MZ |
348 | struct its_collection *col; |
349 | ||
350 | col = dev_event_to_col(desc->its_inv_cmd.dev, | |
351 | desc->its_inv_cmd.event_id); | |
352 | ||
cc2d3216 MZ |
353 | its_encode_cmd(cmd, GITS_CMD_INV); |
354 | its_encode_devid(cmd, desc->its_inv_cmd.dev->device_id); | |
355 | its_encode_event_id(cmd, desc->its_inv_cmd.event_id); | |
356 | ||
357 | its_fixup_cmd(cmd); | |
358 | ||
591e5bec | 359 | return col; |
cc2d3216 MZ |
360 | } |
361 | ||
362 | static struct its_collection *its_build_invall_cmd(struct its_cmd_block *cmd, | |
363 | struct its_cmd_desc *desc) | |
364 | { | |
365 | its_encode_cmd(cmd, GITS_CMD_INVALL); | |
366 | its_encode_collection(cmd, desc->its_mapc_cmd.col->col_id); | |
367 | ||
368 | its_fixup_cmd(cmd); | |
369 | ||
370 | return NULL; | |
371 | } | |
372 | ||
373 | static u64 its_cmd_ptr_to_offset(struct its_node *its, | |
374 | struct its_cmd_block *ptr) | |
375 | { | |
376 | return (ptr - its->cmd_base) * sizeof(*ptr); | |
377 | } | |
378 | ||
379 | static int its_queue_full(struct its_node *its) | |
380 | { | |
381 | int widx; | |
382 | int ridx; | |
383 | ||
384 | widx = its->cmd_write - its->cmd_base; | |
385 | ridx = readl_relaxed(its->base + GITS_CREADR) / sizeof(struct its_cmd_block); | |
386 | ||
387 | /* This is incredibly unlikely to happen, unless the ITS locks up. */ | |
388 | if (((widx + 1) % ITS_CMD_QUEUE_NR_ENTRIES) == ridx) | |
389 | return 1; | |
390 | ||
391 | return 0; | |
392 | } | |
393 | ||
394 | static struct its_cmd_block *its_allocate_entry(struct its_node *its) | |
395 | { | |
396 | struct its_cmd_block *cmd; | |
397 | u32 count = 1000000; /* 1s! */ | |
398 | ||
399 | while (its_queue_full(its)) { | |
400 | count--; | |
401 | if (!count) { | |
402 | pr_err_ratelimited("ITS queue not draining\n"); | |
403 | return NULL; | |
404 | } | |
405 | cpu_relax(); | |
406 | udelay(1); | |
407 | } | |
408 | ||
409 | cmd = its->cmd_write++; | |
410 | ||
411 | /* Handle queue wrapping */ | |
412 | if (its->cmd_write == (its->cmd_base + ITS_CMD_QUEUE_NR_ENTRIES)) | |
413 | its->cmd_write = its->cmd_base; | |
414 | ||
415 | return cmd; | |
416 | } | |
417 | ||
418 | static struct its_cmd_block *its_post_commands(struct its_node *its) | |
419 | { | |
420 | u64 wr = its_cmd_ptr_to_offset(its, its->cmd_write); | |
421 | ||
422 | writel_relaxed(wr, its->base + GITS_CWRITER); | |
423 | ||
424 | return its->cmd_write; | |
425 | } | |
426 | ||
427 | static void its_flush_cmd(struct its_node *its, struct its_cmd_block *cmd) | |
428 | { | |
429 | /* | |
430 | * Make sure the commands written to memory are observable by | |
431 | * the ITS. | |
432 | */ | |
433 | if (its->flags & ITS_FLAGS_CMDQ_NEEDS_FLUSHING) | |
328191c0 | 434 | gic_flush_dcache_to_poc(cmd, sizeof(*cmd)); |
cc2d3216 MZ |
435 | else |
436 | dsb(ishst); | |
437 | } | |
438 | ||
439 | static void its_wait_for_range_completion(struct its_node *its, | |
440 | struct its_cmd_block *from, | |
441 | struct its_cmd_block *to) | |
442 | { | |
443 | u64 rd_idx, from_idx, to_idx; | |
444 | u32 count = 1000000; /* 1s! */ | |
445 | ||
446 | from_idx = its_cmd_ptr_to_offset(its, from); | |
447 | to_idx = its_cmd_ptr_to_offset(its, to); | |
448 | ||
449 | while (1) { | |
450 | rd_idx = readl_relaxed(its->base + GITS_CREADR); | |
451 | if (rd_idx >= to_idx || rd_idx < from_idx) | |
452 | break; | |
453 | ||
454 | count--; | |
455 | if (!count) { | |
456 | pr_err_ratelimited("ITS queue timeout\n"); | |
457 | return; | |
458 | } | |
459 | cpu_relax(); | |
460 | udelay(1); | |
461 | } | |
462 | } | |
463 | ||
464 | static void its_send_single_command(struct its_node *its, | |
465 | its_cmd_builder_t builder, | |
466 | struct its_cmd_desc *desc) | |
467 | { | |
468 | struct its_cmd_block *cmd, *sync_cmd, *next_cmd; | |
469 | struct its_collection *sync_col; | |
3e39e8f5 | 470 | unsigned long flags; |
cc2d3216 | 471 | |
3e39e8f5 | 472 | raw_spin_lock_irqsave(&its->lock, flags); |
cc2d3216 MZ |
473 | |
474 | cmd = its_allocate_entry(its); | |
475 | if (!cmd) { /* We're soooooo screewed... */ | |
476 | pr_err_ratelimited("ITS can't allocate, dropping command\n"); | |
3e39e8f5 | 477 | raw_spin_unlock_irqrestore(&its->lock, flags); |
cc2d3216 MZ |
478 | return; |
479 | } | |
480 | sync_col = builder(cmd, desc); | |
481 | its_flush_cmd(its, cmd); | |
482 | ||
483 | if (sync_col) { | |
484 | sync_cmd = its_allocate_entry(its); | |
485 | if (!sync_cmd) { | |
486 | pr_err_ratelimited("ITS can't SYNC, skipping\n"); | |
487 | goto post; | |
488 | } | |
489 | its_encode_cmd(sync_cmd, GITS_CMD_SYNC); | |
490 | its_encode_target(sync_cmd, sync_col->target_address); | |
491 | its_fixup_cmd(sync_cmd); | |
492 | its_flush_cmd(its, sync_cmd); | |
493 | } | |
494 | ||
495 | post: | |
496 | next_cmd = its_post_commands(its); | |
3e39e8f5 | 497 | raw_spin_unlock_irqrestore(&its->lock, flags); |
cc2d3216 MZ |
498 | |
499 | its_wait_for_range_completion(its, cmd, next_cmd); | |
500 | } | |
501 | ||
502 | static void its_send_inv(struct its_device *dev, u32 event_id) | |
503 | { | |
504 | struct its_cmd_desc desc; | |
505 | ||
506 | desc.its_inv_cmd.dev = dev; | |
507 | desc.its_inv_cmd.event_id = event_id; | |
508 | ||
509 | its_send_single_command(dev->its, its_build_inv_cmd, &desc); | |
510 | } | |
511 | ||
512 | static void its_send_mapd(struct its_device *dev, int valid) | |
513 | { | |
514 | struct its_cmd_desc desc; | |
515 | ||
516 | desc.its_mapd_cmd.dev = dev; | |
517 | desc.its_mapd_cmd.valid = !!valid; | |
518 | ||
519 | its_send_single_command(dev->its, its_build_mapd_cmd, &desc); | |
520 | } | |
521 | ||
522 | static void its_send_mapc(struct its_node *its, struct its_collection *col, | |
523 | int valid) | |
524 | { | |
525 | struct its_cmd_desc desc; | |
526 | ||
527 | desc.its_mapc_cmd.col = col; | |
528 | desc.its_mapc_cmd.valid = !!valid; | |
529 | ||
530 | its_send_single_command(its, its_build_mapc_cmd, &desc); | |
531 | } | |
532 | ||
533 | static void its_send_mapvi(struct its_device *dev, u32 irq_id, u32 id) | |
534 | { | |
535 | struct its_cmd_desc desc; | |
536 | ||
537 | desc.its_mapvi_cmd.dev = dev; | |
538 | desc.its_mapvi_cmd.phys_id = irq_id; | |
539 | desc.its_mapvi_cmd.event_id = id; | |
540 | ||
541 | its_send_single_command(dev->its, its_build_mapvi_cmd, &desc); | |
542 | } | |
543 | ||
544 | static void its_send_movi(struct its_device *dev, | |
545 | struct its_collection *col, u32 id) | |
546 | { | |
547 | struct its_cmd_desc desc; | |
548 | ||
549 | desc.its_movi_cmd.dev = dev; | |
550 | desc.its_movi_cmd.col = col; | |
591e5bec | 551 | desc.its_movi_cmd.event_id = id; |
cc2d3216 MZ |
552 | |
553 | its_send_single_command(dev->its, its_build_movi_cmd, &desc); | |
554 | } | |
555 | ||
556 | static void its_send_discard(struct its_device *dev, u32 id) | |
557 | { | |
558 | struct its_cmd_desc desc; | |
559 | ||
560 | desc.its_discard_cmd.dev = dev; | |
561 | desc.its_discard_cmd.event_id = id; | |
562 | ||
563 | its_send_single_command(dev->its, its_build_discard_cmd, &desc); | |
564 | } | |
565 | ||
566 | static void its_send_invall(struct its_node *its, struct its_collection *col) | |
567 | { | |
568 | struct its_cmd_desc desc; | |
569 | ||
570 | desc.its_invall_cmd.col = col; | |
571 | ||
572 | its_send_single_command(its, its_build_invall_cmd, &desc); | |
573 | } | |
c48ed51c MZ |
574 | |
575 | /* | |
576 | * irqchip functions - assumes MSI, mostly. | |
577 | */ | |
578 | ||
579 | static inline u32 its_get_event_id(struct irq_data *d) | |
580 | { | |
581 | struct its_device *its_dev = irq_data_get_irq_chip_data(d); | |
591e5bec | 582 | return d->hwirq - its_dev->event_map.lpi_base; |
c48ed51c MZ |
583 | } |
584 | ||
585 | static void lpi_set_config(struct irq_data *d, bool enable) | |
586 | { | |
587 | struct its_device *its_dev = irq_data_get_irq_chip_data(d); | |
588 | irq_hw_number_t hwirq = d->hwirq; | |
589 | u32 id = its_get_event_id(d); | |
590 | u8 *cfg = page_address(gic_rdists->prop_page) + hwirq - 8192; | |
591 | ||
592 | if (enable) | |
593 | *cfg |= LPI_PROP_ENABLED; | |
594 | else | |
595 | *cfg &= ~LPI_PROP_ENABLED; | |
596 | ||
597 | /* | |
598 | * Make the above write visible to the redistributors. | |
599 | * And yes, we're flushing exactly: One. Single. Byte. | |
600 | * Humpf... | |
601 | */ | |
602 | if (gic_rdists->flags & RDIST_FLAGS_PROPBASE_NEEDS_FLUSHING) | |
328191c0 | 603 | gic_flush_dcache_to_poc(cfg, sizeof(*cfg)); |
c48ed51c MZ |
604 | else |
605 | dsb(ishst); | |
606 | its_send_inv(its_dev, id); | |
607 | } | |
608 | ||
609 | static void its_mask_irq(struct irq_data *d) | |
610 | { | |
611 | lpi_set_config(d, false); | |
612 | } | |
613 | ||
614 | static void its_unmask_irq(struct irq_data *d) | |
615 | { | |
616 | lpi_set_config(d, true); | |
617 | } | |
618 | ||
c48ed51c MZ |
619 | static int its_set_affinity(struct irq_data *d, const struct cpumask *mask_val, |
620 | bool force) | |
621 | { | |
fbf8f40e GK |
622 | unsigned int cpu; |
623 | const struct cpumask *cpu_mask = cpu_online_mask; | |
c48ed51c MZ |
624 | struct its_device *its_dev = irq_data_get_irq_chip_data(d); |
625 | struct its_collection *target_col; | |
626 | u32 id = its_get_event_id(d); | |
627 | ||
fbf8f40e GK |
628 | /* lpi cannot be routed to a redistributor that is on a foreign node */ |
629 | if (its_dev->its->flags & ITS_FLAGS_WORKAROUND_CAVIUM_23144) { | |
630 | if (its_dev->its->numa_node >= 0) { | |
631 | cpu_mask = cpumask_of_node(its_dev->its->numa_node); | |
632 | if (!cpumask_intersects(mask_val, cpu_mask)) | |
633 | return -EINVAL; | |
634 | } | |
635 | } | |
636 | ||
637 | cpu = cpumask_any_and(mask_val, cpu_mask); | |
638 | ||
c48ed51c MZ |
639 | if (cpu >= nr_cpu_ids) |
640 | return -EINVAL; | |
641 | ||
642 | target_col = &its_dev->its->collections[cpu]; | |
643 | its_send_movi(its_dev, target_col, id); | |
591e5bec | 644 | its_dev->event_map.col_map[id] = cpu; |
c48ed51c MZ |
645 | |
646 | return IRQ_SET_MASK_OK_DONE; | |
647 | } | |
648 | ||
b48ac83d MZ |
649 | static void its_irq_compose_msi_msg(struct irq_data *d, struct msi_msg *msg) |
650 | { | |
651 | struct its_device *its_dev = irq_data_get_irq_chip_data(d); | |
652 | struct its_node *its; | |
653 | u64 addr; | |
654 | ||
655 | its = its_dev->its; | |
656 | addr = its->phys_base + GITS_TRANSLATER; | |
657 | ||
b11283eb VM |
658 | msg->address_lo = lower_32_bits(addr); |
659 | msg->address_hi = upper_32_bits(addr); | |
b48ac83d | 660 | msg->data = its_get_event_id(d); |
44bb7e24 RM |
661 | |
662 | iommu_dma_map_msi_msg(d->irq, msg); | |
b48ac83d MZ |
663 | } |
664 | ||
c48ed51c MZ |
665 | static struct irq_chip its_irq_chip = { |
666 | .name = "ITS", | |
667 | .irq_mask = its_mask_irq, | |
668 | .irq_unmask = its_unmask_irq, | |
004fa08d | 669 | .irq_eoi = irq_chip_eoi_parent, |
c48ed51c | 670 | .irq_set_affinity = its_set_affinity, |
b48ac83d MZ |
671 | .irq_compose_msi_msg = its_irq_compose_msi_msg, |
672 | }; | |
673 | ||
bf9529f8 MZ |
674 | /* |
675 | * How we allocate LPIs: | |
676 | * | |
677 | * The GIC has id_bits bits for interrupt identifiers. From there, we | |
678 | * must subtract 8192 which are reserved for SGIs/PPIs/SPIs. Then, as | |
679 | * we allocate LPIs by chunks of 32, we can shift the whole thing by 5 | |
680 | * bits to the right. | |
681 | * | |
682 | * This gives us (((1UL << id_bits) - 8192) >> 5) possible allocations. | |
683 | */ | |
684 | #define IRQS_PER_CHUNK_SHIFT 5 | |
685 | #define IRQS_PER_CHUNK (1 << IRQS_PER_CHUNK_SHIFT) | |
686 | ||
687 | static unsigned long *lpi_bitmap; | |
688 | static u32 lpi_chunks; | |
689 | static DEFINE_SPINLOCK(lpi_lock); | |
690 | ||
691 | static int its_lpi_to_chunk(int lpi) | |
692 | { | |
693 | return (lpi - 8192) >> IRQS_PER_CHUNK_SHIFT; | |
694 | } | |
695 | ||
696 | static int its_chunk_to_lpi(int chunk) | |
697 | { | |
698 | return (chunk << IRQS_PER_CHUNK_SHIFT) + 8192; | |
699 | } | |
700 | ||
04a0e4de | 701 | static int __init its_lpi_init(u32 id_bits) |
bf9529f8 MZ |
702 | { |
703 | lpi_chunks = its_lpi_to_chunk(1UL << id_bits); | |
704 | ||
705 | lpi_bitmap = kzalloc(BITS_TO_LONGS(lpi_chunks) * sizeof(long), | |
706 | GFP_KERNEL); | |
707 | if (!lpi_bitmap) { | |
708 | lpi_chunks = 0; | |
709 | return -ENOMEM; | |
710 | } | |
711 | ||
712 | pr_info("ITS: Allocated %d chunks for LPIs\n", (int)lpi_chunks); | |
713 | return 0; | |
714 | } | |
715 | ||
716 | static unsigned long *its_lpi_alloc_chunks(int nr_irqs, int *base, int *nr_ids) | |
717 | { | |
718 | unsigned long *bitmap = NULL; | |
719 | int chunk_id; | |
720 | int nr_chunks; | |
721 | int i; | |
722 | ||
723 | nr_chunks = DIV_ROUND_UP(nr_irqs, IRQS_PER_CHUNK); | |
724 | ||
725 | spin_lock(&lpi_lock); | |
726 | ||
727 | do { | |
728 | chunk_id = bitmap_find_next_zero_area(lpi_bitmap, lpi_chunks, | |
729 | 0, nr_chunks, 0); | |
730 | if (chunk_id < lpi_chunks) | |
731 | break; | |
732 | ||
733 | nr_chunks--; | |
734 | } while (nr_chunks > 0); | |
735 | ||
736 | if (!nr_chunks) | |
737 | goto out; | |
738 | ||
739 | bitmap = kzalloc(BITS_TO_LONGS(nr_chunks * IRQS_PER_CHUNK) * sizeof (long), | |
740 | GFP_ATOMIC); | |
741 | if (!bitmap) | |
742 | goto out; | |
743 | ||
744 | for (i = 0; i < nr_chunks; i++) | |
745 | set_bit(chunk_id + i, lpi_bitmap); | |
746 | ||
747 | *base = its_chunk_to_lpi(chunk_id); | |
748 | *nr_ids = nr_chunks * IRQS_PER_CHUNK; | |
749 | ||
750 | out: | |
751 | spin_unlock(&lpi_lock); | |
752 | ||
c8415b94 MZ |
753 | if (!bitmap) |
754 | *base = *nr_ids = 0; | |
755 | ||
bf9529f8 MZ |
756 | return bitmap; |
757 | } | |
758 | ||
591e5bec | 759 | static void its_lpi_free(struct event_lpi_map *map) |
bf9529f8 | 760 | { |
591e5bec MZ |
761 | int base = map->lpi_base; |
762 | int nr_ids = map->nr_lpis; | |
bf9529f8 MZ |
763 | int lpi; |
764 | ||
765 | spin_lock(&lpi_lock); | |
766 | ||
767 | for (lpi = base; lpi < (base + nr_ids); lpi += IRQS_PER_CHUNK) { | |
768 | int chunk = its_lpi_to_chunk(lpi); | |
769 | BUG_ON(chunk > lpi_chunks); | |
770 | if (test_bit(chunk, lpi_bitmap)) { | |
771 | clear_bit(chunk, lpi_bitmap); | |
772 | } else { | |
773 | pr_err("Bad LPI chunk %d\n", chunk); | |
774 | } | |
775 | } | |
776 | ||
777 | spin_unlock(&lpi_lock); | |
778 | ||
591e5bec MZ |
779 | kfree(map->lpi_map); |
780 | kfree(map->col_map); | |
bf9529f8 | 781 | } |
1ac19ca6 MZ |
782 | |
783 | /* | |
784 | * We allocate 64kB for PROPBASE. That gives us at most 64K LPIs to | |
785 | * deal with (one configuration byte per interrupt). PENDBASE has to | |
786 | * be 64kB aligned (one bit per LPI, plus 8192 bits for SPI/PPI/SGI). | |
787 | */ | |
788 | #define LPI_PROPBASE_SZ SZ_64K | |
789 | #define LPI_PENDBASE_SZ (LPI_PROPBASE_SZ / 8 + SZ_1K) | |
790 | ||
791 | /* | |
792 | * This is how many bits of ID we need, including the useless ones. | |
793 | */ | |
794 | #define LPI_NRBITS ilog2(LPI_PROPBASE_SZ + SZ_8K) | |
795 | ||
796 | #define LPI_PROP_DEFAULT_PRIO 0xa0 | |
797 | ||
798 | static int __init its_alloc_lpi_tables(void) | |
799 | { | |
800 | phys_addr_t paddr; | |
801 | ||
802 | gic_rdists->prop_page = alloc_pages(GFP_NOWAIT, | |
803 | get_order(LPI_PROPBASE_SZ)); | |
804 | if (!gic_rdists->prop_page) { | |
805 | pr_err("Failed to allocate PROPBASE\n"); | |
806 | return -ENOMEM; | |
807 | } | |
808 | ||
809 | paddr = page_to_phys(gic_rdists->prop_page); | |
810 | pr_info("GIC: using LPI property table @%pa\n", &paddr); | |
811 | ||
812 | /* Priority 0xa0, Group-1, disabled */ | |
813 | memset(page_address(gic_rdists->prop_page), | |
814 | LPI_PROP_DEFAULT_PRIO | LPI_PROP_GROUP1, | |
815 | LPI_PROPBASE_SZ); | |
816 | ||
817 | /* Make sure the GIC will observe the written configuration */ | |
328191c0 | 818 | gic_flush_dcache_to_poc(page_address(gic_rdists->prop_page), LPI_PROPBASE_SZ); |
1ac19ca6 MZ |
819 | |
820 | return 0; | |
821 | } | |
822 | ||
823 | static const char *its_base_type_string[] = { | |
824 | [GITS_BASER_TYPE_DEVICE] = "Devices", | |
825 | [GITS_BASER_TYPE_VCPU] = "Virtual CPUs", | |
826 | [GITS_BASER_TYPE_CPU] = "Physical CPUs", | |
827 | [GITS_BASER_TYPE_COLLECTION] = "Interrupt Collections", | |
828 | [GITS_BASER_TYPE_RESERVED5] = "Reserved (5)", | |
829 | [GITS_BASER_TYPE_RESERVED6] = "Reserved (6)", | |
830 | [GITS_BASER_TYPE_RESERVED7] = "Reserved (7)", | |
831 | }; | |
832 | ||
2d81d425 SD |
833 | static u64 its_read_baser(struct its_node *its, struct its_baser *baser) |
834 | { | |
835 | u32 idx = baser - its->tables; | |
836 | ||
0968a619 | 837 | return gits_read_baser(its->base + GITS_BASER + (idx << 3)); |
2d81d425 SD |
838 | } |
839 | ||
840 | static void its_write_baser(struct its_node *its, struct its_baser *baser, | |
841 | u64 val) | |
842 | { | |
843 | u32 idx = baser - its->tables; | |
844 | ||
0968a619 | 845 | gits_write_baser(val, its->base + GITS_BASER + (idx << 3)); |
2d81d425 SD |
846 | baser->val = its_read_baser(its, baser); |
847 | } | |
848 | ||
9347359a | 849 | static int its_setup_baser(struct its_node *its, struct its_baser *baser, |
3faf24ea SD |
850 | u64 cache, u64 shr, u32 psz, u32 order, |
851 | bool indirect) | |
9347359a SD |
852 | { |
853 | u64 val = its_read_baser(its, baser); | |
854 | u64 esz = GITS_BASER_ENTRY_SIZE(val); | |
855 | u64 type = GITS_BASER_TYPE(val); | |
856 | u32 alloc_pages; | |
857 | void *base; | |
858 | u64 tmp; | |
859 | ||
860 | retry_alloc_baser: | |
861 | alloc_pages = (PAGE_ORDER_TO_SIZE(order) / psz); | |
862 | if (alloc_pages > GITS_BASER_PAGES_MAX) { | |
863 | pr_warn("ITS@%pa: %s too large, reduce ITS pages %u->%u\n", | |
864 | &its->phys_base, its_base_type_string[type], | |
865 | alloc_pages, GITS_BASER_PAGES_MAX); | |
866 | alloc_pages = GITS_BASER_PAGES_MAX; | |
867 | order = get_order(GITS_BASER_PAGES_MAX * psz); | |
868 | } | |
869 | ||
870 | base = (void *)__get_free_pages(GFP_KERNEL | __GFP_ZERO, order); | |
871 | if (!base) | |
872 | return -ENOMEM; | |
873 | ||
874 | retry_baser: | |
875 | val = (virt_to_phys(base) | | |
876 | (type << GITS_BASER_TYPE_SHIFT) | | |
877 | ((esz - 1) << GITS_BASER_ENTRY_SIZE_SHIFT) | | |
878 | ((alloc_pages - 1) << GITS_BASER_PAGES_SHIFT) | | |
879 | cache | | |
880 | shr | | |
881 | GITS_BASER_VALID); | |
882 | ||
3faf24ea SD |
883 | val |= indirect ? GITS_BASER_INDIRECT : 0x0; |
884 | ||
9347359a SD |
885 | switch (psz) { |
886 | case SZ_4K: | |
887 | val |= GITS_BASER_PAGE_SIZE_4K; | |
888 | break; | |
889 | case SZ_16K: | |
890 | val |= GITS_BASER_PAGE_SIZE_16K; | |
891 | break; | |
892 | case SZ_64K: | |
893 | val |= GITS_BASER_PAGE_SIZE_64K; | |
894 | break; | |
895 | } | |
896 | ||
897 | its_write_baser(its, baser, val); | |
898 | tmp = baser->val; | |
899 | ||
900 | if ((val ^ tmp) & GITS_BASER_SHAREABILITY_MASK) { | |
901 | /* | |
902 | * Shareability didn't stick. Just use | |
903 | * whatever the read reported, which is likely | |
904 | * to be the only thing this redistributor | |
905 | * supports. If that's zero, make it | |
906 | * non-cacheable as well. | |
907 | */ | |
908 | shr = tmp & GITS_BASER_SHAREABILITY_MASK; | |
909 | if (!shr) { | |
910 | cache = GITS_BASER_nC; | |
328191c0 | 911 | gic_flush_dcache_to_poc(base, PAGE_ORDER_TO_SIZE(order)); |
9347359a SD |
912 | } |
913 | goto retry_baser; | |
914 | } | |
915 | ||
916 | if ((val ^ tmp) & GITS_BASER_PAGE_SIZE_MASK) { | |
917 | /* | |
918 | * Page size didn't stick. Let's try a smaller | |
919 | * size and retry. If we reach 4K, then | |
920 | * something is horribly wrong... | |
921 | */ | |
922 | free_pages((unsigned long)base, order); | |
923 | baser->base = NULL; | |
924 | ||
925 | switch (psz) { | |
926 | case SZ_16K: | |
927 | psz = SZ_4K; | |
928 | goto retry_alloc_baser; | |
929 | case SZ_64K: | |
930 | psz = SZ_16K; | |
931 | goto retry_alloc_baser; | |
932 | } | |
933 | } | |
934 | ||
935 | if (val != tmp) { | |
b11283eb | 936 | pr_err("ITS@%pa: %s doesn't stick: %llx %llx\n", |
9347359a | 937 | &its->phys_base, its_base_type_string[type], |
b11283eb | 938 | val, tmp); |
9347359a SD |
939 | free_pages((unsigned long)base, order); |
940 | return -ENXIO; | |
941 | } | |
942 | ||
943 | baser->order = order; | |
944 | baser->base = base; | |
945 | baser->psz = psz; | |
3faf24ea | 946 | tmp = indirect ? GITS_LVL1_ENTRY_SIZE : esz; |
9347359a | 947 | |
3faf24ea | 948 | pr_info("ITS@%pa: allocated %d %s @%lx (%s, esz %d, psz %dK, shr %d)\n", |
d524eaa2 | 949 | &its->phys_base, (int)(PAGE_ORDER_TO_SIZE(order) / (int)tmp), |
9347359a SD |
950 | its_base_type_string[type], |
951 | (unsigned long)virt_to_phys(base), | |
3faf24ea | 952 | indirect ? "indirect" : "flat", (int)esz, |
9347359a SD |
953 | psz / SZ_1K, (int)shr >> GITS_BASER_SHAREABILITY_SHIFT); |
954 | ||
955 | return 0; | |
956 | } | |
957 | ||
3faf24ea SD |
958 | static bool its_parse_baser_device(struct its_node *its, struct its_baser *baser, |
959 | u32 psz, u32 *order) | |
4b75c459 SD |
960 | { |
961 | u64 esz = GITS_BASER_ENTRY_SIZE(its_read_baser(its, baser)); | |
0b12ffad | 962 | u64 val = GITS_BASER_InnerShareable | GITS_BASER_RaWaWb; |
4b75c459 SD |
963 | u32 ids = its->device_ids; |
964 | u32 new_order = *order; | |
3faf24ea SD |
965 | bool indirect = false; |
966 | ||
967 | /* No need to enable Indirection if memory requirement < (psz*2)bytes */ | |
968 | if ((esz << ids) > (psz * 2)) { | |
969 | /* | |
970 | * Find out whether hw supports a single or two-level table by | |
971 | * table by reading bit at offset '62' after writing '1' to it. | |
972 | */ | |
973 | its_write_baser(its, baser, val | GITS_BASER_INDIRECT); | |
974 | indirect = !!(baser->val & GITS_BASER_INDIRECT); | |
975 | ||
976 | if (indirect) { | |
977 | /* | |
978 | * The size of the lvl2 table is equal to ITS page size | |
979 | * which is 'psz'. For computing lvl1 table size, | |
980 | * subtract ID bits that sparse lvl2 table from 'ids' | |
981 | * which is reported by ITS hardware times lvl1 table | |
982 | * entry size. | |
983 | */ | |
d524eaa2 | 984 | ids -= ilog2(psz / (int)esz); |
3faf24ea SD |
985 | esz = GITS_LVL1_ENTRY_SIZE; |
986 | } | |
987 | } | |
4b75c459 SD |
988 | |
989 | /* | |
990 | * Allocate as many entries as required to fit the | |
991 | * range of device IDs that the ITS can grok... The ID | |
992 | * space being incredibly sparse, this results in a | |
3faf24ea SD |
993 | * massive waste of memory if two-level device table |
994 | * feature is not supported by hardware. | |
4b75c459 SD |
995 | */ |
996 | new_order = max_t(u32, get_order(esz << ids), new_order); | |
997 | if (new_order >= MAX_ORDER) { | |
998 | new_order = MAX_ORDER - 1; | |
d524eaa2 | 999 | ids = ilog2(PAGE_ORDER_TO_SIZE(new_order) / (int)esz); |
4b75c459 SD |
1000 | pr_warn("ITS@%pa: Device Table too large, reduce ids %u->%u\n", |
1001 | &its->phys_base, its->device_ids, ids); | |
1002 | } | |
1003 | ||
1004 | *order = new_order; | |
3faf24ea SD |
1005 | |
1006 | return indirect; | |
4b75c459 SD |
1007 | } |
1008 | ||
1ac19ca6 MZ |
1009 | static void its_free_tables(struct its_node *its) |
1010 | { | |
1011 | int i; | |
1012 | ||
1013 | for (i = 0; i < GITS_BASER_NR_REGS; i++) { | |
1a485f4d SD |
1014 | if (its->tables[i].base) { |
1015 | free_pages((unsigned long)its->tables[i].base, | |
1016 | its->tables[i].order); | |
1017 | its->tables[i].base = NULL; | |
1ac19ca6 MZ |
1018 | } |
1019 | } | |
1020 | } | |
1021 | ||
0e0b0f69 | 1022 | static int its_alloc_tables(struct its_node *its) |
1ac19ca6 | 1023 | { |
589ce5f4 | 1024 | u64 typer = gic_read_typer(its->base + GITS_TYPER); |
9347359a | 1025 | u32 ids = GITS_TYPER_DEVBITS(typer); |
1ac19ca6 | 1026 | u64 shr = GITS_BASER_InnerShareable; |
0b12ffad | 1027 | u64 cache = GITS_BASER_RaWaWb; |
9347359a SD |
1028 | u32 psz = SZ_64K; |
1029 | int err, i; | |
94100970 RR |
1030 | |
1031 | if (its->flags & ITS_FLAGS_WORKAROUND_CAVIUM_22375) { | |
1032 | /* | |
9347359a SD |
1033 | * erratum 22375: only alloc 8MB table size |
1034 | * erratum 24313: ignore memory access type | |
1035 | */ | |
1036 | cache = GITS_BASER_nCnB; | |
1037 | ids = 0x14; /* 20 bits, 8MB */ | |
94100970 | 1038 | } |
1ac19ca6 | 1039 | |
466b7d16 SD |
1040 | its->device_ids = ids; |
1041 | ||
1ac19ca6 | 1042 | for (i = 0; i < GITS_BASER_NR_REGS; i++) { |
2d81d425 SD |
1043 | struct its_baser *baser = its->tables + i; |
1044 | u64 val = its_read_baser(its, baser); | |
1ac19ca6 | 1045 | u64 type = GITS_BASER_TYPE(val); |
9347359a | 1046 | u32 order = get_order(psz); |
3faf24ea | 1047 | bool indirect = false; |
1ac19ca6 MZ |
1048 | |
1049 | if (type == GITS_BASER_TYPE_NONE) | |
1050 | continue; | |
1051 | ||
4b75c459 | 1052 | if (type == GITS_BASER_TYPE_DEVICE) |
3faf24ea | 1053 | indirect = its_parse_baser_device(its, baser, psz, &order); |
f54b97ed | 1054 | |
3faf24ea | 1055 | err = its_setup_baser(its, baser, cache, shr, psz, order, indirect); |
9347359a SD |
1056 | if (err < 0) { |
1057 | its_free_tables(its); | |
1058 | return err; | |
1ac19ca6 MZ |
1059 | } |
1060 | ||
9347359a SD |
1061 | /* Update settings which will be used for next BASERn */ |
1062 | psz = baser->psz; | |
1063 | cache = baser->val & GITS_BASER_CACHEABILITY_MASK; | |
1064 | shr = baser->val & GITS_BASER_SHAREABILITY_MASK; | |
1ac19ca6 MZ |
1065 | } |
1066 | ||
1067 | return 0; | |
1ac19ca6 MZ |
1068 | } |
1069 | ||
1070 | static int its_alloc_collections(struct its_node *its) | |
1071 | { | |
1072 | its->collections = kzalloc(nr_cpu_ids * sizeof(*its->collections), | |
1073 | GFP_KERNEL); | |
1074 | if (!its->collections) | |
1075 | return -ENOMEM; | |
1076 | ||
1077 | return 0; | |
1078 | } | |
1079 | ||
1080 | static void its_cpu_init_lpis(void) | |
1081 | { | |
1082 | void __iomem *rbase = gic_data_rdist_rd_base(); | |
1083 | struct page *pend_page; | |
1084 | u64 val, tmp; | |
1085 | ||
1086 | /* If we didn't allocate the pending table yet, do it now */ | |
1087 | pend_page = gic_data_rdist()->pend_page; | |
1088 | if (!pend_page) { | |
1089 | phys_addr_t paddr; | |
1090 | /* | |
1091 | * The pending pages have to be at least 64kB aligned, | |
1092 | * hence the 'max(LPI_PENDBASE_SZ, SZ_64K)' below. | |
1093 | */ | |
1094 | pend_page = alloc_pages(GFP_NOWAIT | __GFP_ZERO, | |
1095 | get_order(max(LPI_PENDBASE_SZ, SZ_64K))); | |
1096 | if (!pend_page) { | |
1097 | pr_err("Failed to allocate PENDBASE for CPU%d\n", | |
1098 | smp_processor_id()); | |
1099 | return; | |
1100 | } | |
1101 | ||
1102 | /* Make sure the GIC will observe the zero-ed page */ | |
328191c0 | 1103 | gic_flush_dcache_to_poc(page_address(pend_page), LPI_PENDBASE_SZ); |
1ac19ca6 MZ |
1104 | |
1105 | paddr = page_to_phys(pend_page); | |
1106 | pr_info("CPU%d: using LPI pending table @%pa\n", | |
1107 | smp_processor_id(), &paddr); | |
1108 | gic_data_rdist()->pend_page = pend_page; | |
1109 | } | |
1110 | ||
1111 | /* Disable LPIs */ | |
1112 | val = readl_relaxed(rbase + GICR_CTLR); | |
1113 | val &= ~GICR_CTLR_ENABLE_LPIS; | |
1114 | writel_relaxed(val, rbase + GICR_CTLR); | |
1115 | ||
1116 | /* | |
1117 | * Make sure any change to the table is observable by the GIC. | |
1118 | */ | |
1119 | dsb(sy); | |
1120 | ||
1121 | /* set PROPBASE */ | |
1122 | val = (page_to_phys(gic_rdists->prop_page) | | |
1123 | GICR_PROPBASER_InnerShareable | | |
0b12ffad | 1124 | GICR_PROPBASER_RaWaWb | |
1ac19ca6 MZ |
1125 | ((LPI_NRBITS - 1) & GICR_PROPBASER_IDBITS_MASK)); |
1126 | ||
0968a619 VM |
1127 | gicr_write_propbaser(val, rbase + GICR_PROPBASER); |
1128 | tmp = gicr_read_propbaser(rbase + GICR_PROPBASER); | |
1ac19ca6 MZ |
1129 | |
1130 | if ((tmp ^ val) & GICR_PROPBASER_SHAREABILITY_MASK) { | |
241a386c MZ |
1131 | if (!(tmp & GICR_PROPBASER_SHAREABILITY_MASK)) { |
1132 | /* | |
1133 | * The HW reports non-shareable, we must | |
1134 | * remove the cacheability attributes as | |
1135 | * well. | |
1136 | */ | |
1137 | val &= ~(GICR_PROPBASER_SHAREABILITY_MASK | | |
1138 | GICR_PROPBASER_CACHEABILITY_MASK); | |
1139 | val |= GICR_PROPBASER_nC; | |
0968a619 | 1140 | gicr_write_propbaser(val, rbase + GICR_PROPBASER); |
241a386c | 1141 | } |
1ac19ca6 MZ |
1142 | pr_info_once("GIC: using cache flushing for LPI property table\n"); |
1143 | gic_rdists->flags |= RDIST_FLAGS_PROPBASE_NEEDS_FLUSHING; | |
1144 | } | |
1145 | ||
1146 | /* set PENDBASE */ | |
1147 | val = (page_to_phys(pend_page) | | |
4ad3e363 | 1148 | GICR_PENDBASER_InnerShareable | |
0b12ffad | 1149 | GICR_PENDBASER_RaWaWb); |
1ac19ca6 | 1150 | |
0968a619 VM |
1151 | gicr_write_pendbaser(val, rbase + GICR_PENDBASER); |
1152 | tmp = gicr_read_pendbaser(rbase + GICR_PENDBASER); | |
241a386c MZ |
1153 | |
1154 | if (!(tmp & GICR_PENDBASER_SHAREABILITY_MASK)) { | |
1155 | /* | |
1156 | * The HW reports non-shareable, we must remove the | |
1157 | * cacheability attributes as well. | |
1158 | */ | |
1159 | val &= ~(GICR_PENDBASER_SHAREABILITY_MASK | | |
1160 | GICR_PENDBASER_CACHEABILITY_MASK); | |
1161 | val |= GICR_PENDBASER_nC; | |
0968a619 | 1162 | gicr_write_pendbaser(val, rbase + GICR_PENDBASER); |
241a386c | 1163 | } |
1ac19ca6 MZ |
1164 | |
1165 | /* Enable LPIs */ | |
1166 | val = readl_relaxed(rbase + GICR_CTLR); | |
1167 | val |= GICR_CTLR_ENABLE_LPIS; | |
1168 | writel_relaxed(val, rbase + GICR_CTLR); | |
1169 | ||
1170 | /* Make sure the GIC has seen the above */ | |
1171 | dsb(sy); | |
1172 | } | |
1173 | ||
1174 | static void its_cpu_init_collection(void) | |
1175 | { | |
1176 | struct its_node *its; | |
1177 | int cpu; | |
1178 | ||
1179 | spin_lock(&its_lock); | |
1180 | cpu = smp_processor_id(); | |
1181 | ||
1182 | list_for_each_entry(its, &its_nodes, entry) { | |
1183 | u64 target; | |
1184 | ||
fbf8f40e GK |
1185 | /* avoid cross node collections and its mapping */ |
1186 | if (its->flags & ITS_FLAGS_WORKAROUND_CAVIUM_23144) { | |
1187 | struct device_node *cpu_node; | |
1188 | ||
1189 | cpu_node = of_get_cpu_node(cpu, NULL); | |
1190 | if (its->numa_node != NUMA_NO_NODE && | |
1191 | its->numa_node != of_node_to_nid(cpu_node)) | |
1192 | continue; | |
1193 | } | |
1194 | ||
1ac19ca6 MZ |
1195 | /* |
1196 | * We now have to bind each collection to its target | |
1197 | * redistributor. | |
1198 | */ | |
589ce5f4 | 1199 | if (gic_read_typer(its->base + GITS_TYPER) & GITS_TYPER_PTA) { |
1ac19ca6 MZ |
1200 | /* |
1201 | * This ITS wants the physical address of the | |
1202 | * redistributor. | |
1203 | */ | |
1204 | target = gic_data_rdist()->phys_base; | |
1205 | } else { | |
1206 | /* | |
1207 | * This ITS wants a linear CPU number. | |
1208 | */ | |
589ce5f4 | 1209 | target = gic_read_typer(gic_data_rdist_rd_base() + GICR_TYPER); |
263fcd31 | 1210 | target = GICR_TYPER_CPU_NUMBER(target) << 16; |
1ac19ca6 MZ |
1211 | } |
1212 | ||
1213 | /* Perform collection mapping */ | |
1214 | its->collections[cpu].target_address = target; | |
1215 | its->collections[cpu].col_id = cpu; | |
1216 | ||
1217 | its_send_mapc(its, &its->collections[cpu], 1); | |
1218 | its_send_invall(its, &its->collections[cpu]); | |
1219 | } | |
1220 | ||
1221 | spin_unlock(&its_lock); | |
1222 | } | |
84a6a2e7 MZ |
1223 | |
1224 | static struct its_device *its_find_device(struct its_node *its, u32 dev_id) | |
1225 | { | |
1226 | struct its_device *its_dev = NULL, *tmp; | |
3e39e8f5 | 1227 | unsigned long flags; |
84a6a2e7 | 1228 | |
3e39e8f5 | 1229 | raw_spin_lock_irqsave(&its->lock, flags); |
84a6a2e7 MZ |
1230 | |
1231 | list_for_each_entry(tmp, &its->its_device_list, entry) { | |
1232 | if (tmp->device_id == dev_id) { | |
1233 | its_dev = tmp; | |
1234 | break; | |
1235 | } | |
1236 | } | |
1237 | ||
3e39e8f5 | 1238 | raw_spin_unlock_irqrestore(&its->lock, flags); |
84a6a2e7 MZ |
1239 | |
1240 | return its_dev; | |
1241 | } | |
1242 | ||
466b7d16 SD |
1243 | static struct its_baser *its_get_baser(struct its_node *its, u32 type) |
1244 | { | |
1245 | int i; | |
1246 | ||
1247 | for (i = 0; i < GITS_BASER_NR_REGS; i++) { | |
1248 | if (GITS_BASER_TYPE(its->tables[i].val) == type) | |
1249 | return &its->tables[i]; | |
1250 | } | |
1251 | ||
1252 | return NULL; | |
1253 | } | |
1254 | ||
3faf24ea SD |
1255 | static bool its_alloc_device_table(struct its_node *its, u32 dev_id) |
1256 | { | |
1257 | struct its_baser *baser; | |
1258 | struct page *page; | |
1259 | u32 esz, idx; | |
1260 | __le64 *table; | |
1261 | ||
1262 | baser = its_get_baser(its, GITS_BASER_TYPE_DEVICE); | |
1263 | ||
1264 | /* Don't allow device id that exceeds ITS hardware limit */ | |
1265 | if (!baser) | |
1266 | return (ilog2(dev_id) < its->device_ids); | |
1267 | ||
1268 | /* Don't allow device id that exceeds single, flat table limit */ | |
1269 | esz = GITS_BASER_ENTRY_SIZE(baser->val); | |
1270 | if (!(baser->val & GITS_BASER_INDIRECT)) | |
1271 | return (dev_id < (PAGE_ORDER_TO_SIZE(baser->order) / esz)); | |
1272 | ||
1273 | /* Compute 1st level table index & check if that exceeds table limit */ | |
1274 | idx = dev_id >> ilog2(baser->psz / esz); | |
1275 | if (idx >= (PAGE_ORDER_TO_SIZE(baser->order) / GITS_LVL1_ENTRY_SIZE)) | |
1276 | return false; | |
1277 | ||
1278 | table = baser->base; | |
1279 | ||
1280 | /* Allocate memory for 2nd level table */ | |
1281 | if (!table[idx]) { | |
1282 | page = alloc_pages(GFP_KERNEL | __GFP_ZERO, get_order(baser->psz)); | |
1283 | if (!page) | |
1284 | return false; | |
1285 | ||
1286 | /* Flush Lvl2 table to PoC if hw doesn't support coherency */ | |
1287 | if (!(baser->val & GITS_BASER_SHAREABILITY_MASK)) | |
328191c0 | 1288 | gic_flush_dcache_to_poc(page_address(page), baser->psz); |
3faf24ea SD |
1289 | |
1290 | table[idx] = cpu_to_le64(page_to_phys(page) | GITS_BASER_VALID); | |
1291 | ||
1292 | /* Flush Lvl1 entry to PoC if hw doesn't support coherency */ | |
1293 | if (!(baser->val & GITS_BASER_SHAREABILITY_MASK)) | |
328191c0 | 1294 | gic_flush_dcache_to_poc(table + idx, GITS_LVL1_ENTRY_SIZE); |
3faf24ea SD |
1295 | |
1296 | /* Ensure updated table contents are visible to ITS hardware */ | |
1297 | dsb(sy); | |
1298 | } | |
1299 | ||
1300 | return true; | |
1301 | } | |
1302 | ||
84a6a2e7 MZ |
1303 | static struct its_device *its_create_device(struct its_node *its, u32 dev_id, |
1304 | int nvecs) | |
1305 | { | |
1306 | struct its_device *dev; | |
1307 | unsigned long *lpi_map; | |
3e39e8f5 | 1308 | unsigned long flags; |
591e5bec | 1309 | u16 *col_map = NULL; |
84a6a2e7 MZ |
1310 | void *itt; |
1311 | int lpi_base; | |
1312 | int nr_lpis; | |
c8481267 | 1313 | int nr_ites; |
84a6a2e7 MZ |
1314 | int sz; |
1315 | ||
3faf24ea | 1316 | if (!its_alloc_device_table(its, dev_id)) |
466b7d16 SD |
1317 | return NULL; |
1318 | ||
84a6a2e7 | 1319 | dev = kzalloc(sizeof(*dev), GFP_KERNEL); |
c8481267 MZ |
1320 | /* |
1321 | * At least one bit of EventID is being used, hence a minimum | |
1322 | * of two entries. No, the architecture doesn't let you | |
1323 | * express an ITT with a single entry. | |
1324 | */ | |
96555c47 | 1325 | nr_ites = max(2UL, roundup_pow_of_two(nvecs)); |
c8481267 | 1326 | sz = nr_ites * its->ite_size; |
84a6a2e7 | 1327 | sz = max(sz, ITS_ITT_ALIGN) + ITS_ITT_ALIGN - 1; |
6c834125 | 1328 | itt = kzalloc(sz, GFP_KERNEL); |
84a6a2e7 | 1329 | lpi_map = its_lpi_alloc_chunks(nvecs, &lpi_base, &nr_lpis); |
591e5bec MZ |
1330 | if (lpi_map) |
1331 | col_map = kzalloc(sizeof(*col_map) * nr_lpis, GFP_KERNEL); | |
84a6a2e7 | 1332 | |
591e5bec | 1333 | if (!dev || !itt || !lpi_map || !col_map) { |
84a6a2e7 MZ |
1334 | kfree(dev); |
1335 | kfree(itt); | |
1336 | kfree(lpi_map); | |
591e5bec | 1337 | kfree(col_map); |
84a6a2e7 MZ |
1338 | return NULL; |
1339 | } | |
1340 | ||
328191c0 | 1341 | gic_flush_dcache_to_poc(itt, sz); |
5a9a8915 | 1342 | |
84a6a2e7 MZ |
1343 | dev->its = its; |
1344 | dev->itt = itt; | |
c8481267 | 1345 | dev->nr_ites = nr_ites; |
591e5bec MZ |
1346 | dev->event_map.lpi_map = lpi_map; |
1347 | dev->event_map.col_map = col_map; | |
1348 | dev->event_map.lpi_base = lpi_base; | |
1349 | dev->event_map.nr_lpis = nr_lpis; | |
84a6a2e7 MZ |
1350 | dev->device_id = dev_id; |
1351 | INIT_LIST_HEAD(&dev->entry); | |
1352 | ||
3e39e8f5 | 1353 | raw_spin_lock_irqsave(&its->lock, flags); |
84a6a2e7 | 1354 | list_add(&dev->entry, &its->its_device_list); |
3e39e8f5 | 1355 | raw_spin_unlock_irqrestore(&its->lock, flags); |
84a6a2e7 | 1356 | |
84a6a2e7 MZ |
1357 | /* Map device to its ITT */ |
1358 | its_send_mapd(dev, 1); | |
1359 | ||
1360 | return dev; | |
1361 | } | |
1362 | ||
1363 | static void its_free_device(struct its_device *its_dev) | |
1364 | { | |
3e39e8f5 MZ |
1365 | unsigned long flags; |
1366 | ||
1367 | raw_spin_lock_irqsave(&its_dev->its->lock, flags); | |
84a6a2e7 | 1368 | list_del(&its_dev->entry); |
3e39e8f5 | 1369 | raw_spin_unlock_irqrestore(&its_dev->its->lock, flags); |
84a6a2e7 MZ |
1370 | kfree(its_dev->itt); |
1371 | kfree(its_dev); | |
1372 | } | |
b48ac83d MZ |
1373 | |
1374 | static int its_alloc_device_irq(struct its_device *dev, irq_hw_number_t *hwirq) | |
1375 | { | |
1376 | int idx; | |
1377 | ||
591e5bec MZ |
1378 | idx = find_first_zero_bit(dev->event_map.lpi_map, |
1379 | dev->event_map.nr_lpis); | |
1380 | if (idx == dev->event_map.nr_lpis) | |
b48ac83d MZ |
1381 | return -ENOSPC; |
1382 | ||
591e5bec MZ |
1383 | *hwirq = dev->event_map.lpi_base + idx; |
1384 | set_bit(idx, dev->event_map.lpi_map); | |
b48ac83d | 1385 | |
b48ac83d MZ |
1386 | return 0; |
1387 | } | |
1388 | ||
54456db9 MZ |
1389 | static int its_msi_prepare(struct irq_domain *domain, struct device *dev, |
1390 | int nvec, msi_alloc_info_t *info) | |
e8137f4f | 1391 | { |
b48ac83d | 1392 | struct its_node *its; |
b48ac83d | 1393 | struct its_device *its_dev; |
54456db9 MZ |
1394 | struct msi_domain_info *msi_info; |
1395 | u32 dev_id; | |
1396 | ||
1397 | /* | |
1398 | * We ignore "dev" entierely, and rely on the dev_id that has | |
1399 | * been passed via the scratchpad. This limits this domain's | |
1400 | * usefulness to upper layers that definitely know that they | |
1401 | * are built on top of the ITS. | |
1402 | */ | |
1403 | dev_id = info->scratchpad[0].ul; | |
1404 | ||
1405 | msi_info = msi_get_domain_info(domain); | |
1406 | its = msi_info->data; | |
e8137f4f | 1407 | |
f130420e | 1408 | its_dev = its_find_device(its, dev_id); |
e8137f4f MZ |
1409 | if (its_dev) { |
1410 | /* | |
1411 | * We already have seen this ID, probably through | |
1412 | * another alias (PCI bridge of some sort). No need to | |
1413 | * create the device. | |
1414 | */ | |
f130420e | 1415 | pr_debug("Reusing ITT for devID %x\n", dev_id); |
e8137f4f MZ |
1416 | goto out; |
1417 | } | |
b48ac83d | 1418 | |
f130420e | 1419 | its_dev = its_create_device(its, dev_id, nvec); |
b48ac83d MZ |
1420 | if (!its_dev) |
1421 | return -ENOMEM; | |
1422 | ||
f130420e | 1423 | pr_debug("ITT %d entries, %d bits\n", nvec, ilog2(nvec)); |
e8137f4f | 1424 | out: |
b48ac83d | 1425 | info->scratchpad[0].ptr = its_dev; |
b48ac83d MZ |
1426 | return 0; |
1427 | } | |
1428 | ||
54456db9 MZ |
1429 | static struct msi_domain_ops its_msi_domain_ops = { |
1430 | .msi_prepare = its_msi_prepare, | |
1431 | }; | |
1432 | ||
b48ac83d MZ |
1433 | static int its_irq_gic_domain_alloc(struct irq_domain *domain, |
1434 | unsigned int virq, | |
1435 | irq_hw_number_t hwirq) | |
1436 | { | |
f833f57f MZ |
1437 | struct irq_fwspec fwspec; |
1438 | ||
1439 | if (irq_domain_get_of_node(domain->parent)) { | |
1440 | fwspec.fwnode = domain->parent->fwnode; | |
1441 | fwspec.param_count = 3; | |
1442 | fwspec.param[0] = GIC_IRQ_TYPE_LPI; | |
1443 | fwspec.param[1] = hwirq; | |
1444 | fwspec.param[2] = IRQ_TYPE_EDGE_RISING; | |
3f010cf1 TN |
1445 | } else if (is_fwnode_irqchip(domain->parent->fwnode)) { |
1446 | fwspec.fwnode = domain->parent->fwnode; | |
1447 | fwspec.param_count = 2; | |
1448 | fwspec.param[0] = hwirq; | |
1449 | fwspec.param[1] = IRQ_TYPE_EDGE_RISING; | |
f833f57f MZ |
1450 | } else { |
1451 | return -EINVAL; | |
1452 | } | |
b48ac83d | 1453 | |
f833f57f | 1454 | return irq_domain_alloc_irqs_parent(domain, virq, 1, &fwspec); |
b48ac83d MZ |
1455 | } |
1456 | ||
1457 | static int its_irq_domain_alloc(struct irq_domain *domain, unsigned int virq, | |
1458 | unsigned int nr_irqs, void *args) | |
1459 | { | |
1460 | msi_alloc_info_t *info = args; | |
1461 | struct its_device *its_dev = info->scratchpad[0].ptr; | |
1462 | irq_hw_number_t hwirq; | |
1463 | int err; | |
1464 | int i; | |
1465 | ||
1466 | for (i = 0; i < nr_irqs; i++) { | |
1467 | err = its_alloc_device_irq(its_dev, &hwirq); | |
1468 | if (err) | |
1469 | return err; | |
1470 | ||
1471 | err = its_irq_gic_domain_alloc(domain, virq + i, hwirq); | |
1472 | if (err) | |
1473 | return err; | |
1474 | ||
1475 | irq_domain_set_hwirq_and_chip(domain, virq + i, | |
1476 | hwirq, &its_irq_chip, its_dev); | |
f130420e MZ |
1477 | pr_debug("ID:%d pID:%d vID:%d\n", |
1478 | (int)(hwirq - its_dev->event_map.lpi_base), | |
1479 | (int) hwirq, virq + i); | |
b48ac83d MZ |
1480 | } |
1481 | ||
1482 | return 0; | |
1483 | } | |
1484 | ||
aca268df MZ |
1485 | static void its_irq_domain_activate(struct irq_domain *domain, |
1486 | struct irq_data *d) | |
1487 | { | |
1488 | struct its_device *its_dev = irq_data_get_irq_chip_data(d); | |
1489 | u32 event = its_get_event_id(d); | |
fbf8f40e GK |
1490 | const struct cpumask *cpu_mask = cpu_online_mask; |
1491 | ||
1492 | /* get the cpu_mask of local node */ | |
1493 | if (its_dev->its->numa_node >= 0) | |
1494 | cpu_mask = cpumask_of_node(its_dev->its->numa_node); | |
aca268df | 1495 | |
591e5bec | 1496 | /* Bind the LPI to the first possible CPU */ |
fbf8f40e | 1497 | its_dev->event_map.col_map[event] = cpumask_first(cpu_mask); |
591e5bec | 1498 | |
aca268df MZ |
1499 | /* Map the GIC IRQ and event to the device */ |
1500 | its_send_mapvi(its_dev, d->hwirq, event); | |
1501 | } | |
1502 | ||
1503 | static void its_irq_domain_deactivate(struct irq_domain *domain, | |
1504 | struct irq_data *d) | |
1505 | { | |
1506 | struct its_device *its_dev = irq_data_get_irq_chip_data(d); | |
1507 | u32 event = its_get_event_id(d); | |
1508 | ||
1509 | /* Stop the delivery of interrupts */ | |
1510 | its_send_discard(its_dev, event); | |
1511 | } | |
1512 | ||
b48ac83d MZ |
1513 | static void its_irq_domain_free(struct irq_domain *domain, unsigned int virq, |
1514 | unsigned int nr_irqs) | |
1515 | { | |
1516 | struct irq_data *d = irq_domain_get_irq_data(domain, virq); | |
1517 | struct its_device *its_dev = irq_data_get_irq_chip_data(d); | |
1518 | int i; | |
1519 | ||
1520 | for (i = 0; i < nr_irqs; i++) { | |
1521 | struct irq_data *data = irq_domain_get_irq_data(domain, | |
1522 | virq + i); | |
aca268df | 1523 | u32 event = its_get_event_id(data); |
b48ac83d MZ |
1524 | |
1525 | /* Mark interrupt index as unused */ | |
591e5bec | 1526 | clear_bit(event, its_dev->event_map.lpi_map); |
b48ac83d MZ |
1527 | |
1528 | /* Nuke the entry in the domain */ | |
2da39949 | 1529 | irq_domain_reset_irq_data(data); |
b48ac83d MZ |
1530 | } |
1531 | ||
1532 | /* If all interrupts have been freed, start mopping the floor */ | |
591e5bec MZ |
1533 | if (bitmap_empty(its_dev->event_map.lpi_map, |
1534 | its_dev->event_map.nr_lpis)) { | |
1535 | its_lpi_free(&its_dev->event_map); | |
b48ac83d MZ |
1536 | |
1537 | /* Unmap device/itt */ | |
1538 | its_send_mapd(its_dev, 0); | |
1539 | its_free_device(its_dev); | |
1540 | } | |
1541 | ||
1542 | irq_domain_free_irqs_parent(domain, virq, nr_irqs); | |
1543 | } | |
1544 | ||
1545 | static const struct irq_domain_ops its_domain_ops = { | |
1546 | .alloc = its_irq_domain_alloc, | |
1547 | .free = its_irq_domain_free, | |
aca268df MZ |
1548 | .activate = its_irq_domain_activate, |
1549 | .deactivate = its_irq_domain_deactivate, | |
b48ac83d | 1550 | }; |
4c21f3c2 | 1551 | |
4559fbb3 YW |
1552 | static int its_force_quiescent(void __iomem *base) |
1553 | { | |
1554 | u32 count = 1000000; /* 1s */ | |
1555 | u32 val; | |
1556 | ||
1557 | val = readl_relaxed(base + GITS_CTLR); | |
7611da86 DD |
1558 | /* |
1559 | * GIC architecture specification requires the ITS to be both | |
1560 | * disabled and quiescent for writes to GITS_BASER<n> or | |
1561 | * GITS_CBASER to not have UNPREDICTABLE results. | |
1562 | */ | |
1563 | if ((val & GITS_CTLR_QUIESCENT) && !(val & GITS_CTLR_ENABLE)) | |
4559fbb3 YW |
1564 | return 0; |
1565 | ||
1566 | /* Disable the generation of all interrupts to this ITS */ | |
1567 | val &= ~GITS_CTLR_ENABLE; | |
1568 | writel_relaxed(val, base + GITS_CTLR); | |
1569 | ||
1570 | /* Poll GITS_CTLR and wait until ITS becomes quiescent */ | |
1571 | while (1) { | |
1572 | val = readl_relaxed(base + GITS_CTLR); | |
1573 | if (val & GITS_CTLR_QUIESCENT) | |
1574 | return 0; | |
1575 | ||
1576 | count--; | |
1577 | if (!count) | |
1578 | return -EBUSY; | |
1579 | ||
1580 | cpu_relax(); | |
1581 | udelay(1); | |
1582 | } | |
1583 | } | |
1584 | ||
94100970 RR |
1585 | static void __maybe_unused its_enable_quirk_cavium_22375(void *data) |
1586 | { | |
1587 | struct its_node *its = data; | |
1588 | ||
1589 | its->flags |= ITS_FLAGS_WORKAROUND_CAVIUM_22375; | |
1590 | } | |
1591 | ||
fbf8f40e GK |
1592 | static void __maybe_unused its_enable_quirk_cavium_23144(void *data) |
1593 | { | |
1594 | struct its_node *its = data; | |
1595 | ||
1596 | its->flags |= ITS_FLAGS_WORKAROUND_CAVIUM_23144; | |
1597 | } | |
1598 | ||
cc89544a SD |
1599 | static void __maybe_unused its_enable_quirk_qdf2400_e0065(void *data) |
1600 | { | |
1601 | struct its_node *its = data; | |
1602 | ||
1603 | /* On QDF2400, the size of the ITE is 16Bytes */ | |
1604 | its->ite_size = 16; | |
1605 | } | |
1606 | ||
67510cca | 1607 | static const struct gic_quirk its_quirks[] = { |
94100970 RR |
1608 | #ifdef CONFIG_CAVIUM_ERRATUM_22375 |
1609 | { | |
1610 | .desc = "ITS: Cavium errata 22375, 24313", | |
1611 | .iidr = 0xa100034c, /* ThunderX pass 1.x */ | |
1612 | .mask = 0xffff0fff, | |
1613 | .init = its_enable_quirk_cavium_22375, | |
1614 | }, | |
fbf8f40e GK |
1615 | #endif |
1616 | #ifdef CONFIG_CAVIUM_ERRATUM_23144 | |
1617 | { | |
1618 | .desc = "ITS: Cavium erratum 23144", | |
1619 | .iidr = 0xa100034c, /* ThunderX pass 1.x */ | |
1620 | .mask = 0xffff0fff, | |
1621 | .init = its_enable_quirk_cavium_23144, | |
1622 | }, | |
cc89544a SD |
1623 | #endif |
1624 | #ifdef CONFIG_QCOM_QDF2400_ERRATUM_0065 | |
1625 | { | |
1626 | .desc = "ITS: QDF2400 erratum 0065", | |
1627 | .iidr = 0x00001070, /* QDF2400 ITS rev 1.x */ | |
1628 | .mask = 0xffffffff, | |
1629 | .init = its_enable_quirk_qdf2400_e0065, | |
1630 | }, | |
94100970 | 1631 | #endif |
67510cca RR |
1632 | { |
1633 | } | |
1634 | }; | |
1635 | ||
1636 | static void its_enable_quirks(struct its_node *its) | |
1637 | { | |
1638 | u32 iidr = readl_relaxed(its->base + GITS_IIDR); | |
1639 | ||
1640 | gic_enable_quirks(iidr, its_quirks, its); | |
1641 | } | |
1642 | ||
db40f0a7 | 1643 | static int its_init_domain(struct fwnode_handle *handle, struct its_node *its) |
d14ae5e6 TN |
1644 | { |
1645 | struct irq_domain *inner_domain; | |
1646 | struct msi_domain_info *info; | |
1647 | ||
1648 | info = kzalloc(sizeof(*info), GFP_KERNEL); | |
1649 | if (!info) | |
1650 | return -ENOMEM; | |
1651 | ||
db40f0a7 | 1652 | inner_domain = irq_domain_create_tree(handle, &its_domain_ops, its); |
d14ae5e6 TN |
1653 | if (!inner_domain) { |
1654 | kfree(info); | |
1655 | return -ENOMEM; | |
1656 | } | |
1657 | ||
db40f0a7 | 1658 | inner_domain->parent = its_parent; |
d14ae5e6 | 1659 | inner_domain->bus_token = DOMAIN_BUS_NEXUS; |
6e8619c5 | 1660 | inner_domain->flags |= IRQ_DOMAIN_FLAG_MSI_REMAP; |
d14ae5e6 TN |
1661 | info->ops = &its_msi_domain_ops; |
1662 | info->data = its; | |
1663 | inner_domain->host_data = info; | |
1664 | ||
1665 | return 0; | |
1666 | } | |
1667 | ||
db40f0a7 TN |
1668 | static int __init its_probe_one(struct resource *res, |
1669 | struct fwnode_handle *handle, int numa_node) | |
4c21f3c2 | 1670 | { |
4c21f3c2 MZ |
1671 | struct its_node *its; |
1672 | void __iomem *its_base; | |
1673 | u32 val; | |
1674 | u64 baser, tmp; | |
1675 | int err; | |
1676 | ||
db40f0a7 | 1677 | its_base = ioremap(res->start, resource_size(res)); |
4c21f3c2 | 1678 | if (!its_base) { |
db40f0a7 | 1679 | pr_warn("ITS@%pa: Unable to map ITS registers\n", &res->start); |
4c21f3c2 MZ |
1680 | return -ENOMEM; |
1681 | } | |
1682 | ||
1683 | val = readl_relaxed(its_base + GITS_PIDR2) & GIC_PIDR2_ARCH_MASK; | |
1684 | if (val != 0x30 && val != 0x40) { | |
db40f0a7 | 1685 | pr_warn("ITS@%pa: No ITS detected, giving up\n", &res->start); |
4c21f3c2 MZ |
1686 | err = -ENODEV; |
1687 | goto out_unmap; | |
1688 | } | |
1689 | ||
4559fbb3 YW |
1690 | err = its_force_quiescent(its_base); |
1691 | if (err) { | |
db40f0a7 | 1692 | pr_warn("ITS@%pa: Failed to quiesce, giving up\n", &res->start); |
4559fbb3 YW |
1693 | goto out_unmap; |
1694 | } | |
1695 | ||
db40f0a7 | 1696 | pr_info("ITS %pR\n", res); |
4c21f3c2 MZ |
1697 | |
1698 | its = kzalloc(sizeof(*its), GFP_KERNEL); | |
1699 | if (!its) { | |
1700 | err = -ENOMEM; | |
1701 | goto out_unmap; | |
1702 | } | |
1703 | ||
1704 | raw_spin_lock_init(&its->lock); | |
1705 | INIT_LIST_HEAD(&its->entry); | |
1706 | INIT_LIST_HEAD(&its->its_device_list); | |
1707 | its->base = its_base; | |
db40f0a7 | 1708 | its->phys_base = res->start; |
589ce5f4 | 1709 | its->ite_size = ((gic_read_typer(its_base + GITS_TYPER) >> 4) & 0xf) + 1; |
db40f0a7 | 1710 | its->numa_node = numa_node; |
4c21f3c2 MZ |
1711 | |
1712 | its->cmd_base = kzalloc(ITS_CMD_QUEUE_SZ, GFP_KERNEL); | |
1713 | if (!its->cmd_base) { | |
1714 | err = -ENOMEM; | |
1715 | goto out_free_its; | |
1716 | } | |
1717 | its->cmd_write = its->cmd_base; | |
1718 | ||
67510cca RR |
1719 | its_enable_quirks(its); |
1720 | ||
0e0b0f69 | 1721 | err = its_alloc_tables(its); |
4c21f3c2 MZ |
1722 | if (err) |
1723 | goto out_free_cmd; | |
1724 | ||
1725 | err = its_alloc_collections(its); | |
1726 | if (err) | |
1727 | goto out_free_tables; | |
1728 | ||
1729 | baser = (virt_to_phys(its->cmd_base) | | |
0b12ffad | 1730 | GITS_CBASER_RaWaWb | |
4c21f3c2 MZ |
1731 | GITS_CBASER_InnerShareable | |
1732 | (ITS_CMD_QUEUE_SZ / SZ_4K - 1) | | |
1733 | GITS_CBASER_VALID); | |
1734 | ||
0968a619 VM |
1735 | gits_write_cbaser(baser, its->base + GITS_CBASER); |
1736 | tmp = gits_read_cbaser(its->base + GITS_CBASER); | |
4c21f3c2 | 1737 | |
4ad3e363 | 1738 | if ((tmp ^ baser) & GITS_CBASER_SHAREABILITY_MASK) { |
241a386c MZ |
1739 | if (!(tmp & GITS_CBASER_SHAREABILITY_MASK)) { |
1740 | /* | |
1741 | * The HW reports non-shareable, we must | |
1742 | * remove the cacheability attributes as | |
1743 | * well. | |
1744 | */ | |
1745 | baser &= ~(GITS_CBASER_SHAREABILITY_MASK | | |
1746 | GITS_CBASER_CACHEABILITY_MASK); | |
1747 | baser |= GITS_CBASER_nC; | |
0968a619 | 1748 | gits_write_cbaser(baser, its->base + GITS_CBASER); |
241a386c | 1749 | } |
4c21f3c2 MZ |
1750 | pr_info("ITS: using cache flushing for cmd queue\n"); |
1751 | its->flags |= ITS_FLAGS_CMDQ_NEEDS_FLUSHING; | |
1752 | } | |
1753 | ||
0968a619 | 1754 | gits_write_cwriter(0, its->base + GITS_CWRITER); |
241a386c MZ |
1755 | writel_relaxed(GITS_CTLR_ENABLE, its->base + GITS_CTLR); |
1756 | ||
db40f0a7 | 1757 | err = its_init_domain(handle, its); |
d14ae5e6 TN |
1758 | if (err) |
1759 | goto out_free_tables; | |
4c21f3c2 MZ |
1760 | |
1761 | spin_lock(&its_lock); | |
1762 | list_add(&its->entry, &its_nodes); | |
1763 | spin_unlock(&its_lock); | |
1764 | ||
1765 | return 0; | |
1766 | ||
4c21f3c2 MZ |
1767 | out_free_tables: |
1768 | its_free_tables(its); | |
1769 | out_free_cmd: | |
1770 | kfree(its->cmd_base); | |
1771 | out_free_its: | |
1772 | kfree(its); | |
1773 | out_unmap: | |
1774 | iounmap(its_base); | |
db40f0a7 | 1775 | pr_err("ITS@%pa: failed probing (%d)\n", &res->start, err); |
4c21f3c2 MZ |
1776 | return err; |
1777 | } | |
1778 | ||
1779 | static bool gic_rdists_supports_plpis(void) | |
1780 | { | |
589ce5f4 | 1781 | return !!(gic_read_typer(gic_data_rdist_rd_base() + GICR_TYPER) & GICR_TYPER_PLPIS); |
4c21f3c2 MZ |
1782 | } |
1783 | ||
1784 | int its_cpu_init(void) | |
1785 | { | |
4c21f3c2 | 1786 | if (!list_empty(&its_nodes)) { |
16acae72 VM |
1787 | if (!gic_rdists_supports_plpis()) { |
1788 | pr_info("CPU%d: LPIs not supported\n", smp_processor_id()); | |
1789 | return -ENXIO; | |
1790 | } | |
4c21f3c2 MZ |
1791 | its_cpu_init_lpis(); |
1792 | its_cpu_init_collection(); | |
1793 | } | |
1794 | ||
1795 | return 0; | |
1796 | } | |
1797 | ||
1798 | static struct of_device_id its_device_id[] = { | |
1799 | { .compatible = "arm,gic-v3-its", }, | |
1800 | {}, | |
1801 | }; | |
1802 | ||
db40f0a7 | 1803 | static int __init its_of_probe(struct device_node *node) |
4c21f3c2 MZ |
1804 | { |
1805 | struct device_node *np; | |
db40f0a7 | 1806 | struct resource res; |
4c21f3c2 MZ |
1807 | |
1808 | for (np = of_find_matching_node(node, its_device_id); np; | |
1809 | np = of_find_matching_node(np, its_device_id)) { | |
d14ae5e6 TN |
1810 | if (!of_property_read_bool(np, "msi-controller")) { |
1811 | pr_warn("%s: no msi-controller property, ITS ignored\n", | |
1812 | np->full_name); | |
1813 | continue; | |
1814 | } | |
1815 | ||
db40f0a7 TN |
1816 | if (of_address_to_resource(np, 0, &res)) { |
1817 | pr_warn("%s: no regs?\n", np->full_name); | |
1818 | continue; | |
1819 | } | |
1820 | ||
1821 | its_probe_one(&res, &np->fwnode, of_node_to_nid(np)); | |
4c21f3c2 | 1822 | } |
db40f0a7 TN |
1823 | return 0; |
1824 | } | |
1825 | ||
3f010cf1 TN |
1826 | #ifdef CONFIG_ACPI |
1827 | ||
1828 | #define ACPI_GICV3_ITS_MEM_SIZE (SZ_128K) | |
1829 | ||
1830 | static int __init gic_acpi_parse_madt_its(struct acpi_subtable_header *header, | |
1831 | const unsigned long end) | |
1832 | { | |
1833 | struct acpi_madt_generic_translator *its_entry; | |
1834 | struct fwnode_handle *dom_handle; | |
1835 | struct resource res; | |
1836 | int err; | |
1837 | ||
1838 | its_entry = (struct acpi_madt_generic_translator *)header; | |
1839 | memset(&res, 0, sizeof(res)); | |
1840 | res.start = its_entry->base_address; | |
1841 | res.end = its_entry->base_address + ACPI_GICV3_ITS_MEM_SIZE - 1; | |
1842 | res.flags = IORESOURCE_MEM; | |
1843 | ||
1844 | dom_handle = irq_domain_alloc_fwnode((void *)its_entry->base_address); | |
1845 | if (!dom_handle) { | |
1846 | pr_err("ITS@%pa: Unable to allocate GICv3 ITS domain token\n", | |
1847 | &res.start); | |
1848 | return -ENOMEM; | |
1849 | } | |
1850 | ||
1851 | err = iort_register_domain_token(its_entry->translation_id, dom_handle); | |
1852 | if (err) { | |
1853 | pr_err("ITS@%pa: Unable to register GICv3 ITS domain token (ITS ID %d) to IORT\n", | |
1854 | &res.start, its_entry->translation_id); | |
1855 | goto dom_err; | |
1856 | } | |
1857 | ||
1858 | err = its_probe_one(&res, dom_handle, NUMA_NO_NODE); | |
1859 | if (!err) | |
1860 | return 0; | |
1861 | ||
1862 | iort_deregister_domain_token(its_entry->translation_id); | |
1863 | dom_err: | |
1864 | irq_domain_free_fwnode(dom_handle); | |
1865 | return err; | |
1866 | } | |
1867 | ||
1868 | static void __init its_acpi_probe(void) | |
1869 | { | |
1870 | acpi_table_parse_madt(ACPI_MADT_TYPE_GENERIC_TRANSLATOR, | |
1871 | gic_acpi_parse_madt_its, 0); | |
1872 | } | |
1873 | #else | |
1874 | static void __init its_acpi_probe(void) { } | |
1875 | #endif | |
1876 | ||
db40f0a7 TN |
1877 | int __init its_init(struct fwnode_handle *handle, struct rdists *rdists, |
1878 | struct irq_domain *parent_domain) | |
1879 | { | |
1880 | struct device_node *of_node; | |
1881 | ||
1882 | its_parent = parent_domain; | |
1883 | of_node = to_of_node(handle); | |
1884 | if (of_node) | |
1885 | its_of_probe(of_node); | |
1886 | else | |
3f010cf1 | 1887 | its_acpi_probe(); |
4c21f3c2 MZ |
1888 | |
1889 | if (list_empty(&its_nodes)) { | |
1890 | pr_warn("ITS: No ITS available, not enabling LPIs\n"); | |
1891 | return -ENXIO; | |
1892 | } | |
1893 | ||
1894 | gic_rdists = rdists; | |
4c21f3c2 MZ |
1895 | its_alloc_lpi_tables(); |
1896 | its_lpi_init(rdists->id_bits); | |
1897 | ||
1898 | return 0; | |
1899 | } |