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cc2d3216 | 1 | /* |
d7276b80 | 2 | * Copyright (C) 2013-2017 ARM Limited, All Rights Reserved. |
cc2d3216 MZ |
3 | * Author: Marc Zyngier <marc.zyngier@arm.com> |
4 | * | |
5 | * This program is free software; you can redistribute it and/or modify | |
6 | * it under the terms of the GNU General Public License version 2 as | |
7 | * published by the Free Software Foundation. | |
8 | * | |
9 | * This program is distributed in the hope that it will be useful, | |
10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
12 | * GNU General Public License for more details. | |
13 | * | |
14 | * You should have received a copy of the GNU General Public License | |
15 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | |
16 | */ | |
17 | ||
3f010cf1 | 18 | #include <linux/acpi.h> |
8d3554b8 | 19 | #include <linux/acpi_iort.h> |
cc2d3216 MZ |
20 | #include <linux/bitmap.h> |
21 | #include <linux/cpu.h> | |
22 | #include <linux/delay.h> | |
44bb7e24 | 23 | #include <linux/dma-iommu.h> |
cc2d3216 | 24 | #include <linux/interrupt.h> |
3f010cf1 | 25 | #include <linux/irqdomain.h> |
cc2d3216 MZ |
26 | #include <linux/log2.h> |
27 | #include <linux/mm.h> | |
28 | #include <linux/msi.h> | |
29 | #include <linux/of.h> | |
30 | #include <linux/of_address.h> | |
31 | #include <linux/of_irq.h> | |
32 | #include <linux/of_pci.h> | |
33 | #include <linux/of_platform.h> | |
34 | #include <linux/percpu.h> | |
35 | #include <linux/slab.h> | |
36 | ||
41a83e06 | 37 | #include <linux/irqchip.h> |
cc2d3216 | 38 | #include <linux/irqchip/arm-gic-v3.h> |
c808eea8 | 39 | #include <linux/irqchip/arm-gic-v4.h> |
cc2d3216 | 40 | |
cc2d3216 MZ |
41 | #include <asm/cputype.h> |
42 | #include <asm/exception.h> | |
43 | ||
67510cca RR |
44 | #include "irq-gic-common.h" |
45 | ||
94100970 RR |
46 | #define ITS_FLAGS_CMDQ_NEEDS_FLUSHING (1ULL << 0) |
47 | #define ITS_FLAGS_WORKAROUND_CAVIUM_22375 (1ULL << 1) | |
fbf8f40e | 48 | #define ITS_FLAGS_WORKAROUND_CAVIUM_23144 (1ULL << 2) |
cc2d3216 | 49 | |
c48ed51c MZ |
50 | #define RDIST_FLAGS_PROPBASE_NEEDS_FLUSHING (1 << 0) |
51 | ||
a13b0404 MZ |
52 | static u32 lpi_id_bits; |
53 | ||
54 | /* | |
55 | * We allocate memory for PROPBASE to cover 2 ^ lpi_id_bits LPIs to | |
56 | * deal with (one configuration byte per interrupt). PENDBASE has to | |
57 | * be 64kB aligned (one bit per LPI, plus 8192 bits for SPI/PPI/SGI). | |
58 | */ | |
59 | #define LPI_NRBITS lpi_id_bits | |
60 | #define LPI_PROPBASE_SZ ALIGN(BIT(LPI_NRBITS), SZ_64K) | |
61 | #define LPI_PENDBASE_SZ ALIGN(BIT(LPI_NRBITS) / 8, SZ_64K) | |
62 | ||
63 | #define LPI_PROP_DEFAULT_PRIO 0xa0 | |
64 | ||
cc2d3216 MZ |
65 | /* |
66 | * Collection structure - just an ID, and a redistributor address to | |
67 | * ping. We use one per CPU as a bag of interrupts assigned to this | |
68 | * CPU. | |
69 | */ | |
70 | struct its_collection { | |
71 | u64 target_address; | |
72 | u16 col_id; | |
73 | }; | |
74 | ||
466b7d16 | 75 | /* |
9347359a SD |
76 | * The ITS_BASER structure - contains memory information, cached |
77 | * value of BASER register configuration and ITS page size. | |
466b7d16 SD |
78 | */ |
79 | struct its_baser { | |
80 | void *base; | |
81 | u64 val; | |
82 | u32 order; | |
9347359a | 83 | u32 psz; |
466b7d16 SD |
84 | }; |
85 | ||
558b0165 AB |
86 | struct its_device; |
87 | ||
cc2d3216 MZ |
88 | /* |
89 | * The ITS structure - contains most of the infrastructure, with the | |
841514ab MZ |
90 | * top-level MSI domain, the command queue, the collections, and the |
91 | * list of devices writing to it. | |
cc2d3216 MZ |
92 | */ |
93 | struct its_node { | |
94 | raw_spinlock_t lock; | |
95 | struct list_head entry; | |
cc2d3216 | 96 | void __iomem *base; |
db40f0a7 | 97 | phys_addr_t phys_base; |
cc2d3216 MZ |
98 | struct its_cmd_block *cmd_base; |
99 | struct its_cmd_block *cmd_write; | |
466b7d16 | 100 | struct its_baser tables[GITS_BASER_NR_REGS]; |
cc2d3216 | 101 | struct its_collection *collections; |
558b0165 AB |
102 | struct fwnode_handle *fwnode_handle; |
103 | u64 (*get_msi_base)(struct its_device *its_dev); | |
cc2d3216 MZ |
104 | struct list_head its_device_list; |
105 | u64 flags; | |
106 | u32 ite_size; | |
466b7d16 | 107 | u32 device_ids; |
fbf8f40e | 108 | int numa_node; |
558b0165 AB |
109 | unsigned int msi_domain_flags; |
110 | u32 pre_its_base; /* for Socionext Synquacer */ | |
3dfa576b | 111 | bool is_v4; |
cc2d3216 MZ |
112 | }; |
113 | ||
114 | #define ITS_ITT_ALIGN SZ_256 | |
115 | ||
2eca0d6c SD |
116 | /* Convert page order to size in bytes */ |
117 | #define PAGE_ORDER_TO_SIZE(o) (PAGE_SIZE << (o)) | |
118 | ||
591e5bec MZ |
119 | struct event_lpi_map { |
120 | unsigned long *lpi_map; | |
121 | u16 *col_map; | |
122 | irq_hw_number_t lpi_base; | |
123 | int nr_lpis; | |
d011e4e6 MZ |
124 | struct mutex vlpi_lock; |
125 | struct its_vm *vm; | |
126 | struct its_vlpi_map *vlpi_maps; | |
127 | int nr_vlpis; | |
591e5bec MZ |
128 | }; |
129 | ||
cc2d3216 | 130 | /* |
d011e4e6 MZ |
131 | * The ITS view of a device - belongs to an ITS, owns an interrupt |
132 | * translation table, and a list of interrupts. If it some of its | |
133 | * LPIs are injected into a guest (GICv4), the event_map.vm field | |
134 | * indicates which one. | |
cc2d3216 MZ |
135 | */ |
136 | struct its_device { | |
137 | struct list_head entry; | |
138 | struct its_node *its; | |
591e5bec | 139 | struct event_lpi_map event_map; |
cc2d3216 | 140 | void *itt; |
cc2d3216 MZ |
141 | u32 nr_ites; |
142 | u32 device_id; | |
143 | }; | |
144 | ||
20b3d54e MZ |
145 | static struct { |
146 | raw_spinlock_t lock; | |
147 | struct its_device *dev; | |
148 | struct its_vpe **vpes; | |
149 | int next_victim; | |
150 | } vpe_proxy; | |
151 | ||
1ac19ca6 MZ |
152 | static LIST_HEAD(its_nodes); |
153 | static DEFINE_SPINLOCK(its_lock); | |
1ac19ca6 | 154 | static struct rdists *gic_rdists; |
db40f0a7 | 155 | static struct irq_domain *its_parent; |
1ac19ca6 | 156 | |
3dfa576b MZ |
157 | /* |
158 | * We have a maximum number of 16 ITSs in the whole system if we're | |
159 | * using the ITSList mechanism | |
160 | */ | |
161 | #define ITS_LIST_MAX 16 | |
162 | ||
163 | static unsigned long its_list_map; | |
3171a47a MZ |
164 | static u16 vmovp_seq_num; |
165 | static DEFINE_RAW_SPINLOCK(vmovp_lock); | |
166 | ||
7d75bbb4 | 167 | static DEFINE_IDA(its_vpeid_ida); |
3dfa576b | 168 | |
1ac19ca6 MZ |
169 | #define gic_data_rdist() (raw_cpu_ptr(gic_rdists->rdist)) |
170 | #define gic_data_rdist_rd_base() (gic_data_rdist()->rd_base) | |
e643d803 | 171 | #define gic_data_rdist_vlpi_base() (gic_data_rdist_rd_base() + SZ_128K) |
1ac19ca6 | 172 | |
591e5bec MZ |
173 | static struct its_collection *dev_event_to_col(struct its_device *its_dev, |
174 | u32 event) | |
175 | { | |
176 | struct its_node *its = its_dev->its; | |
177 | ||
178 | return its->collections + its_dev->event_map.col_map[event]; | |
179 | } | |
180 | ||
cc2d3216 MZ |
181 | /* |
182 | * ITS command descriptors - parameters to be encoded in a command | |
183 | * block. | |
184 | */ | |
185 | struct its_cmd_desc { | |
186 | union { | |
187 | struct { | |
188 | struct its_device *dev; | |
189 | u32 event_id; | |
190 | } its_inv_cmd; | |
191 | ||
8d85dced MZ |
192 | struct { |
193 | struct its_device *dev; | |
194 | u32 event_id; | |
195 | } its_clear_cmd; | |
196 | ||
cc2d3216 MZ |
197 | struct { |
198 | struct its_device *dev; | |
199 | u32 event_id; | |
200 | } its_int_cmd; | |
201 | ||
202 | struct { | |
203 | struct its_device *dev; | |
204 | int valid; | |
205 | } its_mapd_cmd; | |
206 | ||
207 | struct { | |
208 | struct its_collection *col; | |
209 | int valid; | |
210 | } its_mapc_cmd; | |
211 | ||
212 | struct { | |
213 | struct its_device *dev; | |
214 | u32 phys_id; | |
215 | u32 event_id; | |
6a25ad3a | 216 | } its_mapti_cmd; |
cc2d3216 MZ |
217 | |
218 | struct { | |
219 | struct its_device *dev; | |
220 | struct its_collection *col; | |
591e5bec | 221 | u32 event_id; |
cc2d3216 MZ |
222 | } its_movi_cmd; |
223 | ||
224 | struct { | |
225 | struct its_device *dev; | |
226 | u32 event_id; | |
227 | } its_discard_cmd; | |
228 | ||
229 | struct { | |
230 | struct its_collection *col; | |
231 | } its_invall_cmd; | |
d011e4e6 | 232 | |
eb78192b MZ |
233 | struct { |
234 | struct its_vpe *vpe; | |
235 | } its_vinvall_cmd; | |
236 | ||
237 | struct { | |
238 | struct its_vpe *vpe; | |
239 | struct its_collection *col; | |
240 | bool valid; | |
241 | } its_vmapp_cmd; | |
242 | ||
d011e4e6 MZ |
243 | struct { |
244 | struct its_vpe *vpe; | |
245 | struct its_device *dev; | |
246 | u32 virt_id; | |
247 | u32 event_id; | |
248 | bool db_enabled; | |
249 | } its_vmapti_cmd; | |
250 | ||
251 | struct { | |
252 | struct its_vpe *vpe; | |
253 | struct its_device *dev; | |
254 | u32 event_id; | |
255 | bool db_enabled; | |
256 | } its_vmovi_cmd; | |
3171a47a MZ |
257 | |
258 | struct { | |
259 | struct its_vpe *vpe; | |
260 | struct its_collection *col; | |
261 | u16 seq_num; | |
262 | u16 its_list; | |
263 | } its_vmovp_cmd; | |
cc2d3216 MZ |
264 | }; |
265 | }; | |
266 | ||
267 | /* | |
268 | * The ITS command block, which is what the ITS actually parses. | |
269 | */ | |
270 | struct its_cmd_block { | |
271 | u64 raw_cmd[4]; | |
272 | }; | |
273 | ||
274 | #define ITS_CMD_QUEUE_SZ SZ_64K | |
275 | #define ITS_CMD_QUEUE_NR_ENTRIES (ITS_CMD_QUEUE_SZ / sizeof(struct its_cmd_block)) | |
276 | ||
277 | typedef struct its_collection *(*its_cmd_builder_t)(struct its_cmd_block *, | |
278 | struct its_cmd_desc *); | |
279 | ||
d011e4e6 MZ |
280 | typedef struct its_vpe *(*its_cmd_vbuilder_t)(struct its_cmd_block *, |
281 | struct its_cmd_desc *); | |
282 | ||
4d36f136 MZ |
283 | static void its_mask_encode(u64 *raw_cmd, u64 val, int h, int l) |
284 | { | |
285 | u64 mask = GENMASK_ULL(h, l); | |
286 | *raw_cmd &= ~mask; | |
287 | *raw_cmd |= (val << l) & mask; | |
288 | } | |
289 | ||
cc2d3216 MZ |
290 | static void its_encode_cmd(struct its_cmd_block *cmd, u8 cmd_nr) |
291 | { | |
4d36f136 | 292 | its_mask_encode(&cmd->raw_cmd[0], cmd_nr, 7, 0); |
cc2d3216 MZ |
293 | } |
294 | ||
295 | static void its_encode_devid(struct its_cmd_block *cmd, u32 devid) | |
296 | { | |
4d36f136 | 297 | its_mask_encode(&cmd->raw_cmd[0], devid, 63, 32); |
cc2d3216 MZ |
298 | } |
299 | ||
300 | static void its_encode_event_id(struct its_cmd_block *cmd, u32 id) | |
301 | { | |
4d36f136 | 302 | its_mask_encode(&cmd->raw_cmd[1], id, 31, 0); |
cc2d3216 MZ |
303 | } |
304 | ||
305 | static void its_encode_phys_id(struct its_cmd_block *cmd, u32 phys_id) | |
306 | { | |
4d36f136 | 307 | its_mask_encode(&cmd->raw_cmd[1], phys_id, 63, 32); |
cc2d3216 MZ |
308 | } |
309 | ||
310 | static void its_encode_size(struct its_cmd_block *cmd, u8 size) | |
311 | { | |
4d36f136 | 312 | its_mask_encode(&cmd->raw_cmd[1], size, 4, 0); |
cc2d3216 MZ |
313 | } |
314 | ||
315 | static void its_encode_itt(struct its_cmd_block *cmd, u64 itt_addr) | |
316 | { | |
4d36f136 | 317 | its_mask_encode(&cmd->raw_cmd[2], itt_addr >> 8, 50, 8); |
cc2d3216 MZ |
318 | } |
319 | ||
320 | static void its_encode_valid(struct its_cmd_block *cmd, int valid) | |
321 | { | |
4d36f136 | 322 | its_mask_encode(&cmd->raw_cmd[2], !!valid, 63, 63); |
cc2d3216 MZ |
323 | } |
324 | ||
325 | static void its_encode_target(struct its_cmd_block *cmd, u64 target_addr) | |
326 | { | |
4d36f136 | 327 | its_mask_encode(&cmd->raw_cmd[2], target_addr >> 16, 50, 16); |
cc2d3216 MZ |
328 | } |
329 | ||
330 | static void its_encode_collection(struct its_cmd_block *cmd, u16 col) | |
331 | { | |
4d36f136 | 332 | its_mask_encode(&cmd->raw_cmd[2], col, 15, 0); |
cc2d3216 MZ |
333 | } |
334 | ||
d011e4e6 MZ |
335 | static void its_encode_vpeid(struct its_cmd_block *cmd, u16 vpeid) |
336 | { | |
337 | its_mask_encode(&cmd->raw_cmd[1], vpeid, 47, 32); | |
338 | } | |
339 | ||
340 | static void its_encode_virt_id(struct its_cmd_block *cmd, u32 virt_id) | |
341 | { | |
342 | its_mask_encode(&cmd->raw_cmd[2], virt_id, 31, 0); | |
343 | } | |
344 | ||
345 | static void its_encode_db_phys_id(struct its_cmd_block *cmd, u32 db_phys_id) | |
346 | { | |
347 | its_mask_encode(&cmd->raw_cmd[2], db_phys_id, 63, 32); | |
348 | } | |
349 | ||
350 | static void its_encode_db_valid(struct its_cmd_block *cmd, bool db_valid) | |
351 | { | |
352 | its_mask_encode(&cmd->raw_cmd[2], db_valid, 0, 0); | |
353 | } | |
354 | ||
3171a47a MZ |
355 | static void its_encode_seq_num(struct its_cmd_block *cmd, u16 seq_num) |
356 | { | |
357 | its_mask_encode(&cmd->raw_cmd[0], seq_num, 47, 32); | |
358 | } | |
359 | ||
360 | static void its_encode_its_list(struct its_cmd_block *cmd, u16 its_list) | |
361 | { | |
362 | its_mask_encode(&cmd->raw_cmd[1], its_list, 15, 0); | |
363 | } | |
364 | ||
eb78192b MZ |
365 | static void its_encode_vpt_addr(struct its_cmd_block *cmd, u64 vpt_pa) |
366 | { | |
367 | its_mask_encode(&cmd->raw_cmd[3], vpt_pa >> 16, 50, 16); | |
368 | } | |
369 | ||
370 | static void its_encode_vpt_size(struct its_cmd_block *cmd, u8 vpt_size) | |
371 | { | |
372 | its_mask_encode(&cmd->raw_cmd[3], vpt_size, 4, 0); | |
373 | } | |
374 | ||
cc2d3216 MZ |
375 | static inline void its_fixup_cmd(struct its_cmd_block *cmd) |
376 | { | |
377 | /* Let's fixup BE commands */ | |
378 | cmd->raw_cmd[0] = cpu_to_le64(cmd->raw_cmd[0]); | |
379 | cmd->raw_cmd[1] = cpu_to_le64(cmd->raw_cmd[1]); | |
380 | cmd->raw_cmd[2] = cpu_to_le64(cmd->raw_cmd[2]); | |
381 | cmd->raw_cmd[3] = cpu_to_le64(cmd->raw_cmd[3]); | |
382 | } | |
383 | ||
384 | static struct its_collection *its_build_mapd_cmd(struct its_cmd_block *cmd, | |
385 | struct its_cmd_desc *desc) | |
386 | { | |
387 | unsigned long itt_addr; | |
c8481267 | 388 | u8 size = ilog2(desc->its_mapd_cmd.dev->nr_ites); |
cc2d3216 MZ |
389 | |
390 | itt_addr = virt_to_phys(desc->its_mapd_cmd.dev->itt); | |
391 | itt_addr = ALIGN(itt_addr, ITS_ITT_ALIGN); | |
392 | ||
393 | its_encode_cmd(cmd, GITS_CMD_MAPD); | |
394 | its_encode_devid(cmd, desc->its_mapd_cmd.dev->device_id); | |
395 | its_encode_size(cmd, size - 1); | |
396 | its_encode_itt(cmd, itt_addr); | |
397 | its_encode_valid(cmd, desc->its_mapd_cmd.valid); | |
398 | ||
399 | its_fixup_cmd(cmd); | |
400 | ||
591e5bec | 401 | return NULL; |
cc2d3216 MZ |
402 | } |
403 | ||
404 | static struct its_collection *its_build_mapc_cmd(struct its_cmd_block *cmd, | |
405 | struct its_cmd_desc *desc) | |
406 | { | |
407 | its_encode_cmd(cmd, GITS_CMD_MAPC); | |
408 | its_encode_collection(cmd, desc->its_mapc_cmd.col->col_id); | |
409 | its_encode_target(cmd, desc->its_mapc_cmd.col->target_address); | |
410 | its_encode_valid(cmd, desc->its_mapc_cmd.valid); | |
411 | ||
412 | its_fixup_cmd(cmd); | |
413 | ||
414 | return desc->its_mapc_cmd.col; | |
415 | } | |
416 | ||
6a25ad3a | 417 | static struct its_collection *its_build_mapti_cmd(struct its_cmd_block *cmd, |
cc2d3216 MZ |
418 | struct its_cmd_desc *desc) |
419 | { | |
591e5bec MZ |
420 | struct its_collection *col; |
421 | ||
6a25ad3a MZ |
422 | col = dev_event_to_col(desc->its_mapti_cmd.dev, |
423 | desc->its_mapti_cmd.event_id); | |
591e5bec | 424 | |
6a25ad3a MZ |
425 | its_encode_cmd(cmd, GITS_CMD_MAPTI); |
426 | its_encode_devid(cmd, desc->its_mapti_cmd.dev->device_id); | |
427 | its_encode_event_id(cmd, desc->its_mapti_cmd.event_id); | |
428 | its_encode_phys_id(cmd, desc->its_mapti_cmd.phys_id); | |
591e5bec | 429 | its_encode_collection(cmd, col->col_id); |
cc2d3216 MZ |
430 | |
431 | its_fixup_cmd(cmd); | |
432 | ||
591e5bec | 433 | return col; |
cc2d3216 MZ |
434 | } |
435 | ||
436 | static struct its_collection *its_build_movi_cmd(struct its_cmd_block *cmd, | |
437 | struct its_cmd_desc *desc) | |
438 | { | |
591e5bec MZ |
439 | struct its_collection *col; |
440 | ||
441 | col = dev_event_to_col(desc->its_movi_cmd.dev, | |
442 | desc->its_movi_cmd.event_id); | |
443 | ||
cc2d3216 MZ |
444 | its_encode_cmd(cmd, GITS_CMD_MOVI); |
445 | its_encode_devid(cmd, desc->its_movi_cmd.dev->device_id); | |
591e5bec | 446 | its_encode_event_id(cmd, desc->its_movi_cmd.event_id); |
cc2d3216 MZ |
447 | its_encode_collection(cmd, desc->its_movi_cmd.col->col_id); |
448 | ||
449 | its_fixup_cmd(cmd); | |
450 | ||
591e5bec | 451 | return col; |
cc2d3216 MZ |
452 | } |
453 | ||
454 | static struct its_collection *its_build_discard_cmd(struct its_cmd_block *cmd, | |
455 | struct its_cmd_desc *desc) | |
456 | { | |
591e5bec MZ |
457 | struct its_collection *col; |
458 | ||
459 | col = dev_event_to_col(desc->its_discard_cmd.dev, | |
460 | desc->its_discard_cmd.event_id); | |
461 | ||
cc2d3216 MZ |
462 | its_encode_cmd(cmd, GITS_CMD_DISCARD); |
463 | its_encode_devid(cmd, desc->its_discard_cmd.dev->device_id); | |
464 | its_encode_event_id(cmd, desc->its_discard_cmd.event_id); | |
465 | ||
466 | its_fixup_cmd(cmd); | |
467 | ||
591e5bec | 468 | return col; |
cc2d3216 MZ |
469 | } |
470 | ||
471 | static struct its_collection *its_build_inv_cmd(struct its_cmd_block *cmd, | |
472 | struct its_cmd_desc *desc) | |
473 | { | |
591e5bec MZ |
474 | struct its_collection *col; |
475 | ||
476 | col = dev_event_to_col(desc->its_inv_cmd.dev, | |
477 | desc->its_inv_cmd.event_id); | |
478 | ||
cc2d3216 MZ |
479 | its_encode_cmd(cmd, GITS_CMD_INV); |
480 | its_encode_devid(cmd, desc->its_inv_cmd.dev->device_id); | |
481 | its_encode_event_id(cmd, desc->its_inv_cmd.event_id); | |
482 | ||
483 | its_fixup_cmd(cmd); | |
484 | ||
591e5bec | 485 | return col; |
cc2d3216 MZ |
486 | } |
487 | ||
8d85dced MZ |
488 | static struct its_collection *its_build_int_cmd(struct its_cmd_block *cmd, |
489 | struct its_cmd_desc *desc) | |
490 | { | |
491 | struct its_collection *col; | |
492 | ||
493 | col = dev_event_to_col(desc->its_int_cmd.dev, | |
494 | desc->its_int_cmd.event_id); | |
495 | ||
496 | its_encode_cmd(cmd, GITS_CMD_INT); | |
497 | its_encode_devid(cmd, desc->its_int_cmd.dev->device_id); | |
498 | its_encode_event_id(cmd, desc->its_int_cmd.event_id); | |
499 | ||
500 | its_fixup_cmd(cmd); | |
501 | ||
502 | return col; | |
503 | } | |
504 | ||
505 | static struct its_collection *its_build_clear_cmd(struct its_cmd_block *cmd, | |
506 | struct its_cmd_desc *desc) | |
507 | { | |
508 | struct its_collection *col; | |
509 | ||
510 | col = dev_event_to_col(desc->its_clear_cmd.dev, | |
511 | desc->its_clear_cmd.event_id); | |
512 | ||
513 | its_encode_cmd(cmd, GITS_CMD_CLEAR); | |
514 | its_encode_devid(cmd, desc->its_clear_cmd.dev->device_id); | |
515 | its_encode_event_id(cmd, desc->its_clear_cmd.event_id); | |
516 | ||
517 | its_fixup_cmd(cmd); | |
518 | ||
519 | return col; | |
520 | } | |
521 | ||
cc2d3216 MZ |
522 | static struct its_collection *its_build_invall_cmd(struct its_cmd_block *cmd, |
523 | struct its_cmd_desc *desc) | |
524 | { | |
525 | its_encode_cmd(cmd, GITS_CMD_INVALL); | |
526 | its_encode_collection(cmd, desc->its_mapc_cmd.col->col_id); | |
527 | ||
528 | its_fixup_cmd(cmd); | |
529 | ||
530 | return NULL; | |
531 | } | |
532 | ||
eb78192b MZ |
533 | static struct its_vpe *its_build_vinvall_cmd(struct its_cmd_block *cmd, |
534 | struct its_cmd_desc *desc) | |
535 | { | |
536 | its_encode_cmd(cmd, GITS_CMD_VINVALL); | |
537 | its_encode_vpeid(cmd, desc->its_vinvall_cmd.vpe->vpe_id); | |
538 | ||
539 | its_fixup_cmd(cmd); | |
540 | ||
541 | return desc->its_vinvall_cmd.vpe; | |
542 | } | |
543 | ||
544 | static struct its_vpe *its_build_vmapp_cmd(struct its_cmd_block *cmd, | |
545 | struct its_cmd_desc *desc) | |
546 | { | |
547 | unsigned long vpt_addr; | |
548 | ||
549 | vpt_addr = virt_to_phys(page_address(desc->its_vmapp_cmd.vpe->vpt_page)); | |
550 | ||
551 | its_encode_cmd(cmd, GITS_CMD_VMAPP); | |
552 | its_encode_vpeid(cmd, desc->its_vmapp_cmd.vpe->vpe_id); | |
553 | its_encode_valid(cmd, desc->its_vmapp_cmd.valid); | |
554 | its_encode_target(cmd, desc->its_vmapp_cmd.col->target_address); | |
555 | its_encode_vpt_addr(cmd, vpt_addr); | |
556 | its_encode_vpt_size(cmd, LPI_NRBITS - 1); | |
557 | ||
558 | its_fixup_cmd(cmd); | |
559 | ||
560 | return desc->its_vmapp_cmd.vpe; | |
561 | } | |
562 | ||
d011e4e6 MZ |
563 | static struct its_vpe *its_build_vmapti_cmd(struct its_cmd_block *cmd, |
564 | struct its_cmd_desc *desc) | |
565 | { | |
566 | u32 db; | |
567 | ||
568 | if (desc->its_vmapti_cmd.db_enabled) | |
569 | db = desc->its_vmapti_cmd.vpe->vpe_db_lpi; | |
570 | else | |
571 | db = 1023; | |
572 | ||
573 | its_encode_cmd(cmd, GITS_CMD_VMAPTI); | |
574 | its_encode_devid(cmd, desc->its_vmapti_cmd.dev->device_id); | |
575 | its_encode_vpeid(cmd, desc->its_vmapti_cmd.vpe->vpe_id); | |
576 | its_encode_event_id(cmd, desc->its_vmapti_cmd.event_id); | |
577 | its_encode_db_phys_id(cmd, db); | |
578 | its_encode_virt_id(cmd, desc->its_vmapti_cmd.virt_id); | |
579 | ||
580 | its_fixup_cmd(cmd); | |
581 | ||
582 | return desc->its_vmapti_cmd.vpe; | |
583 | } | |
584 | ||
585 | static struct its_vpe *its_build_vmovi_cmd(struct its_cmd_block *cmd, | |
586 | struct its_cmd_desc *desc) | |
587 | { | |
588 | u32 db; | |
589 | ||
590 | if (desc->its_vmovi_cmd.db_enabled) | |
591 | db = desc->its_vmovi_cmd.vpe->vpe_db_lpi; | |
592 | else | |
593 | db = 1023; | |
594 | ||
595 | its_encode_cmd(cmd, GITS_CMD_VMOVI); | |
596 | its_encode_devid(cmd, desc->its_vmovi_cmd.dev->device_id); | |
597 | its_encode_vpeid(cmd, desc->its_vmovi_cmd.vpe->vpe_id); | |
598 | its_encode_event_id(cmd, desc->its_vmovi_cmd.event_id); | |
599 | its_encode_db_phys_id(cmd, db); | |
600 | its_encode_db_valid(cmd, true); | |
601 | ||
602 | its_fixup_cmd(cmd); | |
603 | ||
604 | return desc->its_vmovi_cmd.vpe; | |
605 | } | |
606 | ||
3171a47a MZ |
607 | static struct its_vpe *its_build_vmovp_cmd(struct its_cmd_block *cmd, |
608 | struct its_cmd_desc *desc) | |
609 | { | |
610 | its_encode_cmd(cmd, GITS_CMD_VMOVP); | |
611 | its_encode_seq_num(cmd, desc->its_vmovp_cmd.seq_num); | |
612 | its_encode_its_list(cmd, desc->its_vmovp_cmd.its_list); | |
613 | its_encode_vpeid(cmd, desc->its_vmovp_cmd.vpe->vpe_id); | |
614 | its_encode_target(cmd, desc->its_vmovp_cmd.col->target_address); | |
615 | ||
616 | its_fixup_cmd(cmd); | |
617 | ||
618 | return desc->its_vmovp_cmd.vpe; | |
619 | } | |
620 | ||
cc2d3216 MZ |
621 | static u64 its_cmd_ptr_to_offset(struct its_node *its, |
622 | struct its_cmd_block *ptr) | |
623 | { | |
624 | return (ptr - its->cmd_base) * sizeof(*ptr); | |
625 | } | |
626 | ||
627 | static int its_queue_full(struct its_node *its) | |
628 | { | |
629 | int widx; | |
630 | int ridx; | |
631 | ||
632 | widx = its->cmd_write - its->cmd_base; | |
633 | ridx = readl_relaxed(its->base + GITS_CREADR) / sizeof(struct its_cmd_block); | |
634 | ||
635 | /* This is incredibly unlikely to happen, unless the ITS locks up. */ | |
636 | if (((widx + 1) % ITS_CMD_QUEUE_NR_ENTRIES) == ridx) | |
637 | return 1; | |
638 | ||
639 | return 0; | |
640 | } | |
641 | ||
642 | static struct its_cmd_block *its_allocate_entry(struct its_node *its) | |
643 | { | |
644 | struct its_cmd_block *cmd; | |
645 | u32 count = 1000000; /* 1s! */ | |
646 | ||
647 | while (its_queue_full(its)) { | |
648 | count--; | |
649 | if (!count) { | |
650 | pr_err_ratelimited("ITS queue not draining\n"); | |
651 | return NULL; | |
652 | } | |
653 | cpu_relax(); | |
654 | udelay(1); | |
655 | } | |
656 | ||
657 | cmd = its->cmd_write++; | |
658 | ||
659 | /* Handle queue wrapping */ | |
660 | if (its->cmd_write == (its->cmd_base + ITS_CMD_QUEUE_NR_ENTRIES)) | |
661 | its->cmd_write = its->cmd_base; | |
662 | ||
34d677a9 MZ |
663 | /* Clear command */ |
664 | cmd->raw_cmd[0] = 0; | |
665 | cmd->raw_cmd[1] = 0; | |
666 | cmd->raw_cmd[2] = 0; | |
667 | cmd->raw_cmd[3] = 0; | |
668 | ||
cc2d3216 MZ |
669 | return cmd; |
670 | } | |
671 | ||
672 | static struct its_cmd_block *its_post_commands(struct its_node *its) | |
673 | { | |
674 | u64 wr = its_cmd_ptr_to_offset(its, its->cmd_write); | |
675 | ||
676 | writel_relaxed(wr, its->base + GITS_CWRITER); | |
677 | ||
678 | return its->cmd_write; | |
679 | } | |
680 | ||
681 | static void its_flush_cmd(struct its_node *its, struct its_cmd_block *cmd) | |
682 | { | |
683 | /* | |
684 | * Make sure the commands written to memory are observable by | |
685 | * the ITS. | |
686 | */ | |
687 | if (its->flags & ITS_FLAGS_CMDQ_NEEDS_FLUSHING) | |
328191c0 | 688 | gic_flush_dcache_to_poc(cmd, sizeof(*cmd)); |
cc2d3216 MZ |
689 | else |
690 | dsb(ishst); | |
691 | } | |
692 | ||
693 | static void its_wait_for_range_completion(struct its_node *its, | |
694 | struct its_cmd_block *from, | |
695 | struct its_cmd_block *to) | |
696 | { | |
697 | u64 rd_idx, from_idx, to_idx; | |
698 | u32 count = 1000000; /* 1s! */ | |
699 | ||
700 | from_idx = its_cmd_ptr_to_offset(its, from); | |
701 | to_idx = its_cmd_ptr_to_offset(its, to); | |
702 | ||
703 | while (1) { | |
704 | rd_idx = readl_relaxed(its->base + GITS_CREADR); | |
9bdd8b1c MZ |
705 | |
706 | /* Direct case */ | |
707 | if (from_idx < to_idx && rd_idx >= to_idx) | |
708 | break; | |
709 | ||
710 | /* Wrapped case */ | |
711 | if (from_idx >= to_idx && rd_idx >= to_idx && rd_idx < from_idx) | |
cc2d3216 MZ |
712 | break; |
713 | ||
714 | count--; | |
715 | if (!count) { | |
716 | pr_err_ratelimited("ITS queue timeout\n"); | |
717 | return; | |
718 | } | |
719 | cpu_relax(); | |
720 | udelay(1); | |
721 | } | |
722 | } | |
723 | ||
e4f9094b MZ |
724 | /* Warning, macro hell follows */ |
725 | #define BUILD_SINGLE_CMD_FUNC(name, buildtype, synctype, buildfn) \ | |
726 | void name(struct its_node *its, \ | |
727 | buildtype builder, \ | |
728 | struct its_cmd_desc *desc) \ | |
729 | { \ | |
730 | struct its_cmd_block *cmd, *sync_cmd, *next_cmd; \ | |
731 | synctype *sync_obj; \ | |
732 | unsigned long flags; \ | |
733 | \ | |
734 | raw_spin_lock_irqsave(&its->lock, flags); \ | |
735 | \ | |
736 | cmd = its_allocate_entry(its); \ | |
737 | if (!cmd) { /* We're soooooo screewed... */ \ | |
738 | raw_spin_unlock_irqrestore(&its->lock, flags); \ | |
739 | return; \ | |
740 | } \ | |
741 | sync_obj = builder(cmd, desc); \ | |
742 | its_flush_cmd(its, cmd); \ | |
743 | \ | |
744 | if (sync_obj) { \ | |
745 | sync_cmd = its_allocate_entry(its); \ | |
746 | if (!sync_cmd) \ | |
747 | goto post; \ | |
748 | \ | |
749 | buildfn(sync_cmd, sync_obj); \ | |
750 | its_flush_cmd(its, sync_cmd); \ | |
751 | } \ | |
752 | \ | |
753 | post: \ | |
754 | next_cmd = its_post_commands(its); \ | |
755 | raw_spin_unlock_irqrestore(&its->lock, flags); \ | |
756 | \ | |
757 | its_wait_for_range_completion(its, cmd, next_cmd); \ | |
758 | } | |
cc2d3216 | 759 | |
e4f9094b MZ |
760 | static void its_build_sync_cmd(struct its_cmd_block *sync_cmd, |
761 | struct its_collection *sync_col) | |
762 | { | |
763 | its_encode_cmd(sync_cmd, GITS_CMD_SYNC); | |
764 | its_encode_target(sync_cmd, sync_col->target_address); | |
cc2d3216 | 765 | |
e4f9094b | 766 | its_fixup_cmd(sync_cmd); |
cc2d3216 MZ |
767 | } |
768 | ||
e4f9094b MZ |
769 | static BUILD_SINGLE_CMD_FUNC(its_send_single_command, its_cmd_builder_t, |
770 | struct its_collection, its_build_sync_cmd) | |
771 | ||
d011e4e6 MZ |
772 | static void its_build_vsync_cmd(struct its_cmd_block *sync_cmd, |
773 | struct its_vpe *sync_vpe) | |
774 | { | |
775 | its_encode_cmd(sync_cmd, GITS_CMD_VSYNC); | |
776 | its_encode_vpeid(sync_cmd, sync_vpe->vpe_id); | |
777 | ||
778 | its_fixup_cmd(sync_cmd); | |
779 | } | |
780 | ||
781 | static BUILD_SINGLE_CMD_FUNC(its_send_single_vcommand, its_cmd_vbuilder_t, | |
782 | struct its_vpe, its_build_vsync_cmd) | |
783 | ||
8d85dced | 784 | static void its_send_int(struct its_device *dev, u32 event_id) |
cc2d3216 | 785 | { |
8d85dced | 786 | struct its_cmd_desc desc; |
cc2d3216 | 787 | |
8d85dced MZ |
788 | desc.its_int_cmd.dev = dev; |
789 | desc.its_int_cmd.event_id = event_id; | |
cc2d3216 | 790 | |
8d85dced MZ |
791 | its_send_single_command(dev->its, its_build_int_cmd, &desc); |
792 | } | |
cc2d3216 | 793 | |
8d85dced MZ |
794 | static void its_send_clear(struct its_device *dev, u32 event_id) |
795 | { | |
796 | struct its_cmd_desc desc; | |
cc2d3216 | 797 | |
8d85dced MZ |
798 | desc.its_clear_cmd.dev = dev; |
799 | desc.its_clear_cmd.event_id = event_id; | |
cc2d3216 | 800 | |
8d85dced | 801 | its_send_single_command(dev->its, its_build_clear_cmd, &desc); |
cc2d3216 MZ |
802 | } |
803 | ||
804 | static void its_send_inv(struct its_device *dev, u32 event_id) | |
805 | { | |
806 | struct its_cmd_desc desc; | |
807 | ||
808 | desc.its_inv_cmd.dev = dev; | |
809 | desc.its_inv_cmd.event_id = event_id; | |
810 | ||
811 | its_send_single_command(dev->its, its_build_inv_cmd, &desc); | |
812 | } | |
813 | ||
814 | static void its_send_mapd(struct its_device *dev, int valid) | |
815 | { | |
816 | struct its_cmd_desc desc; | |
817 | ||
818 | desc.its_mapd_cmd.dev = dev; | |
819 | desc.its_mapd_cmd.valid = !!valid; | |
820 | ||
821 | its_send_single_command(dev->its, its_build_mapd_cmd, &desc); | |
822 | } | |
823 | ||
824 | static void its_send_mapc(struct its_node *its, struct its_collection *col, | |
825 | int valid) | |
826 | { | |
827 | struct its_cmd_desc desc; | |
828 | ||
829 | desc.its_mapc_cmd.col = col; | |
830 | desc.its_mapc_cmd.valid = !!valid; | |
831 | ||
832 | its_send_single_command(its, its_build_mapc_cmd, &desc); | |
833 | } | |
834 | ||
6a25ad3a | 835 | static void its_send_mapti(struct its_device *dev, u32 irq_id, u32 id) |
cc2d3216 MZ |
836 | { |
837 | struct its_cmd_desc desc; | |
838 | ||
6a25ad3a MZ |
839 | desc.its_mapti_cmd.dev = dev; |
840 | desc.its_mapti_cmd.phys_id = irq_id; | |
841 | desc.its_mapti_cmd.event_id = id; | |
cc2d3216 | 842 | |
6a25ad3a | 843 | its_send_single_command(dev->its, its_build_mapti_cmd, &desc); |
cc2d3216 MZ |
844 | } |
845 | ||
846 | static void its_send_movi(struct its_device *dev, | |
847 | struct its_collection *col, u32 id) | |
848 | { | |
849 | struct its_cmd_desc desc; | |
850 | ||
851 | desc.its_movi_cmd.dev = dev; | |
852 | desc.its_movi_cmd.col = col; | |
591e5bec | 853 | desc.its_movi_cmd.event_id = id; |
cc2d3216 MZ |
854 | |
855 | its_send_single_command(dev->its, its_build_movi_cmd, &desc); | |
856 | } | |
857 | ||
858 | static void its_send_discard(struct its_device *dev, u32 id) | |
859 | { | |
860 | struct its_cmd_desc desc; | |
861 | ||
862 | desc.its_discard_cmd.dev = dev; | |
863 | desc.its_discard_cmd.event_id = id; | |
864 | ||
865 | its_send_single_command(dev->its, its_build_discard_cmd, &desc); | |
866 | } | |
867 | ||
868 | static void its_send_invall(struct its_node *its, struct its_collection *col) | |
869 | { | |
870 | struct its_cmd_desc desc; | |
871 | ||
872 | desc.its_invall_cmd.col = col; | |
873 | ||
874 | its_send_single_command(its, its_build_invall_cmd, &desc); | |
875 | } | |
c48ed51c | 876 | |
d011e4e6 MZ |
877 | static void its_send_vmapti(struct its_device *dev, u32 id) |
878 | { | |
879 | struct its_vlpi_map *map = &dev->event_map.vlpi_maps[id]; | |
880 | struct its_cmd_desc desc; | |
881 | ||
882 | desc.its_vmapti_cmd.vpe = map->vpe; | |
883 | desc.its_vmapti_cmd.dev = dev; | |
884 | desc.its_vmapti_cmd.virt_id = map->vintid; | |
885 | desc.its_vmapti_cmd.event_id = id; | |
886 | desc.its_vmapti_cmd.db_enabled = map->db_enabled; | |
887 | ||
888 | its_send_single_vcommand(dev->its, its_build_vmapti_cmd, &desc); | |
889 | } | |
890 | ||
891 | static void its_send_vmovi(struct its_device *dev, u32 id) | |
892 | { | |
893 | struct its_vlpi_map *map = &dev->event_map.vlpi_maps[id]; | |
894 | struct its_cmd_desc desc; | |
895 | ||
896 | desc.its_vmovi_cmd.vpe = map->vpe; | |
897 | desc.its_vmovi_cmd.dev = dev; | |
898 | desc.its_vmovi_cmd.event_id = id; | |
899 | desc.its_vmovi_cmd.db_enabled = map->db_enabled; | |
900 | ||
901 | its_send_single_vcommand(dev->its, its_build_vmovi_cmd, &desc); | |
902 | } | |
903 | ||
eb78192b MZ |
904 | static void its_send_vmapp(struct its_vpe *vpe, bool valid) |
905 | { | |
906 | struct its_cmd_desc desc; | |
907 | struct its_node *its; | |
908 | ||
909 | desc.its_vmapp_cmd.vpe = vpe; | |
910 | desc.its_vmapp_cmd.valid = valid; | |
911 | ||
912 | list_for_each_entry(its, &its_nodes, entry) { | |
913 | if (!its->is_v4) | |
914 | continue; | |
915 | ||
916 | desc.its_vmapp_cmd.col = &its->collections[vpe->col_idx]; | |
917 | its_send_single_vcommand(its, its_build_vmapp_cmd, &desc); | |
918 | } | |
919 | } | |
920 | ||
3171a47a MZ |
921 | static void its_send_vmovp(struct its_vpe *vpe) |
922 | { | |
923 | struct its_cmd_desc desc; | |
924 | struct its_node *its; | |
925 | unsigned long flags; | |
926 | int col_id = vpe->col_idx; | |
927 | ||
928 | desc.its_vmovp_cmd.vpe = vpe; | |
929 | desc.its_vmovp_cmd.its_list = (u16)its_list_map; | |
930 | ||
931 | if (!its_list_map) { | |
932 | its = list_first_entry(&its_nodes, struct its_node, entry); | |
933 | desc.its_vmovp_cmd.seq_num = 0; | |
934 | desc.its_vmovp_cmd.col = &its->collections[col_id]; | |
935 | its_send_single_vcommand(its, its_build_vmovp_cmd, &desc); | |
936 | return; | |
937 | } | |
938 | ||
939 | /* | |
940 | * Yet another marvel of the architecture. If using the | |
941 | * its_list "feature", we need to make sure that all ITSs | |
942 | * receive all VMOVP commands in the same order. The only way | |
943 | * to guarantee this is to make vmovp a serialization point. | |
944 | * | |
945 | * Wall <-- Head. | |
946 | */ | |
947 | raw_spin_lock_irqsave(&vmovp_lock, flags); | |
948 | ||
949 | desc.its_vmovp_cmd.seq_num = vmovp_seq_num++; | |
950 | ||
951 | /* Emit VMOVPs */ | |
952 | list_for_each_entry(its, &its_nodes, entry) { | |
953 | if (!its->is_v4) | |
954 | continue; | |
955 | ||
956 | desc.its_vmovp_cmd.col = &its->collections[col_id]; | |
957 | its_send_single_vcommand(its, its_build_vmovp_cmd, &desc); | |
958 | } | |
959 | ||
960 | raw_spin_unlock_irqrestore(&vmovp_lock, flags); | |
961 | } | |
962 | ||
eb78192b MZ |
963 | static void its_send_vinvall(struct its_vpe *vpe) |
964 | { | |
965 | struct its_cmd_desc desc; | |
966 | struct its_node *its; | |
967 | ||
968 | desc.its_vinvall_cmd.vpe = vpe; | |
969 | ||
970 | list_for_each_entry(its, &its_nodes, entry) { | |
971 | if (!its->is_v4) | |
972 | continue; | |
973 | its_send_single_vcommand(its, its_build_vinvall_cmd, &desc); | |
974 | } | |
975 | } | |
976 | ||
c48ed51c MZ |
977 | /* |
978 | * irqchip functions - assumes MSI, mostly. | |
979 | */ | |
980 | ||
981 | static inline u32 its_get_event_id(struct irq_data *d) | |
982 | { | |
983 | struct its_device *its_dev = irq_data_get_irq_chip_data(d); | |
591e5bec | 984 | return d->hwirq - its_dev->event_map.lpi_base; |
c48ed51c MZ |
985 | } |
986 | ||
015ec038 | 987 | static void lpi_write_config(struct irq_data *d, u8 clr, u8 set) |
c48ed51c | 988 | { |
015ec038 | 989 | irq_hw_number_t hwirq; |
adcdb94e MZ |
990 | struct page *prop_page; |
991 | u8 *cfg; | |
c48ed51c | 992 | |
015ec038 MZ |
993 | if (irqd_is_forwarded_to_vcpu(d)) { |
994 | struct its_device *its_dev = irq_data_get_irq_chip_data(d); | |
995 | u32 event = its_get_event_id(d); | |
996 | ||
997 | prop_page = its_dev->event_map.vm->vprop_page; | |
998 | hwirq = its_dev->event_map.vlpi_maps[event].vintid; | |
999 | } else { | |
1000 | prop_page = gic_rdists->prop_page; | |
1001 | hwirq = d->hwirq; | |
1002 | } | |
adcdb94e MZ |
1003 | |
1004 | cfg = page_address(prop_page) + hwirq - 8192; | |
1005 | *cfg &= ~clr; | |
015ec038 | 1006 | *cfg |= set | LPI_PROP_GROUP1; |
c48ed51c MZ |
1007 | |
1008 | /* | |
1009 | * Make the above write visible to the redistributors. | |
1010 | * And yes, we're flushing exactly: One. Single. Byte. | |
1011 | * Humpf... | |
1012 | */ | |
1013 | if (gic_rdists->flags & RDIST_FLAGS_PROPBASE_NEEDS_FLUSHING) | |
328191c0 | 1014 | gic_flush_dcache_to_poc(cfg, sizeof(*cfg)); |
c48ed51c MZ |
1015 | else |
1016 | dsb(ishst); | |
015ec038 MZ |
1017 | } |
1018 | ||
1019 | static void lpi_update_config(struct irq_data *d, u8 clr, u8 set) | |
1020 | { | |
1021 | struct its_device *its_dev = irq_data_get_irq_chip_data(d); | |
1022 | ||
1023 | lpi_write_config(d, clr, set); | |
adcdb94e | 1024 | its_send_inv(its_dev, its_get_event_id(d)); |
c48ed51c MZ |
1025 | } |
1026 | ||
015ec038 MZ |
1027 | static void its_vlpi_set_doorbell(struct irq_data *d, bool enable) |
1028 | { | |
1029 | struct its_device *its_dev = irq_data_get_irq_chip_data(d); | |
1030 | u32 event = its_get_event_id(d); | |
1031 | ||
1032 | if (its_dev->event_map.vlpi_maps[event].db_enabled == enable) | |
1033 | return; | |
1034 | ||
1035 | its_dev->event_map.vlpi_maps[event].db_enabled = enable; | |
1036 | ||
1037 | /* | |
1038 | * More fun with the architecture: | |
1039 | * | |
1040 | * Ideally, we'd issue a VMAPTI to set the doorbell to its LPI | |
1041 | * value or to 1023, depending on the enable bit. But that | |
1042 | * would be issueing a mapping for an /existing/ DevID+EventID | |
1043 | * pair, which is UNPREDICTABLE. Instead, let's issue a VMOVI | |
1044 | * to the /same/ vPE, using this opportunity to adjust the | |
1045 | * doorbell. Mouahahahaha. We loves it, Precious. | |
1046 | */ | |
1047 | its_send_vmovi(its_dev, event); | |
c48ed51c MZ |
1048 | } |
1049 | ||
1050 | static void its_mask_irq(struct irq_data *d) | |
1051 | { | |
015ec038 MZ |
1052 | if (irqd_is_forwarded_to_vcpu(d)) |
1053 | its_vlpi_set_doorbell(d, false); | |
1054 | ||
adcdb94e | 1055 | lpi_update_config(d, LPI_PROP_ENABLED, 0); |
c48ed51c MZ |
1056 | } |
1057 | ||
1058 | static void its_unmask_irq(struct irq_data *d) | |
1059 | { | |
015ec038 MZ |
1060 | if (irqd_is_forwarded_to_vcpu(d)) |
1061 | its_vlpi_set_doorbell(d, true); | |
1062 | ||
adcdb94e | 1063 | lpi_update_config(d, 0, LPI_PROP_ENABLED); |
c48ed51c MZ |
1064 | } |
1065 | ||
c48ed51c MZ |
1066 | static int its_set_affinity(struct irq_data *d, const struct cpumask *mask_val, |
1067 | bool force) | |
1068 | { | |
fbf8f40e GK |
1069 | unsigned int cpu; |
1070 | const struct cpumask *cpu_mask = cpu_online_mask; | |
c48ed51c MZ |
1071 | struct its_device *its_dev = irq_data_get_irq_chip_data(d); |
1072 | struct its_collection *target_col; | |
1073 | u32 id = its_get_event_id(d); | |
1074 | ||
015ec038 MZ |
1075 | /* A forwarded interrupt should use irq_set_vcpu_affinity */ |
1076 | if (irqd_is_forwarded_to_vcpu(d)) | |
1077 | return -EINVAL; | |
1078 | ||
fbf8f40e GK |
1079 | /* lpi cannot be routed to a redistributor that is on a foreign node */ |
1080 | if (its_dev->its->flags & ITS_FLAGS_WORKAROUND_CAVIUM_23144) { | |
1081 | if (its_dev->its->numa_node >= 0) { | |
1082 | cpu_mask = cpumask_of_node(its_dev->its->numa_node); | |
1083 | if (!cpumask_intersects(mask_val, cpu_mask)) | |
1084 | return -EINVAL; | |
1085 | } | |
1086 | } | |
1087 | ||
1088 | cpu = cpumask_any_and(mask_val, cpu_mask); | |
1089 | ||
c48ed51c MZ |
1090 | if (cpu >= nr_cpu_ids) |
1091 | return -EINVAL; | |
1092 | ||
8b8d94a7 M |
1093 | /* don't set the affinity when the target cpu is same as current one */ |
1094 | if (cpu != its_dev->event_map.col_map[id]) { | |
1095 | target_col = &its_dev->its->collections[cpu]; | |
1096 | its_send_movi(its_dev, target_col, id); | |
1097 | its_dev->event_map.col_map[id] = cpu; | |
0d224d35 | 1098 | irq_data_update_effective_affinity(d, cpumask_of(cpu)); |
8b8d94a7 | 1099 | } |
c48ed51c MZ |
1100 | |
1101 | return IRQ_SET_MASK_OK_DONE; | |
1102 | } | |
1103 | ||
558b0165 AB |
1104 | static u64 its_irq_get_msi_base(struct its_device *its_dev) |
1105 | { | |
1106 | struct its_node *its = its_dev->its; | |
1107 | ||
1108 | return its->phys_base + GITS_TRANSLATER; | |
1109 | } | |
1110 | ||
b48ac83d MZ |
1111 | static void its_irq_compose_msi_msg(struct irq_data *d, struct msi_msg *msg) |
1112 | { | |
1113 | struct its_device *its_dev = irq_data_get_irq_chip_data(d); | |
1114 | struct its_node *its; | |
1115 | u64 addr; | |
1116 | ||
1117 | its = its_dev->its; | |
558b0165 | 1118 | addr = its->get_msi_base(its_dev); |
b48ac83d | 1119 | |
b11283eb VM |
1120 | msg->address_lo = lower_32_bits(addr); |
1121 | msg->address_hi = upper_32_bits(addr); | |
b48ac83d | 1122 | msg->data = its_get_event_id(d); |
44bb7e24 RM |
1123 | |
1124 | iommu_dma_map_msi_msg(d->irq, msg); | |
b48ac83d MZ |
1125 | } |
1126 | ||
8d85dced MZ |
1127 | static int its_irq_set_irqchip_state(struct irq_data *d, |
1128 | enum irqchip_irq_state which, | |
1129 | bool state) | |
1130 | { | |
1131 | struct its_device *its_dev = irq_data_get_irq_chip_data(d); | |
1132 | u32 event = its_get_event_id(d); | |
1133 | ||
1134 | if (which != IRQCHIP_STATE_PENDING) | |
1135 | return -EINVAL; | |
1136 | ||
1137 | if (state) | |
1138 | its_send_int(its_dev, event); | |
1139 | else | |
1140 | its_send_clear(its_dev, event); | |
1141 | ||
1142 | return 0; | |
1143 | } | |
1144 | ||
d011e4e6 MZ |
1145 | static int its_vlpi_map(struct irq_data *d, struct its_cmd_info *info) |
1146 | { | |
1147 | struct its_device *its_dev = irq_data_get_irq_chip_data(d); | |
1148 | u32 event = its_get_event_id(d); | |
1149 | int ret = 0; | |
1150 | ||
1151 | if (!info->map) | |
1152 | return -EINVAL; | |
1153 | ||
1154 | mutex_lock(&its_dev->event_map.vlpi_lock); | |
1155 | ||
1156 | if (!its_dev->event_map.vm) { | |
1157 | struct its_vlpi_map *maps; | |
1158 | ||
1159 | maps = kzalloc(sizeof(*maps) * its_dev->event_map.nr_lpis, | |
1160 | GFP_KERNEL); | |
1161 | if (!maps) { | |
1162 | ret = -ENOMEM; | |
1163 | goto out; | |
1164 | } | |
1165 | ||
1166 | its_dev->event_map.vm = info->map->vm; | |
1167 | its_dev->event_map.vlpi_maps = maps; | |
1168 | } else if (its_dev->event_map.vm != info->map->vm) { | |
1169 | ret = -EINVAL; | |
1170 | goto out; | |
1171 | } | |
1172 | ||
1173 | /* Get our private copy of the mapping information */ | |
1174 | its_dev->event_map.vlpi_maps[event] = *info->map; | |
1175 | ||
1176 | if (irqd_is_forwarded_to_vcpu(d)) { | |
1177 | /* Already mapped, move it around */ | |
1178 | its_send_vmovi(its_dev, event); | |
1179 | } else { | |
1180 | /* Drop the physical mapping */ | |
1181 | its_send_discard(its_dev, event); | |
1182 | ||
1183 | /* and install the virtual one */ | |
1184 | its_send_vmapti(its_dev, event); | |
1185 | irqd_set_forwarded_to_vcpu(d); | |
1186 | ||
1187 | /* Increment the number of VLPIs */ | |
1188 | its_dev->event_map.nr_vlpis++; | |
1189 | } | |
1190 | ||
1191 | out: | |
1192 | mutex_unlock(&its_dev->event_map.vlpi_lock); | |
1193 | return ret; | |
1194 | } | |
1195 | ||
1196 | static int its_vlpi_get(struct irq_data *d, struct its_cmd_info *info) | |
1197 | { | |
1198 | struct its_device *its_dev = irq_data_get_irq_chip_data(d); | |
1199 | u32 event = its_get_event_id(d); | |
1200 | int ret = 0; | |
1201 | ||
1202 | mutex_lock(&its_dev->event_map.vlpi_lock); | |
1203 | ||
1204 | if (!its_dev->event_map.vm || | |
1205 | !its_dev->event_map.vlpi_maps[event].vm) { | |
1206 | ret = -EINVAL; | |
1207 | goto out; | |
1208 | } | |
1209 | ||
1210 | /* Copy our mapping information to the incoming request */ | |
1211 | *info->map = its_dev->event_map.vlpi_maps[event]; | |
1212 | ||
1213 | out: | |
1214 | mutex_unlock(&its_dev->event_map.vlpi_lock); | |
1215 | return ret; | |
1216 | } | |
1217 | ||
1218 | static int its_vlpi_unmap(struct irq_data *d) | |
1219 | { | |
1220 | struct its_device *its_dev = irq_data_get_irq_chip_data(d); | |
1221 | u32 event = its_get_event_id(d); | |
1222 | int ret = 0; | |
1223 | ||
1224 | mutex_lock(&its_dev->event_map.vlpi_lock); | |
1225 | ||
1226 | if (!its_dev->event_map.vm || !irqd_is_forwarded_to_vcpu(d)) { | |
1227 | ret = -EINVAL; | |
1228 | goto out; | |
1229 | } | |
1230 | ||
1231 | /* Drop the virtual mapping */ | |
1232 | its_send_discard(its_dev, event); | |
1233 | ||
1234 | /* and restore the physical one */ | |
1235 | irqd_clr_forwarded_to_vcpu(d); | |
1236 | its_send_mapti(its_dev, d->hwirq, event); | |
1237 | lpi_update_config(d, 0xff, (LPI_PROP_DEFAULT_PRIO | | |
1238 | LPI_PROP_ENABLED | | |
1239 | LPI_PROP_GROUP1)); | |
1240 | ||
1241 | /* | |
1242 | * Drop the refcount and make the device available again if | |
1243 | * this was the last VLPI. | |
1244 | */ | |
1245 | if (!--its_dev->event_map.nr_vlpis) { | |
1246 | its_dev->event_map.vm = NULL; | |
1247 | kfree(its_dev->event_map.vlpi_maps); | |
1248 | } | |
1249 | ||
1250 | out: | |
1251 | mutex_unlock(&its_dev->event_map.vlpi_lock); | |
1252 | return ret; | |
1253 | } | |
1254 | ||
015ec038 MZ |
1255 | static int its_vlpi_prop_update(struct irq_data *d, struct its_cmd_info *info) |
1256 | { | |
1257 | struct its_device *its_dev = irq_data_get_irq_chip_data(d); | |
1258 | ||
1259 | if (!its_dev->event_map.vm || !irqd_is_forwarded_to_vcpu(d)) | |
1260 | return -EINVAL; | |
1261 | ||
1262 | if (info->cmd_type == PROP_UPDATE_AND_INV_VLPI) | |
1263 | lpi_update_config(d, 0xff, info->config); | |
1264 | else | |
1265 | lpi_write_config(d, 0xff, info->config); | |
1266 | its_vlpi_set_doorbell(d, !!(info->config & LPI_PROP_ENABLED)); | |
1267 | ||
1268 | return 0; | |
1269 | } | |
1270 | ||
c808eea8 MZ |
1271 | static int its_irq_set_vcpu_affinity(struct irq_data *d, void *vcpu_info) |
1272 | { | |
1273 | struct its_device *its_dev = irq_data_get_irq_chip_data(d); | |
1274 | struct its_cmd_info *info = vcpu_info; | |
1275 | ||
1276 | /* Need a v4 ITS */ | |
d011e4e6 | 1277 | if (!its_dev->its->is_v4) |
c808eea8 MZ |
1278 | return -EINVAL; |
1279 | ||
d011e4e6 MZ |
1280 | /* Unmap request? */ |
1281 | if (!info) | |
1282 | return its_vlpi_unmap(d); | |
1283 | ||
c808eea8 MZ |
1284 | switch (info->cmd_type) { |
1285 | case MAP_VLPI: | |
d011e4e6 | 1286 | return its_vlpi_map(d, info); |
c808eea8 MZ |
1287 | |
1288 | case GET_VLPI: | |
d011e4e6 | 1289 | return its_vlpi_get(d, info); |
c808eea8 MZ |
1290 | |
1291 | case PROP_UPDATE_VLPI: | |
1292 | case PROP_UPDATE_AND_INV_VLPI: | |
015ec038 | 1293 | return its_vlpi_prop_update(d, info); |
c808eea8 MZ |
1294 | |
1295 | default: | |
1296 | return -EINVAL; | |
1297 | } | |
1298 | } | |
1299 | ||
c48ed51c MZ |
1300 | static struct irq_chip its_irq_chip = { |
1301 | .name = "ITS", | |
1302 | .irq_mask = its_mask_irq, | |
1303 | .irq_unmask = its_unmask_irq, | |
004fa08d | 1304 | .irq_eoi = irq_chip_eoi_parent, |
c48ed51c | 1305 | .irq_set_affinity = its_set_affinity, |
b48ac83d | 1306 | .irq_compose_msi_msg = its_irq_compose_msi_msg, |
8d85dced | 1307 | .irq_set_irqchip_state = its_irq_set_irqchip_state, |
c808eea8 | 1308 | .irq_set_vcpu_affinity = its_irq_set_vcpu_affinity, |
b48ac83d MZ |
1309 | }; |
1310 | ||
bf9529f8 MZ |
1311 | /* |
1312 | * How we allocate LPIs: | |
1313 | * | |
1314 | * The GIC has id_bits bits for interrupt identifiers. From there, we | |
1315 | * must subtract 8192 which are reserved for SGIs/PPIs/SPIs. Then, as | |
1316 | * we allocate LPIs by chunks of 32, we can shift the whole thing by 5 | |
1317 | * bits to the right. | |
1318 | * | |
1319 | * This gives us (((1UL << id_bits) - 8192) >> 5) possible allocations. | |
1320 | */ | |
1321 | #define IRQS_PER_CHUNK_SHIFT 5 | |
1322 | #define IRQS_PER_CHUNK (1 << IRQS_PER_CHUNK_SHIFT) | |
6c31e123 | 1323 | #define ITS_MAX_LPI_NRBITS 16 /* 64K LPIs */ |
bf9529f8 MZ |
1324 | |
1325 | static unsigned long *lpi_bitmap; | |
1326 | static u32 lpi_chunks; | |
1327 | static DEFINE_SPINLOCK(lpi_lock); | |
1328 | ||
1329 | static int its_lpi_to_chunk(int lpi) | |
1330 | { | |
1331 | return (lpi - 8192) >> IRQS_PER_CHUNK_SHIFT; | |
1332 | } | |
1333 | ||
1334 | static int its_chunk_to_lpi(int chunk) | |
1335 | { | |
1336 | return (chunk << IRQS_PER_CHUNK_SHIFT) + 8192; | |
1337 | } | |
1338 | ||
04a0e4de | 1339 | static int __init its_lpi_init(u32 id_bits) |
bf9529f8 MZ |
1340 | { |
1341 | lpi_chunks = its_lpi_to_chunk(1UL << id_bits); | |
1342 | ||
1343 | lpi_bitmap = kzalloc(BITS_TO_LONGS(lpi_chunks) * sizeof(long), | |
1344 | GFP_KERNEL); | |
1345 | if (!lpi_bitmap) { | |
1346 | lpi_chunks = 0; | |
1347 | return -ENOMEM; | |
1348 | } | |
1349 | ||
1350 | pr_info("ITS: Allocated %d chunks for LPIs\n", (int)lpi_chunks); | |
1351 | return 0; | |
1352 | } | |
1353 | ||
1354 | static unsigned long *its_lpi_alloc_chunks(int nr_irqs, int *base, int *nr_ids) | |
1355 | { | |
1356 | unsigned long *bitmap = NULL; | |
1357 | int chunk_id; | |
1358 | int nr_chunks; | |
1359 | int i; | |
1360 | ||
1361 | nr_chunks = DIV_ROUND_UP(nr_irqs, IRQS_PER_CHUNK); | |
1362 | ||
1363 | spin_lock(&lpi_lock); | |
1364 | ||
1365 | do { | |
1366 | chunk_id = bitmap_find_next_zero_area(lpi_bitmap, lpi_chunks, | |
1367 | 0, nr_chunks, 0); | |
1368 | if (chunk_id < lpi_chunks) | |
1369 | break; | |
1370 | ||
1371 | nr_chunks--; | |
1372 | } while (nr_chunks > 0); | |
1373 | ||
1374 | if (!nr_chunks) | |
1375 | goto out; | |
1376 | ||
1377 | bitmap = kzalloc(BITS_TO_LONGS(nr_chunks * IRQS_PER_CHUNK) * sizeof (long), | |
1378 | GFP_ATOMIC); | |
1379 | if (!bitmap) | |
1380 | goto out; | |
1381 | ||
1382 | for (i = 0; i < nr_chunks; i++) | |
1383 | set_bit(chunk_id + i, lpi_bitmap); | |
1384 | ||
1385 | *base = its_chunk_to_lpi(chunk_id); | |
1386 | *nr_ids = nr_chunks * IRQS_PER_CHUNK; | |
1387 | ||
1388 | out: | |
1389 | spin_unlock(&lpi_lock); | |
1390 | ||
c8415b94 MZ |
1391 | if (!bitmap) |
1392 | *base = *nr_ids = 0; | |
1393 | ||
bf9529f8 MZ |
1394 | return bitmap; |
1395 | } | |
1396 | ||
cf2be8ba | 1397 | static void its_lpi_free_chunks(unsigned long *bitmap, int base, int nr_ids) |
bf9529f8 MZ |
1398 | { |
1399 | int lpi; | |
1400 | ||
1401 | spin_lock(&lpi_lock); | |
1402 | ||
1403 | for (lpi = base; lpi < (base + nr_ids); lpi += IRQS_PER_CHUNK) { | |
1404 | int chunk = its_lpi_to_chunk(lpi); | |
cf2be8ba | 1405 | |
bf9529f8 MZ |
1406 | BUG_ON(chunk > lpi_chunks); |
1407 | if (test_bit(chunk, lpi_bitmap)) { | |
1408 | clear_bit(chunk, lpi_bitmap); | |
1409 | } else { | |
1410 | pr_err("Bad LPI chunk %d\n", chunk); | |
1411 | } | |
1412 | } | |
1413 | ||
1414 | spin_unlock(&lpi_lock); | |
1415 | ||
cf2be8ba | 1416 | kfree(bitmap); |
bf9529f8 | 1417 | } |
1ac19ca6 | 1418 | |
0e5ccf91 MZ |
1419 | static struct page *its_allocate_prop_table(gfp_t gfp_flags) |
1420 | { | |
1421 | struct page *prop_page; | |
1ac19ca6 | 1422 | |
0e5ccf91 MZ |
1423 | prop_page = alloc_pages(gfp_flags, get_order(LPI_PROPBASE_SZ)); |
1424 | if (!prop_page) | |
1425 | return NULL; | |
1426 | ||
1427 | /* Priority 0xa0, Group-1, disabled */ | |
1428 | memset(page_address(prop_page), | |
1429 | LPI_PROP_DEFAULT_PRIO | LPI_PROP_GROUP1, | |
1430 | LPI_PROPBASE_SZ); | |
1431 | ||
1432 | /* Make sure the GIC will observe the written configuration */ | |
1433 | gic_flush_dcache_to_poc(page_address(prop_page), LPI_PROPBASE_SZ); | |
1434 | ||
1435 | return prop_page; | |
1436 | } | |
1437 | ||
7d75bbb4 MZ |
1438 | static void its_free_prop_table(struct page *prop_page) |
1439 | { | |
1440 | free_pages((unsigned long)page_address(prop_page), | |
1441 | get_order(LPI_PROPBASE_SZ)); | |
1442 | } | |
1ac19ca6 MZ |
1443 | |
1444 | static int __init its_alloc_lpi_tables(void) | |
1445 | { | |
1446 | phys_addr_t paddr; | |
1447 | ||
6c31e123 | 1448 | lpi_id_bits = min_t(u32, gic_rdists->id_bits, ITS_MAX_LPI_NRBITS); |
0e5ccf91 | 1449 | gic_rdists->prop_page = its_allocate_prop_table(GFP_NOWAIT); |
1ac19ca6 MZ |
1450 | if (!gic_rdists->prop_page) { |
1451 | pr_err("Failed to allocate PROPBASE\n"); | |
1452 | return -ENOMEM; | |
1453 | } | |
1454 | ||
1455 | paddr = page_to_phys(gic_rdists->prop_page); | |
1456 | pr_info("GIC: using LPI property table @%pa\n", &paddr); | |
1457 | ||
6c31e123 | 1458 | return its_lpi_init(lpi_id_bits); |
1ac19ca6 MZ |
1459 | } |
1460 | ||
1461 | static const char *its_base_type_string[] = { | |
1462 | [GITS_BASER_TYPE_DEVICE] = "Devices", | |
1463 | [GITS_BASER_TYPE_VCPU] = "Virtual CPUs", | |
4f46de9d | 1464 | [GITS_BASER_TYPE_RESERVED3] = "Reserved (3)", |
1ac19ca6 MZ |
1465 | [GITS_BASER_TYPE_COLLECTION] = "Interrupt Collections", |
1466 | [GITS_BASER_TYPE_RESERVED5] = "Reserved (5)", | |
1467 | [GITS_BASER_TYPE_RESERVED6] = "Reserved (6)", | |
1468 | [GITS_BASER_TYPE_RESERVED7] = "Reserved (7)", | |
1469 | }; | |
1470 | ||
2d81d425 SD |
1471 | static u64 its_read_baser(struct its_node *its, struct its_baser *baser) |
1472 | { | |
1473 | u32 idx = baser - its->tables; | |
1474 | ||
0968a619 | 1475 | return gits_read_baser(its->base + GITS_BASER + (idx << 3)); |
2d81d425 SD |
1476 | } |
1477 | ||
1478 | static void its_write_baser(struct its_node *its, struct its_baser *baser, | |
1479 | u64 val) | |
1480 | { | |
1481 | u32 idx = baser - its->tables; | |
1482 | ||
0968a619 | 1483 | gits_write_baser(val, its->base + GITS_BASER + (idx << 3)); |
2d81d425 SD |
1484 | baser->val = its_read_baser(its, baser); |
1485 | } | |
1486 | ||
9347359a | 1487 | static int its_setup_baser(struct its_node *its, struct its_baser *baser, |
3faf24ea SD |
1488 | u64 cache, u64 shr, u32 psz, u32 order, |
1489 | bool indirect) | |
9347359a SD |
1490 | { |
1491 | u64 val = its_read_baser(its, baser); | |
1492 | u64 esz = GITS_BASER_ENTRY_SIZE(val); | |
1493 | u64 type = GITS_BASER_TYPE(val); | |
1494 | u32 alloc_pages; | |
1495 | void *base; | |
1496 | u64 tmp; | |
1497 | ||
1498 | retry_alloc_baser: | |
1499 | alloc_pages = (PAGE_ORDER_TO_SIZE(order) / psz); | |
1500 | if (alloc_pages > GITS_BASER_PAGES_MAX) { | |
1501 | pr_warn("ITS@%pa: %s too large, reduce ITS pages %u->%u\n", | |
1502 | &its->phys_base, its_base_type_string[type], | |
1503 | alloc_pages, GITS_BASER_PAGES_MAX); | |
1504 | alloc_pages = GITS_BASER_PAGES_MAX; | |
1505 | order = get_order(GITS_BASER_PAGES_MAX * psz); | |
1506 | } | |
1507 | ||
1508 | base = (void *)__get_free_pages(GFP_KERNEL | __GFP_ZERO, order); | |
1509 | if (!base) | |
1510 | return -ENOMEM; | |
1511 | ||
1512 | retry_baser: | |
1513 | val = (virt_to_phys(base) | | |
1514 | (type << GITS_BASER_TYPE_SHIFT) | | |
1515 | ((esz - 1) << GITS_BASER_ENTRY_SIZE_SHIFT) | | |
1516 | ((alloc_pages - 1) << GITS_BASER_PAGES_SHIFT) | | |
1517 | cache | | |
1518 | shr | | |
1519 | GITS_BASER_VALID); | |
1520 | ||
3faf24ea SD |
1521 | val |= indirect ? GITS_BASER_INDIRECT : 0x0; |
1522 | ||
9347359a SD |
1523 | switch (psz) { |
1524 | case SZ_4K: | |
1525 | val |= GITS_BASER_PAGE_SIZE_4K; | |
1526 | break; | |
1527 | case SZ_16K: | |
1528 | val |= GITS_BASER_PAGE_SIZE_16K; | |
1529 | break; | |
1530 | case SZ_64K: | |
1531 | val |= GITS_BASER_PAGE_SIZE_64K; | |
1532 | break; | |
1533 | } | |
1534 | ||
1535 | its_write_baser(its, baser, val); | |
1536 | tmp = baser->val; | |
1537 | ||
1538 | if ((val ^ tmp) & GITS_BASER_SHAREABILITY_MASK) { | |
1539 | /* | |
1540 | * Shareability didn't stick. Just use | |
1541 | * whatever the read reported, which is likely | |
1542 | * to be the only thing this redistributor | |
1543 | * supports. If that's zero, make it | |
1544 | * non-cacheable as well. | |
1545 | */ | |
1546 | shr = tmp & GITS_BASER_SHAREABILITY_MASK; | |
1547 | if (!shr) { | |
1548 | cache = GITS_BASER_nC; | |
328191c0 | 1549 | gic_flush_dcache_to_poc(base, PAGE_ORDER_TO_SIZE(order)); |
9347359a SD |
1550 | } |
1551 | goto retry_baser; | |
1552 | } | |
1553 | ||
1554 | if ((val ^ tmp) & GITS_BASER_PAGE_SIZE_MASK) { | |
1555 | /* | |
1556 | * Page size didn't stick. Let's try a smaller | |
1557 | * size and retry. If we reach 4K, then | |
1558 | * something is horribly wrong... | |
1559 | */ | |
1560 | free_pages((unsigned long)base, order); | |
1561 | baser->base = NULL; | |
1562 | ||
1563 | switch (psz) { | |
1564 | case SZ_16K: | |
1565 | psz = SZ_4K; | |
1566 | goto retry_alloc_baser; | |
1567 | case SZ_64K: | |
1568 | psz = SZ_16K; | |
1569 | goto retry_alloc_baser; | |
1570 | } | |
1571 | } | |
1572 | ||
1573 | if (val != tmp) { | |
b11283eb | 1574 | pr_err("ITS@%pa: %s doesn't stick: %llx %llx\n", |
9347359a | 1575 | &its->phys_base, its_base_type_string[type], |
b11283eb | 1576 | val, tmp); |
9347359a SD |
1577 | free_pages((unsigned long)base, order); |
1578 | return -ENXIO; | |
1579 | } | |
1580 | ||
1581 | baser->order = order; | |
1582 | baser->base = base; | |
1583 | baser->psz = psz; | |
3faf24ea | 1584 | tmp = indirect ? GITS_LVL1_ENTRY_SIZE : esz; |
9347359a | 1585 | |
3faf24ea | 1586 | pr_info("ITS@%pa: allocated %d %s @%lx (%s, esz %d, psz %dK, shr %d)\n", |
d524eaa2 | 1587 | &its->phys_base, (int)(PAGE_ORDER_TO_SIZE(order) / (int)tmp), |
9347359a SD |
1588 | its_base_type_string[type], |
1589 | (unsigned long)virt_to_phys(base), | |
3faf24ea | 1590 | indirect ? "indirect" : "flat", (int)esz, |
9347359a SD |
1591 | psz / SZ_1K, (int)shr >> GITS_BASER_SHAREABILITY_SHIFT); |
1592 | ||
1593 | return 0; | |
1594 | } | |
1595 | ||
4cacac57 MZ |
1596 | static bool its_parse_indirect_baser(struct its_node *its, |
1597 | struct its_baser *baser, | |
1598 | u32 psz, u32 *order) | |
4b75c459 | 1599 | { |
4cacac57 MZ |
1600 | u64 tmp = its_read_baser(its, baser); |
1601 | u64 type = GITS_BASER_TYPE(tmp); | |
1602 | u64 esz = GITS_BASER_ENTRY_SIZE(tmp); | |
2fd632a0 | 1603 | u64 val = GITS_BASER_InnerShareable | GITS_BASER_RaWaWb; |
4b75c459 SD |
1604 | u32 ids = its->device_ids; |
1605 | u32 new_order = *order; | |
3faf24ea SD |
1606 | bool indirect = false; |
1607 | ||
1608 | /* No need to enable Indirection if memory requirement < (psz*2)bytes */ | |
1609 | if ((esz << ids) > (psz * 2)) { | |
1610 | /* | |
1611 | * Find out whether hw supports a single or two-level table by | |
1612 | * table by reading bit at offset '62' after writing '1' to it. | |
1613 | */ | |
1614 | its_write_baser(its, baser, val | GITS_BASER_INDIRECT); | |
1615 | indirect = !!(baser->val & GITS_BASER_INDIRECT); | |
1616 | ||
1617 | if (indirect) { | |
1618 | /* | |
1619 | * The size of the lvl2 table is equal to ITS page size | |
1620 | * which is 'psz'. For computing lvl1 table size, | |
1621 | * subtract ID bits that sparse lvl2 table from 'ids' | |
1622 | * which is reported by ITS hardware times lvl1 table | |
1623 | * entry size. | |
1624 | */ | |
d524eaa2 | 1625 | ids -= ilog2(psz / (int)esz); |
3faf24ea SD |
1626 | esz = GITS_LVL1_ENTRY_SIZE; |
1627 | } | |
1628 | } | |
4b75c459 SD |
1629 | |
1630 | /* | |
1631 | * Allocate as many entries as required to fit the | |
1632 | * range of device IDs that the ITS can grok... The ID | |
1633 | * space being incredibly sparse, this results in a | |
3faf24ea SD |
1634 | * massive waste of memory if two-level device table |
1635 | * feature is not supported by hardware. | |
4b75c459 SD |
1636 | */ |
1637 | new_order = max_t(u32, get_order(esz << ids), new_order); | |
1638 | if (new_order >= MAX_ORDER) { | |
1639 | new_order = MAX_ORDER - 1; | |
d524eaa2 | 1640 | ids = ilog2(PAGE_ORDER_TO_SIZE(new_order) / (int)esz); |
4cacac57 MZ |
1641 | pr_warn("ITS@%pa: %s Table too large, reduce ids %u->%u\n", |
1642 | &its->phys_base, its_base_type_string[type], | |
1643 | its->device_ids, ids); | |
4b75c459 SD |
1644 | } |
1645 | ||
1646 | *order = new_order; | |
3faf24ea SD |
1647 | |
1648 | return indirect; | |
4b75c459 SD |
1649 | } |
1650 | ||
1ac19ca6 MZ |
1651 | static void its_free_tables(struct its_node *its) |
1652 | { | |
1653 | int i; | |
1654 | ||
1655 | for (i = 0; i < GITS_BASER_NR_REGS; i++) { | |
1a485f4d SD |
1656 | if (its->tables[i].base) { |
1657 | free_pages((unsigned long)its->tables[i].base, | |
1658 | its->tables[i].order); | |
1659 | its->tables[i].base = NULL; | |
1ac19ca6 MZ |
1660 | } |
1661 | } | |
1662 | } | |
1663 | ||
0e0b0f69 | 1664 | static int its_alloc_tables(struct its_node *its) |
1ac19ca6 | 1665 | { |
1ac19ca6 | 1666 | u64 shr = GITS_BASER_InnerShareable; |
2fd632a0 | 1667 | u64 cache = GITS_BASER_RaWaWb; |
9347359a SD |
1668 | u32 psz = SZ_64K; |
1669 | int err, i; | |
94100970 | 1670 | |
fa150019 AB |
1671 | if (its->flags & ITS_FLAGS_WORKAROUND_CAVIUM_22375) |
1672 | /* erratum 24313: ignore memory access type */ | |
1673 | cache = GITS_BASER_nCnB; | |
466b7d16 | 1674 | |
1ac19ca6 | 1675 | for (i = 0; i < GITS_BASER_NR_REGS; i++) { |
2d81d425 SD |
1676 | struct its_baser *baser = its->tables + i; |
1677 | u64 val = its_read_baser(its, baser); | |
1ac19ca6 | 1678 | u64 type = GITS_BASER_TYPE(val); |
9347359a | 1679 | u32 order = get_order(psz); |
3faf24ea | 1680 | bool indirect = false; |
1ac19ca6 | 1681 | |
4cacac57 MZ |
1682 | switch (type) { |
1683 | case GITS_BASER_TYPE_NONE: | |
1ac19ca6 MZ |
1684 | continue; |
1685 | ||
4cacac57 MZ |
1686 | case GITS_BASER_TYPE_DEVICE: |
1687 | case GITS_BASER_TYPE_VCPU: | |
1688 | indirect = its_parse_indirect_baser(its, baser, | |
1689 | psz, &order); | |
1690 | break; | |
1691 | } | |
f54b97ed | 1692 | |
3faf24ea | 1693 | err = its_setup_baser(its, baser, cache, shr, psz, order, indirect); |
9347359a SD |
1694 | if (err < 0) { |
1695 | its_free_tables(its); | |
1696 | return err; | |
1ac19ca6 MZ |
1697 | } |
1698 | ||
9347359a SD |
1699 | /* Update settings which will be used for next BASERn */ |
1700 | psz = baser->psz; | |
1701 | cache = baser->val & GITS_BASER_CACHEABILITY_MASK; | |
1702 | shr = baser->val & GITS_BASER_SHAREABILITY_MASK; | |
1ac19ca6 MZ |
1703 | } |
1704 | ||
1705 | return 0; | |
1ac19ca6 MZ |
1706 | } |
1707 | ||
1708 | static int its_alloc_collections(struct its_node *its) | |
1709 | { | |
1710 | its->collections = kzalloc(nr_cpu_ids * sizeof(*its->collections), | |
1711 | GFP_KERNEL); | |
1712 | if (!its->collections) | |
1713 | return -ENOMEM; | |
1714 | ||
1715 | return 0; | |
1716 | } | |
1717 | ||
7c297a2d MZ |
1718 | static struct page *its_allocate_pending_table(gfp_t gfp_flags) |
1719 | { | |
1720 | struct page *pend_page; | |
1721 | /* | |
1722 | * The pending pages have to be at least 64kB aligned, | |
1723 | * hence the 'max(LPI_PENDBASE_SZ, SZ_64K)' below. | |
1724 | */ | |
1725 | pend_page = alloc_pages(gfp_flags | __GFP_ZERO, | |
1726 | get_order(max_t(u32, LPI_PENDBASE_SZ, SZ_64K))); | |
1727 | if (!pend_page) | |
1728 | return NULL; | |
1729 | ||
1730 | /* Make sure the GIC will observe the zero-ed page */ | |
1731 | gic_flush_dcache_to_poc(page_address(pend_page), LPI_PENDBASE_SZ); | |
1732 | ||
1733 | return pend_page; | |
1734 | } | |
1735 | ||
7d75bbb4 MZ |
1736 | static void its_free_pending_table(struct page *pt) |
1737 | { | |
1738 | free_pages((unsigned long)page_address(pt), | |
1739 | get_order(max_t(u32, LPI_PENDBASE_SZ, SZ_64K))); | |
1740 | } | |
1741 | ||
1ac19ca6 MZ |
1742 | static void its_cpu_init_lpis(void) |
1743 | { | |
1744 | void __iomem *rbase = gic_data_rdist_rd_base(); | |
1745 | struct page *pend_page; | |
1746 | u64 val, tmp; | |
1747 | ||
1748 | /* If we didn't allocate the pending table yet, do it now */ | |
1749 | pend_page = gic_data_rdist()->pend_page; | |
1750 | if (!pend_page) { | |
1751 | phys_addr_t paddr; | |
7c297a2d MZ |
1752 | |
1753 | pend_page = its_allocate_pending_table(GFP_NOWAIT); | |
1ac19ca6 MZ |
1754 | if (!pend_page) { |
1755 | pr_err("Failed to allocate PENDBASE for CPU%d\n", | |
1756 | smp_processor_id()); | |
1757 | return; | |
1758 | } | |
1759 | ||
1ac19ca6 MZ |
1760 | paddr = page_to_phys(pend_page); |
1761 | pr_info("CPU%d: using LPI pending table @%pa\n", | |
1762 | smp_processor_id(), &paddr); | |
1763 | gic_data_rdist()->pend_page = pend_page; | |
1764 | } | |
1765 | ||
1766 | /* Disable LPIs */ | |
1767 | val = readl_relaxed(rbase + GICR_CTLR); | |
1768 | val &= ~GICR_CTLR_ENABLE_LPIS; | |
1769 | writel_relaxed(val, rbase + GICR_CTLR); | |
1770 | ||
1771 | /* | |
1772 | * Make sure any change to the table is observable by the GIC. | |
1773 | */ | |
1774 | dsb(sy); | |
1775 | ||
1776 | /* set PROPBASE */ | |
1777 | val = (page_to_phys(gic_rdists->prop_page) | | |
1778 | GICR_PROPBASER_InnerShareable | | |
2fd632a0 | 1779 | GICR_PROPBASER_RaWaWb | |
1ac19ca6 MZ |
1780 | ((LPI_NRBITS - 1) & GICR_PROPBASER_IDBITS_MASK)); |
1781 | ||
0968a619 VM |
1782 | gicr_write_propbaser(val, rbase + GICR_PROPBASER); |
1783 | tmp = gicr_read_propbaser(rbase + GICR_PROPBASER); | |
1ac19ca6 MZ |
1784 | |
1785 | if ((tmp ^ val) & GICR_PROPBASER_SHAREABILITY_MASK) { | |
241a386c MZ |
1786 | if (!(tmp & GICR_PROPBASER_SHAREABILITY_MASK)) { |
1787 | /* | |
1788 | * The HW reports non-shareable, we must | |
1789 | * remove the cacheability attributes as | |
1790 | * well. | |
1791 | */ | |
1792 | val &= ~(GICR_PROPBASER_SHAREABILITY_MASK | | |
1793 | GICR_PROPBASER_CACHEABILITY_MASK); | |
1794 | val |= GICR_PROPBASER_nC; | |
0968a619 | 1795 | gicr_write_propbaser(val, rbase + GICR_PROPBASER); |
241a386c | 1796 | } |
1ac19ca6 MZ |
1797 | pr_info_once("GIC: using cache flushing for LPI property table\n"); |
1798 | gic_rdists->flags |= RDIST_FLAGS_PROPBASE_NEEDS_FLUSHING; | |
1799 | } | |
1800 | ||
1801 | /* set PENDBASE */ | |
1802 | val = (page_to_phys(pend_page) | | |
4ad3e363 | 1803 | GICR_PENDBASER_InnerShareable | |
2fd632a0 | 1804 | GICR_PENDBASER_RaWaWb); |
1ac19ca6 | 1805 | |
0968a619 VM |
1806 | gicr_write_pendbaser(val, rbase + GICR_PENDBASER); |
1807 | tmp = gicr_read_pendbaser(rbase + GICR_PENDBASER); | |
241a386c MZ |
1808 | |
1809 | if (!(tmp & GICR_PENDBASER_SHAREABILITY_MASK)) { | |
1810 | /* | |
1811 | * The HW reports non-shareable, we must remove the | |
1812 | * cacheability attributes as well. | |
1813 | */ | |
1814 | val &= ~(GICR_PENDBASER_SHAREABILITY_MASK | | |
1815 | GICR_PENDBASER_CACHEABILITY_MASK); | |
1816 | val |= GICR_PENDBASER_nC; | |
0968a619 | 1817 | gicr_write_pendbaser(val, rbase + GICR_PENDBASER); |
241a386c | 1818 | } |
1ac19ca6 MZ |
1819 | |
1820 | /* Enable LPIs */ | |
1821 | val = readl_relaxed(rbase + GICR_CTLR); | |
1822 | val |= GICR_CTLR_ENABLE_LPIS; | |
1823 | writel_relaxed(val, rbase + GICR_CTLR); | |
1824 | ||
1825 | /* Make sure the GIC has seen the above */ | |
1826 | dsb(sy); | |
1827 | } | |
1828 | ||
1829 | static void its_cpu_init_collection(void) | |
1830 | { | |
1831 | struct its_node *its; | |
1832 | int cpu; | |
1833 | ||
1834 | spin_lock(&its_lock); | |
1835 | cpu = smp_processor_id(); | |
1836 | ||
1837 | list_for_each_entry(its, &its_nodes, entry) { | |
1838 | u64 target; | |
1839 | ||
fbf8f40e GK |
1840 | /* avoid cross node collections and its mapping */ |
1841 | if (its->flags & ITS_FLAGS_WORKAROUND_CAVIUM_23144) { | |
1842 | struct device_node *cpu_node; | |
1843 | ||
1844 | cpu_node = of_get_cpu_node(cpu, NULL); | |
1845 | if (its->numa_node != NUMA_NO_NODE && | |
1846 | its->numa_node != of_node_to_nid(cpu_node)) | |
1847 | continue; | |
1848 | } | |
1849 | ||
1ac19ca6 MZ |
1850 | /* |
1851 | * We now have to bind each collection to its target | |
1852 | * redistributor. | |
1853 | */ | |
589ce5f4 | 1854 | if (gic_read_typer(its->base + GITS_TYPER) & GITS_TYPER_PTA) { |
1ac19ca6 MZ |
1855 | /* |
1856 | * This ITS wants the physical address of the | |
1857 | * redistributor. | |
1858 | */ | |
1859 | target = gic_data_rdist()->phys_base; | |
1860 | } else { | |
1861 | /* | |
1862 | * This ITS wants a linear CPU number. | |
1863 | */ | |
589ce5f4 | 1864 | target = gic_read_typer(gic_data_rdist_rd_base() + GICR_TYPER); |
263fcd31 | 1865 | target = GICR_TYPER_CPU_NUMBER(target) << 16; |
1ac19ca6 MZ |
1866 | } |
1867 | ||
1868 | /* Perform collection mapping */ | |
1869 | its->collections[cpu].target_address = target; | |
1870 | its->collections[cpu].col_id = cpu; | |
1871 | ||
1872 | its_send_mapc(its, &its->collections[cpu], 1); | |
1873 | its_send_invall(its, &its->collections[cpu]); | |
1874 | } | |
1875 | ||
1876 | spin_unlock(&its_lock); | |
1877 | } | |
84a6a2e7 MZ |
1878 | |
1879 | static struct its_device *its_find_device(struct its_node *its, u32 dev_id) | |
1880 | { | |
1881 | struct its_device *its_dev = NULL, *tmp; | |
3e39e8f5 | 1882 | unsigned long flags; |
84a6a2e7 | 1883 | |
3e39e8f5 | 1884 | raw_spin_lock_irqsave(&its->lock, flags); |
84a6a2e7 MZ |
1885 | |
1886 | list_for_each_entry(tmp, &its->its_device_list, entry) { | |
1887 | if (tmp->device_id == dev_id) { | |
1888 | its_dev = tmp; | |
1889 | break; | |
1890 | } | |
1891 | } | |
1892 | ||
3e39e8f5 | 1893 | raw_spin_unlock_irqrestore(&its->lock, flags); |
84a6a2e7 MZ |
1894 | |
1895 | return its_dev; | |
1896 | } | |
1897 | ||
466b7d16 SD |
1898 | static struct its_baser *its_get_baser(struct its_node *its, u32 type) |
1899 | { | |
1900 | int i; | |
1901 | ||
1902 | for (i = 0; i < GITS_BASER_NR_REGS; i++) { | |
1903 | if (GITS_BASER_TYPE(its->tables[i].val) == type) | |
1904 | return &its->tables[i]; | |
1905 | } | |
1906 | ||
1907 | return NULL; | |
1908 | } | |
1909 | ||
70cc81ed | 1910 | static bool its_alloc_table_entry(struct its_baser *baser, u32 id) |
3faf24ea | 1911 | { |
3faf24ea SD |
1912 | struct page *page; |
1913 | u32 esz, idx; | |
1914 | __le64 *table; | |
1915 | ||
3faf24ea SD |
1916 | /* Don't allow device id that exceeds single, flat table limit */ |
1917 | esz = GITS_BASER_ENTRY_SIZE(baser->val); | |
1918 | if (!(baser->val & GITS_BASER_INDIRECT)) | |
70cc81ed | 1919 | return (id < (PAGE_ORDER_TO_SIZE(baser->order) / esz)); |
3faf24ea SD |
1920 | |
1921 | /* Compute 1st level table index & check if that exceeds table limit */ | |
70cc81ed | 1922 | idx = id >> ilog2(baser->psz / esz); |
3faf24ea SD |
1923 | if (idx >= (PAGE_ORDER_TO_SIZE(baser->order) / GITS_LVL1_ENTRY_SIZE)) |
1924 | return false; | |
1925 | ||
1926 | table = baser->base; | |
1927 | ||
1928 | /* Allocate memory for 2nd level table */ | |
1929 | if (!table[idx]) { | |
1930 | page = alloc_pages(GFP_KERNEL | __GFP_ZERO, get_order(baser->psz)); | |
1931 | if (!page) | |
1932 | return false; | |
1933 | ||
1934 | /* Flush Lvl2 table to PoC if hw doesn't support coherency */ | |
1935 | if (!(baser->val & GITS_BASER_SHAREABILITY_MASK)) | |
328191c0 | 1936 | gic_flush_dcache_to_poc(page_address(page), baser->psz); |
3faf24ea SD |
1937 | |
1938 | table[idx] = cpu_to_le64(page_to_phys(page) | GITS_BASER_VALID); | |
1939 | ||
1940 | /* Flush Lvl1 entry to PoC if hw doesn't support coherency */ | |
1941 | if (!(baser->val & GITS_BASER_SHAREABILITY_MASK)) | |
328191c0 | 1942 | gic_flush_dcache_to_poc(table + idx, GITS_LVL1_ENTRY_SIZE); |
3faf24ea SD |
1943 | |
1944 | /* Ensure updated table contents are visible to ITS hardware */ | |
1945 | dsb(sy); | |
1946 | } | |
1947 | ||
1948 | return true; | |
1949 | } | |
1950 | ||
70cc81ed MZ |
1951 | static bool its_alloc_device_table(struct its_node *its, u32 dev_id) |
1952 | { | |
1953 | struct its_baser *baser; | |
1954 | ||
1955 | baser = its_get_baser(its, GITS_BASER_TYPE_DEVICE); | |
1956 | ||
1957 | /* Don't allow device id that exceeds ITS hardware limit */ | |
1958 | if (!baser) | |
1959 | return (ilog2(dev_id) < its->device_ids); | |
1960 | ||
1961 | return its_alloc_table_entry(baser, dev_id); | |
1962 | } | |
1963 | ||
7d75bbb4 MZ |
1964 | static bool its_alloc_vpe_table(u32 vpe_id) |
1965 | { | |
1966 | struct its_node *its; | |
1967 | ||
1968 | /* | |
1969 | * Make sure the L2 tables are allocated on *all* v4 ITSs. We | |
1970 | * could try and only do it on ITSs corresponding to devices | |
1971 | * that have interrupts targeted at this VPE, but the | |
1972 | * complexity becomes crazy (and you have tons of memory | |
1973 | * anyway, right?). | |
1974 | */ | |
1975 | list_for_each_entry(its, &its_nodes, entry) { | |
1976 | struct its_baser *baser; | |
1977 | ||
1978 | if (!its->is_v4) | |
1979 | continue; | |
3faf24ea | 1980 | |
7d75bbb4 MZ |
1981 | baser = its_get_baser(its, GITS_BASER_TYPE_VCPU); |
1982 | if (!baser) | |
1983 | return false; | |
3faf24ea | 1984 | |
7d75bbb4 MZ |
1985 | if (!its_alloc_table_entry(baser, vpe_id)) |
1986 | return false; | |
3faf24ea SD |
1987 | } |
1988 | ||
1989 | return true; | |
1990 | } | |
1991 | ||
84a6a2e7 | 1992 | static struct its_device *its_create_device(struct its_node *its, u32 dev_id, |
93f94ea0 | 1993 | int nvecs, bool alloc_lpis) |
84a6a2e7 MZ |
1994 | { |
1995 | struct its_device *dev; | |
93f94ea0 | 1996 | unsigned long *lpi_map = NULL; |
3e39e8f5 | 1997 | unsigned long flags; |
591e5bec | 1998 | u16 *col_map = NULL; |
84a6a2e7 MZ |
1999 | void *itt; |
2000 | int lpi_base; | |
2001 | int nr_lpis; | |
c8481267 | 2002 | int nr_ites; |
84a6a2e7 MZ |
2003 | int sz; |
2004 | ||
3faf24ea | 2005 | if (!its_alloc_device_table(its, dev_id)) |
466b7d16 SD |
2006 | return NULL; |
2007 | ||
84a6a2e7 | 2008 | dev = kzalloc(sizeof(*dev), GFP_KERNEL); |
c8481267 MZ |
2009 | /* |
2010 | * At least one bit of EventID is being used, hence a minimum | |
2011 | * of two entries. No, the architecture doesn't let you | |
2012 | * express an ITT with a single entry. | |
2013 | */ | |
96555c47 | 2014 | nr_ites = max(2UL, roundup_pow_of_two(nvecs)); |
c8481267 | 2015 | sz = nr_ites * its->ite_size; |
84a6a2e7 | 2016 | sz = max(sz, ITS_ITT_ALIGN) + ITS_ITT_ALIGN - 1; |
6c834125 | 2017 | itt = kzalloc(sz, GFP_KERNEL); |
93f94ea0 MZ |
2018 | if (alloc_lpis) { |
2019 | lpi_map = its_lpi_alloc_chunks(nvecs, &lpi_base, &nr_lpis); | |
2020 | if (lpi_map) | |
2021 | col_map = kzalloc(sizeof(*col_map) * nr_lpis, | |
2022 | GFP_KERNEL); | |
2023 | } else { | |
2024 | col_map = kzalloc(sizeof(*col_map) * nr_ites, GFP_KERNEL); | |
2025 | nr_lpis = 0; | |
2026 | lpi_base = 0; | |
2027 | } | |
84a6a2e7 | 2028 | |
93f94ea0 | 2029 | if (!dev || !itt || !col_map || (!lpi_map && alloc_lpis)) { |
84a6a2e7 MZ |
2030 | kfree(dev); |
2031 | kfree(itt); | |
2032 | kfree(lpi_map); | |
591e5bec | 2033 | kfree(col_map); |
84a6a2e7 MZ |
2034 | return NULL; |
2035 | } | |
2036 | ||
328191c0 | 2037 | gic_flush_dcache_to_poc(itt, sz); |
5a9a8915 | 2038 | |
84a6a2e7 MZ |
2039 | dev->its = its; |
2040 | dev->itt = itt; | |
c8481267 | 2041 | dev->nr_ites = nr_ites; |
591e5bec MZ |
2042 | dev->event_map.lpi_map = lpi_map; |
2043 | dev->event_map.col_map = col_map; | |
2044 | dev->event_map.lpi_base = lpi_base; | |
2045 | dev->event_map.nr_lpis = nr_lpis; | |
d011e4e6 | 2046 | mutex_init(&dev->event_map.vlpi_lock); |
84a6a2e7 MZ |
2047 | dev->device_id = dev_id; |
2048 | INIT_LIST_HEAD(&dev->entry); | |
2049 | ||
3e39e8f5 | 2050 | raw_spin_lock_irqsave(&its->lock, flags); |
84a6a2e7 | 2051 | list_add(&dev->entry, &its->its_device_list); |
3e39e8f5 | 2052 | raw_spin_unlock_irqrestore(&its->lock, flags); |
84a6a2e7 | 2053 | |
84a6a2e7 MZ |
2054 | /* Map device to its ITT */ |
2055 | its_send_mapd(dev, 1); | |
2056 | ||
2057 | return dev; | |
2058 | } | |
2059 | ||
2060 | static void its_free_device(struct its_device *its_dev) | |
2061 | { | |
3e39e8f5 MZ |
2062 | unsigned long flags; |
2063 | ||
2064 | raw_spin_lock_irqsave(&its_dev->its->lock, flags); | |
84a6a2e7 | 2065 | list_del(&its_dev->entry); |
3e39e8f5 | 2066 | raw_spin_unlock_irqrestore(&its_dev->its->lock, flags); |
84a6a2e7 MZ |
2067 | kfree(its_dev->itt); |
2068 | kfree(its_dev); | |
2069 | } | |
b48ac83d MZ |
2070 | |
2071 | static int its_alloc_device_irq(struct its_device *dev, irq_hw_number_t *hwirq) | |
2072 | { | |
2073 | int idx; | |
2074 | ||
591e5bec MZ |
2075 | idx = find_first_zero_bit(dev->event_map.lpi_map, |
2076 | dev->event_map.nr_lpis); | |
2077 | if (idx == dev->event_map.nr_lpis) | |
b48ac83d MZ |
2078 | return -ENOSPC; |
2079 | ||
591e5bec MZ |
2080 | *hwirq = dev->event_map.lpi_base + idx; |
2081 | set_bit(idx, dev->event_map.lpi_map); | |
b48ac83d | 2082 | |
b48ac83d MZ |
2083 | return 0; |
2084 | } | |
2085 | ||
54456db9 MZ |
2086 | static int its_msi_prepare(struct irq_domain *domain, struct device *dev, |
2087 | int nvec, msi_alloc_info_t *info) | |
e8137f4f | 2088 | { |
b48ac83d | 2089 | struct its_node *its; |
b48ac83d | 2090 | struct its_device *its_dev; |
54456db9 MZ |
2091 | struct msi_domain_info *msi_info; |
2092 | u32 dev_id; | |
2093 | ||
2094 | /* | |
2095 | * We ignore "dev" entierely, and rely on the dev_id that has | |
2096 | * been passed via the scratchpad. This limits this domain's | |
2097 | * usefulness to upper layers that definitely know that they | |
2098 | * are built on top of the ITS. | |
2099 | */ | |
2100 | dev_id = info->scratchpad[0].ul; | |
2101 | ||
2102 | msi_info = msi_get_domain_info(domain); | |
2103 | its = msi_info->data; | |
e8137f4f | 2104 | |
20b3d54e MZ |
2105 | if (!gic_rdists->has_direct_lpi && |
2106 | vpe_proxy.dev && | |
2107 | vpe_proxy.dev->its == its && | |
2108 | dev_id == vpe_proxy.dev->device_id) { | |
2109 | /* Bad luck. Get yourself a better implementation */ | |
2110 | WARN_ONCE(1, "DevId %x clashes with GICv4 VPE proxy device\n", | |
2111 | dev_id); | |
2112 | return -EINVAL; | |
2113 | } | |
2114 | ||
f130420e | 2115 | its_dev = its_find_device(its, dev_id); |
e8137f4f MZ |
2116 | if (its_dev) { |
2117 | /* | |
2118 | * We already have seen this ID, probably through | |
2119 | * another alias (PCI bridge of some sort). No need to | |
2120 | * create the device. | |
2121 | */ | |
f130420e | 2122 | pr_debug("Reusing ITT for devID %x\n", dev_id); |
e8137f4f MZ |
2123 | goto out; |
2124 | } | |
b48ac83d | 2125 | |
93f94ea0 | 2126 | its_dev = its_create_device(its, dev_id, nvec, true); |
b48ac83d MZ |
2127 | if (!its_dev) |
2128 | return -ENOMEM; | |
2129 | ||
f130420e | 2130 | pr_debug("ITT %d entries, %d bits\n", nvec, ilog2(nvec)); |
e8137f4f | 2131 | out: |
b48ac83d | 2132 | info->scratchpad[0].ptr = its_dev; |
b48ac83d MZ |
2133 | return 0; |
2134 | } | |
2135 | ||
54456db9 MZ |
2136 | static struct msi_domain_ops its_msi_domain_ops = { |
2137 | .msi_prepare = its_msi_prepare, | |
2138 | }; | |
2139 | ||
b48ac83d MZ |
2140 | static int its_irq_gic_domain_alloc(struct irq_domain *domain, |
2141 | unsigned int virq, | |
2142 | irq_hw_number_t hwirq) | |
2143 | { | |
f833f57f MZ |
2144 | struct irq_fwspec fwspec; |
2145 | ||
2146 | if (irq_domain_get_of_node(domain->parent)) { | |
2147 | fwspec.fwnode = domain->parent->fwnode; | |
2148 | fwspec.param_count = 3; | |
2149 | fwspec.param[0] = GIC_IRQ_TYPE_LPI; | |
2150 | fwspec.param[1] = hwirq; | |
2151 | fwspec.param[2] = IRQ_TYPE_EDGE_RISING; | |
3f010cf1 TN |
2152 | } else if (is_fwnode_irqchip(domain->parent->fwnode)) { |
2153 | fwspec.fwnode = domain->parent->fwnode; | |
2154 | fwspec.param_count = 2; | |
2155 | fwspec.param[0] = hwirq; | |
2156 | fwspec.param[1] = IRQ_TYPE_EDGE_RISING; | |
f833f57f MZ |
2157 | } else { |
2158 | return -EINVAL; | |
2159 | } | |
b48ac83d | 2160 | |
f833f57f | 2161 | return irq_domain_alloc_irqs_parent(domain, virq, 1, &fwspec); |
b48ac83d MZ |
2162 | } |
2163 | ||
2164 | static int its_irq_domain_alloc(struct irq_domain *domain, unsigned int virq, | |
2165 | unsigned int nr_irqs, void *args) | |
2166 | { | |
2167 | msi_alloc_info_t *info = args; | |
2168 | struct its_device *its_dev = info->scratchpad[0].ptr; | |
2169 | irq_hw_number_t hwirq; | |
2170 | int err; | |
2171 | int i; | |
2172 | ||
2173 | for (i = 0; i < nr_irqs; i++) { | |
2174 | err = its_alloc_device_irq(its_dev, &hwirq); | |
2175 | if (err) | |
2176 | return err; | |
2177 | ||
2178 | err = its_irq_gic_domain_alloc(domain, virq + i, hwirq); | |
2179 | if (err) | |
2180 | return err; | |
2181 | ||
2182 | irq_domain_set_hwirq_and_chip(domain, virq + i, | |
2183 | hwirq, &its_irq_chip, its_dev); | |
0d224d35 | 2184 | irqd_set_single_target(irq_desc_get_irq_data(irq_to_desc(virq + i))); |
f130420e MZ |
2185 | pr_debug("ID:%d pID:%d vID:%d\n", |
2186 | (int)(hwirq - its_dev->event_map.lpi_base), | |
2187 | (int) hwirq, virq + i); | |
b48ac83d MZ |
2188 | } |
2189 | ||
2190 | return 0; | |
2191 | } | |
2192 | ||
72491643 TG |
2193 | static int its_irq_domain_activate(struct irq_domain *domain, |
2194 | struct irq_data *d, bool early) | |
aca268df MZ |
2195 | { |
2196 | struct its_device *its_dev = irq_data_get_irq_chip_data(d); | |
2197 | u32 event = its_get_event_id(d); | |
fbf8f40e | 2198 | const struct cpumask *cpu_mask = cpu_online_mask; |
0d224d35 | 2199 | int cpu; |
fbf8f40e GK |
2200 | |
2201 | /* get the cpu_mask of local node */ | |
2202 | if (its_dev->its->numa_node >= 0) | |
2203 | cpu_mask = cpumask_of_node(its_dev->its->numa_node); | |
aca268df | 2204 | |
591e5bec | 2205 | /* Bind the LPI to the first possible CPU */ |
0d224d35 MZ |
2206 | cpu = cpumask_first(cpu_mask); |
2207 | its_dev->event_map.col_map[event] = cpu; | |
2208 | irq_data_update_effective_affinity(d, cpumask_of(cpu)); | |
591e5bec | 2209 | |
aca268df | 2210 | /* Map the GIC IRQ and event to the device */ |
6a25ad3a | 2211 | its_send_mapti(its_dev, d->hwirq, event); |
72491643 | 2212 | return 0; |
aca268df MZ |
2213 | } |
2214 | ||
2215 | static void its_irq_domain_deactivate(struct irq_domain *domain, | |
2216 | struct irq_data *d) | |
2217 | { | |
2218 | struct its_device *its_dev = irq_data_get_irq_chip_data(d); | |
2219 | u32 event = its_get_event_id(d); | |
2220 | ||
2221 | /* Stop the delivery of interrupts */ | |
2222 | its_send_discard(its_dev, event); | |
2223 | } | |
2224 | ||
b48ac83d MZ |
2225 | static void its_irq_domain_free(struct irq_domain *domain, unsigned int virq, |
2226 | unsigned int nr_irqs) | |
2227 | { | |
2228 | struct irq_data *d = irq_domain_get_irq_data(domain, virq); | |
2229 | struct its_device *its_dev = irq_data_get_irq_chip_data(d); | |
2230 | int i; | |
2231 | ||
2232 | for (i = 0; i < nr_irqs; i++) { | |
2233 | struct irq_data *data = irq_domain_get_irq_data(domain, | |
2234 | virq + i); | |
aca268df | 2235 | u32 event = its_get_event_id(data); |
b48ac83d MZ |
2236 | |
2237 | /* Mark interrupt index as unused */ | |
591e5bec | 2238 | clear_bit(event, its_dev->event_map.lpi_map); |
b48ac83d MZ |
2239 | |
2240 | /* Nuke the entry in the domain */ | |
2da39949 | 2241 | irq_domain_reset_irq_data(data); |
b48ac83d MZ |
2242 | } |
2243 | ||
2244 | /* If all interrupts have been freed, start mopping the floor */ | |
591e5bec MZ |
2245 | if (bitmap_empty(its_dev->event_map.lpi_map, |
2246 | its_dev->event_map.nr_lpis)) { | |
cf2be8ba MZ |
2247 | its_lpi_free_chunks(its_dev->event_map.lpi_map, |
2248 | its_dev->event_map.lpi_base, | |
2249 | its_dev->event_map.nr_lpis); | |
2250 | kfree(its_dev->event_map.col_map); | |
b48ac83d MZ |
2251 | |
2252 | /* Unmap device/itt */ | |
2253 | its_send_mapd(its_dev, 0); | |
2254 | its_free_device(its_dev); | |
2255 | } | |
2256 | ||
2257 | irq_domain_free_irqs_parent(domain, virq, nr_irqs); | |
2258 | } | |
2259 | ||
2260 | static const struct irq_domain_ops its_domain_ops = { | |
2261 | .alloc = its_irq_domain_alloc, | |
2262 | .free = its_irq_domain_free, | |
aca268df MZ |
2263 | .activate = its_irq_domain_activate, |
2264 | .deactivate = its_irq_domain_deactivate, | |
b48ac83d | 2265 | }; |
4c21f3c2 | 2266 | |
20b3d54e MZ |
2267 | /* |
2268 | * This is insane. | |
2269 | * | |
2270 | * If a GICv4 doesn't implement Direct LPIs (which is extremely | |
2271 | * likely), the only way to perform an invalidate is to use a fake | |
2272 | * device to issue an INV command, implying that the LPI has first | |
2273 | * been mapped to some event on that device. Since this is not exactly | |
2274 | * cheap, we try to keep that mapping around as long as possible, and | |
2275 | * only issue an UNMAP if we're short on available slots. | |
2276 | * | |
2277 | * Broken by design(tm). | |
2278 | */ | |
2279 | static void its_vpe_db_proxy_unmap_locked(struct its_vpe *vpe) | |
2280 | { | |
2281 | /* Already unmapped? */ | |
2282 | if (vpe->vpe_proxy_event == -1) | |
2283 | return; | |
2284 | ||
2285 | its_send_discard(vpe_proxy.dev, vpe->vpe_proxy_event); | |
2286 | vpe_proxy.vpes[vpe->vpe_proxy_event] = NULL; | |
2287 | ||
2288 | /* | |
2289 | * We don't track empty slots at all, so let's move the | |
2290 | * next_victim pointer if we can quickly reuse that slot | |
2291 | * instead of nuking an existing entry. Not clear that this is | |
2292 | * always a win though, and this might just generate a ripple | |
2293 | * effect... Let's just hope VPEs don't migrate too often. | |
2294 | */ | |
2295 | if (vpe_proxy.vpes[vpe_proxy.next_victim]) | |
2296 | vpe_proxy.next_victim = vpe->vpe_proxy_event; | |
2297 | ||
2298 | vpe->vpe_proxy_event = -1; | |
2299 | } | |
2300 | ||
2301 | static void its_vpe_db_proxy_unmap(struct its_vpe *vpe) | |
2302 | { | |
2303 | if (!gic_rdists->has_direct_lpi) { | |
2304 | unsigned long flags; | |
2305 | ||
2306 | raw_spin_lock_irqsave(&vpe_proxy.lock, flags); | |
2307 | its_vpe_db_proxy_unmap_locked(vpe); | |
2308 | raw_spin_unlock_irqrestore(&vpe_proxy.lock, flags); | |
2309 | } | |
2310 | } | |
2311 | ||
2312 | static void its_vpe_db_proxy_map_locked(struct its_vpe *vpe) | |
2313 | { | |
2314 | /* Already mapped? */ | |
2315 | if (vpe->vpe_proxy_event != -1) | |
2316 | return; | |
2317 | ||
2318 | /* This slot was already allocated. Kick the other VPE out. */ | |
2319 | if (vpe_proxy.vpes[vpe_proxy.next_victim]) | |
2320 | its_vpe_db_proxy_unmap_locked(vpe_proxy.vpes[vpe_proxy.next_victim]); | |
2321 | ||
2322 | /* Map the new VPE instead */ | |
2323 | vpe_proxy.vpes[vpe_proxy.next_victim] = vpe; | |
2324 | vpe->vpe_proxy_event = vpe_proxy.next_victim; | |
2325 | vpe_proxy.next_victim = (vpe_proxy.next_victim + 1) % vpe_proxy.dev->nr_ites; | |
2326 | ||
2327 | vpe_proxy.dev->event_map.col_map[vpe->vpe_proxy_event] = vpe->col_idx; | |
2328 | its_send_mapti(vpe_proxy.dev, vpe->vpe_db_lpi, vpe->vpe_proxy_event); | |
2329 | } | |
2330 | ||
958b90d1 MZ |
2331 | static void its_vpe_db_proxy_move(struct its_vpe *vpe, int from, int to) |
2332 | { | |
2333 | unsigned long flags; | |
2334 | struct its_collection *target_col; | |
2335 | ||
2336 | if (gic_rdists->has_direct_lpi) { | |
2337 | void __iomem *rdbase; | |
2338 | ||
2339 | rdbase = per_cpu_ptr(gic_rdists->rdist, from)->rd_base; | |
2340 | gic_write_lpir(vpe->vpe_db_lpi, rdbase + GICR_CLRLPIR); | |
2341 | while (gic_read_lpir(rdbase + GICR_SYNCR) & 1) | |
2342 | cpu_relax(); | |
2343 | ||
2344 | return; | |
2345 | } | |
2346 | ||
2347 | raw_spin_lock_irqsave(&vpe_proxy.lock, flags); | |
2348 | ||
2349 | its_vpe_db_proxy_map_locked(vpe); | |
2350 | ||
2351 | target_col = &vpe_proxy.dev->its->collections[to]; | |
2352 | its_send_movi(vpe_proxy.dev, target_col, vpe->vpe_proxy_event); | |
2353 | vpe_proxy.dev->event_map.col_map[vpe->vpe_proxy_event] = to; | |
2354 | ||
2355 | raw_spin_unlock_irqrestore(&vpe_proxy.lock, flags); | |
2356 | } | |
2357 | ||
3171a47a MZ |
2358 | static int its_vpe_set_affinity(struct irq_data *d, |
2359 | const struct cpumask *mask_val, | |
2360 | bool force) | |
2361 | { | |
2362 | struct its_vpe *vpe = irq_data_get_irq_chip_data(d); | |
2363 | int cpu = cpumask_first(mask_val); | |
2364 | ||
2365 | /* | |
2366 | * Changing affinity is mega expensive, so let's be as lazy as | |
20b3d54e | 2367 | * we can and only do it if we really have to. Also, if mapped |
958b90d1 MZ |
2368 | * into the proxy device, we need to move the doorbell |
2369 | * interrupt to its new location. | |
3171a47a MZ |
2370 | */ |
2371 | if (vpe->col_idx != cpu) { | |
958b90d1 MZ |
2372 | int from = vpe->col_idx; |
2373 | ||
3171a47a MZ |
2374 | vpe->col_idx = cpu; |
2375 | its_send_vmovp(vpe); | |
958b90d1 | 2376 | its_vpe_db_proxy_move(vpe, from, cpu); |
3171a47a MZ |
2377 | } |
2378 | ||
2379 | return IRQ_SET_MASK_OK_DONE; | |
2380 | } | |
2381 | ||
e643d803 MZ |
2382 | static void its_vpe_schedule(struct its_vpe *vpe) |
2383 | { | |
2384 | void * __iomem vlpi_base = gic_data_rdist_vlpi_base(); | |
2385 | u64 val; | |
2386 | ||
2387 | /* Schedule the VPE */ | |
2388 | val = virt_to_phys(page_address(vpe->its_vm->vprop_page)) & | |
2389 | GENMASK_ULL(51, 12); | |
2390 | val |= (LPI_NRBITS - 1) & GICR_VPROPBASER_IDBITS_MASK; | |
2391 | val |= GICR_VPROPBASER_RaWb; | |
2392 | val |= GICR_VPROPBASER_InnerShareable; | |
2393 | gits_write_vpropbaser(val, vlpi_base + GICR_VPROPBASER); | |
2394 | ||
2395 | val = virt_to_phys(page_address(vpe->vpt_page)) & | |
2396 | GENMASK_ULL(51, 16); | |
2397 | val |= GICR_VPENDBASER_RaWaWb; | |
2398 | val |= GICR_VPENDBASER_NonShareable; | |
2399 | /* | |
2400 | * There is no good way of finding out if the pending table is | |
2401 | * empty as we can race against the doorbell interrupt very | |
2402 | * easily. So in the end, vpe->pending_last is only an | |
2403 | * indication that the vcpu has something pending, not one | |
2404 | * that the pending table is empty. A good implementation | |
2405 | * would be able to read its coarse map pretty quickly anyway, | |
2406 | * making this a tolerable issue. | |
2407 | */ | |
2408 | val |= GICR_VPENDBASER_PendingLast; | |
2409 | val |= vpe->idai ? GICR_VPENDBASER_IDAI : 0; | |
2410 | val |= GICR_VPENDBASER_Valid; | |
2411 | gits_write_vpendbaser(val, vlpi_base + GICR_VPENDBASER); | |
2412 | } | |
2413 | ||
2414 | static void its_vpe_deschedule(struct its_vpe *vpe) | |
2415 | { | |
2416 | void * __iomem vlpi_base = gic_data_rdist_vlpi_base(); | |
2417 | u32 count = 1000000; /* 1s! */ | |
2418 | bool clean; | |
2419 | u64 val; | |
2420 | ||
2421 | /* We're being scheduled out */ | |
2422 | val = gits_read_vpendbaser(vlpi_base + GICR_VPENDBASER); | |
2423 | val &= ~GICR_VPENDBASER_Valid; | |
2424 | gits_write_vpendbaser(val, vlpi_base + GICR_VPENDBASER); | |
2425 | ||
2426 | do { | |
2427 | val = gits_read_vpendbaser(vlpi_base + GICR_VPENDBASER); | |
2428 | clean = !(val & GICR_VPENDBASER_Dirty); | |
2429 | if (!clean) { | |
2430 | count--; | |
2431 | cpu_relax(); | |
2432 | udelay(1); | |
2433 | } | |
2434 | } while (!clean && count); | |
2435 | ||
2436 | if (unlikely(!clean && !count)) { | |
2437 | pr_err_ratelimited("ITS virtual pending table not cleaning\n"); | |
2438 | vpe->idai = false; | |
2439 | vpe->pending_last = true; | |
2440 | } else { | |
2441 | vpe->idai = !!(val & GICR_VPENDBASER_IDAI); | |
2442 | vpe->pending_last = !!(val & GICR_VPENDBASER_PendingLast); | |
2443 | } | |
2444 | } | |
2445 | ||
2446 | static int its_vpe_set_vcpu_affinity(struct irq_data *d, void *vcpu_info) | |
2447 | { | |
2448 | struct its_vpe *vpe = irq_data_get_irq_chip_data(d); | |
2449 | struct its_cmd_info *info = vcpu_info; | |
2450 | ||
2451 | switch (info->cmd_type) { | |
2452 | case SCHEDULE_VPE: | |
2453 | its_vpe_schedule(vpe); | |
2454 | return 0; | |
2455 | ||
2456 | case DESCHEDULE_VPE: | |
2457 | its_vpe_deschedule(vpe); | |
2458 | return 0; | |
2459 | ||
5e2f7642 MZ |
2460 | case INVALL_VPE: |
2461 | its_send_vinvall(vpe); | |
2462 | return 0; | |
2463 | ||
e643d803 MZ |
2464 | default: |
2465 | return -EINVAL; | |
2466 | } | |
2467 | } | |
2468 | ||
20b3d54e MZ |
2469 | static void its_vpe_send_cmd(struct its_vpe *vpe, |
2470 | void (*cmd)(struct its_device *, u32)) | |
2471 | { | |
2472 | unsigned long flags; | |
2473 | ||
2474 | raw_spin_lock_irqsave(&vpe_proxy.lock, flags); | |
2475 | ||
2476 | its_vpe_db_proxy_map_locked(vpe); | |
2477 | cmd(vpe_proxy.dev, vpe->vpe_proxy_event); | |
2478 | ||
2479 | raw_spin_unlock_irqrestore(&vpe_proxy.lock, flags); | |
2480 | } | |
2481 | ||
f6a91da7 MZ |
2482 | static void its_vpe_send_inv(struct irq_data *d) |
2483 | { | |
2484 | struct its_vpe *vpe = irq_data_get_irq_chip_data(d); | |
f6a91da7 | 2485 | |
20b3d54e MZ |
2486 | if (gic_rdists->has_direct_lpi) { |
2487 | void __iomem *rdbase; | |
2488 | ||
2489 | rdbase = per_cpu_ptr(gic_rdists->rdist, vpe->col_idx)->rd_base; | |
2490 | gic_write_lpir(vpe->vpe_db_lpi, rdbase + GICR_INVLPIR); | |
2491 | while (gic_read_lpir(rdbase + GICR_SYNCR) & 1) | |
2492 | cpu_relax(); | |
2493 | } else { | |
2494 | its_vpe_send_cmd(vpe, its_send_inv); | |
2495 | } | |
f6a91da7 MZ |
2496 | } |
2497 | ||
2498 | static void its_vpe_mask_irq(struct irq_data *d) | |
2499 | { | |
2500 | /* | |
2501 | * We need to unmask the LPI, which is described by the parent | |
2502 | * irq_data. Instead of calling into the parent (which won't | |
2503 | * exactly do the right thing, let's simply use the | |
2504 | * parent_data pointer. Yes, I'm naughty. | |
2505 | */ | |
2506 | lpi_write_config(d->parent_data, LPI_PROP_ENABLED, 0); | |
2507 | its_vpe_send_inv(d); | |
2508 | } | |
2509 | ||
2510 | static void its_vpe_unmask_irq(struct irq_data *d) | |
2511 | { | |
2512 | /* Same hack as above... */ | |
2513 | lpi_write_config(d->parent_data, 0, LPI_PROP_ENABLED); | |
2514 | its_vpe_send_inv(d); | |
2515 | } | |
2516 | ||
e57a3e28 MZ |
2517 | static int its_vpe_set_irqchip_state(struct irq_data *d, |
2518 | enum irqchip_irq_state which, | |
2519 | bool state) | |
2520 | { | |
2521 | struct its_vpe *vpe = irq_data_get_irq_chip_data(d); | |
2522 | ||
2523 | if (which != IRQCHIP_STATE_PENDING) | |
2524 | return -EINVAL; | |
2525 | ||
2526 | if (gic_rdists->has_direct_lpi) { | |
2527 | void __iomem *rdbase; | |
2528 | ||
2529 | rdbase = per_cpu_ptr(gic_rdists->rdist, vpe->col_idx)->rd_base; | |
2530 | if (state) { | |
2531 | gic_write_lpir(vpe->vpe_db_lpi, rdbase + GICR_SETLPIR); | |
2532 | } else { | |
2533 | gic_write_lpir(vpe->vpe_db_lpi, rdbase + GICR_CLRLPIR); | |
2534 | while (gic_read_lpir(rdbase + GICR_SYNCR) & 1) | |
2535 | cpu_relax(); | |
2536 | } | |
2537 | } else { | |
2538 | if (state) | |
2539 | its_vpe_send_cmd(vpe, its_send_int); | |
2540 | else | |
2541 | its_vpe_send_cmd(vpe, its_send_clear); | |
2542 | } | |
2543 | ||
2544 | return 0; | |
2545 | } | |
2546 | ||
8fff27ae MZ |
2547 | static struct irq_chip its_vpe_irq_chip = { |
2548 | .name = "GICv4-vpe", | |
f6a91da7 MZ |
2549 | .irq_mask = its_vpe_mask_irq, |
2550 | .irq_unmask = its_vpe_unmask_irq, | |
2551 | .irq_eoi = irq_chip_eoi_parent, | |
3171a47a | 2552 | .irq_set_affinity = its_vpe_set_affinity, |
e57a3e28 | 2553 | .irq_set_irqchip_state = its_vpe_set_irqchip_state, |
e643d803 | 2554 | .irq_set_vcpu_affinity = its_vpe_set_vcpu_affinity, |
8fff27ae MZ |
2555 | }; |
2556 | ||
7d75bbb4 MZ |
2557 | static int its_vpe_id_alloc(void) |
2558 | { | |
2559 | return ida_simple_get(&its_vpeid_ida, 0, 1 << 16, GFP_KERNEL); | |
2560 | } | |
2561 | ||
2562 | static void its_vpe_id_free(u16 id) | |
2563 | { | |
2564 | ida_simple_remove(&its_vpeid_ida, id); | |
2565 | } | |
2566 | ||
2567 | static int its_vpe_init(struct its_vpe *vpe) | |
2568 | { | |
2569 | struct page *vpt_page; | |
2570 | int vpe_id; | |
2571 | ||
2572 | /* Allocate vpe_id */ | |
2573 | vpe_id = its_vpe_id_alloc(); | |
2574 | if (vpe_id < 0) | |
2575 | return vpe_id; | |
2576 | ||
2577 | /* Allocate VPT */ | |
2578 | vpt_page = its_allocate_pending_table(GFP_KERNEL); | |
2579 | if (!vpt_page) { | |
2580 | its_vpe_id_free(vpe_id); | |
2581 | return -ENOMEM; | |
2582 | } | |
2583 | ||
2584 | if (!its_alloc_vpe_table(vpe_id)) { | |
2585 | its_vpe_id_free(vpe_id); | |
2586 | its_free_pending_table(vpe->vpt_page); | |
2587 | return -ENOMEM; | |
2588 | } | |
2589 | ||
2590 | vpe->vpe_id = vpe_id; | |
2591 | vpe->vpt_page = vpt_page; | |
20b3d54e | 2592 | vpe->vpe_proxy_event = -1; |
7d75bbb4 MZ |
2593 | |
2594 | return 0; | |
2595 | } | |
2596 | ||
2597 | static void its_vpe_teardown(struct its_vpe *vpe) | |
2598 | { | |
20b3d54e | 2599 | its_vpe_db_proxy_unmap(vpe); |
7d75bbb4 MZ |
2600 | its_vpe_id_free(vpe->vpe_id); |
2601 | its_free_pending_table(vpe->vpt_page); | |
2602 | } | |
2603 | ||
2604 | static void its_vpe_irq_domain_free(struct irq_domain *domain, | |
2605 | unsigned int virq, | |
2606 | unsigned int nr_irqs) | |
2607 | { | |
2608 | struct its_vm *vm = domain->host_data; | |
2609 | int i; | |
2610 | ||
2611 | irq_domain_free_irqs_parent(domain, virq, nr_irqs); | |
2612 | ||
2613 | for (i = 0; i < nr_irqs; i++) { | |
2614 | struct irq_data *data = irq_domain_get_irq_data(domain, | |
2615 | virq + i); | |
2616 | struct its_vpe *vpe = irq_data_get_irq_chip_data(data); | |
2617 | ||
2618 | BUG_ON(vm != vpe->its_vm); | |
2619 | ||
2620 | clear_bit(data->hwirq, vm->db_bitmap); | |
2621 | its_vpe_teardown(vpe); | |
2622 | irq_domain_reset_irq_data(data); | |
2623 | } | |
2624 | ||
2625 | if (bitmap_empty(vm->db_bitmap, vm->nr_db_lpis)) { | |
2626 | its_lpi_free_chunks(vm->db_bitmap, vm->db_lpi_base, vm->nr_db_lpis); | |
2627 | its_free_prop_table(vm->vprop_page); | |
2628 | } | |
2629 | } | |
2630 | ||
2631 | static int its_vpe_irq_domain_alloc(struct irq_domain *domain, unsigned int virq, | |
2632 | unsigned int nr_irqs, void *args) | |
2633 | { | |
2634 | struct its_vm *vm = args; | |
2635 | unsigned long *bitmap; | |
2636 | struct page *vprop_page; | |
2637 | int base, nr_ids, i, err = 0; | |
2638 | ||
2639 | BUG_ON(!vm); | |
2640 | ||
2641 | bitmap = its_lpi_alloc_chunks(nr_irqs, &base, &nr_ids); | |
2642 | if (!bitmap) | |
2643 | return -ENOMEM; | |
2644 | ||
2645 | if (nr_ids < nr_irqs) { | |
2646 | its_lpi_free_chunks(bitmap, base, nr_ids); | |
2647 | return -ENOMEM; | |
2648 | } | |
2649 | ||
2650 | vprop_page = its_allocate_prop_table(GFP_KERNEL); | |
2651 | if (!vprop_page) { | |
2652 | its_lpi_free_chunks(bitmap, base, nr_ids); | |
2653 | return -ENOMEM; | |
2654 | } | |
2655 | ||
2656 | vm->db_bitmap = bitmap; | |
2657 | vm->db_lpi_base = base; | |
2658 | vm->nr_db_lpis = nr_ids; | |
2659 | vm->vprop_page = vprop_page; | |
2660 | ||
2661 | for (i = 0; i < nr_irqs; i++) { | |
2662 | vm->vpes[i]->vpe_db_lpi = base + i; | |
2663 | err = its_vpe_init(vm->vpes[i]); | |
2664 | if (err) | |
2665 | break; | |
2666 | err = its_irq_gic_domain_alloc(domain, virq + i, | |
2667 | vm->vpes[i]->vpe_db_lpi); | |
2668 | if (err) | |
2669 | break; | |
2670 | irq_domain_set_hwirq_and_chip(domain, virq + i, i, | |
2671 | &its_vpe_irq_chip, vm->vpes[i]); | |
2672 | set_bit(i, bitmap); | |
2673 | } | |
2674 | ||
2675 | if (err) { | |
2676 | if (i > 0) | |
2677 | its_vpe_irq_domain_free(domain, virq, i - 1); | |
2678 | ||
2679 | its_lpi_free_chunks(bitmap, base, nr_ids); | |
2680 | its_free_prop_table(vprop_page); | |
2681 | } | |
2682 | ||
2683 | return err; | |
2684 | } | |
2685 | ||
72491643 TG |
2686 | static int its_vpe_irq_domain_activate(struct irq_domain *domain, |
2687 | struct irq_data *d, bool early) | |
eb78192b MZ |
2688 | { |
2689 | struct its_vpe *vpe = irq_data_get_irq_chip_data(d); | |
2690 | ||
2691 | /* Map the VPE to the first possible CPU */ | |
2692 | vpe->col_idx = cpumask_first(cpu_online_mask); | |
2693 | its_send_vmapp(vpe, true); | |
2694 | its_send_vinvall(vpe); | |
72491643 | 2695 | return 0; |
eb78192b MZ |
2696 | } |
2697 | ||
2698 | static void its_vpe_irq_domain_deactivate(struct irq_domain *domain, | |
2699 | struct irq_data *d) | |
2700 | { | |
2701 | struct its_vpe *vpe = irq_data_get_irq_chip_data(d); | |
2702 | ||
2703 | its_send_vmapp(vpe, false); | |
2704 | } | |
2705 | ||
8fff27ae | 2706 | static const struct irq_domain_ops its_vpe_domain_ops = { |
7d75bbb4 MZ |
2707 | .alloc = its_vpe_irq_domain_alloc, |
2708 | .free = its_vpe_irq_domain_free, | |
eb78192b MZ |
2709 | .activate = its_vpe_irq_domain_activate, |
2710 | .deactivate = its_vpe_irq_domain_deactivate, | |
8fff27ae MZ |
2711 | }; |
2712 | ||
4559fbb3 YW |
2713 | static int its_force_quiescent(void __iomem *base) |
2714 | { | |
2715 | u32 count = 1000000; /* 1s */ | |
2716 | u32 val; | |
2717 | ||
2718 | val = readl_relaxed(base + GITS_CTLR); | |
7611da86 DD |
2719 | /* |
2720 | * GIC architecture specification requires the ITS to be both | |
2721 | * disabled and quiescent for writes to GITS_BASER<n> or | |
2722 | * GITS_CBASER to not have UNPREDICTABLE results. | |
2723 | */ | |
2724 | if ((val & GITS_CTLR_QUIESCENT) && !(val & GITS_CTLR_ENABLE)) | |
4559fbb3 YW |
2725 | return 0; |
2726 | ||
2727 | /* Disable the generation of all interrupts to this ITS */ | |
d51c4b4d | 2728 | val &= ~(GITS_CTLR_ENABLE | GITS_CTLR_ImDe); |
4559fbb3 YW |
2729 | writel_relaxed(val, base + GITS_CTLR); |
2730 | ||
2731 | /* Poll GITS_CTLR and wait until ITS becomes quiescent */ | |
2732 | while (1) { | |
2733 | val = readl_relaxed(base + GITS_CTLR); | |
2734 | if (val & GITS_CTLR_QUIESCENT) | |
2735 | return 0; | |
2736 | ||
2737 | count--; | |
2738 | if (!count) | |
2739 | return -EBUSY; | |
2740 | ||
2741 | cpu_relax(); | |
2742 | udelay(1); | |
2743 | } | |
2744 | } | |
2745 | ||
9d111d49 | 2746 | static bool __maybe_unused its_enable_quirk_cavium_22375(void *data) |
94100970 RR |
2747 | { |
2748 | struct its_node *its = data; | |
2749 | ||
fa150019 AB |
2750 | /* erratum 22375: only alloc 8MB table size */ |
2751 | its->device_ids = 0x14; /* 20 bits, 8MB */ | |
94100970 | 2752 | its->flags |= ITS_FLAGS_WORKAROUND_CAVIUM_22375; |
9d111d49 AB |
2753 | |
2754 | return true; | |
94100970 RR |
2755 | } |
2756 | ||
9d111d49 | 2757 | static bool __maybe_unused its_enable_quirk_cavium_23144(void *data) |
fbf8f40e GK |
2758 | { |
2759 | struct its_node *its = data; | |
2760 | ||
2761 | its->flags |= ITS_FLAGS_WORKAROUND_CAVIUM_23144; | |
9d111d49 AB |
2762 | |
2763 | return true; | |
fbf8f40e GK |
2764 | } |
2765 | ||
9d111d49 | 2766 | static bool __maybe_unused its_enable_quirk_qdf2400_e0065(void *data) |
90922a2d SD |
2767 | { |
2768 | struct its_node *its = data; | |
2769 | ||
2770 | /* On QDF2400, the size of the ITE is 16Bytes */ | |
2771 | its->ite_size = 16; | |
9d111d49 AB |
2772 | |
2773 | return true; | |
90922a2d SD |
2774 | } |
2775 | ||
558b0165 AB |
2776 | static u64 its_irq_get_msi_base_pre_its(struct its_device *its_dev) |
2777 | { | |
2778 | struct its_node *its = its_dev->its; | |
2779 | ||
2780 | /* | |
2781 | * The Socionext Synquacer SoC has a so-called 'pre-ITS', | |
2782 | * which maps 32-bit writes targeted at a separate window of | |
2783 | * size '4 << device_id_bits' onto writes to GITS_TRANSLATER | |
2784 | * with device ID taken from bits [device_id_bits + 1:2] of | |
2785 | * the window offset. | |
2786 | */ | |
2787 | return its->pre_its_base + (its_dev->device_id << 2); | |
2788 | } | |
2789 | ||
2790 | static bool __maybe_unused its_enable_quirk_socionext_synquacer(void *data) | |
2791 | { | |
2792 | struct its_node *its = data; | |
2793 | u32 pre_its_window[2]; | |
2794 | u32 ids; | |
2795 | ||
2796 | if (!fwnode_property_read_u32_array(its->fwnode_handle, | |
2797 | "socionext,synquacer-pre-its", | |
2798 | pre_its_window, | |
2799 | ARRAY_SIZE(pre_its_window))) { | |
2800 | ||
2801 | its->pre_its_base = pre_its_window[0]; | |
2802 | its->get_msi_base = its_irq_get_msi_base_pre_its; | |
2803 | ||
2804 | ids = ilog2(pre_its_window[1]) - 2; | |
2805 | if (its->device_ids > ids) | |
2806 | its->device_ids = ids; | |
2807 | ||
2808 | /* the pre-ITS breaks isolation, so disable MSI remapping */ | |
2809 | its->msi_domain_flags &= ~IRQ_DOMAIN_FLAG_MSI_REMAP; | |
2810 | return true; | |
2811 | } | |
2812 | return false; | |
2813 | } | |
2814 | ||
67510cca | 2815 | static const struct gic_quirk its_quirks[] = { |
94100970 RR |
2816 | #ifdef CONFIG_CAVIUM_ERRATUM_22375 |
2817 | { | |
2818 | .desc = "ITS: Cavium errata 22375, 24313", | |
2819 | .iidr = 0xa100034c, /* ThunderX pass 1.x */ | |
2820 | .mask = 0xffff0fff, | |
2821 | .init = its_enable_quirk_cavium_22375, | |
2822 | }, | |
fbf8f40e GK |
2823 | #endif |
2824 | #ifdef CONFIG_CAVIUM_ERRATUM_23144 | |
2825 | { | |
2826 | .desc = "ITS: Cavium erratum 23144", | |
2827 | .iidr = 0xa100034c, /* ThunderX pass 1.x */ | |
2828 | .mask = 0xffff0fff, | |
2829 | .init = its_enable_quirk_cavium_23144, | |
2830 | }, | |
90922a2d SD |
2831 | #endif |
2832 | #ifdef CONFIG_QCOM_QDF2400_ERRATUM_0065 | |
2833 | { | |
2834 | .desc = "ITS: QDF2400 erratum 0065", | |
2835 | .iidr = 0x00001070, /* QDF2400 ITS rev 1.x */ | |
2836 | .mask = 0xffffffff, | |
2837 | .init = its_enable_quirk_qdf2400_e0065, | |
2838 | }, | |
558b0165 AB |
2839 | #endif |
2840 | #ifdef CONFIG_SOCIONEXT_SYNQUACER_PREITS | |
2841 | { | |
2842 | /* | |
2843 | * The Socionext Synquacer SoC incorporates ARM's own GIC-500 | |
2844 | * implementation, but with a 'pre-ITS' added that requires | |
2845 | * special handling in software. | |
2846 | */ | |
2847 | .desc = "ITS: Socionext Synquacer pre-ITS", | |
2848 | .iidr = 0x0001143b, | |
2849 | .mask = 0xffffffff, | |
2850 | .init = its_enable_quirk_socionext_synquacer, | |
2851 | }, | |
94100970 | 2852 | #endif |
67510cca RR |
2853 | { |
2854 | } | |
2855 | }; | |
2856 | ||
2857 | static void its_enable_quirks(struct its_node *its) | |
2858 | { | |
2859 | u32 iidr = readl_relaxed(its->base + GITS_IIDR); | |
2860 | ||
2861 | gic_enable_quirks(iidr, its_quirks, its); | |
2862 | } | |
2863 | ||
db40f0a7 | 2864 | static int its_init_domain(struct fwnode_handle *handle, struct its_node *its) |
d14ae5e6 TN |
2865 | { |
2866 | struct irq_domain *inner_domain; | |
2867 | struct msi_domain_info *info; | |
2868 | ||
2869 | info = kzalloc(sizeof(*info), GFP_KERNEL); | |
2870 | if (!info) | |
2871 | return -ENOMEM; | |
2872 | ||
db40f0a7 | 2873 | inner_domain = irq_domain_create_tree(handle, &its_domain_ops, its); |
d14ae5e6 TN |
2874 | if (!inner_domain) { |
2875 | kfree(info); | |
2876 | return -ENOMEM; | |
2877 | } | |
2878 | ||
db40f0a7 | 2879 | inner_domain->parent = its_parent; |
96f0d93a | 2880 | irq_domain_update_bus_token(inner_domain, DOMAIN_BUS_NEXUS); |
558b0165 | 2881 | inner_domain->flags |= its->msi_domain_flags; |
d14ae5e6 TN |
2882 | info->ops = &its_msi_domain_ops; |
2883 | info->data = its; | |
2884 | inner_domain->host_data = info; | |
2885 | ||
2886 | return 0; | |
2887 | } | |
2888 | ||
8fff27ae MZ |
2889 | static int its_init_vpe_domain(void) |
2890 | { | |
20b3d54e MZ |
2891 | struct its_node *its; |
2892 | u32 devid; | |
2893 | int entries; | |
2894 | ||
2895 | if (gic_rdists->has_direct_lpi) { | |
2896 | pr_info("ITS: Using DirectLPI for VPE invalidation\n"); | |
2897 | return 0; | |
2898 | } | |
2899 | ||
2900 | /* Any ITS will do, even if not v4 */ | |
2901 | its = list_first_entry(&its_nodes, struct its_node, entry); | |
2902 | ||
2903 | entries = roundup_pow_of_two(nr_cpu_ids); | |
2904 | vpe_proxy.vpes = kzalloc(sizeof(*vpe_proxy.vpes) * entries, | |
2905 | GFP_KERNEL); | |
2906 | if (!vpe_proxy.vpes) { | |
2907 | pr_err("ITS: Can't allocate GICv4 proxy device array\n"); | |
2908 | return -ENOMEM; | |
2909 | } | |
2910 | ||
2911 | /* Use the last possible DevID */ | |
2912 | devid = GENMASK(its->device_ids - 1, 0); | |
2913 | vpe_proxy.dev = its_create_device(its, devid, entries, false); | |
2914 | if (!vpe_proxy.dev) { | |
2915 | kfree(vpe_proxy.vpes); | |
2916 | pr_err("ITS: Can't allocate GICv4 proxy device\n"); | |
2917 | return -ENOMEM; | |
2918 | } | |
2919 | ||
2920 | BUG_ON(entries != vpe_proxy.dev->nr_ites); | |
2921 | ||
2922 | raw_spin_lock_init(&vpe_proxy.lock); | |
2923 | vpe_proxy.next_victim = 0; | |
2924 | pr_info("ITS: Allocated DevID %x as GICv4 proxy device (%d slots)\n", | |
2925 | devid, vpe_proxy.dev->nr_ites); | |
2926 | ||
8fff27ae MZ |
2927 | return 0; |
2928 | } | |
2929 | ||
3dfa576b MZ |
2930 | static int __init its_compute_its_list_map(struct resource *res, |
2931 | void __iomem *its_base) | |
2932 | { | |
2933 | int its_number; | |
2934 | u32 ctlr; | |
2935 | ||
2936 | /* | |
2937 | * This is assumed to be done early enough that we're | |
2938 | * guaranteed to be single-threaded, hence no | |
2939 | * locking. Should this change, we should address | |
2940 | * this. | |
2941 | */ | |
2942 | its_number = find_first_zero_bit(&its_list_map, ITS_LIST_MAX); | |
2943 | if (its_number >= ITS_LIST_MAX) { | |
2944 | pr_err("ITS@%pa: No ITSList entry available!\n", | |
2945 | &res->start); | |
2946 | return -EINVAL; | |
2947 | } | |
2948 | ||
2949 | ctlr = readl_relaxed(its_base + GITS_CTLR); | |
2950 | ctlr &= ~GITS_CTLR_ITS_NUMBER; | |
2951 | ctlr |= its_number << GITS_CTLR_ITS_NUMBER_SHIFT; | |
2952 | writel_relaxed(ctlr, its_base + GITS_CTLR); | |
2953 | ctlr = readl_relaxed(its_base + GITS_CTLR); | |
2954 | if ((ctlr & GITS_CTLR_ITS_NUMBER) != (its_number << GITS_CTLR_ITS_NUMBER_SHIFT)) { | |
2955 | its_number = ctlr & GITS_CTLR_ITS_NUMBER; | |
2956 | its_number >>= GITS_CTLR_ITS_NUMBER_SHIFT; | |
2957 | } | |
2958 | ||
2959 | if (test_and_set_bit(its_number, &its_list_map)) { | |
2960 | pr_err("ITS@%pa: Duplicate ITSList entry %d\n", | |
2961 | &res->start, its_number); | |
2962 | return -EINVAL; | |
2963 | } | |
2964 | ||
2965 | return its_number; | |
2966 | } | |
2967 | ||
db40f0a7 TN |
2968 | static int __init its_probe_one(struct resource *res, |
2969 | struct fwnode_handle *handle, int numa_node) | |
4c21f3c2 | 2970 | { |
4c21f3c2 MZ |
2971 | struct its_node *its; |
2972 | void __iomem *its_base; | |
3dfa576b MZ |
2973 | u32 val, ctlr; |
2974 | u64 baser, tmp, typer; | |
4c21f3c2 MZ |
2975 | int err; |
2976 | ||
db40f0a7 | 2977 | its_base = ioremap(res->start, resource_size(res)); |
4c21f3c2 | 2978 | if (!its_base) { |
db40f0a7 | 2979 | pr_warn("ITS@%pa: Unable to map ITS registers\n", &res->start); |
4c21f3c2 MZ |
2980 | return -ENOMEM; |
2981 | } | |
2982 | ||
2983 | val = readl_relaxed(its_base + GITS_PIDR2) & GIC_PIDR2_ARCH_MASK; | |
2984 | if (val != 0x30 && val != 0x40) { | |
db40f0a7 | 2985 | pr_warn("ITS@%pa: No ITS detected, giving up\n", &res->start); |
4c21f3c2 MZ |
2986 | err = -ENODEV; |
2987 | goto out_unmap; | |
2988 | } | |
2989 | ||
4559fbb3 YW |
2990 | err = its_force_quiescent(its_base); |
2991 | if (err) { | |
db40f0a7 | 2992 | pr_warn("ITS@%pa: Failed to quiesce, giving up\n", &res->start); |
4559fbb3 YW |
2993 | goto out_unmap; |
2994 | } | |
2995 | ||
db40f0a7 | 2996 | pr_info("ITS %pR\n", res); |
4c21f3c2 MZ |
2997 | |
2998 | its = kzalloc(sizeof(*its), GFP_KERNEL); | |
2999 | if (!its) { | |
3000 | err = -ENOMEM; | |
3001 | goto out_unmap; | |
3002 | } | |
3003 | ||
3004 | raw_spin_lock_init(&its->lock); | |
3005 | INIT_LIST_HEAD(&its->entry); | |
3006 | INIT_LIST_HEAD(&its->its_device_list); | |
3dfa576b | 3007 | typer = gic_read_typer(its_base + GITS_TYPER); |
4c21f3c2 | 3008 | its->base = its_base; |
db40f0a7 | 3009 | its->phys_base = res->start; |
3dfa576b | 3010 | its->ite_size = GITS_TYPER_ITT_ENTRY_SIZE(typer); |
fa150019 | 3011 | its->device_ids = GITS_TYPER_DEVBITS(typer); |
3dfa576b MZ |
3012 | its->is_v4 = !!(typer & GITS_TYPER_VLPIS); |
3013 | if (its->is_v4) { | |
3014 | if (!(typer & GITS_TYPER_VMOVP)) { | |
3015 | err = its_compute_its_list_map(res, its_base); | |
3016 | if (err < 0) | |
3017 | goto out_free_its; | |
3018 | ||
3019 | pr_info("ITS@%pa: Using ITS number %d\n", | |
3020 | &res->start, err); | |
3021 | } else { | |
3022 | pr_info("ITS@%pa: Single VMOVP capable\n", &res->start); | |
3023 | } | |
3024 | } | |
3025 | ||
db40f0a7 | 3026 | its->numa_node = numa_node; |
4c21f3c2 | 3027 | |
5bc13c2c RR |
3028 | its->cmd_base = (void *)__get_free_pages(GFP_KERNEL | __GFP_ZERO, |
3029 | get_order(ITS_CMD_QUEUE_SZ)); | |
4c21f3c2 MZ |
3030 | if (!its->cmd_base) { |
3031 | err = -ENOMEM; | |
3032 | goto out_free_its; | |
3033 | } | |
3034 | its->cmd_write = its->cmd_base; | |
558b0165 AB |
3035 | its->fwnode_handle = handle; |
3036 | its->get_msi_base = its_irq_get_msi_base; | |
3037 | its->msi_domain_flags = IRQ_DOMAIN_FLAG_MSI_REMAP; | |
4c21f3c2 | 3038 | |
67510cca RR |
3039 | its_enable_quirks(its); |
3040 | ||
0e0b0f69 | 3041 | err = its_alloc_tables(its); |
4c21f3c2 MZ |
3042 | if (err) |
3043 | goto out_free_cmd; | |
3044 | ||
3045 | err = its_alloc_collections(its); | |
3046 | if (err) | |
3047 | goto out_free_tables; | |
3048 | ||
3049 | baser = (virt_to_phys(its->cmd_base) | | |
2fd632a0 | 3050 | GITS_CBASER_RaWaWb | |
4c21f3c2 MZ |
3051 | GITS_CBASER_InnerShareable | |
3052 | (ITS_CMD_QUEUE_SZ / SZ_4K - 1) | | |
3053 | GITS_CBASER_VALID); | |
3054 | ||
0968a619 VM |
3055 | gits_write_cbaser(baser, its->base + GITS_CBASER); |
3056 | tmp = gits_read_cbaser(its->base + GITS_CBASER); | |
4c21f3c2 | 3057 | |
4ad3e363 | 3058 | if ((tmp ^ baser) & GITS_CBASER_SHAREABILITY_MASK) { |
241a386c MZ |
3059 | if (!(tmp & GITS_CBASER_SHAREABILITY_MASK)) { |
3060 | /* | |
3061 | * The HW reports non-shareable, we must | |
3062 | * remove the cacheability attributes as | |
3063 | * well. | |
3064 | */ | |
3065 | baser &= ~(GITS_CBASER_SHAREABILITY_MASK | | |
3066 | GITS_CBASER_CACHEABILITY_MASK); | |
3067 | baser |= GITS_CBASER_nC; | |
0968a619 | 3068 | gits_write_cbaser(baser, its->base + GITS_CBASER); |
241a386c | 3069 | } |
4c21f3c2 MZ |
3070 | pr_info("ITS: using cache flushing for cmd queue\n"); |
3071 | its->flags |= ITS_FLAGS_CMDQ_NEEDS_FLUSHING; | |
3072 | } | |
3073 | ||
0968a619 | 3074 | gits_write_cwriter(0, its->base + GITS_CWRITER); |
3dfa576b | 3075 | ctlr = readl_relaxed(its->base + GITS_CTLR); |
d51c4b4d MZ |
3076 | ctlr |= GITS_CTLR_ENABLE; |
3077 | if (its->is_v4) | |
3078 | ctlr |= GITS_CTLR_ImDe; | |
3079 | writel_relaxed(ctlr, its->base + GITS_CTLR); | |
241a386c | 3080 | |
db40f0a7 | 3081 | err = its_init_domain(handle, its); |
d14ae5e6 TN |
3082 | if (err) |
3083 | goto out_free_tables; | |
4c21f3c2 MZ |
3084 | |
3085 | spin_lock(&its_lock); | |
3086 | list_add(&its->entry, &its_nodes); | |
3087 | spin_unlock(&its_lock); | |
3088 | ||
3089 | return 0; | |
3090 | ||
4c21f3c2 MZ |
3091 | out_free_tables: |
3092 | its_free_tables(its); | |
3093 | out_free_cmd: | |
5bc13c2c | 3094 | free_pages((unsigned long)its->cmd_base, get_order(ITS_CMD_QUEUE_SZ)); |
4c21f3c2 MZ |
3095 | out_free_its: |
3096 | kfree(its); | |
3097 | out_unmap: | |
3098 | iounmap(its_base); | |
db40f0a7 | 3099 | pr_err("ITS@%pa: failed probing (%d)\n", &res->start, err); |
4c21f3c2 MZ |
3100 | return err; |
3101 | } | |
3102 | ||
3103 | static bool gic_rdists_supports_plpis(void) | |
3104 | { | |
589ce5f4 | 3105 | return !!(gic_read_typer(gic_data_rdist_rd_base() + GICR_TYPER) & GICR_TYPER_PLPIS); |
4c21f3c2 MZ |
3106 | } |
3107 | ||
3108 | int its_cpu_init(void) | |
3109 | { | |
4c21f3c2 | 3110 | if (!list_empty(&its_nodes)) { |
16acae72 VM |
3111 | if (!gic_rdists_supports_plpis()) { |
3112 | pr_info("CPU%d: LPIs not supported\n", smp_processor_id()); | |
3113 | return -ENXIO; | |
3114 | } | |
4c21f3c2 MZ |
3115 | its_cpu_init_lpis(); |
3116 | its_cpu_init_collection(); | |
3117 | } | |
3118 | ||
3119 | return 0; | |
3120 | } | |
3121 | ||
935bba7c | 3122 | static const struct of_device_id its_device_id[] = { |
4c21f3c2 MZ |
3123 | { .compatible = "arm,gic-v3-its", }, |
3124 | {}, | |
3125 | }; | |
3126 | ||
db40f0a7 | 3127 | static int __init its_of_probe(struct device_node *node) |
4c21f3c2 MZ |
3128 | { |
3129 | struct device_node *np; | |
db40f0a7 | 3130 | struct resource res; |
4c21f3c2 MZ |
3131 | |
3132 | for (np = of_find_matching_node(node, its_device_id); np; | |
3133 | np = of_find_matching_node(np, its_device_id)) { | |
d14ae5e6 | 3134 | if (!of_property_read_bool(np, "msi-controller")) { |
e81f54c6 RH |
3135 | pr_warn("%pOF: no msi-controller property, ITS ignored\n", |
3136 | np); | |
d14ae5e6 TN |
3137 | continue; |
3138 | } | |
3139 | ||
db40f0a7 | 3140 | if (of_address_to_resource(np, 0, &res)) { |
e81f54c6 | 3141 | pr_warn("%pOF: no regs?\n", np); |
db40f0a7 TN |
3142 | continue; |
3143 | } | |
3144 | ||
3145 | its_probe_one(&res, &np->fwnode, of_node_to_nid(np)); | |
4c21f3c2 | 3146 | } |
db40f0a7 TN |
3147 | return 0; |
3148 | } | |
3149 | ||
3f010cf1 TN |
3150 | #ifdef CONFIG_ACPI |
3151 | ||
3152 | #define ACPI_GICV3_ITS_MEM_SIZE (SZ_128K) | |
3153 | ||
d1ce263f | 3154 | #ifdef CONFIG_ACPI_NUMA |
dbd2b826 GK |
3155 | struct its_srat_map { |
3156 | /* numa node id */ | |
3157 | u32 numa_node; | |
3158 | /* GIC ITS ID */ | |
3159 | u32 its_id; | |
3160 | }; | |
3161 | ||
fdf6e7a8 | 3162 | static struct its_srat_map *its_srat_maps __initdata; |
dbd2b826 GK |
3163 | static int its_in_srat __initdata; |
3164 | ||
3165 | static int __init acpi_get_its_numa_node(u32 its_id) | |
3166 | { | |
3167 | int i; | |
3168 | ||
3169 | for (i = 0; i < its_in_srat; i++) { | |
3170 | if (its_id == its_srat_maps[i].its_id) | |
3171 | return its_srat_maps[i].numa_node; | |
3172 | } | |
3173 | return NUMA_NO_NODE; | |
3174 | } | |
3175 | ||
fdf6e7a8 HG |
3176 | static int __init gic_acpi_match_srat_its(struct acpi_subtable_header *header, |
3177 | const unsigned long end) | |
3178 | { | |
3179 | return 0; | |
3180 | } | |
3181 | ||
dbd2b826 GK |
3182 | static int __init gic_acpi_parse_srat_its(struct acpi_subtable_header *header, |
3183 | const unsigned long end) | |
3184 | { | |
3185 | int node; | |
3186 | struct acpi_srat_gic_its_affinity *its_affinity; | |
3187 | ||
3188 | its_affinity = (struct acpi_srat_gic_its_affinity *)header; | |
3189 | if (!its_affinity) | |
3190 | return -EINVAL; | |
3191 | ||
3192 | if (its_affinity->header.length < sizeof(*its_affinity)) { | |
3193 | pr_err("SRAT: Invalid header length %d in ITS affinity\n", | |
3194 | its_affinity->header.length); | |
3195 | return -EINVAL; | |
3196 | } | |
3197 | ||
dbd2b826 GK |
3198 | node = acpi_map_pxm_to_node(its_affinity->proximity_domain); |
3199 | ||
3200 | if (node == NUMA_NO_NODE || node >= MAX_NUMNODES) { | |
3201 | pr_err("SRAT: Invalid NUMA node %d in ITS affinity\n", node); | |
3202 | return 0; | |
3203 | } | |
3204 | ||
3205 | its_srat_maps[its_in_srat].numa_node = node; | |
3206 | its_srat_maps[its_in_srat].its_id = its_affinity->its_id; | |
3207 | its_in_srat++; | |
3208 | pr_info("SRAT: PXM %d -> ITS %d -> Node %d\n", | |
3209 | its_affinity->proximity_domain, its_affinity->its_id, node); | |
3210 | ||
3211 | return 0; | |
3212 | } | |
3213 | ||
3214 | static void __init acpi_table_parse_srat_its(void) | |
3215 | { | |
fdf6e7a8 HG |
3216 | int count; |
3217 | ||
3218 | count = acpi_table_parse_entries(ACPI_SIG_SRAT, | |
3219 | sizeof(struct acpi_table_srat), | |
3220 | ACPI_SRAT_TYPE_GIC_ITS_AFFINITY, | |
3221 | gic_acpi_match_srat_its, 0); | |
3222 | if (count <= 0) | |
3223 | return; | |
3224 | ||
3225 | its_srat_maps = kmalloc(count * sizeof(struct its_srat_map), | |
3226 | GFP_KERNEL); | |
3227 | if (!its_srat_maps) { | |
3228 | pr_warn("SRAT: Failed to allocate memory for its_srat_maps!\n"); | |
3229 | return; | |
3230 | } | |
3231 | ||
dbd2b826 GK |
3232 | acpi_table_parse_entries(ACPI_SIG_SRAT, |
3233 | sizeof(struct acpi_table_srat), | |
3234 | ACPI_SRAT_TYPE_GIC_ITS_AFFINITY, | |
3235 | gic_acpi_parse_srat_its, 0); | |
3236 | } | |
fdf6e7a8 HG |
3237 | |
3238 | /* free the its_srat_maps after ITS probing */ | |
3239 | static void __init acpi_its_srat_maps_free(void) | |
3240 | { | |
3241 | kfree(its_srat_maps); | |
3242 | } | |
dbd2b826 GK |
3243 | #else |
3244 | static void __init acpi_table_parse_srat_its(void) { } | |
3245 | static int __init acpi_get_its_numa_node(u32 its_id) { return NUMA_NO_NODE; } | |
fdf6e7a8 | 3246 | static void __init acpi_its_srat_maps_free(void) { } |
dbd2b826 GK |
3247 | #endif |
3248 | ||
3f010cf1 TN |
3249 | static int __init gic_acpi_parse_madt_its(struct acpi_subtable_header *header, |
3250 | const unsigned long end) | |
3251 | { | |
3252 | struct acpi_madt_generic_translator *its_entry; | |
3253 | struct fwnode_handle *dom_handle; | |
3254 | struct resource res; | |
3255 | int err; | |
3256 | ||
3257 | its_entry = (struct acpi_madt_generic_translator *)header; | |
3258 | memset(&res, 0, sizeof(res)); | |
3259 | res.start = its_entry->base_address; | |
3260 | res.end = its_entry->base_address + ACPI_GICV3_ITS_MEM_SIZE - 1; | |
3261 | res.flags = IORESOURCE_MEM; | |
3262 | ||
3263 | dom_handle = irq_domain_alloc_fwnode((void *)its_entry->base_address); | |
3264 | if (!dom_handle) { | |
3265 | pr_err("ITS@%pa: Unable to allocate GICv3 ITS domain token\n", | |
3266 | &res.start); | |
3267 | return -ENOMEM; | |
3268 | } | |
3269 | ||
3270 | err = iort_register_domain_token(its_entry->translation_id, dom_handle); | |
3271 | if (err) { | |
3272 | pr_err("ITS@%pa: Unable to register GICv3 ITS domain token (ITS ID %d) to IORT\n", | |
3273 | &res.start, its_entry->translation_id); | |
3274 | goto dom_err; | |
3275 | } | |
3276 | ||
dbd2b826 GK |
3277 | err = its_probe_one(&res, dom_handle, |
3278 | acpi_get_its_numa_node(its_entry->translation_id)); | |
3f010cf1 TN |
3279 | if (!err) |
3280 | return 0; | |
3281 | ||
3282 | iort_deregister_domain_token(its_entry->translation_id); | |
3283 | dom_err: | |
3284 | irq_domain_free_fwnode(dom_handle); | |
3285 | return err; | |
3286 | } | |
3287 | ||
3288 | static void __init its_acpi_probe(void) | |
3289 | { | |
dbd2b826 | 3290 | acpi_table_parse_srat_its(); |
3f010cf1 TN |
3291 | acpi_table_parse_madt(ACPI_MADT_TYPE_GENERIC_TRANSLATOR, |
3292 | gic_acpi_parse_madt_its, 0); | |
fdf6e7a8 | 3293 | acpi_its_srat_maps_free(); |
3f010cf1 TN |
3294 | } |
3295 | #else | |
3296 | static void __init its_acpi_probe(void) { } | |
3297 | #endif | |
3298 | ||
db40f0a7 TN |
3299 | int __init its_init(struct fwnode_handle *handle, struct rdists *rdists, |
3300 | struct irq_domain *parent_domain) | |
3301 | { | |
3302 | struct device_node *of_node; | |
8fff27ae MZ |
3303 | struct its_node *its; |
3304 | bool has_v4 = false; | |
3305 | int err; | |
db40f0a7 TN |
3306 | |
3307 | its_parent = parent_domain; | |
3308 | of_node = to_of_node(handle); | |
3309 | if (of_node) | |
3310 | its_of_probe(of_node); | |
3311 | else | |
3f010cf1 | 3312 | its_acpi_probe(); |
4c21f3c2 MZ |
3313 | |
3314 | if (list_empty(&its_nodes)) { | |
3315 | pr_warn("ITS: No ITS available, not enabling LPIs\n"); | |
3316 | return -ENXIO; | |
3317 | } | |
3318 | ||
3319 | gic_rdists = rdists; | |
8fff27ae MZ |
3320 | err = its_alloc_lpi_tables(); |
3321 | if (err) | |
3322 | return err; | |
3323 | ||
3324 | list_for_each_entry(its, &its_nodes, entry) | |
3325 | has_v4 |= its->is_v4; | |
3326 | ||
3327 | if (has_v4 & rdists->has_vlpis) { | |
3d63cb53 MZ |
3328 | if (its_init_vpe_domain() || |
3329 | its_init_v4(parent_domain, &its_vpe_domain_ops)) { | |
8fff27ae MZ |
3330 | rdists->has_vlpis = false; |
3331 | pr_err("ITS: Disabling GICv4 support\n"); | |
3332 | } | |
3333 | } | |
3334 | ||
3335 | return 0; | |
4c21f3c2 | 3336 | } |