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cc2d3216 MZ |
1 | /* |
2 | * Copyright (C) 2013, 2014 ARM Limited, All Rights Reserved. | |
3 | * Author: Marc Zyngier <marc.zyngier@arm.com> | |
4 | * | |
5 | * This program is free software; you can redistribute it and/or modify | |
6 | * it under the terms of the GNU General Public License version 2 as | |
7 | * published by the Free Software Foundation. | |
8 | * | |
9 | * This program is distributed in the hope that it will be useful, | |
10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
12 | * GNU General Public License for more details. | |
13 | * | |
14 | * You should have received a copy of the GNU General Public License | |
15 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | |
16 | */ | |
17 | ||
3f010cf1 | 18 | #include <linux/acpi.h> |
8d3554b8 | 19 | #include <linux/acpi_iort.h> |
cc2d3216 MZ |
20 | #include <linux/bitmap.h> |
21 | #include <linux/cpu.h> | |
22 | #include <linux/delay.h> | |
44bb7e24 | 23 | #include <linux/dma-iommu.h> |
cc2d3216 | 24 | #include <linux/interrupt.h> |
3f010cf1 | 25 | #include <linux/irqdomain.h> |
cc2d3216 MZ |
26 | #include <linux/log2.h> |
27 | #include <linux/mm.h> | |
28 | #include <linux/msi.h> | |
29 | #include <linux/of.h> | |
30 | #include <linux/of_address.h> | |
31 | #include <linux/of_irq.h> | |
32 | #include <linux/of_pci.h> | |
33 | #include <linux/of_platform.h> | |
34 | #include <linux/percpu.h> | |
35 | #include <linux/slab.h> | |
36 | ||
41a83e06 | 37 | #include <linux/irqchip.h> |
cc2d3216 MZ |
38 | #include <linux/irqchip/arm-gic-v3.h> |
39 | ||
cc2d3216 MZ |
40 | #include <asm/cputype.h> |
41 | #include <asm/exception.h> | |
42 | ||
67510cca RR |
43 | #include "irq-gic-common.h" |
44 | ||
94100970 RR |
45 | #define ITS_FLAGS_CMDQ_NEEDS_FLUSHING (1ULL << 0) |
46 | #define ITS_FLAGS_WORKAROUND_CAVIUM_22375 (1ULL << 1) | |
fbf8f40e | 47 | #define ITS_FLAGS_WORKAROUND_CAVIUM_23144 (1ULL << 2) |
cc2d3216 | 48 | |
c48ed51c MZ |
49 | #define RDIST_FLAGS_PROPBASE_NEEDS_FLUSHING (1 << 0) |
50 | ||
a13b0404 MZ |
51 | static u32 lpi_id_bits; |
52 | ||
53 | /* | |
54 | * We allocate memory for PROPBASE to cover 2 ^ lpi_id_bits LPIs to | |
55 | * deal with (one configuration byte per interrupt). PENDBASE has to | |
56 | * be 64kB aligned (one bit per LPI, plus 8192 bits for SPI/PPI/SGI). | |
57 | */ | |
58 | #define LPI_NRBITS lpi_id_bits | |
59 | #define LPI_PROPBASE_SZ ALIGN(BIT(LPI_NRBITS), SZ_64K) | |
60 | #define LPI_PENDBASE_SZ ALIGN(BIT(LPI_NRBITS) / 8, SZ_64K) | |
61 | ||
62 | #define LPI_PROP_DEFAULT_PRIO 0xa0 | |
63 | ||
cc2d3216 MZ |
64 | /* |
65 | * Collection structure - just an ID, and a redistributor address to | |
66 | * ping. We use one per CPU as a bag of interrupts assigned to this | |
67 | * CPU. | |
68 | */ | |
69 | struct its_collection { | |
70 | u64 target_address; | |
71 | u16 col_id; | |
72 | }; | |
73 | ||
466b7d16 | 74 | /* |
9347359a SD |
75 | * The ITS_BASER structure - contains memory information, cached |
76 | * value of BASER register configuration and ITS page size. | |
466b7d16 SD |
77 | */ |
78 | struct its_baser { | |
79 | void *base; | |
80 | u64 val; | |
81 | u32 order; | |
9347359a | 82 | u32 psz; |
466b7d16 SD |
83 | }; |
84 | ||
cc2d3216 MZ |
85 | /* |
86 | * The ITS structure - contains most of the infrastructure, with the | |
841514ab MZ |
87 | * top-level MSI domain, the command queue, the collections, and the |
88 | * list of devices writing to it. | |
cc2d3216 MZ |
89 | */ |
90 | struct its_node { | |
91 | raw_spinlock_t lock; | |
92 | struct list_head entry; | |
cc2d3216 | 93 | void __iomem *base; |
db40f0a7 | 94 | phys_addr_t phys_base; |
cc2d3216 MZ |
95 | struct its_cmd_block *cmd_base; |
96 | struct its_cmd_block *cmd_write; | |
466b7d16 | 97 | struct its_baser tables[GITS_BASER_NR_REGS]; |
cc2d3216 MZ |
98 | struct its_collection *collections; |
99 | struct list_head its_device_list; | |
100 | u64 flags; | |
101 | u32 ite_size; | |
466b7d16 | 102 | u32 device_ids; |
fbf8f40e | 103 | int numa_node; |
3dfa576b | 104 | bool is_v4; |
cc2d3216 MZ |
105 | }; |
106 | ||
107 | #define ITS_ITT_ALIGN SZ_256 | |
108 | ||
2eca0d6c SD |
109 | /* Convert page order to size in bytes */ |
110 | #define PAGE_ORDER_TO_SIZE(o) (PAGE_SIZE << (o)) | |
111 | ||
591e5bec MZ |
112 | struct event_lpi_map { |
113 | unsigned long *lpi_map; | |
114 | u16 *col_map; | |
115 | irq_hw_number_t lpi_base; | |
116 | int nr_lpis; | |
117 | }; | |
118 | ||
cc2d3216 MZ |
119 | /* |
120 | * The ITS view of a device - belongs to an ITS, a collection, owns an | |
121 | * interrupt translation table, and a list of interrupts. | |
122 | */ | |
123 | struct its_device { | |
124 | struct list_head entry; | |
125 | struct its_node *its; | |
591e5bec | 126 | struct event_lpi_map event_map; |
cc2d3216 | 127 | void *itt; |
cc2d3216 MZ |
128 | u32 nr_ites; |
129 | u32 device_id; | |
130 | }; | |
131 | ||
1ac19ca6 MZ |
132 | static LIST_HEAD(its_nodes); |
133 | static DEFINE_SPINLOCK(its_lock); | |
1ac19ca6 | 134 | static struct rdists *gic_rdists; |
db40f0a7 | 135 | static struct irq_domain *its_parent; |
1ac19ca6 | 136 | |
3dfa576b MZ |
137 | /* |
138 | * We have a maximum number of 16 ITSs in the whole system if we're | |
139 | * using the ITSList mechanism | |
140 | */ | |
141 | #define ITS_LIST_MAX 16 | |
142 | ||
143 | static unsigned long its_list_map; | |
144 | ||
1ac19ca6 MZ |
145 | #define gic_data_rdist() (raw_cpu_ptr(gic_rdists->rdist)) |
146 | #define gic_data_rdist_rd_base() (gic_data_rdist()->rd_base) | |
147 | ||
591e5bec MZ |
148 | static struct its_collection *dev_event_to_col(struct its_device *its_dev, |
149 | u32 event) | |
150 | { | |
151 | struct its_node *its = its_dev->its; | |
152 | ||
153 | return its->collections + its_dev->event_map.col_map[event]; | |
154 | } | |
155 | ||
cc2d3216 MZ |
156 | /* |
157 | * ITS command descriptors - parameters to be encoded in a command | |
158 | * block. | |
159 | */ | |
160 | struct its_cmd_desc { | |
161 | union { | |
162 | struct { | |
163 | struct its_device *dev; | |
164 | u32 event_id; | |
165 | } its_inv_cmd; | |
166 | ||
8d85dced MZ |
167 | struct { |
168 | struct its_device *dev; | |
169 | u32 event_id; | |
170 | } its_clear_cmd; | |
171 | ||
cc2d3216 MZ |
172 | struct { |
173 | struct its_device *dev; | |
174 | u32 event_id; | |
175 | } its_int_cmd; | |
176 | ||
177 | struct { | |
178 | struct its_device *dev; | |
179 | int valid; | |
180 | } its_mapd_cmd; | |
181 | ||
182 | struct { | |
183 | struct its_collection *col; | |
184 | int valid; | |
185 | } its_mapc_cmd; | |
186 | ||
187 | struct { | |
188 | struct its_device *dev; | |
189 | u32 phys_id; | |
190 | u32 event_id; | |
6a25ad3a | 191 | } its_mapti_cmd; |
cc2d3216 MZ |
192 | |
193 | struct { | |
194 | struct its_device *dev; | |
195 | struct its_collection *col; | |
591e5bec | 196 | u32 event_id; |
cc2d3216 MZ |
197 | } its_movi_cmd; |
198 | ||
199 | struct { | |
200 | struct its_device *dev; | |
201 | u32 event_id; | |
202 | } its_discard_cmd; | |
203 | ||
204 | struct { | |
205 | struct its_collection *col; | |
206 | } its_invall_cmd; | |
207 | }; | |
208 | }; | |
209 | ||
210 | /* | |
211 | * The ITS command block, which is what the ITS actually parses. | |
212 | */ | |
213 | struct its_cmd_block { | |
214 | u64 raw_cmd[4]; | |
215 | }; | |
216 | ||
217 | #define ITS_CMD_QUEUE_SZ SZ_64K | |
218 | #define ITS_CMD_QUEUE_NR_ENTRIES (ITS_CMD_QUEUE_SZ / sizeof(struct its_cmd_block)) | |
219 | ||
220 | typedef struct its_collection *(*its_cmd_builder_t)(struct its_cmd_block *, | |
221 | struct its_cmd_desc *); | |
222 | ||
4d36f136 MZ |
223 | static void its_mask_encode(u64 *raw_cmd, u64 val, int h, int l) |
224 | { | |
225 | u64 mask = GENMASK_ULL(h, l); | |
226 | *raw_cmd &= ~mask; | |
227 | *raw_cmd |= (val << l) & mask; | |
228 | } | |
229 | ||
cc2d3216 MZ |
230 | static void its_encode_cmd(struct its_cmd_block *cmd, u8 cmd_nr) |
231 | { | |
4d36f136 | 232 | its_mask_encode(&cmd->raw_cmd[0], cmd_nr, 7, 0); |
cc2d3216 MZ |
233 | } |
234 | ||
235 | static void its_encode_devid(struct its_cmd_block *cmd, u32 devid) | |
236 | { | |
4d36f136 | 237 | its_mask_encode(&cmd->raw_cmd[0], devid, 63, 32); |
cc2d3216 MZ |
238 | } |
239 | ||
240 | static void its_encode_event_id(struct its_cmd_block *cmd, u32 id) | |
241 | { | |
4d36f136 | 242 | its_mask_encode(&cmd->raw_cmd[1], id, 31, 0); |
cc2d3216 MZ |
243 | } |
244 | ||
245 | static void its_encode_phys_id(struct its_cmd_block *cmd, u32 phys_id) | |
246 | { | |
4d36f136 | 247 | its_mask_encode(&cmd->raw_cmd[1], phys_id, 63, 32); |
cc2d3216 MZ |
248 | } |
249 | ||
250 | static void its_encode_size(struct its_cmd_block *cmd, u8 size) | |
251 | { | |
4d36f136 | 252 | its_mask_encode(&cmd->raw_cmd[1], size, 4, 0); |
cc2d3216 MZ |
253 | } |
254 | ||
255 | static void its_encode_itt(struct its_cmd_block *cmd, u64 itt_addr) | |
256 | { | |
4d36f136 | 257 | its_mask_encode(&cmd->raw_cmd[2], itt_addr >> 8, 50, 8); |
cc2d3216 MZ |
258 | } |
259 | ||
260 | static void its_encode_valid(struct its_cmd_block *cmd, int valid) | |
261 | { | |
4d36f136 | 262 | its_mask_encode(&cmd->raw_cmd[2], !!valid, 63, 63); |
cc2d3216 MZ |
263 | } |
264 | ||
265 | static void its_encode_target(struct its_cmd_block *cmd, u64 target_addr) | |
266 | { | |
4d36f136 | 267 | its_mask_encode(&cmd->raw_cmd[2], target_addr >> 16, 50, 16); |
cc2d3216 MZ |
268 | } |
269 | ||
270 | static void its_encode_collection(struct its_cmd_block *cmd, u16 col) | |
271 | { | |
4d36f136 | 272 | its_mask_encode(&cmd->raw_cmd[2], col, 15, 0); |
cc2d3216 MZ |
273 | } |
274 | ||
275 | static inline void its_fixup_cmd(struct its_cmd_block *cmd) | |
276 | { | |
277 | /* Let's fixup BE commands */ | |
278 | cmd->raw_cmd[0] = cpu_to_le64(cmd->raw_cmd[0]); | |
279 | cmd->raw_cmd[1] = cpu_to_le64(cmd->raw_cmd[1]); | |
280 | cmd->raw_cmd[2] = cpu_to_le64(cmd->raw_cmd[2]); | |
281 | cmd->raw_cmd[3] = cpu_to_le64(cmd->raw_cmd[3]); | |
282 | } | |
283 | ||
284 | static struct its_collection *its_build_mapd_cmd(struct its_cmd_block *cmd, | |
285 | struct its_cmd_desc *desc) | |
286 | { | |
287 | unsigned long itt_addr; | |
c8481267 | 288 | u8 size = ilog2(desc->its_mapd_cmd.dev->nr_ites); |
cc2d3216 MZ |
289 | |
290 | itt_addr = virt_to_phys(desc->its_mapd_cmd.dev->itt); | |
291 | itt_addr = ALIGN(itt_addr, ITS_ITT_ALIGN); | |
292 | ||
293 | its_encode_cmd(cmd, GITS_CMD_MAPD); | |
294 | its_encode_devid(cmd, desc->its_mapd_cmd.dev->device_id); | |
295 | its_encode_size(cmd, size - 1); | |
296 | its_encode_itt(cmd, itt_addr); | |
297 | its_encode_valid(cmd, desc->its_mapd_cmd.valid); | |
298 | ||
299 | its_fixup_cmd(cmd); | |
300 | ||
591e5bec | 301 | return NULL; |
cc2d3216 MZ |
302 | } |
303 | ||
304 | static struct its_collection *its_build_mapc_cmd(struct its_cmd_block *cmd, | |
305 | struct its_cmd_desc *desc) | |
306 | { | |
307 | its_encode_cmd(cmd, GITS_CMD_MAPC); | |
308 | its_encode_collection(cmd, desc->its_mapc_cmd.col->col_id); | |
309 | its_encode_target(cmd, desc->its_mapc_cmd.col->target_address); | |
310 | its_encode_valid(cmd, desc->its_mapc_cmd.valid); | |
311 | ||
312 | its_fixup_cmd(cmd); | |
313 | ||
314 | return desc->its_mapc_cmd.col; | |
315 | } | |
316 | ||
6a25ad3a | 317 | static struct its_collection *its_build_mapti_cmd(struct its_cmd_block *cmd, |
cc2d3216 MZ |
318 | struct its_cmd_desc *desc) |
319 | { | |
591e5bec MZ |
320 | struct its_collection *col; |
321 | ||
6a25ad3a MZ |
322 | col = dev_event_to_col(desc->its_mapti_cmd.dev, |
323 | desc->its_mapti_cmd.event_id); | |
591e5bec | 324 | |
6a25ad3a MZ |
325 | its_encode_cmd(cmd, GITS_CMD_MAPTI); |
326 | its_encode_devid(cmd, desc->its_mapti_cmd.dev->device_id); | |
327 | its_encode_event_id(cmd, desc->its_mapti_cmd.event_id); | |
328 | its_encode_phys_id(cmd, desc->its_mapti_cmd.phys_id); | |
591e5bec | 329 | its_encode_collection(cmd, col->col_id); |
cc2d3216 MZ |
330 | |
331 | its_fixup_cmd(cmd); | |
332 | ||
591e5bec | 333 | return col; |
cc2d3216 MZ |
334 | } |
335 | ||
336 | static struct its_collection *its_build_movi_cmd(struct its_cmd_block *cmd, | |
337 | struct its_cmd_desc *desc) | |
338 | { | |
591e5bec MZ |
339 | struct its_collection *col; |
340 | ||
341 | col = dev_event_to_col(desc->its_movi_cmd.dev, | |
342 | desc->its_movi_cmd.event_id); | |
343 | ||
cc2d3216 MZ |
344 | its_encode_cmd(cmd, GITS_CMD_MOVI); |
345 | its_encode_devid(cmd, desc->its_movi_cmd.dev->device_id); | |
591e5bec | 346 | its_encode_event_id(cmd, desc->its_movi_cmd.event_id); |
cc2d3216 MZ |
347 | its_encode_collection(cmd, desc->its_movi_cmd.col->col_id); |
348 | ||
349 | its_fixup_cmd(cmd); | |
350 | ||
591e5bec | 351 | return col; |
cc2d3216 MZ |
352 | } |
353 | ||
354 | static struct its_collection *its_build_discard_cmd(struct its_cmd_block *cmd, | |
355 | struct its_cmd_desc *desc) | |
356 | { | |
591e5bec MZ |
357 | struct its_collection *col; |
358 | ||
359 | col = dev_event_to_col(desc->its_discard_cmd.dev, | |
360 | desc->its_discard_cmd.event_id); | |
361 | ||
cc2d3216 MZ |
362 | its_encode_cmd(cmd, GITS_CMD_DISCARD); |
363 | its_encode_devid(cmd, desc->its_discard_cmd.dev->device_id); | |
364 | its_encode_event_id(cmd, desc->its_discard_cmd.event_id); | |
365 | ||
366 | its_fixup_cmd(cmd); | |
367 | ||
591e5bec | 368 | return col; |
cc2d3216 MZ |
369 | } |
370 | ||
371 | static struct its_collection *its_build_inv_cmd(struct its_cmd_block *cmd, | |
372 | struct its_cmd_desc *desc) | |
373 | { | |
591e5bec MZ |
374 | struct its_collection *col; |
375 | ||
376 | col = dev_event_to_col(desc->its_inv_cmd.dev, | |
377 | desc->its_inv_cmd.event_id); | |
378 | ||
cc2d3216 MZ |
379 | its_encode_cmd(cmd, GITS_CMD_INV); |
380 | its_encode_devid(cmd, desc->its_inv_cmd.dev->device_id); | |
381 | its_encode_event_id(cmd, desc->its_inv_cmd.event_id); | |
382 | ||
383 | its_fixup_cmd(cmd); | |
384 | ||
591e5bec | 385 | return col; |
cc2d3216 MZ |
386 | } |
387 | ||
8d85dced MZ |
388 | static struct its_collection *its_build_int_cmd(struct its_cmd_block *cmd, |
389 | struct its_cmd_desc *desc) | |
390 | { | |
391 | struct its_collection *col; | |
392 | ||
393 | col = dev_event_to_col(desc->its_int_cmd.dev, | |
394 | desc->its_int_cmd.event_id); | |
395 | ||
396 | its_encode_cmd(cmd, GITS_CMD_INT); | |
397 | its_encode_devid(cmd, desc->its_int_cmd.dev->device_id); | |
398 | its_encode_event_id(cmd, desc->its_int_cmd.event_id); | |
399 | ||
400 | its_fixup_cmd(cmd); | |
401 | ||
402 | return col; | |
403 | } | |
404 | ||
405 | static struct its_collection *its_build_clear_cmd(struct its_cmd_block *cmd, | |
406 | struct its_cmd_desc *desc) | |
407 | { | |
408 | struct its_collection *col; | |
409 | ||
410 | col = dev_event_to_col(desc->its_clear_cmd.dev, | |
411 | desc->its_clear_cmd.event_id); | |
412 | ||
413 | its_encode_cmd(cmd, GITS_CMD_CLEAR); | |
414 | its_encode_devid(cmd, desc->its_clear_cmd.dev->device_id); | |
415 | its_encode_event_id(cmd, desc->its_clear_cmd.event_id); | |
416 | ||
417 | its_fixup_cmd(cmd); | |
418 | ||
419 | return col; | |
420 | } | |
421 | ||
cc2d3216 MZ |
422 | static struct its_collection *its_build_invall_cmd(struct its_cmd_block *cmd, |
423 | struct its_cmd_desc *desc) | |
424 | { | |
425 | its_encode_cmd(cmd, GITS_CMD_INVALL); | |
426 | its_encode_collection(cmd, desc->its_mapc_cmd.col->col_id); | |
427 | ||
428 | its_fixup_cmd(cmd); | |
429 | ||
430 | return NULL; | |
431 | } | |
432 | ||
433 | static u64 its_cmd_ptr_to_offset(struct its_node *its, | |
434 | struct its_cmd_block *ptr) | |
435 | { | |
436 | return (ptr - its->cmd_base) * sizeof(*ptr); | |
437 | } | |
438 | ||
439 | static int its_queue_full(struct its_node *its) | |
440 | { | |
441 | int widx; | |
442 | int ridx; | |
443 | ||
444 | widx = its->cmd_write - its->cmd_base; | |
445 | ridx = readl_relaxed(its->base + GITS_CREADR) / sizeof(struct its_cmd_block); | |
446 | ||
447 | /* This is incredibly unlikely to happen, unless the ITS locks up. */ | |
448 | if (((widx + 1) % ITS_CMD_QUEUE_NR_ENTRIES) == ridx) | |
449 | return 1; | |
450 | ||
451 | return 0; | |
452 | } | |
453 | ||
454 | static struct its_cmd_block *its_allocate_entry(struct its_node *its) | |
455 | { | |
456 | struct its_cmd_block *cmd; | |
457 | u32 count = 1000000; /* 1s! */ | |
458 | ||
459 | while (its_queue_full(its)) { | |
460 | count--; | |
461 | if (!count) { | |
462 | pr_err_ratelimited("ITS queue not draining\n"); | |
463 | return NULL; | |
464 | } | |
465 | cpu_relax(); | |
466 | udelay(1); | |
467 | } | |
468 | ||
469 | cmd = its->cmd_write++; | |
470 | ||
471 | /* Handle queue wrapping */ | |
472 | if (its->cmd_write == (its->cmd_base + ITS_CMD_QUEUE_NR_ENTRIES)) | |
473 | its->cmd_write = its->cmd_base; | |
474 | ||
34d677a9 MZ |
475 | /* Clear command */ |
476 | cmd->raw_cmd[0] = 0; | |
477 | cmd->raw_cmd[1] = 0; | |
478 | cmd->raw_cmd[2] = 0; | |
479 | cmd->raw_cmd[3] = 0; | |
480 | ||
cc2d3216 MZ |
481 | return cmd; |
482 | } | |
483 | ||
484 | static struct its_cmd_block *its_post_commands(struct its_node *its) | |
485 | { | |
486 | u64 wr = its_cmd_ptr_to_offset(its, its->cmd_write); | |
487 | ||
488 | writel_relaxed(wr, its->base + GITS_CWRITER); | |
489 | ||
490 | return its->cmd_write; | |
491 | } | |
492 | ||
493 | static void its_flush_cmd(struct its_node *its, struct its_cmd_block *cmd) | |
494 | { | |
495 | /* | |
496 | * Make sure the commands written to memory are observable by | |
497 | * the ITS. | |
498 | */ | |
499 | if (its->flags & ITS_FLAGS_CMDQ_NEEDS_FLUSHING) | |
328191c0 | 500 | gic_flush_dcache_to_poc(cmd, sizeof(*cmd)); |
cc2d3216 MZ |
501 | else |
502 | dsb(ishst); | |
503 | } | |
504 | ||
505 | static void its_wait_for_range_completion(struct its_node *its, | |
506 | struct its_cmd_block *from, | |
507 | struct its_cmd_block *to) | |
508 | { | |
509 | u64 rd_idx, from_idx, to_idx; | |
510 | u32 count = 1000000; /* 1s! */ | |
511 | ||
512 | from_idx = its_cmd_ptr_to_offset(its, from); | |
513 | to_idx = its_cmd_ptr_to_offset(its, to); | |
514 | ||
515 | while (1) { | |
516 | rd_idx = readl_relaxed(its->base + GITS_CREADR); | |
9bdd8b1c MZ |
517 | |
518 | /* Direct case */ | |
519 | if (from_idx < to_idx && rd_idx >= to_idx) | |
520 | break; | |
521 | ||
522 | /* Wrapped case */ | |
523 | if (from_idx >= to_idx && rd_idx >= to_idx && rd_idx < from_idx) | |
cc2d3216 MZ |
524 | break; |
525 | ||
526 | count--; | |
527 | if (!count) { | |
528 | pr_err_ratelimited("ITS queue timeout\n"); | |
529 | return; | |
530 | } | |
531 | cpu_relax(); | |
532 | udelay(1); | |
533 | } | |
534 | } | |
535 | ||
e4f9094b MZ |
536 | /* Warning, macro hell follows */ |
537 | #define BUILD_SINGLE_CMD_FUNC(name, buildtype, synctype, buildfn) \ | |
538 | void name(struct its_node *its, \ | |
539 | buildtype builder, \ | |
540 | struct its_cmd_desc *desc) \ | |
541 | { \ | |
542 | struct its_cmd_block *cmd, *sync_cmd, *next_cmd; \ | |
543 | synctype *sync_obj; \ | |
544 | unsigned long flags; \ | |
545 | \ | |
546 | raw_spin_lock_irqsave(&its->lock, flags); \ | |
547 | \ | |
548 | cmd = its_allocate_entry(its); \ | |
549 | if (!cmd) { /* We're soooooo screewed... */ \ | |
550 | raw_spin_unlock_irqrestore(&its->lock, flags); \ | |
551 | return; \ | |
552 | } \ | |
553 | sync_obj = builder(cmd, desc); \ | |
554 | its_flush_cmd(its, cmd); \ | |
555 | \ | |
556 | if (sync_obj) { \ | |
557 | sync_cmd = its_allocate_entry(its); \ | |
558 | if (!sync_cmd) \ | |
559 | goto post; \ | |
560 | \ | |
561 | buildfn(sync_cmd, sync_obj); \ | |
562 | its_flush_cmd(its, sync_cmd); \ | |
563 | } \ | |
564 | \ | |
565 | post: \ | |
566 | next_cmd = its_post_commands(its); \ | |
567 | raw_spin_unlock_irqrestore(&its->lock, flags); \ | |
568 | \ | |
569 | its_wait_for_range_completion(its, cmd, next_cmd); \ | |
570 | } | |
cc2d3216 | 571 | |
e4f9094b MZ |
572 | static void its_build_sync_cmd(struct its_cmd_block *sync_cmd, |
573 | struct its_collection *sync_col) | |
574 | { | |
575 | its_encode_cmd(sync_cmd, GITS_CMD_SYNC); | |
576 | its_encode_target(sync_cmd, sync_col->target_address); | |
cc2d3216 | 577 | |
e4f9094b | 578 | its_fixup_cmd(sync_cmd); |
cc2d3216 MZ |
579 | } |
580 | ||
e4f9094b MZ |
581 | static BUILD_SINGLE_CMD_FUNC(its_send_single_command, its_cmd_builder_t, |
582 | struct its_collection, its_build_sync_cmd) | |
583 | ||
8d85dced MZ |
584 | static void its_send_int(struct its_device *dev, u32 event_id) |
585 | { | |
586 | struct its_cmd_desc desc; | |
587 | ||
588 | desc.its_int_cmd.dev = dev; | |
589 | desc.its_int_cmd.event_id = event_id; | |
590 | ||
591 | its_send_single_command(dev->its, its_build_int_cmd, &desc); | |
592 | } | |
593 | ||
594 | static void its_send_clear(struct its_device *dev, u32 event_id) | |
595 | { | |
596 | struct its_cmd_desc desc; | |
597 | ||
598 | desc.its_clear_cmd.dev = dev; | |
599 | desc.its_clear_cmd.event_id = event_id; | |
600 | ||
601 | its_send_single_command(dev->its, its_build_clear_cmd, &desc); | |
602 | } | |
603 | ||
cc2d3216 MZ |
604 | static void its_send_inv(struct its_device *dev, u32 event_id) |
605 | { | |
606 | struct its_cmd_desc desc; | |
607 | ||
608 | desc.its_inv_cmd.dev = dev; | |
609 | desc.its_inv_cmd.event_id = event_id; | |
610 | ||
611 | its_send_single_command(dev->its, its_build_inv_cmd, &desc); | |
612 | } | |
613 | ||
614 | static void its_send_mapd(struct its_device *dev, int valid) | |
615 | { | |
616 | struct its_cmd_desc desc; | |
617 | ||
618 | desc.its_mapd_cmd.dev = dev; | |
619 | desc.its_mapd_cmd.valid = !!valid; | |
620 | ||
621 | its_send_single_command(dev->its, its_build_mapd_cmd, &desc); | |
622 | } | |
623 | ||
624 | static void its_send_mapc(struct its_node *its, struct its_collection *col, | |
625 | int valid) | |
626 | { | |
627 | struct its_cmd_desc desc; | |
628 | ||
629 | desc.its_mapc_cmd.col = col; | |
630 | desc.its_mapc_cmd.valid = !!valid; | |
631 | ||
632 | its_send_single_command(its, its_build_mapc_cmd, &desc); | |
633 | } | |
634 | ||
6a25ad3a | 635 | static void its_send_mapti(struct its_device *dev, u32 irq_id, u32 id) |
cc2d3216 MZ |
636 | { |
637 | struct its_cmd_desc desc; | |
638 | ||
6a25ad3a MZ |
639 | desc.its_mapti_cmd.dev = dev; |
640 | desc.its_mapti_cmd.phys_id = irq_id; | |
641 | desc.its_mapti_cmd.event_id = id; | |
cc2d3216 | 642 | |
6a25ad3a | 643 | its_send_single_command(dev->its, its_build_mapti_cmd, &desc); |
cc2d3216 MZ |
644 | } |
645 | ||
646 | static void its_send_movi(struct its_device *dev, | |
647 | struct its_collection *col, u32 id) | |
648 | { | |
649 | struct its_cmd_desc desc; | |
650 | ||
651 | desc.its_movi_cmd.dev = dev; | |
652 | desc.its_movi_cmd.col = col; | |
591e5bec | 653 | desc.its_movi_cmd.event_id = id; |
cc2d3216 MZ |
654 | |
655 | its_send_single_command(dev->its, its_build_movi_cmd, &desc); | |
656 | } | |
657 | ||
658 | static void its_send_discard(struct its_device *dev, u32 id) | |
659 | { | |
660 | struct its_cmd_desc desc; | |
661 | ||
662 | desc.its_discard_cmd.dev = dev; | |
663 | desc.its_discard_cmd.event_id = id; | |
664 | ||
665 | its_send_single_command(dev->its, its_build_discard_cmd, &desc); | |
666 | } | |
667 | ||
668 | static void its_send_invall(struct its_node *its, struct its_collection *col) | |
669 | { | |
670 | struct its_cmd_desc desc; | |
671 | ||
672 | desc.its_invall_cmd.col = col; | |
673 | ||
674 | its_send_single_command(its, its_build_invall_cmd, &desc); | |
675 | } | |
c48ed51c MZ |
676 | |
677 | /* | |
678 | * irqchip functions - assumes MSI, mostly. | |
679 | */ | |
680 | ||
681 | static inline u32 its_get_event_id(struct irq_data *d) | |
682 | { | |
683 | struct its_device *its_dev = irq_data_get_irq_chip_data(d); | |
591e5bec | 684 | return d->hwirq - its_dev->event_map.lpi_base; |
c48ed51c MZ |
685 | } |
686 | ||
687 | static void lpi_set_config(struct irq_data *d, bool enable) | |
688 | { | |
689 | struct its_device *its_dev = irq_data_get_irq_chip_data(d); | |
690 | irq_hw_number_t hwirq = d->hwirq; | |
691 | u32 id = its_get_event_id(d); | |
692 | u8 *cfg = page_address(gic_rdists->prop_page) + hwirq - 8192; | |
693 | ||
694 | if (enable) | |
695 | *cfg |= LPI_PROP_ENABLED; | |
696 | else | |
697 | *cfg &= ~LPI_PROP_ENABLED; | |
698 | ||
699 | /* | |
700 | * Make the above write visible to the redistributors. | |
701 | * And yes, we're flushing exactly: One. Single. Byte. | |
702 | * Humpf... | |
703 | */ | |
704 | if (gic_rdists->flags & RDIST_FLAGS_PROPBASE_NEEDS_FLUSHING) | |
328191c0 | 705 | gic_flush_dcache_to_poc(cfg, sizeof(*cfg)); |
c48ed51c MZ |
706 | else |
707 | dsb(ishst); | |
708 | its_send_inv(its_dev, id); | |
709 | } | |
710 | ||
711 | static void its_mask_irq(struct irq_data *d) | |
712 | { | |
713 | lpi_set_config(d, false); | |
714 | } | |
715 | ||
716 | static void its_unmask_irq(struct irq_data *d) | |
717 | { | |
718 | lpi_set_config(d, true); | |
719 | } | |
720 | ||
c48ed51c MZ |
721 | static int its_set_affinity(struct irq_data *d, const struct cpumask *mask_val, |
722 | bool force) | |
723 | { | |
fbf8f40e GK |
724 | unsigned int cpu; |
725 | const struct cpumask *cpu_mask = cpu_online_mask; | |
c48ed51c MZ |
726 | struct its_device *its_dev = irq_data_get_irq_chip_data(d); |
727 | struct its_collection *target_col; | |
728 | u32 id = its_get_event_id(d); | |
729 | ||
fbf8f40e GK |
730 | /* lpi cannot be routed to a redistributor that is on a foreign node */ |
731 | if (its_dev->its->flags & ITS_FLAGS_WORKAROUND_CAVIUM_23144) { | |
732 | if (its_dev->its->numa_node >= 0) { | |
733 | cpu_mask = cpumask_of_node(its_dev->its->numa_node); | |
734 | if (!cpumask_intersects(mask_val, cpu_mask)) | |
735 | return -EINVAL; | |
736 | } | |
737 | } | |
738 | ||
739 | cpu = cpumask_any_and(mask_val, cpu_mask); | |
740 | ||
c48ed51c MZ |
741 | if (cpu >= nr_cpu_ids) |
742 | return -EINVAL; | |
743 | ||
8b8d94a7 M |
744 | /* don't set the affinity when the target cpu is same as current one */ |
745 | if (cpu != its_dev->event_map.col_map[id]) { | |
746 | target_col = &its_dev->its->collections[cpu]; | |
747 | its_send_movi(its_dev, target_col, id); | |
748 | its_dev->event_map.col_map[id] = cpu; | |
749 | } | |
c48ed51c MZ |
750 | |
751 | return IRQ_SET_MASK_OK_DONE; | |
752 | } | |
753 | ||
b48ac83d MZ |
754 | static void its_irq_compose_msi_msg(struct irq_data *d, struct msi_msg *msg) |
755 | { | |
756 | struct its_device *its_dev = irq_data_get_irq_chip_data(d); | |
757 | struct its_node *its; | |
758 | u64 addr; | |
759 | ||
760 | its = its_dev->its; | |
761 | addr = its->phys_base + GITS_TRANSLATER; | |
762 | ||
b11283eb VM |
763 | msg->address_lo = lower_32_bits(addr); |
764 | msg->address_hi = upper_32_bits(addr); | |
b48ac83d | 765 | msg->data = its_get_event_id(d); |
44bb7e24 RM |
766 | |
767 | iommu_dma_map_msi_msg(d->irq, msg); | |
b48ac83d MZ |
768 | } |
769 | ||
8d85dced MZ |
770 | static int its_irq_set_irqchip_state(struct irq_data *d, |
771 | enum irqchip_irq_state which, | |
772 | bool state) | |
773 | { | |
774 | struct its_device *its_dev = irq_data_get_irq_chip_data(d); | |
775 | u32 event = its_get_event_id(d); | |
776 | ||
777 | if (which != IRQCHIP_STATE_PENDING) | |
778 | return -EINVAL; | |
779 | ||
780 | if (state) | |
781 | its_send_int(its_dev, event); | |
782 | else | |
783 | its_send_clear(its_dev, event); | |
784 | ||
785 | return 0; | |
786 | } | |
787 | ||
c48ed51c MZ |
788 | static struct irq_chip its_irq_chip = { |
789 | .name = "ITS", | |
790 | .irq_mask = its_mask_irq, | |
791 | .irq_unmask = its_unmask_irq, | |
004fa08d | 792 | .irq_eoi = irq_chip_eoi_parent, |
c48ed51c | 793 | .irq_set_affinity = its_set_affinity, |
b48ac83d | 794 | .irq_compose_msi_msg = its_irq_compose_msi_msg, |
8d85dced | 795 | .irq_set_irqchip_state = its_irq_set_irqchip_state, |
b48ac83d MZ |
796 | }; |
797 | ||
bf9529f8 MZ |
798 | /* |
799 | * How we allocate LPIs: | |
800 | * | |
801 | * The GIC has id_bits bits for interrupt identifiers. From there, we | |
802 | * must subtract 8192 which are reserved for SGIs/PPIs/SPIs. Then, as | |
803 | * we allocate LPIs by chunks of 32, we can shift the whole thing by 5 | |
804 | * bits to the right. | |
805 | * | |
806 | * This gives us (((1UL << id_bits) - 8192) >> 5) possible allocations. | |
807 | */ | |
808 | #define IRQS_PER_CHUNK_SHIFT 5 | |
809 | #define IRQS_PER_CHUNK (1 << IRQS_PER_CHUNK_SHIFT) | |
6c31e123 | 810 | #define ITS_MAX_LPI_NRBITS 16 /* 64K LPIs */ |
bf9529f8 MZ |
811 | |
812 | static unsigned long *lpi_bitmap; | |
813 | static u32 lpi_chunks; | |
814 | static DEFINE_SPINLOCK(lpi_lock); | |
815 | ||
816 | static int its_lpi_to_chunk(int lpi) | |
817 | { | |
818 | return (lpi - 8192) >> IRQS_PER_CHUNK_SHIFT; | |
819 | } | |
820 | ||
821 | static int its_chunk_to_lpi(int chunk) | |
822 | { | |
823 | return (chunk << IRQS_PER_CHUNK_SHIFT) + 8192; | |
824 | } | |
825 | ||
04a0e4de | 826 | static int __init its_lpi_init(u32 id_bits) |
bf9529f8 MZ |
827 | { |
828 | lpi_chunks = its_lpi_to_chunk(1UL << id_bits); | |
829 | ||
830 | lpi_bitmap = kzalloc(BITS_TO_LONGS(lpi_chunks) * sizeof(long), | |
831 | GFP_KERNEL); | |
832 | if (!lpi_bitmap) { | |
833 | lpi_chunks = 0; | |
834 | return -ENOMEM; | |
835 | } | |
836 | ||
837 | pr_info("ITS: Allocated %d chunks for LPIs\n", (int)lpi_chunks); | |
838 | return 0; | |
839 | } | |
840 | ||
841 | static unsigned long *its_lpi_alloc_chunks(int nr_irqs, int *base, int *nr_ids) | |
842 | { | |
843 | unsigned long *bitmap = NULL; | |
844 | int chunk_id; | |
845 | int nr_chunks; | |
846 | int i; | |
847 | ||
848 | nr_chunks = DIV_ROUND_UP(nr_irqs, IRQS_PER_CHUNK); | |
849 | ||
850 | spin_lock(&lpi_lock); | |
851 | ||
852 | do { | |
853 | chunk_id = bitmap_find_next_zero_area(lpi_bitmap, lpi_chunks, | |
854 | 0, nr_chunks, 0); | |
855 | if (chunk_id < lpi_chunks) | |
856 | break; | |
857 | ||
858 | nr_chunks--; | |
859 | } while (nr_chunks > 0); | |
860 | ||
861 | if (!nr_chunks) | |
862 | goto out; | |
863 | ||
864 | bitmap = kzalloc(BITS_TO_LONGS(nr_chunks * IRQS_PER_CHUNK) * sizeof (long), | |
865 | GFP_ATOMIC); | |
866 | if (!bitmap) | |
867 | goto out; | |
868 | ||
869 | for (i = 0; i < nr_chunks; i++) | |
870 | set_bit(chunk_id + i, lpi_bitmap); | |
871 | ||
872 | *base = its_chunk_to_lpi(chunk_id); | |
873 | *nr_ids = nr_chunks * IRQS_PER_CHUNK; | |
874 | ||
875 | out: | |
876 | spin_unlock(&lpi_lock); | |
877 | ||
c8415b94 MZ |
878 | if (!bitmap) |
879 | *base = *nr_ids = 0; | |
880 | ||
bf9529f8 MZ |
881 | return bitmap; |
882 | } | |
883 | ||
591e5bec | 884 | static void its_lpi_free(struct event_lpi_map *map) |
bf9529f8 | 885 | { |
591e5bec MZ |
886 | int base = map->lpi_base; |
887 | int nr_ids = map->nr_lpis; | |
bf9529f8 MZ |
888 | int lpi; |
889 | ||
890 | spin_lock(&lpi_lock); | |
891 | ||
892 | for (lpi = base; lpi < (base + nr_ids); lpi += IRQS_PER_CHUNK) { | |
893 | int chunk = its_lpi_to_chunk(lpi); | |
894 | BUG_ON(chunk > lpi_chunks); | |
895 | if (test_bit(chunk, lpi_bitmap)) { | |
896 | clear_bit(chunk, lpi_bitmap); | |
897 | } else { | |
898 | pr_err("Bad LPI chunk %d\n", chunk); | |
899 | } | |
900 | } | |
901 | ||
902 | spin_unlock(&lpi_lock); | |
903 | ||
591e5bec MZ |
904 | kfree(map->lpi_map); |
905 | kfree(map->col_map); | |
bf9529f8 | 906 | } |
1ac19ca6 | 907 | |
1ac19ca6 MZ |
908 | static int __init its_alloc_lpi_tables(void) |
909 | { | |
910 | phys_addr_t paddr; | |
911 | ||
6c31e123 | 912 | lpi_id_bits = min_t(u32, gic_rdists->id_bits, ITS_MAX_LPI_NRBITS); |
1ac19ca6 MZ |
913 | gic_rdists->prop_page = alloc_pages(GFP_NOWAIT, |
914 | get_order(LPI_PROPBASE_SZ)); | |
915 | if (!gic_rdists->prop_page) { | |
916 | pr_err("Failed to allocate PROPBASE\n"); | |
917 | return -ENOMEM; | |
918 | } | |
919 | ||
920 | paddr = page_to_phys(gic_rdists->prop_page); | |
921 | pr_info("GIC: using LPI property table @%pa\n", &paddr); | |
922 | ||
923 | /* Priority 0xa0, Group-1, disabled */ | |
924 | memset(page_address(gic_rdists->prop_page), | |
925 | LPI_PROP_DEFAULT_PRIO | LPI_PROP_GROUP1, | |
926 | LPI_PROPBASE_SZ); | |
927 | ||
928 | /* Make sure the GIC will observe the written configuration */ | |
328191c0 | 929 | gic_flush_dcache_to_poc(page_address(gic_rdists->prop_page), LPI_PROPBASE_SZ); |
1ac19ca6 | 930 | |
6c31e123 | 931 | return its_lpi_init(lpi_id_bits); |
1ac19ca6 MZ |
932 | } |
933 | ||
934 | static const char *its_base_type_string[] = { | |
935 | [GITS_BASER_TYPE_DEVICE] = "Devices", | |
936 | [GITS_BASER_TYPE_VCPU] = "Virtual CPUs", | |
4f46de9d | 937 | [GITS_BASER_TYPE_RESERVED3] = "Reserved (3)", |
1ac19ca6 MZ |
938 | [GITS_BASER_TYPE_COLLECTION] = "Interrupt Collections", |
939 | [GITS_BASER_TYPE_RESERVED5] = "Reserved (5)", | |
940 | [GITS_BASER_TYPE_RESERVED6] = "Reserved (6)", | |
941 | [GITS_BASER_TYPE_RESERVED7] = "Reserved (7)", | |
942 | }; | |
943 | ||
2d81d425 SD |
944 | static u64 its_read_baser(struct its_node *its, struct its_baser *baser) |
945 | { | |
946 | u32 idx = baser - its->tables; | |
947 | ||
0968a619 | 948 | return gits_read_baser(its->base + GITS_BASER + (idx << 3)); |
2d81d425 SD |
949 | } |
950 | ||
951 | static void its_write_baser(struct its_node *its, struct its_baser *baser, | |
952 | u64 val) | |
953 | { | |
954 | u32 idx = baser - its->tables; | |
955 | ||
0968a619 | 956 | gits_write_baser(val, its->base + GITS_BASER + (idx << 3)); |
2d81d425 SD |
957 | baser->val = its_read_baser(its, baser); |
958 | } | |
959 | ||
9347359a | 960 | static int its_setup_baser(struct its_node *its, struct its_baser *baser, |
3faf24ea SD |
961 | u64 cache, u64 shr, u32 psz, u32 order, |
962 | bool indirect) | |
9347359a SD |
963 | { |
964 | u64 val = its_read_baser(its, baser); | |
965 | u64 esz = GITS_BASER_ENTRY_SIZE(val); | |
966 | u64 type = GITS_BASER_TYPE(val); | |
967 | u32 alloc_pages; | |
968 | void *base; | |
969 | u64 tmp; | |
970 | ||
971 | retry_alloc_baser: | |
972 | alloc_pages = (PAGE_ORDER_TO_SIZE(order) / psz); | |
973 | if (alloc_pages > GITS_BASER_PAGES_MAX) { | |
974 | pr_warn("ITS@%pa: %s too large, reduce ITS pages %u->%u\n", | |
975 | &its->phys_base, its_base_type_string[type], | |
976 | alloc_pages, GITS_BASER_PAGES_MAX); | |
977 | alloc_pages = GITS_BASER_PAGES_MAX; | |
978 | order = get_order(GITS_BASER_PAGES_MAX * psz); | |
979 | } | |
980 | ||
981 | base = (void *)__get_free_pages(GFP_KERNEL | __GFP_ZERO, order); | |
982 | if (!base) | |
983 | return -ENOMEM; | |
984 | ||
985 | retry_baser: | |
986 | val = (virt_to_phys(base) | | |
987 | (type << GITS_BASER_TYPE_SHIFT) | | |
988 | ((esz - 1) << GITS_BASER_ENTRY_SIZE_SHIFT) | | |
989 | ((alloc_pages - 1) << GITS_BASER_PAGES_SHIFT) | | |
990 | cache | | |
991 | shr | | |
992 | GITS_BASER_VALID); | |
993 | ||
3faf24ea SD |
994 | val |= indirect ? GITS_BASER_INDIRECT : 0x0; |
995 | ||
9347359a SD |
996 | switch (psz) { |
997 | case SZ_4K: | |
998 | val |= GITS_BASER_PAGE_SIZE_4K; | |
999 | break; | |
1000 | case SZ_16K: | |
1001 | val |= GITS_BASER_PAGE_SIZE_16K; | |
1002 | break; | |
1003 | case SZ_64K: | |
1004 | val |= GITS_BASER_PAGE_SIZE_64K; | |
1005 | break; | |
1006 | } | |
1007 | ||
1008 | its_write_baser(its, baser, val); | |
1009 | tmp = baser->val; | |
1010 | ||
1011 | if ((val ^ tmp) & GITS_BASER_SHAREABILITY_MASK) { | |
1012 | /* | |
1013 | * Shareability didn't stick. Just use | |
1014 | * whatever the read reported, which is likely | |
1015 | * to be the only thing this redistributor | |
1016 | * supports. If that's zero, make it | |
1017 | * non-cacheable as well. | |
1018 | */ | |
1019 | shr = tmp & GITS_BASER_SHAREABILITY_MASK; | |
1020 | if (!shr) { | |
1021 | cache = GITS_BASER_nC; | |
328191c0 | 1022 | gic_flush_dcache_to_poc(base, PAGE_ORDER_TO_SIZE(order)); |
9347359a SD |
1023 | } |
1024 | goto retry_baser; | |
1025 | } | |
1026 | ||
1027 | if ((val ^ tmp) & GITS_BASER_PAGE_SIZE_MASK) { | |
1028 | /* | |
1029 | * Page size didn't stick. Let's try a smaller | |
1030 | * size and retry. If we reach 4K, then | |
1031 | * something is horribly wrong... | |
1032 | */ | |
1033 | free_pages((unsigned long)base, order); | |
1034 | baser->base = NULL; | |
1035 | ||
1036 | switch (psz) { | |
1037 | case SZ_16K: | |
1038 | psz = SZ_4K; | |
1039 | goto retry_alloc_baser; | |
1040 | case SZ_64K: | |
1041 | psz = SZ_16K; | |
1042 | goto retry_alloc_baser; | |
1043 | } | |
1044 | } | |
1045 | ||
1046 | if (val != tmp) { | |
b11283eb | 1047 | pr_err("ITS@%pa: %s doesn't stick: %llx %llx\n", |
9347359a | 1048 | &its->phys_base, its_base_type_string[type], |
b11283eb | 1049 | val, tmp); |
9347359a SD |
1050 | free_pages((unsigned long)base, order); |
1051 | return -ENXIO; | |
1052 | } | |
1053 | ||
1054 | baser->order = order; | |
1055 | baser->base = base; | |
1056 | baser->psz = psz; | |
3faf24ea | 1057 | tmp = indirect ? GITS_LVL1_ENTRY_SIZE : esz; |
9347359a | 1058 | |
3faf24ea | 1059 | pr_info("ITS@%pa: allocated %d %s @%lx (%s, esz %d, psz %dK, shr %d)\n", |
d524eaa2 | 1060 | &its->phys_base, (int)(PAGE_ORDER_TO_SIZE(order) / (int)tmp), |
9347359a SD |
1061 | its_base_type_string[type], |
1062 | (unsigned long)virt_to_phys(base), | |
3faf24ea | 1063 | indirect ? "indirect" : "flat", (int)esz, |
9347359a SD |
1064 | psz / SZ_1K, (int)shr >> GITS_BASER_SHAREABILITY_SHIFT); |
1065 | ||
1066 | return 0; | |
1067 | } | |
1068 | ||
3faf24ea SD |
1069 | static bool its_parse_baser_device(struct its_node *its, struct its_baser *baser, |
1070 | u32 psz, u32 *order) | |
4b75c459 SD |
1071 | { |
1072 | u64 esz = GITS_BASER_ENTRY_SIZE(its_read_baser(its, baser)); | |
2fd632a0 | 1073 | u64 val = GITS_BASER_InnerShareable | GITS_BASER_RaWaWb; |
4b75c459 SD |
1074 | u32 ids = its->device_ids; |
1075 | u32 new_order = *order; | |
3faf24ea SD |
1076 | bool indirect = false; |
1077 | ||
1078 | /* No need to enable Indirection if memory requirement < (psz*2)bytes */ | |
1079 | if ((esz << ids) > (psz * 2)) { | |
1080 | /* | |
1081 | * Find out whether hw supports a single or two-level table by | |
1082 | * table by reading bit at offset '62' after writing '1' to it. | |
1083 | */ | |
1084 | its_write_baser(its, baser, val | GITS_BASER_INDIRECT); | |
1085 | indirect = !!(baser->val & GITS_BASER_INDIRECT); | |
1086 | ||
1087 | if (indirect) { | |
1088 | /* | |
1089 | * The size of the lvl2 table is equal to ITS page size | |
1090 | * which is 'psz'. For computing lvl1 table size, | |
1091 | * subtract ID bits that sparse lvl2 table from 'ids' | |
1092 | * which is reported by ITS hardware times lvl1 table | |
1093 | * entry size. | |
1094 | */ | |
d524eaa2 | 1095 | ids -= ilog2(psz / (int)esz); |
3faf24ea SD |
1096 | esz = GITS_LVL1_ENTRY_SIZE; |
1097 | } | |
1098 | } | |
4b75c459 SD |
1099 | |
1100 | /* | |
1101 | * Allocate as many entries as required to fit the | |
1102 | * range of device IDs that the ITS can grok... The ID | |
1103 | * space being incredibly sparse, this results in a | |
3faf24ea SD |
1104 | * massive waste of memory if two-level device table |
1105 | * feature is not supported by hardware. | |
4b75c459 SD |
1106 | */ |
1107 | new_order = max_t(u32, get_order(esz << ids), new_order); | |
1108 | if (new_order >= MAX_ORDER) { | |
1109 | new_order = MAX_ORDER - 1; | |
d524eaa2 | 1110 | ids = ilog2(PAGE_ORDER_TO_SIZE(new_order) / (int)esz); |
4b75c459 SD |
1111 | pr_warn("ITS@%pa: Device Table too large, reduce ids %u->%u\n", |
1112 | &its->phys_base, its->device_ids, ids); | |
1113 | } | |
1114 | ||
1115 | *order = new_order; | |
3faf24ea SD |
1116 | |
1117 | return indirect; | |
4b75c459 SD |
1118 | } |
1119 | ||
1ac19ca6 MZ |
1120 | static void its_free_tables(struct its_node *its) |
1121 | { | |
1122 | int i; | |
1123 | ||
1124 | for (i = 0; i < GITS_BASER_NR_REGS; i++) { | |
1a485f4d SD |
1125 | if (its->tables[i].base) { |
1126 | free_pages((unsigned long)its->tables[i].base, | |
1127 | its->tables[i].order); | |
1128 | its->tables[i].base = NULL; | |
1ac19ca6 MZ |
1129 | } |
1130 | } | |
1131 | } | |
1132 | ||
0e0b0f69 | 1133 | static int its_alloc_tables(struct its_node *its) |
1ac19ca6 | 1134 | { |
589ce5f4 | 1135 | u64 typer = gic_read_typer(its->base + GITS_TYPER); |
9347359a | 1136 | u32 ids = GITS_TYPER_DEVBITS(typer); |
1ac19ca6 | 1137 | u64 shr = GITS_BASER_InnerShareable; |
2fd632a0 | 1138 | u64 cache = GITS_BASER_RaWaWb; |
9347359a SD |
1139 | u32 psz = SZ_64K; |
1140 | int err, i; | |
94100970 RR |
1141 | |
1142 | if (its->flags & ITS_FLAGS_WORKAROUND_CAVIUM_22375) { | |
1143 | /* | |
9347359a SD |
1144 | * erratum 22375: only alloc 8MB table size |
1145 | * erratum 24313: ignore memory access type | |
1146 | */ | |
1147 | cache = GITS_BASER_nCnB; | |
1148 | ids = 0x14; /* 20 bits, 8MB */ | |
94100970 | 1149 | } |
1ac19ca6 | 1150 | |
466b7d16 SD |
1151 | its->device_ids = ids; |
1152 | ||
1ac19ca6 | 1153 | for (i = 0; i < GITS_BASER_NR_REGS; i++) { |
2d81d425 SD |
1154 | struct its_baser *baser = its->tables + i; |
1155 | u64 val = its_read_baser(its, baser); | |
1ac19ca6 | 1156 | u64 type = GITS_BASER_TYPE(val); |
9347359a | 1157 | u32 order = get_order(psz); |
3faf24ea | 1158 | bool indirect = false; |
1ac19ca6 MZ |
1159 | |
1160 | if (type == GITS_BASER_TYPE_NONE) | |
1161 | continue; | |
1162 | ||
4b75c459 | 1163 | if (type == GITS_BASER_TYPE_DEVICE) |
3faf24ea | 1164 | indirect = its_parse_baser_device(its, baser, psz, &order); |
f54b97ed | 1165 | |
3faf24ea | 1166 | err = its_setup_baser(its, baser, cache, shr, psz, order, indirect); |
9347359a SD |
1167 | if (err < 0) { |
1168 | its_free_tables(its); | |
1169 | return err; | |
1ac19ca6 MZ |
1170 | } |
1171 | ||
9347359a SD |
1172 | /* Update settings which will be used for next BASERn */ |
1173 | psz = baser->psz; | |
1174 | cache = baser->val & GITS_BASER_CACHEABILITY_MASK; | |
1175 | shr = baser->val & GITS_BASER_SHAREABILITY_MASK; | |
1ac19ca6 MZ |
1176 | } |
1177 | ||
1178 | return 0; | |
1ac19ca6 MZ |
1179 | } |
1180 | ||
1181 | static int its_alloc_collections(struct its_node *its) | |
1182 | { | |
1183 | its->collections = kzalloc(nr_cpu_ids * sizeof(*its->collections), | |
1184 | GFP_KERNEL); | |
1185 | if (!its->collections) | |
1186 | return -ENOMEM; | |
1187 | ||
1188 | return 0; | |
1189 | } | |
1190 | ||
1191 | static void its_cpu_init_lpis(void) | |
1192 | { | |
1193 | void __iomem *rbase = gic_data_rdist_rd_base(); | |
1194 | struct page *pend_page; | |
1195 | u64 val, tmp; | |
1196 | ||
1197 | /* If we didn't allocate the pending table yet, do it now */ | |
1198 | pend_page = gic_data_rdist()->pend_page; | |
1199 | if (!pend_page) { | |
1200 | phys_addr_t paddr; | |
1201 | /* | |
1202 | * The pending pages have to be at least 64kB aligned, | |
1203 | * hence the 'max(LPI_PENDBASE_SZ, SZ_64K)' below. | |
1204 | */ | |
1205 | pend_page = alloc_pages(GFP_NOWAIT | __GFP_ZERO, | |
6c31e123 | 1206 | get_order(max_t(u32, LPI_PENDBASE_SZ, SZ_64K))); |
1ac19ca6 MZ |
1207 | if (!pend_page) { |
1208 | pr_err("Failed to allocate PENDBASE for CPU%d\n", | |
1209 | smp_processor_id()); | |
1210 | return; | |
1211 | } | |
1212 | ||
1213 | /* Make sure the GIC will observe the zero-ed page */ | |
328191c0 | 1214 | gic_flush_dcache_to_poc(page_address(pend_page), LPI_PENDBASE_SZ); |
1ac19ca6 MZ |
1215 | |
1216 | paddr = page_to_phys(pend_page); | |
1217 | pr_info("CPU%d: using LPI pending table @%pa\n", | |
1218 | smp_processor_id(), &paddr); | |
1219 | gic_data_rdist()->pend_page = pend_page; | |
1220 | } | |
1221 | ||
1222 | /* Disable LPIs */ | |
1223 | val = readl_relaxed(rbase + GICR_CTLR); | |
1224 | val &= ~GICR_CTLR_ENABLE_LPIS; | |
1225 | writel_relaxed(val, rbase + GICR_CTLR); | |
1226 | ||
1227 | /* | |
1228 | * Make sure any change to the table is observable by the GIC. | |
1229 | */ | |
1230 | dsb(sy); | |
1231 | ||
1232 | /* set PROPBASE */ | |
1233 | val = (page_to_phys(gic_rdists->prop_page) | | |
1234 | GICR_PROPBASER_InnerShareable | | |
2fd632a0 | 1235 | GICR_PROPBASER_RaWaWb | |
1ac19ca6 MZ |
1236 | ((LPI_NRBITS - 1) & GICR_PROPBASER_IDBITS_MASK)); |
1237 | ||
0968a619 VM |
1238 | gicr_write_propbaser(val, rbase + GICR_PROPBASER); |
1239 | tmp = gicr_read_propbaser(rbase + GICR_PROPBASER); | |
1ac19ca6 MZ |
1240 | |
1241 | if ((tmp ^ val) & GICR_PROPBASER_SHAREABILITY_MASK) { | |
241a386c MZ |
1242 | if (!(tmp & GICR_PROPBASER_SHAREABILITY_MASK)) { |
1243 | /* | |
1244 | * The HW reports non-shareable, we must | |
1245 | * remove the cacheability attributes as | |
1246 | * well. | |
1247 | */ | |
1248 | val &= ~(GICR_PROPBASER_SHAREABILITY_MASK | | |
1249 | GICR_PROPBASER_CACHEABILITY_MASK); | |
1250 | val |= GICR_PROPBASER_nC; | |
0968a619 | 1251 | gicr_write_propbaser(val, rbase + GICR_PROPBASER); |
241a386c | 1252 | } |
1ac19ca6 MZ |
1253 | pr_info_once("GIC: using cache flushing for LPI property table\n"); |
1254 | gic_rdists->flags |= RDIST_FLAGS_PROPBASE_NEEDS_FLUSHING; | |
1255 | } | |
1256 | ||
1257 | /* set PENDBASE */ | |
1258 | val = (page_to_phys(pend_page) | | |
4ad3e363 | 1259 | GICR_PENDBASER_InnerShareable | |
2fd632a0 | 1260 | GICR_PENDBASER_RaWaWb); |
1ac19ca6 | 1261 | |
0968a619 VM |
1262 | gicr_write_pendbaser(val, rbase + GICR_PENDBASER); |
1263 | tmp = gicr_read_pendbaser(rbase + GICR_PENDBASER); | |
241a386c MZ |
1264 | |
1265 | if (!(tmp & GICR_PENDBASER_SHAREABILITY_MASK)) { | |
1266 | /* | |
1267 | * The HW reports non-shareable, we must remove the | |
1268 | * cacheability attributes as well. | |
1269 | */ | |
1270 | val &= ~(GICR_PENDBASER_SHAREABILITY_MASK | | |
1271 | GICR_PENDBASER_CACHEABILITY_MASK); | |
1272 | val |= GICR_PENDBASER_nC; | |
0968a619 | 1273 | gicr_write_pendbaser(val, rbase + GICR_PENDBASER); |
241a386c | 1274 | } |
1ac19ca6 MZ |
1275 | |
1276 | /* Enable LPIs */ | |
1277 | val = readl_relaxed(rbase + GICR_CTLR); | |
1278 | val |= GICR_CTLR_ENABLE_LPIS; | |
1279 | writel_relaxed(val, rbase + GICR_CTLR); | |
1280 | ||
1281 | /* Make sure the GIC has seen the above */ | |
1282 | dsb(sy); | |
1283 | } | |
1284 | ||
1285 | static void its_cpu_init_collection(void) | |
1286 | { | |
1287 | struct its_node *its; | |
1288 | int cpu; | |
1289 | ||
1290 | spin_lock(&its_lock); | |
1291 | cpu = smp_processor_id(); | |
1292 | ||
1293 | list_for_each_entry(its, &its_nodes, entry) { | |
1294 | u64 target; | |
1295 | ||
fbf8f40e GK |
1296 | /* avoid cross node collections and its mapping */ |
1297 | if (its->flags & ITS_FLAGS_WORKAROUND_CAVIUM_23144) { | |
1298 | struct device_node *cpu_node; | |
1299 | ||
1300 | cpu_node = of_get_cpu_node(cpu, NULL); | |
1301 | if (its->numa_node != NUMA_NO_NODE && | |
1302 | its->numa_node != of_node_to_nid(cpu_node)) | |
1303 | continue; | |
1304 | } | |
1305 | ||
1ac19ca6 MZ |
1306 | /* |
1307 | * We now have to bind each collection to its target | |
1308 | * redistributor. | |
1309 | */ | |
589ce5f4 | 1310 | if (gic_read_typer(its->base + GITS_TYPER) & GITS_TYPER_PTA) { |
1ac19ca6 MZ |
1311 | /* |
1312 | * This ITS wants the physical address of the | |
1313 | * redistributor. | |
1314 | */ | |
1315 | target = gic_data_rdist()->phys_base; | |
1316 | } else { | |
1317 | /* | |
1318 | * This ITS wants a linear CPU number. | |
1319 | */ | |
589ce5f4 | 1320 | target = gic_read_typer(gic_data_rdist_rd_base() + GICR_TYPER); |
263fcd31 | 1321 | target = GICR_TYPER_CPU_NUMBER(target) << 16; |
1ac19ca6 MZ |
1322 | } |
1323 | ||
1324 | /* Perform collection mapping */ | |
1325 | its->collections[cpu].target_address = target; | |
1326 | its->collections[cpu].col_id = cpu; | |
1327 | ||
1328 | its_send_mapc(its, &its->collections[cpu], 1); | |
1329 | its_send_invall(its, &its->collections[cpu]); | |
1330 | } | |
1331 | ||
1332 | spin_unlock(&its_lock); | |
1333 | } | |
84a6a2e7 MZ |
1334 | |
1335 | static struct its_device *its_find_device(struct its_node *its, u32 dev_id) | |
1336 | { | |
1337 | struct its_device *its_dev = NULL, *tmp; | |
3e39e8f5 | 1338 | unsigned long flags; |
84a6a2e7 | 1339 | |
3e39e8f5 | 1340 | raw_spin_lock_irqsave(&its->lock, flags); |
84a6a2e7 MZ |
1341 | |
1342 | list_for_each_entry(tmp, &its->its_device_list, entry) { | |
1343 | if (tmp->device_id == dev_id) { | |
1344 | its_dev = tmp; | |
1345 | break; | |
1346 | } | |
1347 | } | |
1348 | ||
3e39e8f5 | 1349 | raw_spin_unlock_irqrestore(&its->lock, flags); |
84a6a2e7 MZ |
1350 | |
1351 | return its_dev; | |
1352 | } | |
1353 | ||
466b7d16 SD |
1354 | static struct its_baser *its_get_baser(struct its_node *its, u32 type) |
1355 | { | |
1356 | int i; | |
1357 | ||
1358 | for (i = 0; i < GITS_BASER_NR_REGS; i++) { | |
1359 | if (GITS_BASER_TYPE(its->tables[i].val) == type) | |
1360 | return &its->tables[i]; | |
1361 | } | |
1362 | ||
1363 | return NULL; | |
1364 | } | |
1365 | ||
3faf24ea SD |
1366 | static bool its_alloc_device_table(struct its_node *its, u32 dev_id) |
1367 | { | |
1368 | struct its_baser *baser; | |
1369 | struct page *page; | |
1370 | u32 esz, idx; | |
1371 | __le64 *table; | |
1372 | ||
1373 | baser = its_get_baser(its, GITS_BASER_TYPE_DEVICE); | |
1374 | ||
1375 | /* Don't allow device id that exceeds ITS hardware limit */ | |
1376 | if (!baser) | |
1377 | return (ilog2(dev_id) < its->device_ids); | |
1378 | ||
1379 | /* Don't allow device id that exceeds single, flat table limit */ | |
1380 | esz = GITS_BASER_ENTRY_SIZE(baser->val); | |
1381 | if (!(baser->val & GITS_BASER_INDIRECT)) | |
1382 | return (dev_id < (PAGE_ORDER_TO_SIZE(baser->order) / esz)); | |
1383 | ||
1384 | /* Compute 1st level table index & check if that exceeds table limit */ | |
1385 | idx = dev_id >> ilog2(baser->psz / esz); | |
1386 | if (idx >= (PAGE_ORDER_TO_SIZE(baser->order) / GITS_LVL1_ENTRY_SIZE)) | |
1387 | return false; | |
1388 | ||
1389 | table = baser->base; | |
1390 | ||
1391 | /* Allocate memory for 2nd level table */ | |
1392 | if (!table[idx]) { | |
1393 | page = alloc_pages(GFP_KERNEL | __GFP_ZERO, get_order(baser->psz)); | |
1394 | if (!page) | |
1395 | return false; | |
1396 | ||
1397 | /* Flush Lvl2 table to PoC if hw doesn't support coherency */ | |
1398 | if (!(baser->val & GITS_BASER_SHAREABILITY_MASK)) | |
328191c0 | 1399 | gic_flush_dcache_to_poc(page_address(page), baser->psz); |
3faf24ea SD |
1400 | |
1401 | table[idx] = cpu_to_le64(page_to_phys(page) | GITS_BASER_VALID); | |
1402 | ||
1403 | /* Flush Lvl1 entry to PoC if hw doesn't support coherency */ | |
1404 | if (!(baser->val & GITS_BASER_SHAREABILITY_MASK)) | |
328191c0 | 1405 | gic_flush_dcache_to_poc(table + idx, GITS_LVL1_ENTRY_SIZE); |
3faf24ea SD |
1406 | |
1407 | /* Ensure updated table contents are visible to ITS hardware */ | |
1408 | dsb(sy); | |
1409 | } | |
1410 | ||
1411 | return true; | |
1412 | } | |
1413 | ||
84a6a2e7 MZ |
1414 | static struct its_device *its_create_device(struct its_node *its, u32 dev_id, |
1415 | int nvecs) | |
1416 | { | |
1417 | struct its_device *dev; | |
1418 | unsigned long *lpi_map; | |
3e39e8f5 | 1419 | unsigned long flags; |
591e5bec | 1420 | u16 *col_map = NULL; |
84a6a2e7 MZ |
1421 | void *itt; |
1422 | int lpi_base; | |
1423 | int nr_lpis; | |
c8481267 | 1424 | int nr_ites; |
84a6a2e7 MZ |
1425 | int sz; |
1426 | ||
3faf24ea | 1427 | if (!its_alloc_device_table(its, dev_id)) |
466b7d16 SD |
1428 | return NULL; |
1429 | ||
84a6a2e7 | 1430 | dev = kzalloc(sizeof(*dev), GFP_KERNEL); |
c8481267 MZ |
1431 | /* |
1432 | * At least one bit of EventID is being used, hence a minimum | |
1433 | * of two entries. No, the architecture doesn't let you | |
1434 | * express an ITT with a single entry. | |
1435 | */ | |
96555c47 | 1436 | nr_ites = max(2UL, roundup_pow_of_two(nvecs)); |
c8481267 | 1437 | sz = nr_ites * its->ite_size; |
84a6a2e7 | 1438 | sz = max(sz, ITS_ITT_ALIGN) + ITS_ITT_ALIGN - 1; |
6c834125 | 1439 | itt = kzalloc(sz, GFP_KERNEL); |
84a6a2e7 | 1440 | lpi_map = its_lpi_alloc_chunks(nvecs, &lpi_base, &nr_lpis); |
591e5bec MZ |
1441 | if (lpi_map) |
1442 | col_map = kzalloc(sizeof(*col_map) * nr_lpis, GFP_KERNEL); | |
84a6a2e7 | 1443 | |
591e5bec | 1444 | if (!dev || !itt || !lpi_map || !col_map) { |
84a6a2e7 MZ |
1445 | kfree(dev); |
1446 | kfree(itt); | |
1447 | kfree(lpi_map); | |
591e5bec | 1448 | kfree(col_map); |
84a6a2e7 MZ |
1449 | return NULL; |
1450 | } | |
1451 | ||
328191c0 | 1452 | gic_flush_dcache_to_poc(itt, sz); |
5a9a8915 | 1453 | |
84a6a2e7 MZ |
1454 | dev->its = its; |
1455 | dev->itt = itt; | |
c8481267 | 1456 | dev->nr_ites = nr_ites; |
591e5bec MZ |
1457 | dev->event_map.lpi_map = lpi_map; |
1458 | dev->event_map.col_map = col_map; | |
1459 | dev->event_map.lpi_base = lpi_base; | |
1460 | dev->event_map.nr_lpis = nr_lpis; | |
84a6a2e7 MZ |
1461 | dev->device_id = dev_id; |
1462 | INIT_LIST_HEAD(&dev->entry); | |
1463 | ||
3e39e8f5 | 1464 | raw_spin_lock_irqsave(&its->lock, flags); |
84a6a2e7 | 1465 | list_add(&dev->entry, &its->its_device_list); |
3e39e8f5 | 1466 | raw_spin_unlock_irqrestore(&its->lock, flags); |
84a6a2e7 | 1467 | |
84a6a2e7 MZ |
1468 | /* Map device to its ITT */ |
1469 | its_send_mapd(dev, 1); | |
1470 | ||
1471 | return dev; | |
1472 | } | |
1473 | ||
1474 | static void its_free_device(struct its_device *its_dev) | |
1475 | { | |
3e39e8f5 MZ |
1476 | unsigned long flags; |
1477 | ||
1478 | raw_spin_lock_irqsave(&its_dev->its->lock, flags); | |
84a6a2e7 | 1479 | list_del(&its_dev->entry); |
3e39e8f5 | 1480 | raw_spin_unlock_irqrestore(&its_dev->its->lock, flags); |
84a6a2e7 MZ |
1481 | kfree(its_dev->itt); |
1482 | kfree(its_dev); | |
1483 | } | |
b48ac83d MZ |
1484 | |
1485 | static int its_alloc_device_irq(struct its_device *dev, irq_hw_number_t *hwirq) | |
1486 | { | |
1487 | int idx; | |
1488 | ||
591e5bec MZ |
1489 | idx = find_first_zero_bit(dev->event_map.lpi_map, |
1490 | dev->event_map.nr_lpis); | |
1491 | if (idx == dev->event_map.nr_lpis) | |
b48ac83d MZ |
1492 | return -ENOSPC; |
1493 | ||
591e5bec MZ |
1494 | *hwirq = dev->event_map.lpi_base + idx; |
1495 | set_bit(idx, dev->event_map.lpi_map); | |
b48ac83d | 1496 | |
b48ac83d MZ |
1497 | return 0; |
1498 | } | |
1499 | ||
54456db9 MZ |
1500 | static int its_msi_prepare(struct irq_domain *domain, struct device *dev, |
1501 | int nvec, msi_alloc_info_t *info) | |
e8137f4f | 1502 | { |
b48ac83d | 1503 | struct its_node *its; |
b48ac83d | 1504 | struct its_device *its_dev; |
54456db9 MZ |
1505 | struct msi_domain_info *msi_info; |
1506 | u32 dev_id; | |
1507 | ||
1508 | /* | |
1509 | * We ignore "dev" entierely, and rely on the dev_id that has | |
1510 | * been passed via the scratchpad. This limits this domain's | |
1511 | * usefulness to upper layers that definitely know that they | |
1512 | * are built on top of the ITS. | |
1513 | */ | |
1514 | dev_id = info->scratchpad[0].ul; | |
1515 | ||
1516 | msi_info = msi_get_domain_info(domain); | |
1517 | its = msi_info->data; | |
e8137f4f | 1518 | |
f130420e | 1519 | its_dev = its_find_device(its, dev_id); |
e8137f4f MZ |
1520 | if (its_dev) { |
1521 | /* | |
1522 | * We already have seen this ID, probably through | |
1523 | * another alias (PCI bridge of some sort). No need to | |
1524 | * create the device. | |
1525 | */ | |
f130420e | 1526 | pr_debug("Reusing ITT for devID %x\n", dev_id); |
e8137f4f MZ |
1527 | goto out; |
1528 | } | |
b48ac83d | 1529 | |
f130420e | 1530 | its_dev = its_create_device(its, dev_id, nvec); |
b48ac83d MZ |
1531 | if (!its_dev) |
1532 | return -ENOMEM; | |
1533 | ||
f130420e | 1534 | pr_debug("ITT %d entries, %d bits\n", nvec, ilog2(nvec)); |
e8137f4f | 1535 | out: |
b48ac83d | 1536 | info->scratchpad[0].ptr = its_dev; |
b48ac83d MZ |
1537 | return 0; |
1538 | } | |
1539 | ||
54456db9 MZ |
1540 | static struct msi_domain_ops its_msi_domain_ops = { |
1541 | .msi_prepare = its_msi_prepare, | |
1542 | }; | |
1543 | ||
b48ac83d MZ |
1544 | static int its_irq_gic_domain_alloc(struct irq_domain *domain, |
1545 | unsigned int virq, | |
1546 | irq_hw_number_t hwirq) | |
1547 | { | |
f833f57f MZ |
1548 | struct irq_fwspec fwspec; |
1549 | ||
1550 | if (irq_domain_get_of_node(domain->parent)) { | |
1551 | fwspec.fwnode = domain->parent->fwnode; | |
1552 | fwspec.param_count = 3; | |
1553 | fwspec.param[0] = GIC_IRQ_TYPE_LPI; | |
1554 | fwspec.param[1] = hwirq; | |
1555 | fwspec.param[2] = IRQ_TYPE_EDGE_RISING; | |
3f010cf1 TN |
1556 | } else if (is_fwnode_irqchip(domain->parent->fwnode)) { |
1557 | fwspec.fwnode = domain->parent->fwnode; | |
1558 | fwspec.param_count = 2; | |
1559 | fwspec.param[0] = hwirq; | |
1560 | fwspec.param[1] = IRQ_TYPE_EDGE_RISING; | |
f833f57f MZ |
1561 | } else { |
1562 | return -EINVAL; | |
1563 | } | |
b48ac83d | 1564 | |
f833f57f | 1565 | return irq_domain_alloc_irqs_parent(domain, virq, 1, &fwspec); |
b48ac83d MZ |
1566 | } |
1567 | ||
1568 | static int its_irq_domain_alloc(struct irq_domain *domain, unsigned int virq, | |
1569 | unsigned int nr_irqs, void *args) | |
1570 | { | |
1571 | msi_alloc_info_t *info = args; | |
1572 | struct its_device *its_dev = info->scratchpad[0].ptr; | |
1573 | irq_hw_number_t hwirq; | |
1574 | int err; | |
1575 | int i; | |
1576 | ||
1577 | for (i = 0; i < nr_irqs; i++) { | |
1578 | err = its_alloc_device_irq(its_dev, &hwirq); | |
1579 | if (err) | |
1580 | return err; | |
1581 | ||
1582 | err = its_irq_gic_domain_alloc(domain, virq + i, hwirq); | |
1583 | if (err) | |
1584 | return err; | |
1585 | ||
1586 | irq_domain_set_hwirq_and_chip(domain, virq + i, | |
1587 | hwirq, &its_irq_chip, its_dev); | |
f130420e MZ |
1588 | pr_debug("ID:%d pID:%d vID:%d\n", |
1589 | (int)(hwirq - its_dev->event_map.lpi_base), | |
1590 | (int) hwirq, virq + i); | |
b48ac83d MZ |
1591 | } |
1592 | ||
1593 | return 0; | |
1594 | } | |
1595 | ||
aca268df MZ |
1596 | static void its_irq_domain_activate(struct irq_domain *domain, |
1597 | struct irq_data *d) | |
1598 | { | |
1599 | struct its_device *its_dev = irq_data_get_irq_chip_data(d); | |
1600 | u32 event = its_get_event_id(d); | |
fbf8f40e GK |
1601 | const struct cpumask *cpu_mask = cpu_online_mask; |
1602 | ||
1603 | /* get the cpu_mask of local node */ | |
1604 | if (its_dev->its->numa_node >= 0) | |
1605 | cpu_mask = cpumask_of_node(its_dev->its->numa_node); | |
aca268df | 1606 | |
591e5bec | 1607 | /* Bind the LPI to the first possible CPU */ |
fbf8f40e | 1608 | its_dev->event_map.col_map[event] = cpumask_first(cpu_mask); |
591e5bec | 1609 | |
aca268df | 1610 | /* Map the GIC IRQ and event to the device */ |
6a25ad3a | 1611 | its_send_mapti(its_dev, d->hwirq, event); |
aca268df MZ |
1612 | } |
1613 | ||
1614 | static void its_irq_domain_deactivate(struct irq_domain *domain, | |
1615 | struct irq_data *d) | |
1616 | { | |
1617 | struct its_device *its_dev = irq_data_get_irq_chip_data(d); | |
1618 | u32 event = its_get_event_id(d); | |
1619 | ||
1620 | /* Stop the delivery of interrupts */ | |
1621 | its_send_discard(its_dev, event); | |
1622 | } | |
1623 | ||
b48ac83d MZ |
1624 | static void its_irq_domain_free(struct irq_domain *domain, unsigned int virq, |
1625 | unsigned int nr_irqs) | |
1626 | { | |
1627 | struct irq_data *d = irq_domain_get_irq_data(domain, virq); | |
1628 | struct its_device *its_dev = irq_data_get_irq_chip_data(d); | |
1629 | int i; | |
1630 | ||
1631 | for (i = 0; i < nr_irqs; i++) { | |
1632 | struct irq_data *data = irq_domain_get_irq_data(domain, | |
1633 | virq + i); | |
aca268df | 1634 | u32 event = its_get_event_id(data); |
b48ac83d MZ |
1635 | |
1636 | /* Mark interrupt index as unused */ | |
591e5bec | 1637 | clear_bit(event, its_dev->event_map.lpi_map); |
b48ac83d MZ |
1638 | |
1639 | /* Nuke the entry in the domain */ | |
2da39949 | 1640 | irq_domain_reset_irq_data(data); |
b48ac83d MZ |
1641 | } |
1642 | ||
1643 | /* If all interrupts have been freed, start mopping the floor */ | |
591e5bec MZ |
1644 | if (bitmap_empty(its_dev->event_map.lpi_map, |
1645 | its_dev->event_map.nr_lpis)) { | |
1646 | its_lpi_free(&its_dev->event_map); | |
b48ac83d MZ |
1647 | |
1648 | /* Unmap device/itt */ | |
1649 | its_send_mapd(its_dev, 0); | |
1650 | its_free_device(its_dev); | |
1651 | } | |
1652 | ||
1653 | irq_domain_free_irqs_parent(domain, virq, nr_irqs); | |
1654 | } | |
1655 | ||
1656 | static const struct irq_domain_ops its_domain_ops = { | |
1657 | .alloc = its_irq_domain_alloc, | |
1658 | .free = its_irq_domain_free, | |
aca268df MZ |
1659 | .activate = its_irq_domain_activate, |
1660 | .deactivate = its_irq_domain_deactivate, | |
b48ac83d | 1661 | }; |
4c21f3c2 | 1662 | |
4559fbb3 YW |
1663 | static int its_force_quiescent(void __iomem *base) |
1664 | { | |
1665 | u32 count = 1000000; /* 1s */ | |
1666 | u32 val; | |
1667 | ||
1668 | val = readl_relaxed(base + GITS_CTLR); | |
7611da86 DD |
1669 | /* |
1670 | * GIC architecture specification requires the ITS to be both | |
1671 | * disabled and quiescent for writes to GITS_BASER<n> or | |
1672 | * GITS_CBASER to not have UNPREDICTABLE results. | |
1673 | */ | |
1674 | if ((val & GITS_CTLR_QUIESCENT) && !(val & GITS_CTLR_ENABLE)) | |
4559fbb3 YW |
1675 | return 0; |
1676 | ||
1677 | /* Disable the generation of all interrupts to this ITS */ | |
1678 | val &= ~GITS_CTLR_ENABLE; | |
1679 | writel_relaxed(val, base + GITS_CTLR); | |
1680 | ||
1681 | /* Poll GITS_CTLR and wait until ITS becomes quiescent */ | |
1682 | while (1) { | |
1683 | val = readl_relaxed(base + GITS_CTLR); | |
1684 | if (val & GITS_CTLR_QUIESCENT) | |
1685 | return 0; | |
1686 | ||
1687 | count--; | |
1688 | if (!count) | |
1689 | return -EBUSY; | |
1690 | ||
1691 | cpu_relax(); | |
1692 | udelay(1); | |
1693 | } | |
1694 | } | |
1695 | ||
94100970 RR |
1696 | static void __maybe_unused its_enable_quirk_cavium_22375(void *data) |
1697 | { | |
1698 | struct its_node *its = data; | |
1699 | ||
1700 | its->flags |= ITS_FLAGS_WORKAROUND_CAVIUM_22375; | |
1701 | } | |
1702 | ||
fbf8f40e GK |
1703 | static void __maybe_unused its_enable_quirk_cavium_23144(void *data) |
1704 | { | |
1705 | struct its_node *its = data; | |
1706 | ||
1707 | its->flags |= ITS_FLAGS_WORKAROUND_CAVIUM_23144; | |
1708 | } | |
1709 | ||
90922a2d SD |
1710 | static void __maybe_unused its_enable_quirk_qdf2400_e0065(void *data) |
1711 | { | |
1712 | struct its_node *its = data; | |
1713 | ||
1714 | /* On QDF2400, the size of the ITE is 16Bytes */ | |
1715 | its->ite_size = 16; | |
1716 | } | |
1717 | ||
67510cca | 1718 | static const struct gic_quirk its_quirks[] = { |
94100970 RR |
1719 | #ifdef CONFIG_CAVIUM_ERRATUM_22375 |
1720 | { | |
1721 | .desc = "ITS: Cavium errata 22375, 24313", | |
1722 | .iidr = 0xa100034c, /* ThunderX pass 1.x */ | |
1723 | .mask = 0xffff0fff, | |
1724 | .init = its_enable_quirk_cavium_22375, | |
1725 | }, | |
fbf8f40e GK |
1726 | #endif |
1727 | #ifdef CONFIG_CAVIUM_ERRATUM_23144 | |
1728 | { | |
1729 | .desc = "ITS: Cavium erratum 23144", | |
1730 | .iidr = 0xa100034c, /* ThunderX pass 1.x */ | |
1731 | .mask = 0xffff0fff, | |
1732 | .init = its_enable_quirk_cavium_23144, | |
1733 | }, | |
90922a2d SD |
1734 | #endif |
1735 | #ifdef CONFIG_QCOM_QDF2400_ERRATUM_0065 | |
1736 | { | |
1737 | .desc = "ITS: QDF2400 erratum 0065", | |
1738 | .iidr = 0x00001070, /* QDF2400 ITS rev 1.x */ | |
1739 | .mask = 0xffffffff, | |
1740 | .init = its_enable_quirk_qdf2400_e0065, | |
1741 | }, | |
94100970 | 1742 | #endif |
67510cca RR |
1743 | { |
1744 | } | |
1745 | }; | |
1746 | ||
1747 | static void its_enable_quirks(struct its_node *its) | |
1748 | { | |
1749 | u32 iidr = readl_relaxed(its->base + GITS_IIDR); | |
1750 | ||
1751 | gic_enable_quirks(iidr, its_quirks, its); | |
1752 | } | |
1753 | ||
db40f0a7 | 1754 | static int its_init_domain(struct fwnode_handle *handle, struct its_node *its) |
d14ae5e6 TN |
1755 | { |
1756 | struct irq_domain *inner_domain; | |
1757 | struct msi_domain_info *info; | |
1758 | ||
1759 | info = kzalloc(sizeof(*info), GFP_KERNEL); | |
1760 | if (!info) | |
1761 | return -ENOMEM; | |
1762 | ||
db40f0a7 | 1763 | inner_domain = irq_domain_create_tree(handle, &its_domain_ops, its); |
d14ae5e6 TN |
1764 | if (!inner_domain) { |
1765 | kfree(info); | |
1766 | return -ENOMEM; | |
1767 | } | |
1768 | ||
db40f0a7 | 1769 | inner_domain->parent = its_parent; |
96f0d93a | 1770 | irq_domain_update_bus_token(inner_domain, DOMAIN_BUS_NEXUS); |
59768527 | 1771 | inner_domain->flags |= IRQ_DOMAIN_FLAG_MSI_REMAP; |
d14ae5e6 TN |
1772 | info->ops = &its_msi_domain_ops; |
1773 | info->data = its; | |
1774 | inner_domain->host_data = info; | |
1775 | ||
1776 | return 0; | |
1777 | } | |
1778 | ||
3dfa576b MZ |
1779 | static int __init its_compute_its_list_map(struct resource *res, |
1780 | void __iomem *its_base) | |
1781 | { | |
1782 | int its_number; | |
1783 | u32 ctlr; | |
1784 | ||
1785 | /* | |
1786 | * This is assumed to be done early enough that we're | |
1787 | * guaranteed to be single-threaded, hence no | |
1788 | * locking. Should this change, we should address | |
1789 | * this. | |
1790 | */ | |
1791 | its_number = find_first_zero_bit(&its_list_map, ITS_LIST_MAX); | |
1792 | if (its_number >= ITS_LIST_MAX) { | |
1793 | pr_err("ITS@%pa: No ITSList entry available!\n", | |
1794 | &res->start); | |
1795 | return -EINVAL; | |
1796 | } | |
1797 | ||
1798 | ctlr = readl_relaxed(its_base + GITS_CTLR); | |
1799 | ctlr &= ~GITS_CTLR_ITS_NUMBER; | |
1800 | ctlr |= its_number << GITS_CTLR_ITS_NUMBER_SHIFT; | |
1801 | writel_relaxed(ctlr, its_base + GITS_CTLR); | |
1802 | ctlr = readl_relaxed(its_base + GITS_CTLR); | |
1803 | if ((ctlr & GITS_CTLR_ITS_NUMBER) != (its_number << GITS_CTLR_ITS_NUMBER_SHIFT)) { | |
1804 | its_number = ctlr & GITS_CTLR_ITS_NUMBER; | |
1805 | its_number >>= GITS_CTLR_ITS_NUMBER_SHIFT; | |
1806 | } | |
1807 | ||
1808 | if (test_and_set_bit(its_number, &its_list_map)) { | |
1809 | pr_err("ITS@%pa: Duplicate ITSList entry %d\n", | |
1810 | &res->start, its_number); | |
1811 | return -EINVAL; | |
1812 | } | |
1813 | ||
1814 | return its_number; | |
1815 | } | |
1816 | ||
db40f0a7 TN |
1817 | static int __init its_probe_one(struct resource *res, |
1818 | struct fwnode_handle *handle, int numa_node) | |
4c21f3c2 | 1819 | { |
4c21f3c2 MZ |
1820 | struct its_node *its; |
1821 | void __iomem *its_base; | |
3dfa576b MZ |
1822 | u32 val, ctlr; |
1823 | u64 baser, tmp, typer; | |
4c21f3c2 MZ |
1824 | int err; |
1825 | ||
db40f0a7 | 1826 | its_base = ioremap(res->start, resource_size(res)); |
4c21f3c2 | 1827 | if (!its_base) { |
db40f0a7 | 1828 | pr_warn("ITS@%pa: Unable to map ITS registers\n", &res->start); |
4c21f3c2 MZ |
1829 | return -ENOMEM; |
1830 | } | |
1831 | ||
1832 | val = readl_relaxed(its_base + GITS_PIDR2) & GIC_PIDR2_ARCH_MASK; | |
1833 | if (val != 0x30 && val != 0x40) { | |
db40f0a7 | 1834 | pr_warn("ITS@%pa: No ITS detected, giving up\n", &res->start); |
4c21f3c2 MZ |
1835 | err = -ENODEV; |
1836 | goto out_unmap; | |
1837 | } | |
1838 | ||
4559fbb3 YW |
1839 | err = its_force_quiescent(its_base); |
1840 | if (err) { | |
db40f0a7 | 1841 | pr_warn("ITS@%pa: Failed to quiesce, giving up\n", &res->start); |
4559fbb3 YW |
1842 | goto out_unmap; |
1843 | } | |
1844 | ||
db40f0a7 | 1845 | pr_info("ITS %pR\n", res); |
4c21f3c2 MZ |
1846 | |
1847 | its = kzalloc(sizeof(*its), GFP_KERNEL); | |
1848 | if (!its) { | |
1849 | err = -ENOMEM; | |
1850 | goto out_unmap; | |
1851 | } | |
1852 | ||
1853 | raw_spin_lock_init(&its->lock); | |
1854 | INIT_LIST_HEAD(&its->entry); | |
1855 | INIT_LIST_HEAD(&its->its_device_list); | |
3dfa576b | 1856 | typer = gic_read_typer(its_base + GITS_TYPER); |
4c21f3c2 | 1857 | its->base = its_base; |
db40f0a7 | 1858 | its->phys_base = res->start; |
3dfa576b MZ |
1859 | its->ite_size = GITS_TYPER_ITT_ENTRY_SIZE(typer); |
1860 | its->is_v4 = !!(typer & GITS_TYPER_VLPIS); | |
1861 | if (its->is_v4) { | |
1862 | if (!(typer & GITS_TYPER_VMOVP)) { | |
1863 | err = its_compute_its_list_map(res, its_base); | |
1864 | if (err < 0) | |
1865 | goto out_free_its; | |
1866 | ||
1867 | pr_info("ITS@%pa: Using ITS number %d\n", | |
1868 | &res->start, err); | |
1869 | } else { | |
1870 | pr_info("ITS@%pa: Single VMOVP capable\n", &res->start); | |
1871 | } | |
1872 | } | |
1873 | ||
db40f0a7 | 1874 | its->numa_node = numa_node; |
4c21f3c2 | 1875 | |
5bc13c2c RR |
1876 | its->cmd_base = (void *)__get_free_pages(GFP_KERNEL | __GFP_ZERO, |
1877 | get_order(ITS_CMD_QUEUE_SZ)); | |
4c21f3c2 MZ |
1878 | if (!its->cmd_base) { |
1879 | err = -ENOMEM; | |
1880 | goto out_free_its; | |
1881 | } | |
1882 | its->cmd_write = its->cmd_base; | |
1883 | ||
67510cca RR |
1884 | its_enable_quirks(its); |
1885 | ||
0e0b0f69 | 1886 | err = its_alloc_tables(its); |
4c21f3c2 MZ |
1887 | if (err) |
1888 | goto out_free_cmd; | |
1889 | ||
1890 | err = its_alloc_collections(its); | |
1891 | if (err) | |
1892 | goto out_free_tables; | |
1893 | ||
1894 | baser = (virt_to_phys(its->cmd_base) | | |
2fd632a0 | 1895 | GITS_CBASER_RaWaWb | |
4c21f3c2 MZ |
1896 | GITS_CBASER_InnerShareable | |
1897 | (ITS_CMD_QUEUE_SZ / SZ_4K - 1) | | |
1898 | GITS_CBASER_VALID); | |
1899 | ||
0968a619 VM |
1900 | gits_write_cbaser(baser, its->base + GITS_CBASER); |
1901 | tmp = gits_read_cbaser(its->base + GITS_CBASER); | |
4c21f3c2 | 1902 | |
4ad3e363 | 1903 | if ((tmp ^ baser) & GITS_CBASER_SHAREABILITY_MASK) { |
241a386c MZ |
1904 | if (!(tmp & GITS_CBASER_SHAREABILITY_MASK)) { |
1905 | /* | |
1906 | * The HW reports non-shareable, we must | |
1907 | * remove the cacheability attributes as | |
1908 | * well. | |
1909 | */ | |
1910 | baser &= ~(GITS_CBASER_SHAREABILITY_MASK | | |
1911 | GITS_CBASER_CACHEABILITY_MASK); | |
1912 | baser |= GITS_CBASER_nC; | |
0968a619 | 1913 | gits_write_cbaser(baser, its->base + GITS_CBASER); |
241a386c | 1914 | } |
4c21f3c2 MZ |
1915 | pr_info("ITS: using cache flushing for cmd queue\n"); |
1916 | its->flags |= ITS_FLAGS_CMDQ_NEEDS_FLUSHING; | |
1917 | } | |
1918 | ||
0968a619 | 1919 | gits_write_cwriter(0, its->base + GITS_CWRITER); |
3dfa576b MZ |
1920 | ctlr = readl_relaxed(its->base + GITS_CTLR); |
1921 | writel_relaxed(ctlr | GITS_CTLR_ENABLE, its->base + GITS_CTLR); | |
241a386c | 1922 | |
db40f0a7 | 1923 | err = its_init_domain(handle, its); |
d14ae5e6 TN |
1924 | if (err) |
1925 | goto out_free_tables; | |
4c21f3c2 MZ |
1926 | |
1927 | spin_lock(&its_lock); | |
1928 | list_add(&its->entry, &its_nodes); | |
1929 | spin_unlock(&its_lock); | |
1930 | ||
1931 | return 0; | |
1932 | ||
4c21f3c2 MZ |
1933 | out_free_tables: |
1934 | its_free_tables(its); | |
1935 | out_free_cmd: | |
5bc13c2c | 1936 | free_pages((unsigned long)its->cmd_base, get_order(ITS_CMD_QUEUE_SZ)); |
4c21f3c2 MZ |
1937 | out_free_its: |
1938 | kfree(its); | |
1939 | out_unmap: | |
1940 | iounmap(its_base); | |
db40f0a7 | 1941 | pr_err("ITS@%pa: failed probing (%d)\n", &res->start, err); |
4c21f3c2 MZ |
1942 | return err; |
1943 | } | |
1944 | ||
1945 | static bool gic_rdists_supports_plpis(void) | |
1946 | { | |
589ce5f4 | 1947 | return !!(gic_read_typer(gic_data_rdist_rd_base() + GICR_TYPER) & GICR_TYPER_PLPIS); |
4c21f3c2 MZ |
1948 | } |
1949 | ||
1950 | int its_cpu_init(void) | |
1951 | { | |
4c21f3c2 | 1952 | if (!list_empty(&its_nodes)) { |
16acae72 VM |
1953 | if (!gic_rdists_supports_plpis()) { |
1954 | pr_info("CPU%d: LPIs not supported\n", smp_processor_id()); | |
1955 | return -ENXIO; | |
1956 | } | |
4c21f3c2 MZ |
1957 | its_cpu_init_lpis(); |
1958 | its_cpu_init_collection(); | |
1959 | } | |
1960 | ||
1961 | return 0; | |
1962 | } | |
1963 | ||
935bba7c | 1964 | static const struct of_device_id its_device_id[] = { |
4c21f3c2 MZ |
1965 | { .compatible = "arm,gic-v3-its", }, |
1966 | {}, | |
1967 | }; | |
1968 | ||
db40f0a7 | 1969 | static int __init its_of_probe(struct device_node *node) |
4c21f3c2 MZ |
1970 | { |
1971 | struct device_node *np; | |
db40f0a7 | 1972 | struct resource res; |
4c21f3c2 MZ |
1973 | |
1974 | for (np = of_find_matching_node(node, its_device_id); np; | |
1975 | np = of_find_matching_node(np, its_device_id)) { | |
d14ae5e6 | 1976 | if (!of_property_read_bool(np, "msi-controller")) { |
e81f54c6 RH |
1977 | pr_warn("%pOF: no msi-controller property, ITS ignored\n", |
1978 | np); | |
d14ae5e6 TN |
1979 | continue; |
1980 | } | |
1981 | ||
db40f0a7 | 1982 | if (of_address_to_resource(np, 0, &res)) { |
e81f54c6 | 1983 | pr_warn("%pOF: no regs?\n", np); |
db40f0a7 TN |
1984 | continue; |
1985 | } | |
1986 | ||
1987 | its_probe_one(&res, &np->fwnode, of_node_to_nid(np)); | |
4c21f3c2 | 1988 | } |
db40f0a7 TN |
1989 | return 0; |
1990 | } | |
1991 | ||
3f010cf1 TN |
1992 | #ifdef CONFIG_ACPI |
1993 | ||
1994 | #define ACPI_GICV3_ITS_MEM_SIZE (SZ_128K) | |
1995 | ||
dbd2b826 GK |
1996 | #if defined(CONFIG_ACPI_NUMA) && (ACPI_CA_VERSION >= 0x20170531) |
1997 | struct its_srat_map { | |
1998 | /* numa node id */ | |
1999 | u32 numa_node; | |
2000 | /* GIC ITS ID */ | |
2001 | u32 its_id; | |
2002 | }; | |
2003 | ||
2004 | static struct its_srat_map its_srat_maps[MAX_NUMNODES] __initdata; | |
2005 | static int its_in_srat __initdata; | |
2006 | ||
2007 | static int __init acpi_get_its_numa_node(u32 its_id) | |
2008 | { | |
2009 | int i; | |
2010 | ||
2011 | for (i = 0; i < its_in_srat; i++) { | |
2012 | if (its_id == its_srat_maps[i].its_id) | |
2013 | return its_srat_maps[i].numa_node; | |
2014 | } | |
2015 | return NUMA_NO_NODE; | |
2016 | } | |
2017 | ||
2018 | static int __init gic_acpi_parse_srat_its(struct acpi_subtable_header *header, | |
2019 | const unsigned long end) | |
2020 | { | |
2021 | int node; | |
2022 | struct acpi_srat_gic_its_affinity *its_affinity; | |
2023 | ||
2024 | its_affinity = (struct acpi_srat_gic_its_affinity *)header; | |
2025 | if (!its_affinity) | |
2026 | return -EINVAL; | |
2027 | ||
2028 | if (its_affinity->header.length < sizeof(*its_affinity)) { | |
2029 | pr_err("SRAT: Invalid header length %d in ITS affinity\n", | |
2030 | its_affinity->header.length); | |
2031 | return -EINVAL; | |
2032 | } | |
2033 | ||
2034 | if (its_in_srat >= MAX_NUMNODES) { | |
2035 | pr_err("SRAT: ITS affinity exceeding max count[%d]\n", | |
2036 | MAX_NUMNODES); | |
2037 | return -EINVAL; | |
2038 | } | |
2039 | ||
2040 | node = acpi_map_pxm_to_node(its_affinity->proximity_domain); | |
2041 | ||
2042 | if (node == NUMA_NO_NODE || node >= MAX_NUMNODES) { | |
2043 | pr_err("SRAT: Invalid NUMA node %d in ITS affinity\n", node); | |
2044 | return 0; | |
2045 | } | |
2046 | ||
2047 | its_srat_maps[its_in_srat].numa_node = node; | |
2048 | its_srat_maps[its_in_srat].its_id = its_affinity->its_id; | |
2049 | its_in_srat++; | |
2050 | pr_info("SRAT: PXM %d -> ITS %d -> Node %d\n", | |
2051 | its_affinity->proximity_domain, its_affinity->its_id, node); | |
2052 | ||
2053 | return 0; | |
2054 | } | |
2055 | ||
2056 | static void __init acpi_table_parse_srat_its(void) | |
2057 | { | |
2058 | acpi_table_parse_entries(ACPI_SIG_SRAT, | |
2059 | sizeof(struct acpi_table_srat), | |
2060 | ACPI_SRAT_TYPE_GIC_ITS_AFFINITY, | |
2061 | gic_acpi_parse_srat_its, 0); | |
2062 | } | |
2063 | #else | |
2064 | static void __init acpi_table_parse_srat_its(void) { } | |
2065 | static int __init acpi_get_its_numa_node(u32 its_id) { return NUMA_NO_NODE; } | |
2066 | #endif | |
2067 | ||
3f010cf1 TN |
2068 | static int __init gic_acpi_parse_madt_its(struct acpi_subtable_header *header, |
2069 | const unsigned long end) | |
2070 | { | |
2071 | struct acpi_madt_generic_translator *its_entry; | |
2072 | struct fwnode_handle *dom_handle; | |
2073 | struct resource res; | |
2074 | int err; | |
2075 | ||
2076 | its_entry = (struct acpi_madt_generic_translator *)header; | |
2077 | memset(&res, 0, sizeof(res)); | |
2078 | res.start = its_entry->base_address; | |
2079 | res.end = its_entry->base_address + ACPI_GICV3_ITS_MEM_SIZE - 1; | |
2080 | res.flags = IORESOURCE_MEM; | |
2081 | ||
2082 | dom_handle = irq_domain_alloc_fwnode((void *)its_entry->base_address); | |
2083 | if (!dom_handle) { | |
2084 | pr_err("ITS@%pa: Unable to allocate GICv3 ITS domain token\n", | |
2085 | &res.start); | |
2086 | return -ENOMEM; | |
2087 | } | |
2088 | ||
2089 | err = iort_register_domain_token(its_entry->translation_id, dom_handle); | |
2090 | if (err) { | |
2091 | pr_err("ITS@%pa: Unable to register GICv3 ITS domain token (ITS ID %d) to IORT\n", | |
2092 | &res.start, its_entry->translation_id); | |
2093 | goto dom_err; | |
2094 | } | |
2095 | ||
dbd2b826 GK |
2096 | err = its_probe_one(&res, dom_handle, |
2097 | acpi_get_its_numa_node(its_entry->translation_id)); | |
3f010cf1 TN |
2098 | if (!err) |
2099 | return 0; | |
2100 | ||
2101 | iort_deregister_domain_token(its_entry->translation_id); | |
2102 | dom_err: | |
2103 | irq_domain_free_fwnode(dom_handle); | |
2104 | return err; | |
2105 | } | |
2106 | ||
2107 | static void __init its_acpi_probe(void) | |
2108 | { | |
dbd2b826 | 2109 | acpi_table_parse_srat_its(); |
3f010cf1 TN |
2110 | acpi_table_parse_madt(ACPI_MADT_TYPE_GENERIC_TRANSLATOR, |
2111 | gic_acpi_parse_madt_its, 0); | |
2112 | } | |
2113 | #else | |
2114 | static void __init its_acpi_probe(void) { } | |
2115 | #endif | |
2116 | ||
db40f0a7 TN |
2117 | int __init its_init(struct fwnode_handle *handle, struct rdists *rdists, |
2118 | struct irq_domain *parent_domain) | |
2119 | { | |
2120 | struct device_node *of_node; | |
2121 | ||
2122 | its_parent = parent_domain; | |
2123 | of_node = to_of_node(handle); | |
2124 | if (of_node) | |
2125 | its_of_probe(of_node); | |
2126 | else | |
3f010cf1 | 2127 | its_acpi_probe(); |
4c21f3c2 MZ |
2128 | |
2129 | if (list_empty(&its_nodes)) { | |
2130 | pr_warn("ITS: No ITS available, not enabling LPIs\n"); | |
2131 | return -ENXIO; | |
2132 | } | |
2133 | ||
2134 | gic_rdists = rdists; | |
6c31e123 | 2135 | return its_alloc_lpi_tables(); |
4c21f3c2 | 2136 | } |