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cc2d3216 | 1 | /* |
d7276b80 | 2 | * Copyright (C) 2013-2017 ARM Limited, All Rights Reserved. |
cc2d3216 MZ |
3 | * Author: Marc Zyngier <marc.zyngier@arm.com> |
4 | * | |
5 | * This program is free software; you can redistribute it and/or modify | |
6 | * it under the terms of the GNU General Public License version 2 as | |
7 | * published by the Free Software Foundation. | |
8 | * | |
9 | * This program is distributed in the hope that it will be useful, | |
10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
12 | * GNU General Public License for more details. | |
13 | * | |
14 | * You should have received a copy of the GNU General Public License | |
15 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | |
16 | */ | |
17 | ||
3f010cf1 | 18 | #include <linux/acpi.h> |
8d3554b8 | 19 | #include <linux/acpi_iort.h> |
cc2d3216 MZ |
20 | #include <linux/bitmap.h> |
21 | #include <linux/cpu.h> | |
22 | #include <linux/delay.h> | |
44bb7e24 | 23 | #include <linux/dma-iommu.h> |
cc2d3216 | 24 | #include <linux/interrupt.h> |
3f010cf1 | 25 | #include <linux/irqdomain.h> |
cc2d3216 MZ |
26 | #include <linux/log2.h> |
27 | #include <linux/mm.h> | |
28 | #include <linux/msi.h> | |
29 | #include <linux/of.h> | |
30 | #include <linux/of_address.h> | |
31 | #include <linux/of_irq.h> | |
32 | #include <linux/of_pci.h> | |
33 | #include <linux/of_platform.h> | |
34 | #include <linux/percpu.h> | |
35 | #include <linux/slab.h> | |
36 | ||
41a83e06 | 37 | #include <linux/irqchip.h> |
cc2d3216 | 38 | #include <linux/irqchip/arm-gic-v3.h> |
c808eea8 | 39 | #include <linux/irqchip/arm-gic-v4.h> |
cc2d3216 | 40 | |
cc2d3216 MZ |
41 | #include <asm/cputype.h> |
42 | #include <asm/exception.h> | |
43 | ||
67510cca RR |
44 | #include "irq-gic-common.h" |
45 | ||
94100970 RR |
46 | #define ITS_FLAGS_CMDQ_NEEDS_FLUSHING (1ULL << 0) |
47 | #define ITS_FLAGS_WORKAROUND_CAVIUM_22375 (1ULL << 1) | |
fbf8f40e | 48 | #define ITS_FLAGS_WORKAROUND_CAVIUM_23144 (1ULL << 2) |
cc2d3216 | 49 | |
c48ed51c MZ |
50 | #define RDIST_FLAGS_PROPBASE_NEEDS_FLUSHING (1 << 0) |
51 | ||
a13b0404 MZ |
52 | static u32 lpi_id_bits; |
53 | ||
54 | /* | |
55 | * We allocate memory for PROPBASE to cover 2 ^ lpi_id_bits LPIs to | |
56 | * deal with (one configuration byte per interrupt). PENDBASE has to | |
57 | * be 64kB aligned (one bit per LPI, plus 8192 bits for SPI/PPI/SGI). | |
58 | */ | |
59 | #define LPI_NRBITS lpi_id_bits | |
60 | #define LPI_PROPBASE_SZ ALIGN(BIT(LPI_NRBITS), SZ_64K) | |
61 | #define LPI_PENDBASE_SZ ALIGN(BIT(LPI_NRBITS) / 8, SZ_64K) | |
62 | ||
63 | #define LPI_PROP_DEFAULT_PRIO 0xa0 | |
64 | ||
cc2d3216 MZ |
65 | /* |
66 | * Collection structure - just an ID, and a redistributor address to | |
67 | * ping. We use one per CPU as a bag of interrupts assigned to this | |
68 | * CPU. | |
69 | */ | |
70 | struct its_collection { | |
71 | u64 target_address; | |
72 | u16 col_id; | |
73 | }; | |
74 | ||
466b7d16 | 75 | /* |
9347359a SD |
76 | * The ITS_BASER structure - contains memory information, cached |
77 | * value of BASER register configuration and ITS page size. | |
466b7d16 SD |
78 | */ |
79 | struct its_baser { | |
80 | void *base; | |
81 | u64 val; | |
82 | u32 order; | |
9347359a | 83 | u32 psz; |
466b7d16 SD |
84 | }; |
85 | ||
cc2d3216 MZ |
86 | /* |
87 | * The ITS structure - contains most of the infrastructure, with the | |
841514ab MZ |
88 | * top-level MSI domain, the command queue, the collections, and the |
89 | * list of devices writing to it. | |
cc2d3216 MZ |
90 | */ |
91 | struct its_node { | |
92 | raw_spinlock_t lock; | |
93 | struct list_head entry; | |
cc2d3216 | 94 | void __iomem *base; |
db40f0a7 | 95 | phys_addr_t phys_base; |
cc2d3216 MZ |
96 | struct its_cmd_block *cmd_base; |
97 | struct its_cmd_block *cmd_write; | |
466b7d16 | 98 | struct its_baser tables[GITS_BASER_NR_REGS]; |
cc2d3216 MZ |
99 | struct its_collection *collections; |
100 | struct list_head its_device_list; | |
101 | u64 flags; | |
102 | u32 ite_size; | |
466b7d16 | 103 | u32 device_ids; |
fbf8f40e | 104 | int numa_node; |
3dfa576b | 105 | bool is_v4; |
cc2d3216 MZ |
106 | }; |
107 | ||
108 | #define ITS_ITT_ALIGN SZ_256 | |
109 | ||
2eca0d6c SD |
110 | /* Convert page order to size in bytes */ |
111 | #define PAGE_ORDER_TO_SIZE(o) (PAGE_SIZE << (o)) | |
112 | ||
591e5bec MZ |
113 | struct event_lpi_map { |
114 | unsigned long *lpi_map; | |
115 | u16 *col_map; | |
116 | irq_hw_number_t lpi_base; | |
117 | int nr_lpis; | |
d011e4e6 MZ |
118 | struct mutex vlpi_lock; |
119 | struct its_vm *vm; | |
120 | struct its_vlpi_map *vlpi_maps; | |
121 | int nr_vlpis; | |
591e5bec MZ |
122 | }; |
123 | ||
cc2d3216 | 124 | /* |
d011e4e6 MZ |
125 | * The ITS view of a device - belongs to an ITS, owns an interrupt |
126 | * translation table, and a list of interrupts. If it some of its | |
127 | * LPIs are injected into a guest (GICv4), the event_map.vm field | |
128 | * indicates which one. | |
cc2d3216 MZ |
129 | */ |
130 | struct its_device { | |
131 | struct list_head entry; | |
132 | struct its_node *its; | |
591e5bec | 133 | struct event_lpi_map event_map; |
cc2d3216 | 134 | void *itt; |
cc2d3216 MZ |
135 | u32 nr_ites; |
136 | u32 device_id; | |
137 | }; | |
138 | ||
1ac19ca6 MZ |
139 | static LIST_HEAD(its_nodes); |
140 | static DEFINE_SPINLOCK(its_lock); | |
1ac19ca6 | 141 | static struct rdists *gic_rdists; |
db40f0a7 | 142 | static struct irq_domain *its_parent; |
1ac19ca6 | 143 | |
3dfa576b MZ |
144 | /* |
145 | * We have a maximum number of 16 ITSs in the whole system if we're | |
146 | * using the ITSList mechanism | |
147 | */ | |
148 | #define ITS_LIST_MAX 16 | |
149 | ||
150 | static unsigned long its_list_map; | |
151 | ||
1ac19ca6 MZ |
152 | #define gic_data_rdist() (raw_cpu_ptr(gic_rdists->rdist)) |
153 | #define gic_data_rdist_rd_base() (gic_data_rdist()->rd_base) | |
154 | ||
591e5bec MZ |
155 | static struct its_collection *dev_event_to_col(struct its_device *its_dev, |
156 | u32 event) | |
157 | { | |
158 | struct its_node *its = its_dev->its; | |
159 | ||
160 | return its->collections + its_dev->event_map.col_map[event]; | |
161 | } | |
162 | ||
cc2d3216 MZ |
163 | /* |
164 | * ITS command descriptors - parameters to be encoded in a command | |
165 | * block. | |
166 | */ | |
167 | struct its_cmd_desc { | |
168 | union { | |
169 | struct { | |
170 | struct its_device *dev; | |
171 | u32 event_id; | |
172 | } its_inv_cmd; | |
173 | ||
8d85dced MZ |
174 | struct { |
175 | struct its_device *dev; | |
176 | u32 event_id; | |
177 | } its_clear_cmd; | |
178 | ||
cc2d3216 MZ |
179 | struct { |
180 | struct its_device *dev; | |
181 | u32 event_id; | |
182 | } its_int_cmd; | |
183 | ||
184 | struct { | |
185 | struct its_device *dev; | |
186 | int valid; | |
187 | } its_mapd_cmd; | |
188 | ||
189 | struct { | |
190 | struct its_collection *col; | |
191 | int valid; | |
192 | } its_mapc_cmd; | |
193 | ||
194 | struct { | |
195 | struct its_device *dev; | |
196 | u32 phys_id; | |
197 | u32 event_id; | |
6a25ad3a | 198 | } its_mapti_cmd; |
cc2d3216 MZ |
199 | |
200 | struct { | |
201 | struct its_device *dev; | |
202 | struct its_collection *col; | |
591e5bec | 203 | u32 event_id; |
cc2d3216 MZ |
204 | } its_movi_cmd; |
205 | ||
206 | struct { | |
207 | struct its_device *dev; | |
208 | u32 event_id; | |
209 | } its_discard_cmd; | |
210 | ||
211 | struct { | |
212 | struct its_collection *col; | |
213 | } its_invall_cmd; | |
d011e4e6 MZ |
214 | |
215 | struct { | |
216 | struct its_vpe *vpe; | |
217 | struct its_device *dev; | |
218 | u32 virt_id; | |
219 | u32 event_id; | |
220 | bool db_enabled; | |
221 | } its_vmapti_cmd; | |
222 | ||
223 | struct { | |
224 | struct its_vpe *vpe; | |
225 | struct its_device *dev; | |
226 | u32 event_id; | |
227 | bool db_enabled; | |
228 | } its_vmovi_cmd; | |
cc2d3216 MZ |
229 | }; |
230 | }; | |
231 | ||
232 | /* | |
233 | * The ITS command block, which is what the ITS actually parses. | |
234 | */ | |
235 | struct its_cmd_block { | |
236 | u64 raw_cmd[4]; | |
237 | }; | |
238 | ||
239 | #define ITS_CMD_QUEUE_SZ SZ_64K | |
240 | #define ITS_CMD_QUEUE_NR_ENTRIES (ITS_CMD_QUEUE_SZ / sizeof(struct its_cmd_block)) | |
241 | ||
242 | typedef struct its_collection *(*its_cmd_builder_t)(struct its_cmd_block *, | |
243 | struct its_cmd_desc *); | |
244 | ||
d011e4e6 MZ |
245 | typedef struct its_vpe *(*its_cmd_vbuilder_t)(struct its_cmd_block *, |
246 | struct its_cmd_desc *); | |
247 | ||
4d36f136 MZ |
248 | static void its_mask_encode(u64 *raw_cmd, u64 val, int h, int l) |
249 | { | |
250 | u64 mask = GENMASK_ULL(h, l); | |
251 | *raw_cmd &= ~mask; | |
252 | *raw_cmd |= (val << l) & mask; | |
253 | } | |
254 | ||
cc2d3216 MZ |
255 | static void its_encode_cmd(struct its_cmd_block *cmd, u8 cmd_nr) |
256 | { | |
4d36f136 | 257 | its_mask_encode(&cmd->raw_cmd[0], cmd_nr, 7, 0); |
cc2d3216 MZ |
258 | } |
259 | ||
260 | static void its_encode_devid(struct its_cmd_block *cmd, u32 devid) | |
261 | { | |
4d36f136 | 262 | its_mask_encode(&cmd->raw_cmd[0], devid, 63, 32); |
cc2d3216 MZ |
263 | } |
264 | ||
265 | static void its_encode_event_id(struct its_cmd_block *cmd, u32 id) | |
266 | { | |
4d36f136 | 267 | its_mask_encode(&cmd->raw_cmd[1], id, 31, 0); |
cc2d3216 MZ |
268 | } |
269 | ||
270 | static void its_encode_phys_id(struct its_cmd_block *cmd, u32 phys_id) | |
271 | { | |
4d36f136 | 272 | its_mask_encode(&cmd->raw_cmd[1], phys_id, 63, 32); |
cc2d3216 MZ |
273 | } |
274 | ||
275 | static void its_encode_size(struct its_cmd_block *cmd, u8 size) | |
276 | { | |
4d36f136 | 277 | its_mask_encode(&cmd->raw_cmd[1], size, 4, 0); |
cc2d3216 MZ |
278 | } |
279 | ||
280 | static void its_encode_itt(struct its_cmd_block *cmd, u64 itt_addr) | |
281 | { | |
4d36f136 | 282 | its_mask_encode(&cmd->raw_cmd[2], itt_addr >> 8, 50, 8); |
cc2d3216 MZ |
283 | } |
284 | ||
285 | static void its_encode_valid(struct its_cmd_block *cmd, int valid) | |
286 | { | |
4d36f136 | 287 | its_mask_encode(&cmd->raw_cmd[2], !!valid, 63, 63); |
cc2d3216 MZ |
288 | } |
289 | ||
290 | static void its_encode_target(struct its_cmd_block *cmd, u64 target_addr) | |
291 | { | |
4d36f136 | 292 | its_mask_encode(&cmd->raw_cmd[2], target_addr >> 16, 50, 16); |
cc2d3216 MZ |
293 | } |
294 | ||
295 | static void its_encode_collection(struct its_cmd_block *cmd, u16 col) | |
296 | { | |
4d36f136 | 297 | its_mask_encode(&cmd->raw_cmd[2], col, 15, 0); |
cc2d3216 MZ |
298 | } |
299 | ||
d011e4e6 MZ |
300 | static void its_encode_vpeid(struct its_cmd_block *cmd, u16 vpeid) |
301 | { | |
302 | its_mask_encode(&cmd->raw_cmd[1], vpeid, 47, 32); | |
303 | } | |
304 | ||
305 | static void its_encode_virt_id(struct its_cmd_block *cmd, u32 virt_id) | |
306 | { | |
307 | its_mask_encode(&cmd->raw_cmd[2], virt_id, 31, 0); | |
308 | } | |
309 | ||
310 | static void its_encode_db_phys_id(struct its_cmd_block *cmd, u32 db_phys_id) | |
311 | { | |
312 | its_mask_encode(&cmd->raw_cmd[2], db_phys_id, 63, 32); | |
313 | } | |
314 | ||
315 | static void its_encode_db_valid(struct its_cmd_block *cmd, bool db_valid) | |
316 | { | |
317 | its_mask_encode(&cmd->raw_cmd[2], db_valid, 0, 0); | |
318 | } | |
319 | ||
cc2d3216 MZ |
320 | static inline void its_fixup_cmd(struct its_cmd_block *cmd) |
321 | { | |
322 | /* Let's fixup BE commands */ | |
323 | cmd->raw_cmd[0] = cpu_to_le64(cmd->raw_cmd[0]); | |
324 | cmd->raw_cmd[1] = cpu_to_le64(cmd->raw_cmd[1]); | |
325 | cmd->raw_cmd[2] = cpu_to_le64(cmd->raw_cmd[2]); | |
326 | cmd->raw_cmd[3] = cpu_to_le64(cmd->raw_cmd[3]); | |
327 | } | |
328 | ||
329 | static struct its_collection *its_build_mapd_cmd(struct its_cmd_block *cmd, | |
330 | struct its_cmd_desc *desc) | |
331 | { | |
332 | unsigned long itt_addr; | |
c8481267 | 333 | u8 size = ilog2(desc->its_mapd_cmd.dev->nr_ites); |
cc2d3216 MZ |
334 | |
335 | itt_addr = virt_to_phys(desc->its_mapd_cmd.dev->itt); | |
336 | itt_addr = ALIGN(itt_addr, ITS_ITT_ALIGN); | |
337 | ||
338 | its_encode_cmd(cmd, GITS_CMD_MAPD); | |
339 | its_encode_devid(cmd, desc->its_mapd_cmd.dev->device_id); | |
340 | its_encode_size(cmd, size - 1); | |
341 | its_encode_itt(cmd, itt_addr); | |
342 | its_encode_valid(cmd, desc->its_mapd_cmd.valid); | |
343 | ||
344 | its_fixup_cmd(cmd); | |
345 | ||
591e5bec | 346 | return NULL; |
cc2d3216 MZ |
347 | } |
348 | ||
349 | static struct its_collection *its_build_mapc_cmd(struct its_cmd_block *cmd, | |
350 | struct its_cmd_desc *desc) | |
351 | { | |
352 | its_encode_cmd(cmd, GITS_CMD_MAPC); | |
353 | its_encode_collection(cmd, desc->its_mapc_cmd.col->col_id); | |
354 | its_encode_target(cmd, desc->its_mapc_cmd.col->target_address); | |
355 | its_encode_valid(cmd, desc->its_mapc_cmd.valid); | |
356 | ||
357 | its_fixup_cmd(cmd); | |
358 | ||
359 | return desc->its_mapc_cmd.col; | |
360 | } | |
361 | ||
6a25ad3a | 362 | static struct its_collection *its_build_mapti_cmd(struct its_cmd_block *cmd, |
cc2d3216 MZ |
363 | struct its_cmd_desc *desc) |
364 | { | |
591e5bec MZ |
365 | struct its_collection *col; |
366 | ||
6a25ad3a MZ |
367 | col = dev_event_to_col(desc->its_mapti_cmd.dev, |
368 | desc->its_mapti_cmd.event_id); | |
591e5bec | 369 | |
6a25ad3a MZ |
370 | its_encode_cmd(cmd, GITS_CMD_MAPTI); |
371 | its_encode_devid(cmd, desc->its_mapti_cmd.dev->device_id); | |
372 | its_encode_event_id(cmd, desc->its_mapti_cmd.event_id); | |
373 | its_encode_phys_id(cmd, desc->its_mapti_cmd.phys_id); | |
591e5bec | 374 | its_encode_collection(cmd, col->col_id); |
cc2d3216 MZ |
375 | |
376 | its_fixup_cmd(cmd); | |
377 | ||
591e5bec | 378 | return col; |
cc2d3216 MZ |
379 | } |
380 | ||
381 | static struct its_collection *its_build_movi_cmd(struct its_cmd_block *cmd, | |
382 | struct its_cmd_desc *desc) | |
383 | { | |
591e5bec MZ |
384 | struct its_collection *col; |
385 | ||
386 | col = dev_event_to_col(desc->its_movi_cmd.dev, | |
387 | desc->its_movi_cmd.event_id); | |
388 | ||
cc2d3216 MZ |
389 | its_encode_cmd(cmd, GITS_CMD_MOVI); |
390 | its_encode_devid(cmd, desc->its_movi_cmd.dev->device_id); | |
591e5bec | 391 | its_encode_event_id(cmd, desc->its_movi_cmd.event_id); |
cc2d3216 MZ |
392 | its_encode_collection(cmd, desc->its_movi_cmd.col->col_id); |
393 | ||
394 | its_fixup_cmd(cmd); | |
395 | ||
591e5bec | 396 | return col; |
cc2d3216 MZ |
397 | } |
398 | ||
399 | static struct its_collection *its_build_discard_cmd(struct its_cmd_block *cmd, | |
400 | struct its_cmd_desc *desc) | |
401 | { | |
591e5bec MZ |
402 | struct its_collection *col; |
403 | ||
404 | col = dev_event_to_col(desc->its_discard_cmd.dev, | |
405 | desc->its_discard_cmd.event_id); | |
406 | ||
cc2d3216 MZ |
407 | its_encode_cmd(cmd, GITS_CMD_DISCARD); |
408 | its_encode_devid(cmd, desc->its_discard_cmd.dev->device_id); | |
409 | its_encode_event_id(cmd, desc->its_discard_cmd.event_id); | |
410 | ||
411 | its_fixup_cmd(cmd); | |
412 | ||
591e5bec | 413 | return col; |
cc2d3216 MZ |
414 | } |
415 | ||
416 | static struct its_collection *its_build_inv_cmd(struct its_cmd_block *cmd, | |
417 | struct its_cmd_desc *desc) | |
418 | { | |
591e5bec MZ |
419 | struct its_collection *col; |
420 | ||
421 | col = dev_event_to_col(desc->its_inv_cmd.dev, | |
422 | desc->its_inv_cmd.event_id); | |
423 | ||
cc2d3216 MZ |
424 | its_encode_cmd(cmd, GITS_CMD_INV); |
425 | its_encode_devid(cmd, desc->its_inv_cmd.dev->device_id); | |
426 | its_encode_event_id(cmd, desc->its_inv_cmd.event_id); | |
427 | ||
428 | its_fixup_cmd(cmd); | |
429 | ||
591e5bec | 430 | return col; |
cc2d3216 MZ |
431 | } |
432 | ||
8d85dced MZ |
433 | static struct its_collection *its_build_int_cmd(struct its_cmd_block *cmd, |
434 | struct its_cmd_desc *desc) | |
435 | { | |
436 | struct its_collection *col; | |
437 | ||
438 | col = dev_event_to_col(desc->its_int_cmd.dev, | |
439 | desc->its_int_cmd.event_id); | |
440 | ||
441 | its_encode_cmd(cmd, GITS_CMD_INT); | |
442 | its_encode_devid(cmd, desc->its_int_cmd.dev->device_id); | |
443 | its_encode_event_id(cmd, desc->its_int_cmd.event_id); | |
444 | ||
445 | its_fixup_cmd(cmd); | |
446 | ||
447 | return col; | |
448 | } | |
449 | ||
450 | static struct its_collection *its_build_clear_cmd(struct its_cmd_block *cmd, | |
451 | struct its_cmd_desc *desc) | |
452 | { | |
453 | struct its_collection *col; | |
454 | ||
455 | col = dev_event_to_col(desc->its_clear_cmd.dev, | |
456 | desc->its_clear_cmd.event_id); | |
457 | ||
458 | its_encode_cmd(cmd, GITS_CMD_CLEAR); | |
459 | its_encode_devid(cmd, desc->its_clear_cmd.dev->device_id); | |
460 | its_encode_event_id(cmd, desc->its_clear_cmd.event_id); | |
461 | ||
462 | its_fixup_cmd(cmd); | |
463 | ||
464 | return col; | |
465 | } | |
466 | ||
cc2d3216 MZ |
467 | static struct its_collection *its_build_invall_cmd(struct its_cmd_block *cmd, |
468 | struct its_cmd_desc *desc) | |
469 | { | |
470 | its_encode_cmd(cmd, GITS_CMD_INVALL); | |
471 | its_encode_collection(cmd, desc->its_mapc_cmd.col->col_id); | |
472 | ||
473 | its_fixup_cmd(cmd); | |
474 | ||
475 | return NULL; | |
476 | } | |
477 | ||
d011e4e6 MZ |
478 | static struct its_vpe *its_build_vmapti_cmd(struct its_cmd_block *cmd, |
479 | struct its_cmd_desc *desc) | |
480 | { | |
481 | u32 db; | |
482 | ||
483 | if (desc->its_vmapti_cmd.db_enabled) | |
484 | db = desc->its_vmapti_cmd.vpe->vpe_db_lpi; | |
485 | else | |
486 | db = 1023; | |
487 | ||
488 | its_encode_cmd(cmd, GITS_CMD_VMAPTI); | |
489 | its_encode_devid(cmd, desc->its_vmapti_cmd.dev->device_id); | |
490 | its_encode_vpeid(cmd, desc->its_vmapti_cmd.vpe->vpe_id); | |
491 | its_encode_event_id(cmd, desc->its_vmapti_cmd.event_id); | |
492 | its_encode_db_phys_id(cmd, db); | |
493 | its_encode_virt_id(cmd, desc->its_vmapti_cmd.virt_id); | |
494 | ||
495 | its_fixup_cmd(cmd); | |
496 | ||
497 | return desc->its_vmapti_cmd.vpe; | |
498 | } | |
499 | ||
500 | static struct its_vpe *its_build_vmovi_cmd(struct its_cmd_block *cmd, | |
501 | struct its_cmd_desc *desc) | |
502 | { | |
503 | u32 db; | |
504 | ||
505 | if (desc->its_vmovi_cmd.db_enabled) | |
506 | db = desc->its_vmovi_cmd.vpe->vpe_db_lpi; | |
507 | else | |
508 | db = 1023; | |
509 | ||
510 | its_encode_cmd(cmd, GITS_CMD_VMOVI); | |
511 | its_encode_devid(cmd, desc->its_vmovi_cmd.dev->device_id); | |
512 | its_encode_vpeid(cmd, desc->its_vmovi_cmd.vpe->vpe_id); | |
513 | its_encode_event_id(cmd, desc->its_vmovi_cmd.event_id); | |
514 | its_encode_db_phys_id(cmd, db); | |
515 | its_encode_db_valid(cmd, true); | |
516 | ||
517 | its_fixup_cmd(cmd); | |
518 | ||
519 | return desc->its_vmovi_cmd.vpe; | |
520 | } | |
521 | ||
cc2d3216 MZ |
522 | static u64 its_cmd_ptr_to_offset(struct its_node *its, |
523 | struct its_cmd_block *ptr) | |
524 | { | |
525 | return (ptr - its->cmd_base) * sizeof(*ptr); | |
526 | } | |
527 | ||
528 | static int its_queue_full(struct its_node *its) | |
529 | { | |
530 | int widx; | |
531 | int ridx; | |
532 | ||
533 | widx = its->cmd_write - its->cmd_base; | |
534 | ridx = readl_relaxed(its->base + GITS_CREADR) / sizeof(struct its_cmd_block); | |
535 | ||
536 | /* This is incredibly unlikely to happen, unless the ITS locks up. */ | |
537 | if (((widx + 1) % ITS_CMD_QUEUE_NR_ENTRIES) == ridx) | |
538 | return 1; | |
539 | ||
540 | return 0; | |
541 | } | |
542 | ||
543 | static struct its_cmd_block *its_allocate_entry(struct its_node *its) | |
544 | { | |
545 | struct its_cmd_block *cmd; | |
546 | u32 count = 1000000; /* 1s! */ | |
547 | ||
548 | while (its_queue_full(its)) { | |
549 | count--; | |
550 | if (!count) { | |
551 | pr_err_ratelimited("ITS queue not draining\n"); | |
552 | return NULL; | |
553 | } | |
554 | cpu_relax(); | |
555 | udelay(1); | |
556 | } | |
557 | ||
558 | cmd = its->cmd_write++; | |
559 | ||
560 | /* Handle queue wrapping */ | |
561 | if (its->cmd_write == (its->cmd_base + ITS_CMD_QUEUE_NR_ENTRIES)) | |
562 | its->cmd_write = its->cmd_base; | |
563 | ||
34d677a9 MZ |
564 | /* Clear command */ |
565 | cmd->raw_cmd[0] = 0; | |
566 | cmd->raw_cmd[1] = 0; | |
567 | cmd->raw_cmd[2] = 0; | |
568 | cmd->raw_cmd[3] = 0; | |
569 | ||
cc2d3216 MZ |
570 | return cmd; |
571 | } | |
572 | ||
573 | static struct its_cmd_block *its_post_commands(struct its_node *its) | |
574 | { | |
575 | u64 wr = its_cmd_ptr_to_offset(its, its->cmd_write); | |
576 | ||
577 | writel_relaxed(wr, its->base + GITS_CWRITER); | |
578 | ||
579 | return its->cmd_write; | |
580 | } | |
581 | ||
582 | static void its_flush_cmd(struct its_node *its, struct its_cmd_block *cmd) | |
583 | { | |
584 | /* | |
585 | * Make sure the commands written to memory are observable by | |
586 | * the ITS. | |
587 | */ | |
588 | if (its->flags & ITS_FLAGS_CMDQ_NEEDS_FLUSHING) | |
328191c0 | 589 | gic_flush_dcache_to_poc(cmd, sizeof(*cmd)); |
cc2d3216 MZ |
590 | else |
591 | dsb(ishst); | |
592 | } | |
593 | ||
594 | static void its_wait_for_range_completion(struct its_node *its, | |
595 | struct its_cmd_block *from, | |
596 | struct its_cmd_block *to) | |
597 | { | |
598 | u64 rd_idx, from_idx, to_idx; | |
599 | u32 count = 1000000; /* 1s! */ | |
600 | ||
601 | from_idx = its_cmd_ptr_to_offset(its, from); | |
602 | to_idx = its_cmd_ptr_to_offset(its, to); | |
603 | ||
604 | while (1) { | |
605 | rd_idx = readl_relaxed(its->base + GITS_CREADR); | |
9bdd8b1c MZ |
606 | |
607 | /* Direct case */ | |
608 | if (from_idx < to_idx && rd_idx >= to_idx) | |
609 | break; | |
610 | ||
611 | /* Wrapped case */ | |
612 | if (from_idx >= to_idx && rd_idx >= to_idx && rd_idx < from_idx) | |
cc2d3216 MZ |
613 | break; |
614 | ||
615 | count--; | |
616 | if (!count) { | |
617 | pr_err_ratelimited("ITS queue timeout\n"); | |
618 | return; | |
619 | } | |
620 | cpu_relax(); | |
621 | udelay(1); | |
622 | } | |
623 | } | |
624 | ||
e4f9094b MZ |
625 | /* Warning, macro hell follows */ |
626 | #define BUILD_SINGLE_CMD_FUNC(name, buildtype, synctype, buildfn) \ | |
627 | void name(struct its_node *its, \ | |
628 | buildtype builder, \ | |
629 | struct its_cmd_desc *desc) \ | |
630 | { \ | |
631 | struct its_cmd_block *cmd, *sync_cmd, *next_cmd; \ | |
632 | synctype *sync_obj; \ | |
633 | unsigned long flags; \ | |
634 | \ | |
635 | raw_spin_lock_irqsave(&its->lock, flags); \ | |
636 | \ | |
637 | cmd = its_allocate_entry(its); \ | |
638 | if (!cmd) { /* We're soooooo screewed... */ \ | |
639 | raw_spin_unlock_irqrestore(&its->lock, flags); \ | |
640 | return; \ | |
641 | } \ | |
642 | sync_obj = builder(cmd, desc); \ | |
643 | its_flush_cmd(its, cmd); \ | |
644 | \ | |
645 | if (sync_obj) { \ | |
646 | sync_cmd = its_allocate_entry(its); \ | |
647 | if (!sync_cmd) \ | |
648 | goto post; \ | |
649 | \ | |
650 | buildfn(sync_cmd, sync_obj); \ | |
651 | its_flush_cmd(its, sync_cmd); \ | |
652 | } \ | |
653 | \ | |
654 | post: \ | |
655 | next_cmd = its_post_commands(its); \ | |
656 | raw_spin_unlock_irqrestore(&its->lock, flags); \ | |
657 | \ | |
658 | its_wait_for_range_completion(its, cmd, next_cmd); \ | |
659 | } | |
cc2d3216 | 660 | |
e4f9094b MZ |
661 | static void its_build_sync_cmd(struct its_cmd_block *sync_cmd, |
662 | struct its_collection *sync_col) | |
663 | { | |
664 | its_encode_cmd(sync_cmd, GITS_CMD_SYNC); | |
665 | its_encode_target(sync_cmd, sync_col->target_address); | |
cc2d3216 | 666 | |
e4f9094b | 667 | its_fixup_cmd(sync_cmd); |
cc2d3216 MZ |
668 | } |
669 | ||
e4f9094b MZ |
670 | static BUILD_SINGLE_CMD_FUNC(its_send_single_command, its_cmd_builder_t, |
671 | struct its_collection, its_build_sync_cmd) | |
672 | ||
d011e4e6 MZ |
673 | static void its_build_vsync_cmd(struct its_cmd_block *sync_cmd, |
674 | struct its_vpe *sync_vpe) | |
675 | { | |
676 | its_encode_cmd(sync_cmd, GITS_CMD_VSYNC); | |
677 | its_encode_vpeid(sync_cmd, sync_vpe->vpe_id); | |
678 | ||
679 | its_fixup_cmd(sync_cmd); | |
680 | } | |
681 | ||
682 | static BUILD_SINGLE_CMD_FUNC(its_send_single_vcommand, its_cmd_vbuilder_t, | |
683 | struct its_vpe, its_build_vsync_cmd) | |
684 | ||
8d85dced MZ |
685 | static void its_send_int(struct its_device *dev, u32 event_id) |
686 | { | |
687 | struct its_cmd_desc desc; | |
688 | ||
689 | desc.its_int_cmd.dev = dev; | |
690 | desc.its_int_cmd.event_id = event_id; | |
691 | ||
692 | its_send_single_command(dev->its, its_build_int_cmd, &desc); | |
693 | } | |
694 | ||
695 | static void its_send_clear(struct its_device *dev, u32 event_id) | |
696 | { | |
697 | struct its_cmd_desc desc; | |
698 | ||
699 | desc.its_clear_cmd.dev = dev; | |
700 | desc.its_clear_cmd.event_id = event_id; | |
701 | ||
702 | its_send_single_command(dev->its, its_build_clear_cmd, &desc); | |
703 | } | |
704 | ||
cc2d3216 MZ |
705 | static void its_send_inv(struct its_device *dev, u32 event_id) |
706 | { | |
707 | struct its_cmd_desc desc; | |
708 | ||
709 | desc.its_inv_cmd.dev = dev; | |
710 | desc.its_inv_cmd.event_id = event_id; | |
711 | ||
712 | its_send_single_command(dev->its, its_build_inv_cmd, &desc); | |
713 | } | |
714 | ||
715 | static void its_send_mapd(struct its_device *dev, int valid) | |
716 | { | |
717 | struct its_cmd_desc desc; | |
718 | ||
719 | desc.its_mapd_cmd.dev = dev; | |
720 | desc.its_mapd_cmd.valid = !!valid; | |
721 | ||
722 | its_send_single_command(dev->its, its_build_mapd_cmd, &desc); | |
723 | } | |
724 | ||
725 | static void its_send_mapc(struct its_node *its, struct its_collection *col, | |
726 | int valid) | |
727 | { | |
728 | struct its_cmd_desc desc; | |
729 | ||
730 | desc.its_mapc_cmd.col = col; | |
731 | desc.its_mapc_cmd.valid = !!valid; | |
732 | ||
733 | its_send_single_command(its, its_build_mapc_cmd, &desc); | |
734 | } | |
735 | ||
6a25ad3a | 736 | static void its_send_mapti(struct its_device *dev, u32 irq_id, u32 id) |
cc2d3216 MZ |
737 | { |
738 | struct its_cmd_desc desc; | |
739 | ||
6a25ad3a MZ |
740 | desc.its_mapti_cmd.dev = dev; |
741 | desc.its_mapti_cmd.phys_id = irq_id; | |
742 | desc.its_mapti_cmd.event_id = id; | |
cc2d3216 | 743 | |
6a25ad3a | 744 | its_send_single_command(dev->its, its_build_mapti_cmd, &desc); |
cc2d3216 MZ |
745 | } |
746 | ||
747 | static void its_send_movi(struct its_device *dev, | |
748 | struct its_collection *col, u32 id) | |
749 | { | |
750 | struct its_cmd_desc desc; | |
751 | ||
752 | desc.its_movi_cmd.dev = dev; | |
753 | desc.its_movi_cmd.col = col; | |
591e5bec | 754 | desc.its_movi_cmd.event_id = id; |
cc2d3216 MZ |
755 | |
756 | its_send_single_command(dev->its, its_build_movi_cmd, &desc); | |
757 | } | |
758 | ||
759 | static void its_send_discard(struct its_device *dev, u32 id) | |
760 | { | |
761 | struct its_cmd_desc desc; | |
762 | ||
763 | desc.its_discard_cmd.dev = dev; | |
764 | desc.its_discard_cmd.event_id = id; | |
765 | ||
766 | its_send_single_command(dev->its, its_build_discard_cmd, &desc); | |
767 | } | |
768 | ||
769 | static void its_send_invall(struct its_node *its, struct its_collection *col) | |
770 | { | |
771 | struct its_cmd_desc desc; | |
772 | ||
773 | desc.its_invall_cmd.col = col; | |
774 | ||
775 | its_send_single_command(its, its_build_invall_cmd, &desc); | |
776 | } | |
c48ed51c | 777 | |
d011e4e6 MZ |
778 | static void its_send_vmapti(struct its_device *dev, u32 id) |
779 | { | |
780 | struct its_vlpi_map *map = &dev->event_map.vlpi_maps[id]; | |
781 | struct its_cmd_desc desc; | |
782 | ||
783 | desc.its_vmapti_cmd.vpe = map->vpe; | |
784 | desc.its_vmapti_cmd.dev = dev; | |
785 | desc.its_vmapti_cmd.virt_id = map->vintid; | |
786 | desc.its_vmapti_cmd.event_id = id; | |
787 | desc.its_vmapti_cmd.db_enabled = map->db_enabled; | |
788 | ||
789 | its_send_single_vcommand(dev->its, its_build_vmapti_cmd, &desc); | |
790 | } | |
791 | ||
792 | static void its_send_vmovi(struct its_device *dev, u32 id) | |
793 | { | |
794 | struct its_vlpi_map *map = &dev->event_map.vlpi_maps[id]; | |
795 | struct its_cmd_desc desc; | |
796 | ||
797 | desc.its_vmovi_cmd.vpe = map->vpe; | |
798 | desc.its_vmovi_cmd.dev = dev; | |
799 | desc.its_vmovi_cmd.event_id = id; | |
800 | desc.its_vmovi_cmd.db_enabled = map->db_enabled; | |
801 | ||
802 | its_send_single_vcommand(dev->its, its_build_vmovi_cmd, &desc); | |
803 | } | |
804 | ||
c48ed51c MZ |
805 | /* |
806 | * irqchip functions - assumes MSI, mostly. | |
807 | */ | |
808 | ||
809 | static inline u32 its_get_event_id(struct irq_data *d) | |
810 | { | |
811 | struct its_device *its_dev = irq_data_get_irq_chip_data(d); | |
591e5bec | 812 | return d->hwirq - its_dev->event_map.lpi_base; |
c48ed51c MZ |
813 | } |
814 | ||
015ec038 | 815 | static void lpi_write_config(struct irq_data *d, u8 clr, u8 set) |
c48ed51c | 816 | { |
015ec038 | 817 | irq_hw_number_t hwirq; |
adcdb94e MZ |
818 | struct page *prop_page; |
819 | u8 *cfg; | |
c48ed51c | 820 | |
015ec038 MZ |
821 | if (irqd_is_forwarded_to_vcpu(d)) { |
822 | struct its_device *its_dev = irq_data_get_irq_chip_data(d); | |
823 | u32 event = its_get_event_id(d); | |
824 | ||
825 | prop_page = its_dev->event_map.vm->vprop_page; | |
826 | hwirq = its_dev->event_map.vlpi_maps[event].vintid; | |
827 | } else { | |
828 | prop_page = gic_rdists->prop_page; | |
829 | hwirq = d->hwirq; | |
830 | } | |
adcdb94e MZ |
831 | |
832 | cfg = page_address(prop_page) + hwirq - 8192; | |
833 | *cfg &= ~clr; | |
015ec038 | 834 | *cfg |= set | LPI_PROP_GROUP1; |
c48ed51c MZ |
835 | |
836 | /* | |
837 | * Make the above write visible to the redistributors. | |
838 | * And yes, we're flushing exactly: One. Single. Byte. | |
839 | * Humpf... | |
840 | */ | |
841 | if (gic_rdists->flags & RDIST_FLAGS_PROPBASE_NEEDS_FLUSHING) | |
328191c0 | 842 | gic_flush_dcache_to_poc(cfg, sizeof(*cfg)); |
c48ed51c MZ |
843 | else |
844 | dsb(ishst); | |
015ec038 MZ |
845 | } |
846 | ||
847 | static void lpi_update_config(struct irq_data *d, u8 clr, u8 set) | |
848 | { | |
849 | struct its_device *its_dev = irq_data_get_irq_chip_data(d); | |
850 | ||
851 | lpi_write_config(d, clr, set); | |
adcdb94e | 852 | its_send_inv(its_dev, its_get_event_id(d)); |
c48ed51c MZ |
853 | } |
854 | ||
015ec038 MZ |
855 | static void its_vlpi_set_doorbell(struct irq_data *d, bool enable) |
856 | { | |
857 | struct its_device *its_dev = irq_data_get_irq_chip_data(d); | |
858 | u32 event = its_get_event_id(d); | |
859 | ||
860 | if (its_dev->event_map.vlpi_maps[event].db_enabled == enable) | |
861 | return; | |
862 | ||
863 | its_dev->event_map.vlpi_maps[event].db_enabled = enable; | |
864 | ||
865 | /* | |
866 | * More fun with the architecture: | |
867 | * | |
868 | * Ideally, we'd issue a VMAPTI to set the doorbell to its LPI | |
869 | * value or to 1023, depending on the enable bit. But that | |
870 | * would be issueing a mapping for an /existing/ DevID+EventID | |
871 | * pair, which is UNPREDICTABLE. Instead, let's issue a VMOVI | |
872 | * to the /same/ vPE, using this opportunity to adjust the | |
873 | * doorbell. Mouahahahaha. We loves it, Precious. | |
874 | */ | |
875 | its_send_vmovi(its_dev, event); | |
876 | } | |
877 | ||
c48ed51c MZ |
878 | static void its_mask_irq(struct irq_data *d) |
879 | { | |
015ec038 MZ |
880 | if (irqd_is_forwarded_to_vcpu(d)) |
881 | its_vlpi_set_doorbell(d, false); | |
882 | ||
adcdb94e | 883 | lpi_update_config(d, LPI_PROP_ENABLED, 0); |
c48ed51c MZ |
884 | } |
885 | ||
886 | static void its_unmask_irq(struct irq_data *d) | |
887 | { | |
015ec038 MZ |
888 | if (irqd_is_forwarded_to_vcpu(d)) |
889 | its_vlpi_set_doorbell(d, true); | |
890 | ||
adcdb94e | 891 | lpi_update_config(d, 0, LPI_PROP_ENABLED); |
c48ed51c MZ |
892 | } |
893 | ||
c48ed51c MZ |
894 | static int its_set_affinity(struct irq_data *d, const struct cpumask *mask_val, |
895 | bool force) | |
896 | { | |
fbf8f40e GK |
897 | unsigned int cpu; |
898 | const struct cpumask *cpu_mask = cpu_online_mask; | |
c48ed51c MZ |
899 | struct its_device *its_dev = irq_data_get_irq_chip_data(d); |
900 | struct its_collection *target_col; | |
901 | u32 id = its_get_event_id(d); | |
902 | ||
015ec038 MZ |
903 | /* A forwarded interrupt should use irq_set_vcpu_affinity */ |
904 | if (irqd_is_forwarded_to_vcpu(d)) | |
905 | return -EINVAL; | |
906 | ||
fbf8f40e GK |
907 | /* lpi cannot be routed to a redistributor that is on a foreign node */ |
908 | if (its_dev->its->flags & ITS_FLAGS_WORKAROUND_CAVIUM_23144) { | |
909 | if (its_dev->its->numa_node >= 0) { | |
910 | cpu_mask = cpumask_of_node(its_dev->its->numa_node); | |
911 | if (!cpumask_intersects(mask_val, cpu_mask)) | |
912 | return -EINVAL; | |
913 | } | |
914 | } | |
915 | ||
916 | cpu = cpumask_any_and(mask_val, cpu_mask); | |
917 | ||
c48ed51c MZ |
918 | if (cpu >= nr_cpu_ids) |
919 | return -EINVAL; | |
920 | ||
8b8d94a7 M |
921 | /* don't set the affinity when the target cpu is same as current one */ |
922 | if (cpu != its_dev->event_map.col_map[id]) { | |
923 | target_col = &its_dev->its->collections[cpu]; | |
924 | its_send_movi(its_dev, target_col, id); | |
925 | its_dev->event_map.col_map[id] = cpu; | |
926 | } | |
c48ed51c MZ |
927 | |
928 | return IRQ_SET_MASK_OK_DONE; | |
929 | } | |
930 | ||
b48ac83d MZ |
931 | static void its_irq_compose_msi_msg(struct irq_data *d, struct msi_msg *msg) |
932 | { | |
933 | struct its_device *its_dev = irq_data_get_irq_chip_data(d); | |
934 | struct its_node *its; | |
935 | u64 addr; | |
936 | ||
937 | its = its_dev->its; | |
938 | addr = its->phys_base + GITS_TRANSLATER; | |
939 | ||
b11283eb VM |
940 | msg->address_lo = lower_32_bits(addr); |
941 | msg->address_hi = upper_32_bits(addr); | |
b48ac83d | 942 | msg->data = its_get_event_id(d); |
44bb7e24 RM |
943 | |
944 | iommu_dma_map_msi_msg(d->irq, msg); | |
b48ac83d MZ |
945 | } |
946 | ||
8d85dced MZ |
947 | static int its_irq_set_irqchip_state(struct irq_data *d, |
948 | enum irqchip_irq_state which, | |
949 | bool state) | |
950 | { | |
951 | struct its_device *its_dev = irq_data_get_irq_chip_data(d); | |
952 | u32 event = its_get_event_id(d); | |
953 | ||
954 | if (which != IRQCHIP_STATE_PENDING) | |
955 | return -EINVAL; | |
956 | ||
957 | if (state) | |
958 | its_send_int(its_dev, event); | |
959 | else | |
960 | its_send_clear(its_dev, event); | |
961 | ||
962 | return 0; | |
963 | } | |
964 | ||
d011e4e6 MZ |
965 | static int its_vlpi_map(struct irq_data *d, struct its_cmd_info *info) |
966 | { | |
967 | struct its_device *its_dev = irq_data_get_irq_chip_data(d); | |
968 | u32 event = its_get_event_id(d); | |
969 | int ret = 0; | |
970 | ||
971 | if (!info->map) | |
972 | return -EINVAL; | |
973 | ||
974 | mutex_lock(&its_dev->event_map.vlpi_lock); | |
975 | ||
976 | if (!its_dev->event_map.vm) { | |
977 | struct its_vlpi_map *maps; | |
978 | ||
979 | maps = kzalloc(sizeof(*maps) * its_dev->event_map.nr_lpis, | |
980 | GFP_KERNEL); | |
981 | if (!maps) { | |
982 | ret = -ENOMEM; | |
983 | goto out; | |
984 | } | |
985 | ||
986 | its_dev->event_map.vm = info->map->vm; | |
987 | its_dev->event_map.vlpi_maps = maps; | |
988 | } else if (its_dev->event_map.vm != info->map->vm) { | |
989 | ret = -EINVAL; | |
990 | goto out; | |
991 | } | |
992 | ||
993 | /* Get our private copy of the mapping information */ | |
994 | its_dev->event_map.vlpi_maps[event] = *info->map; | |
995 | ||
996 | if (irqd_is_forwarded_to_vcpu(d)) { | |
997 | /* Already mapped, move it around */ | |
998 | its_send_vmovi(its_dev, event); | |
999 | } else { | |
1000 | /* Drop the physical mapping */ | |
1001 | its_send_discard(its_dev, event); | |
1002 | ||
1003 | /* and install the virtual one */ | |
1004 | its_send_vmapti(its_dev, event); | |
1005 | irqd_set_forwarded_to_vcpu(d); | |
1006 | ||
1007 | /* Increment the number of VLPIs */ | |
1008 | its_dev->event_map.nr_vlpis++; | |
1009 | } | |
1010 | ||
1011 | out: | |
1012 | mutex_unlock(&its_dev->event_map.vlpi_lock); | |
1013 | return ret; | |
1014 | } | |
1015 | ||
1016 | static int its_vlpi_get(struct irq_data *d, struct its_cmd_info *info) | |
1017 | { | |
1018 | struct its_device *its_dev = irq_data_get_irq_chip_data(d); | |
1019 | u32 event = its_get_event_id(d); | |
1020 | int ret = 0; | |
1021 | ||
1022 | mutex_lock(&its_dev->event_map.vlpi_lock); | |
1023 | ||
1024 | if (!its_dev->event_map.vm || | |
1025 | !its_dev->event_map.vlpi_maps[event].vm) { | |
1026 | ret = -EINVAL; | |
1027 | goto out; | |
1028 | } | |
1029 | ||
1030 | /* Copy our mapping information to the incoming request */ | |
1031 | *info->map = its_dev->event_map.vlpi_maps[event]; | |
1032 | ||
1033 | out: | |
1034 | mutex_unlock(&its_dev->event_map.vlpi_lock); | |
1035 | return ret; | |
1036 | } | |
1037 | ||
1038 | static int its_vlpi_unmap(struct irq_data *d) | |
1039 | { | |
1040 | struct its_device *its_dev = irq_data_get_irq_chip_data(d); | |
1041 | u32 event = its_get_event_id(d); | |
1042 | int ret = 0; | |
1043 | ||
1044 | mutex_lock(&its_dev->event_map.vlpi_lock); | |
1045 | ||
1046 | if (!its_dev->event_map.vm || !irqd_is_forwarded_to_vcpu(d)) { | |
1047 | ret = -EINVAL; | |
1048 | goto out; | |
1049 | } | |
1050 | ||
1051 | /* Drop the virtual mapping */ | |
1052 | its_send_discard(its_dev, event); | |
1053 | ||
1054 | /* and restore the physical one */ | |
1055 | irqd_clr_forwarded_to_vcpu(d); | |
1056 | its_send_mapti(its_dev, d->hwirq, event); | |
1057 | lpi_update_config(d, 0xff, (LPI_PROP_DEFAULT_PRIO | | |
1058 | LPI_PROP_ENABLED | | |
1059 | LPI_PROP_GROUP1)); | |
1060 | ||
1061 | /* | |
1062 | * Drop the refcount and make the device available again if | |
1063 | * this was the last VLPI. | |
1064 | */ | |
1065 | if (!--its_dev->event_map.nr_vlpis) { | |
1066 | its_dev->event_map.vm = NULL; | |
1067 | kfree(its_dev->event_map.vlpi_maps); | |
1068 | } | |
1069 | ||
1070 | out: | |
1071 | mutex_unlock(&its_dev->event_map.vlpi_lock); | |
1072 | return ret; | |
1073 | } | |
1074 | ||
015ec038 MZ |
1075 | static int its_vlpi_prop_update(struct irq_data *d, struct its_cmd_info *info) |
1076 | { | |
1077 | struct its_device *its_dev = irq_data_get_irq_chip_data(d); | |
1078 | ||
1079 | if (!its_dev->event_map.vm || !irqd_is_forwarded_to_vcpu(d)) | |
1080 | return -EINVAL; | |
1081 | ||
1082 | if (info->cmd_type == PROP_UPDATE_AND_INV_VLPI) | |
1083 | lpi_update_config(d, 0xff, info->config); | |
1084 | else | |
1085 | lpi_write_config(d, 0xff, info->config); | |
1086 | its_vlpi_set_doorbell(d, !!(info->config & LPI_PROP_ENABLED)); | |
1087 | ||
1088 | return 0; | |
1089 | } | |
1090 | ||
c808eea8 MZ |
1091 | static int its_irq_set_vcpu_affinity(struct irq_data *d, void *vcpu_info) |
1092 | { | |
1093 | struct its_device *its_dev = irq_data_get_irq_chip_data(d); | |
1094 | struct its_cmd_info *info = vcpu_info; | |
1095 | ||
1096 | /* Need a v4 ITS */ | |
d011e4e6 | 1097 | if (!its_dev->its->is_v4) |
c808eea8 MZ |
1098 | return -EINVAL; |
1099 | ||
d011e4e6 MZ |
1100 | /* Unmap request? */ |
1101 | if (!info) | |
1102 | return its_vlpi_unmap(d); | |
1103 | ||
c808eea8 MZ |
1104 | switch (info->cmd_type) { |
1105 | case MAP_VLPI: | |
d011e4e6 | 1106 | return its_vlpi_map(d, info); |
c808eea8 MZ |
1107 | |
1108 | case GET_VLPI: | |
d011e4e6 | 1109 | return its_vlpi_get(d, info); |
c808eea8 MZ |
1110 | |
1111 | case PROP_UPDATE_VLPI: | |
1112 | case PROP_UPDATE_AND_INV_VLPI: | |
015ec038 | 1113 | return its_vlpi_prop_update(d, info); |
c808eea8 MZ |
1114 | |
1115 | default: | |
1116 | return -EINVAL; | |
1117 | } | |
1118 | } | |
1119 | ||
c48ed51c MZ |
1120 | static struct irq_chip its_irq_chip = { |
1121 | .name = "ITS", | |
1122 | .irq_mask = its_mask_irq, | |
1123 | .irq_unmask = its_unmask_irq, | |
004fa08d | 1124 | .irq_eoi = irq_chip_eoi_parent, |
c48ed51c | 1125 | .irq_set_affinity = its_set_affinity, |
b48ac83d | 1126 | .irq_compose_msi_msg = its_irq_compose_msi_msg, |
8d85dced | 1127 | .irq_set_irqchip_state = its_irq_set_irqchip_state, |
c808eea8 | 1128 | .irq_set_vcpu_affinity = its_irq_set_vcpu_affinity, |
b48ac83d MZ |
1129 | }; |
1130 | ||
bf9529f8 MZ |
1131 | /* |
1132 | * How we allocate LPIs: | |
1133 | * | |
1134 | * The GIC has id_bits bits for interrupt identifiers. From there, we | |
1135 | * must subtract 8192 which are reserved for SGIs/PPIs/SPIs. Then, as | |
1136 | * we allocate LPIs by chunks of 32, we can shift the whole thing by 5 | |
1137 | * bits to the right. | |
1138 | * | |
1139 | * This gives us (((1UL << id_bits) - 8192) >> 5) possible allocations. | |
1140 | */ | |
1141 | #define IRQS_PER_CHUNK_SHIFT 5 | |
1142 | #define IRQS_PER_CHUNK (1 << IRQS_PER_CHUNK_SHIFT) | |
6c31e123 | 1143 | #define ITS_MAX_LPI_NRBITS 16 /* 64K LPIs */ |
bf9529f8 MZ |
1144 | |
1145 | static unsigned long *lpi_bitmap; | |
1146 | static u32 lpi_chunks; | |
1147 | static DEFINE_SPINLOCK(lpi_lock); | |
1148 | ||
1149 | static int its_lpi_to_chunk(int lpi) | |
1150 | { | |
1151 | return (lpi - 8192) >> IRQS_PER_CHUNK_SHIFT; | |
1152 | } | |
1153 | ||
1154 | static int its_chunk_to_lpi(int chunk) | |
1155 | { | |
1156 | return (chunk << IRQS_PER_CHUNK_SHIFT) + 8192; | |
1157 | } | |
1158 | ||
04a0e4de | 1159 | static int __init its_lpi_init(u32 id_bits) |
bf9529f8 MZ |
1160 | { |
1161 | lpi_chunks = its_lpi_to_chunk(1UL << id_bits); | |
1162 | ||
1163 | lpi_bitmap = kzalloc(BITS_TO_LONGS(lpi_chunks) * sizeof(long), | |
1164 | GFP_KERNEL); | |
1165 | if (!lpi_bitmap) { | |
1166 | lpi_chunks = 0; | |
1167 | return -ENOMEM; | |
1168 | } | |
1169 | ||
1170 | pr_info("ITS: Allocated %d chunks for LPIs\n", (int)lpi_chunks); | |
1171 | return 0; | |
1172 | } | |
1173 | ||
1174 | static unsigned long *its_lpi_alloc_chunks(int nr_irqs, int *base, int *nr_ids) | |
1175 | { | |
1176 | unsigned long *bitmap = NULL; | |
1177 | int chunk_id; | |
1178 | int nr_chunks; | |
1179 | int i; | |
1180 | ||
1181 | nr_chunks = DIV_ROUND_UP(nr_irqs, IRQS_PER_CHUNK); | |
1182 | ||
1183 | spin_lock(&lpi_lock); | |
1184 | ||
1185 | do { | |
1186 | chunk_id = bitmap_find_next_zero_area(lpi_bitmap, lpi_chunks, | |
1187 | 0, nr_chunks, 0); | |
1188 | if (chunk_id < lpi_chunks) | |
1189 | break; | |
1190 | ||
1191 | nr_chunks--; | |
1192 | } while (nr_chunks > 0); | |
1193 | ||
1194 | if (!nr_chunks) | |
1195 | goto out; | |
1196 | ||
1197 | bitmap = kzalloc(BITS_TO_LONGS(nr_chunks * IRQS_PER_CHUNK) * sizeof (long), | |
1198 | GFP_ATOMIC); | |
1199 | if (!bitmap) | |
1200 | goto out; | |
1201 | ||
1202 | for (i = 0; i < nr_chunks; i++) | |
1203 | set_bit(chunk_id + i, lpi_bitmap); | |
1204 | ||
1205 | *base = its_chunk_to_lpi(chunk_id); | |
1206 | *nr_ids = nr_chunks * IRQS_PER_CHUNK; | |
1207 | ||
1208 | out: | |
1209 | spin_unlock(&lpi_lock); | |
1210 | ||
c8415b94 MZ |
1211 | if (!bitmap) |
1212 | *base = *nr_ids = 0; | |
1213 | ||
bf9529f8 MZ |
1214 | return bitmap; |
1215 | } | |
1216 | ||
cf2be8ba | 1217 | static void its_lpi_free_chunks(unsigned long *bitmap, int base, int nr_ids) |
bf9529f8 MZ |
1218 | { |
1219 | int lpi; | |
1220 | ||
1221 | spin_lock(&lpi_lock); | |
1222 | ||
1223 | for (lpi = base; lpi < (base + nr_ids); lpi += IRQS_PER_CHUNK) { | |
1224 | int chunk = its_lpi_to_chunk(lpi); | |
cf2be8ba | 1225 | |
bf9529f8 MZ |
1226 | BUG_ON(chunk > lpi_chunks); |
1227 | if (test_bit(chunk, lpi_bitmap)) { | |
1228 | clear_bit(chunk, lpi_bitmap); | |
1229 | } else { | |
1230 | pr_err("Bad LPI chunk %d\n", chunk); | |
1231 | } | |
1232 | } | |
1233 | ||
1234 | spin_unlock(&lpi_lock); | |
1235 | ||
cf2be8ba | 1236 | kfree(bitmap); |
bf9529f8 | 1237 | } |
1ac19ca6 | 1238 | |
0e5ccf91 MZ |
1239 | static struct page *its_allocate_prop_table(gfp_t gfp_flags) |
1240 | { | |
1241 | struct page *prop_page; | |
1242 | ||
1243 | prop_page = alloc_pages(gfp_flags, get_order(LPI_PROPBASE_SZ)); | |
1244 | if (!prop_page) | |
1245 | return NULL; | |
1246 | ||
1247 | /* Priority 0xa0, Group-1, disabled */ | |
1248 | memset(page_address(prop_page), | |
1249 | LPI_PROP_DEFAULT_PRIO | LPI_PROP_GROUP1, | |
1250 | LPI_PROPBASE_SZ); | |
1251 | ||
1252 | /* Make sure the GIC will observe the written configuration */ | |
1253 | gic_flush_dcache_to_poc(page_address(prop_page), LPI_PROPBASE_SZ); | |
1254 | ||
1255 | return prop_page; | |
1256 | } | |
1257 | ||
1258 | ||
1ac19ca6 MZ |
1259 | static int __init its_alloc_lpi_tables(void) |
1260 | { | |
1261 | phys_addr_t paddr; | |
1262 | ||
6c31e123 | 1263 | lpi_id_bits = min_t(u32, gic_rdists->id_bits, ITS_MAX_LPI_NRBITS); |
0e5ccf91 | 1264 | gic_rdists->prop_page = its_allocate_prop_table(GFP_NOWAIT); |
1ac19ca6 MZ |
1265 | if (!gic_rdists->prop_page) { |
1266 | pr_err("Failed to allocate PROPBASE\n"); | |
1267 | return -ENOMEM; | |
1268 | } | |
1269 | ||
1270 | paddr = page_to_phys(gic_rdists->prop_page); | |
1271 | pr_info("GIC: using LPI property table @%pa\n", &paddr); | |
1272 | ||
6c31e123 | 1273 | return its_lpi_init(lpi_id_bits); |
1ac19ca6 MZ |
1274 | } |
1275 | ||
1276 | static const char *its_base_type_string[] = { | |
1277 | [GITS_BASER_TYPE_DEVICE] = "Devices", | |
1278 | [GITS_BASER_TYPE_VCPU] = "Virtual CPUs", | |
4f46de9d | 1279 | [GITS_BASER_TYPE_RESERVED3] = "Reserved (3)", |
1ac19ca6 MZ |
1280 | [GITS_BASER_TYPE_COLLECTION] = "Interrupt Collections", |
1281 | [GITS_BASER_TYPE_RESERVED5] = "Reserved (5)", | |
1282 | [GITS_BASER_TYPE_RESERVED6] = "Reserved (6)", | |
1283 | [GITS_BASER_TYPE_RESERVED7] = "Reserved (7)", | |
1284 | }; | |
1285 | ||
2d81d425 SD |
1286 | static u64 its_read_baser(struct its_node *its, struct its_baser *baser) |
1287 | { | |
1288 | u32 idx = baser - its->tables; | |
1289 | ||
0968a619 | 1290 | return gits_read_baser(its->base + GITS_BASER + (idx << 3)); |
2d81d425 SD |
1291 | } |
1292 | ||
1293 | static void its_write_baser(struct its_node *its, struct its_baser *baser, | |
1294 | u64 val) | |
1295 | { | |
1296 | u32 idx = baser - its->tables; | |
1297 | ||
0968a619 | 1298 | gits_write_baser(val, its->base + GITS_BASER + (idx << 3)); |
2d81d425 SD |
1299 | baser->val = its_read_baser(its, baser); |
1300 | } | |
1301 | ||
9347359a | 1302 | static int its_setup_baser(struct its_node *its, struct its_baser *baser, |
3faf24ea SD |
1303 | u64 cache, u64 shr, u32 psz, u32 order, |
1304 | bool indirect) | |
9347359a SD |
1305 | { |
1306 | u64 val = its_read_baser(its, baser); | |
1307 | u64 esz = GITS_BASER_ENTRY_SIZE(val); | |
1308 | u64 type = GITS_BASER_TYPE(val); | |
1309 | u32 alloc_pages; | |
1310 | void *base; | |
1311 | u64 tmp; | |
1312 | ||
1313 | retry_alloc_baser: | |
1314 | alloc_pages = (PAGE_ORDER_TO_SIZE(order) / psz); | |
1315 | if (alloc_pages > GITS_BASER_PAGES_MAX) { | |
1316 | pr_warn("ITS@%pa: %s too large, reduce ITS pages %u->%u\n", | |
1317 | &its->phys_base, its_base_type_string[type], | |
1318 | alloc_pages, GITS_BASER_PAGES_MAX); | |
1319 | alloc_pages = GITS_BASER_PAGES_MAX; | |
1320 | order = get_order(GITS_BASER_PAGES_MAX * psz); | |
1321 | } | |
1322 | ||
1323 | base = (void *)__get_free_pages(GFP_KERNEL | __GFP_ZERO, order); | |
1324 | if (!base) | |
1325 | return -ENOMEM; | |
1326 | ||
1327 | retry_baser: | |
1328 | val = (virt_to_phys(base) | | |
1329 | (type << GITS_BASER_TYPE_SHIFT) | | |
1330 | ((esz - 1) << GITS_BASER_ENTRY_SIZE_SHIFT) | | |
1331 | ((alloc_pages - 1) << GITS_BASER_PAGES_SHIFT) | | |
1332 | cache | | |
1333 | shr | | |
1334 | GITS_BASER_VALID); | |
1335 | ||
3faf24ea SD |
1336 | val |= indirect ? GITS_BASER_INDIRECT : 0x0; |
1337 | ||
9347359a SD |
1338 | switch (psz) { |
1339 | case SZ_4K: | |
1340 | val |= GITS_BASER_PAGE_SIZE_4K; | |
1341 | break; | |
1342 | case SZ_16K: | |
1343 | val |= GITS_BASER_PAGE_SIZE_16K; | |
1344 | break; | |
1345 | case SZ_64K: | |
1346 | val |= GITS_BASER_PAGE_SIZE_64K; | |
1347 | break; | |
1348 | } | |
1349 | ||
1350 | its_write_baser(its, baser, val); | |
1351 | tmp = baser->val; | |
1352 | ||
1353 | if ((val ^ tmp) & GITS_BASER_SHAREABILITY_MASK) { | |
1354 | /* | |
1355 | * Shareability didn't stick. Just use | |
1356 | * whatever the read reported, which is likely | |
1357 | * to be the only thing this redistributor | |
1358 | * supports. If that's zero, make it | |
1359 | * non-cacheable as well. | |
1360 | */ | |
1361 | shr = tmp & GITS_BASER_SHAREABILITY_MASK; | |
1362 | if (!shr) { | |
1363 | cache = GITS_BASER_nC; | |
328191c0 | 1364 | gic_flush_dcache_to_poc(base, PAGE_ORDER_TO_SIZE(order)); |
9347359a SD |
1365 | } |
1366 | goto retry_baser; | |
1367 | } | |
1368 | ||
1369 | if ((val ^ tmp) & GITS_BASER_PAGE_SIZE_MASK) { | |
1370 | /* | |
1371 | * Page size didn't stick. Let's try a smaller | |
1372 | * size and retry. If we reach 4K, then | |
1373 | * something is horribly wrong... | |
1374 | */ | |
1375 | free_pages((unsigned long)base, order); | |
1376 | baser->base = NULL; | |
1377 | ||
1378 | switch (psz) { | |
1379 | case SZ_16K: | |
1380 | psz = SZ_4K; | |
1381 | goto retry_alloc_baser; | |
1382 | case SZ_64K: | |
1383 | psz = SZ_16K; | |
1384 | goto retry_alloc_baser; | |
1385 | } | |
1386 | } | |
1387 | ||
1388 | if (val != tmp) { | |
b11283eb | 1389 | pr_err("ITS@%pa: %s doesn't stick: %llx %llx\n", |
9347359a | 1390 | &its->phys_base, its_base_type_string[type], |
b11283eb | 1391 | val, tmp); |
9347359a SD |
1392 | free_pages((unsigned long)base, order); |
1393 | return -ENXIO; | |
1394 | } | |
1395 | ||
1396 | baser->order = order; | |
1397 | baser->base = base; | |
1398 | baser->psz = psz; | |
3faf24ea | 1399 | tmp = indirect ? GITS_LVL1_ENTRY_SIZE : esz; |
9347359a | 1400 | |
3faf24ea | 1401 | pr_info("ITS@%pa: allocated %d %s @%lx (%s, esz %d, psz %dK, shr %d)\n", |
d524eaa2 | 1402 | &its->phys_base, (int)(PAGE_ORDER_TO_SIZE(order) / (int)tmp), |
9347359a SD |
1403 | its_base_type_string[type], |
1404 | (unsigned long)virt_to_phys(base), | |
3faf24ea | 1405 | indirect ? "indirect" : "flat", (int)esz, |
9347359a SD |
1406 | psz / SZ_1K, (int)shr >> GITS_BASER_SHAREABILITY_SHIFT); |
1407 | ||
1408 | return 0; | |
1409 | } | |
1410 | ||
4cacac57 MZ |
1411 | static bool its_parse_indirect_baser(struct its_node *its, |
1412 | struct its_baser *baser, | |
1413 | u32 psz, u32 *order) | |
4b75c459 | 1414 | { |
4cacac57 MZ |
1415 | u64 tmp = its_read_baser(its, baser); |
1416 | u64 type = GITS_BASER_TYPE(tmp); | |
1417 | u64 esz = GITS_BASER_ENTRY_SIZE(tmp); | |
2fd632a0 | 1418 | u64 val = GITS_BASER_InnerShareable | GITS_BASER_RaWaWb; |
4b75c459 SD |
1419 | u32 ids = its->device_ids; |
1420 | u32 new_order = *order; | |
3faf24ea SD |
1421 | bool indirect = false; |
1422 | ||
1423 | /* No need to enable Indirection if memory requirement < (psz*2)bytes */ | |
1424 | if ((esz << ids) > (psz * 2)) { | |
1425 | /* | |
1426 | * Find out whether hw supports a single or two-level table by | |
1427 | * table by reading bit at offset '62' after writing '1' to it. | |
1428 | */ | |
1429 | its_write_baser(its, baser, val | GITS_BASER_INDIRECT); | |
1430 | indirect = !!(baser->val & GITS_BASER_INDIRECT); | |
1431 | ||
1432 | if (indirect) { | |
1433 | /* | |
1434 | * The size of the lvl2 table is equal to ITS page size | |
1435 | * which is 'psz'. For computing lvl1 table size, | |
1436 | * subtract ID bits that sparse lvl2 table from 'ids' | |
1437 | * which is reported by ITS hardware times lvl1 table | |
1438 | * entry size. | |
1439 | */ | |
d524eaa2 | 1440 | ids -= ilog2(psz / (int)esz); |
3faf24ea SD |
1441 | esz = GITS_LVL1_ENTRY_SIZE; |
1442 | } | |
1443 | } | |
4b75c459 SD |
1444 | |
1445 | /* | |
1446 | * Allocate as many entries as required to fit the | |
1447 | * range of device IDs that the ITS can grok... The ID | |
1448 | * space being incredibly sparse, this results in a | |
3faf24ea SD |
1449 | * massive waste of memory if two-level device table |
1450 | * feature is not supported by hardware. | |
4b75c459 SD |
1451 | */ |
1452 | new_order = max_t(u32, get_order(esz << ids), new_order); | |
1453 | if (new_order >= MAX_ORDER) { | |
1454 | new_order = MAX_ORDER - 1; | |
d524eaa2 | 1455 | ids = ilog2(PAGE_ORDER_TO_SIZE(new_order) / (int)esz); |
4cacac57 MZ |
1456 | pr_warn("ITS@%pa: %s Table too large, reduce ids %u->%u\n", |
1457 | &its->phys_base, its_base_type_string[type], | |
1458 | its->device_ids, ids); | |
4b75c459 SD |
1459 | } |
1460 | ||
1461 | *order = new_order; | |
3faf24ea SD |
1462 | |
1463 | return indirect; | |
4b75c459 SD |
1464 | } |
1465 | ||
1ac19ca6 MZ |
1466 | static void its_free_tables(struct its_node *its) |
1467 | { | |
1468 | int i; | |
1469 | ||
1470 | for (i = 0; i < GITS_BASER_NR_REGS; i++) { | |
1a485f4d SD |
1471 | if (its->tables[i].base) { |
1472 | free_pages((unsigned long)its->tables[i].base, | |
1473 | its->tables[i].order); | |
1474 | its->tables[i].base = NULL; | |
1ac19ca6 MZ |
1475 | } |
1476 | } | |
1477 | } | |
1478 | ||
0e0b0f69 | 1479 | static int its_alloc_tables(struct its_node *its) |
1ac19ca6 | 1480 | { |
589ce5f4 | 1481 | u64 typer = gic_read_typer(its->base + GITS_TYPER); |
9347359a | 1482 | u32 ids = GITS_TYPER_DEVBITS(typer); |
1ac19ca6 | 1483 | u64 shr = GITS_BASER_InnerShareable; |
2fd632a0 | 1484 | u64 cache = GITS_BASER_RaWaWb; |
9347359a SD |
1485 | u32 psz = SZ_64K; |
1486 | int err, i; | |
94100970 RR |
1487 | |
1488 | if (its->flags & ITS_FLAGS_WORKAROUND_CAVIUM_22375) { | |
1489 | /* | |
9347359a SD |
1490 | * erratum 22375: only alloc 8MB table size |
1491 | * erratum 24313: ignore memory access type | |
1492 | */ | |
1493 | cache = GITS_BASER_nCnB; | |
1494 | ids = 0x14; /* 20 bits, 8MB */ | |
94100970 | 1495 | } |
1ac19ca6 | 1496 | |
466b7d16 SD |
1497 | its->device_ids = ids; |
1498 | ||
1ac19ca6 | 1499 | for (i = 0; i < GITS_BASER_NR_REGS; i++) { |
2d81d425 SD |
1500 | struct its_baser *baser = its->tables + i; |
1501 | u64 val = its_read_baser(its, baser); | |
1ac19ca6 | 1502 | u64 type = GITS_BASER_TYPE(val); |
9347359a | 1503 | u32 order = get_order(psz); |
3faf24ea | 1504 | bool indirect = false; |
1ac19ca6 | 1505 | |
4cacac57 MZ |
1506 | switch (type) { |
1507 | case GITS_BASER_TYPE_NONE: | |
1ac19ca6 MZ |
1508 | continue; |
1509 | ||
4cacac57 MZ |
1510 | case GITS_BASER_TYPE_DEVICE: |
1511 | case GITS_BASER_TYPE_VCPU: | |
1512 | indirect = its_parse_indirect_baser(its, baser, | |
1513 | psz, &order); | |
1514 | break; | |
1515 | } | |
f54b97ed | 1516 | |
3faf24ea | 1517 | err = its_setup_baser(its, baser, cache, shr, psz, order, indirect); |
9347359a SD |
1518 | if (err < 0) { |
1519 | its_free_tables(its); | |
1520 | return err; | |
1ac19ca6 MZ |
1521 | } |
1522 | ||
9347359a SD |
1523 | /* Update settings which will be used for next BASERn */ |
1524 | psz = baser->psz; | |
1525 | cache = baser->val & GITS_BASER_CACHEABILITY_MASK; | |
1526 | shr = baser->val & GITS_BASER_SHAREABILITY_MASK; | |
1ac19ca6 MZ |
1527 | } |
1528 | ||
1529 | return 0; | |
1ac19ca6 MZ |
1530 | } |
1531 | ||
1532 | static int its_alloc_collections(struct its_node *its) | |
1533 | { | |
1534 | its->collections = kzalloc(nr_cpu_ids * sizeof(*its->collections), | |
1535 | GFP_KERNEL); | |
1536 | if (!its->collections) | |
1537 | return -ENOMEM; | |
1538 | ||
1539 | return 0; | |
1540 | } | |
1541 | ||
7c297a2d MZ |
1542 | static struct page *its_allocate_pending_table(gfp_t gfp_flags) |
1543 | { | |
1544 | struct page *pend_page; | |
1545 | /* | |
1546 | * The pending pages have to be at least 64kB aligned, | |
1547 | * hence the 'max(LPI_PENDBASE_SZ, SZ_64K)' below. | |
1548 | */ | |
1549 | pend_page = alloc_pages(gfp_flags | __GFP_ZERO, | |
1550 | get_order(max_t(u32, LPI_PENDBASE_SZ, SZ_64K))); | |
1551 | if (!pend_page) | |
1552 | return NULL; | |
1553 | ||
1554 | /* Make sure the GIC will observe the zero-ed page */ | |
1555 | gic_flush_dcache_to_poc(page_address(pend_page), LPI_PENDBASE_SZ); | |
1556 | ||
1557 | return pend_page; | |
1558 | } | |
1559 | ||
1ac19ca6 MZ |
1560 | static void its_cpu_init_lpis(void) |
1561 | { | |
1562 | void __iomem *rbase = gic_data_rdist_rd_base(); | |
1563 | struct page *pend_page; | |
1564 | u64 val, tmp; | |
1565 | ||
1566 | /* If we didn't allocate the pending table yet, do it now */ | |
1567 | pend_page = gic_data_rdist()->pend_page; | |
1568 | if (!pend_page) { | |
1569 | phys_addr_t paddr; | |
7c297a2d MZ |
1570 | |
1571 | pend_page = its_allocate_pending_table(GFP_NOWAIT); | |
1ac19ca6 MZ |
1572 | if (!pend_page) { |
1573 | pr_err("Failed to allocate PENDBASE for CPU%d\n", | |
1574 | smp_processor_id()); | |
1575 | return; | |
1576 | } | |
1577 | ||
1ac19ca6 MZ |
1578 | paddr = page_to_phys(pend_page); |
1579 | pr_info("CPU%d: using LPI pending table @%pa\n", | |
1580 | smp_processor_id(), &paddr); | |
1581 | gic_data_rdist()->pend_page = pend_page; | |
1582 | } | |
1583 | ||
1584 | /* Disable LPIs */ | |
1585 | val = readl_relaxed(rbase + GICR_CTLR); | |
1586 | val &= ~GICR_CTLR_ENABLE_LPIS; | |
1587 | writel_relaxed(val, rbase + GICR_CTLR); | |
1588 | ||
1589 | /* | |
1590 | * Make sure any change to the table is observable by the GIC. | |
1591 | */ | |
1592 | dsb(sy); | |
1593 | ||
1594 | /* set PROPBASE */ | |
1595 | val = (page_to_phys(gic_rdists->prop_page) | | |
1596 | GICR_PROPBASER_InnerShareable | | |
2fd632a0 | 1597 | GICR_PROPBASER_RaWaWb | |
1ac19ca6 MZ |
1598 | ((LPI_NRBITS - 1) & GICR_PROPBASER_IDBITS_MASK)); |
1599 | ||
0968a619 VM |
1600 | gicr_write_propbaser(val, rbase + GICR_PROPBASER); |
1601 | tmp = gicr_read_propbaser(rbase + GICR_PROPBASER); | |
1ac19ca6 MZ |
1602 | |
1603 | if ((tmp ^ val) & GICR_PROPBASER_SHAREABILITY_MASK) { | |
241a386c MZ |
1604 | if (!(tmp & GICR_PROPBASER_SHAREABILITY_MASK)) { |
1605 | /* | |
1606 | * The HW reports non-shareable, we must | |
1607 | * remove the cacheability attributes as | |
1608 | * well. | |
1609 | */ | |
1610 | val &= ~(GICR_PROPBASER_SHAREABILITY_MASK | | |
1611 | GICR_PROPBASER_CACHEABILITY_MASK); | |
1612 | val |= GICR_PROPBASER_nC; | |
0968a619 | 1613 | gicr_write_propbaser(val, rbase + GICR_PROPBASER); |
241a386c | 1614 | } |
1ac19ca6 MZ |
1615 | pr_info_once("GIC: using cache flushing for LPI property table\n"); |
1616 | gic_rdists->flags |= RDIST_FLAGS_PROPBASE_NEEDS_FLUSHING; | |
1617 | } | |
1618 | ||
1619 | /* set PENDBASE */ | |
1620 | val = (page_to_phys(pend_page) | | |
4ad3e363 | 1621 | GICR_PENDBASER_InnerShareable | |
2fd632a0 | 1622 | GICR_PENDBASER_RaWaWb); |
1ac19ca6 | 1623 | |
0968a619 VM |
1624 | gicr_write_pendbaser(val, rbase + GICR_PENDBASER); |
1625 | tmp = gicr_read_pendbaser(rbase + GICR_PENDBASER); | |
241a386c MZ |
1626 | |
1627 | if (!(tmp & GICR_PENDBASER_SHAREABILITY_MASK)) { | |
1628 | /* | |
1629 | * The HW reports non-shareable, we must remove the | |
1630 | * cacheability attributes as well. | |
1631 | */ | |
1632 | val &= ~(GICR_PENDBASER_SHAREABILITY_MASK | | |
1633 | GICR_PENDBASER_CACHEABILITY_MASK); | |
1634 | val |= GICR_PENDBASER_nC; | |
0968a619 | 1635 | gicr_write_pendbaser(val, rbase + GICR_PENDBASER); |
241a386c | 1636 | } |
1ac19ca6 MZ |
1637 | |
1638 | /* Enable LPIs */ | |
1639 | val = readl_relaxed(rbase + GICR_CTLR); | |
1640 | val |= GICR_CTLR_ENABLE_LPIS; | |
1641 | writel_relaxed(val, rbase + GICR_CTLR); | |
1642 | ||
1643 | /* Make sure the GIC has seen the above */ | |
1644 | dsb(sy); | |
1645 | } | |
1646 | ||
1647 | static void its_cpu_init_collection(void) | |
1648 | { | |
1649 | struct its_node *its; | |
1650 | int cpu; | |
1651 | ||
1652 | spin_lock(&its_lock); | |
1653 | cpu = smp_processor_id(); | |
1654 | ||
1655 | list_for_each_entry(its, &its_nodes, entry) { | |
1656 | u64 target; | |
1657 | ||
fbf8f40e GK |
1658 | /* avoid cross node collections and its mapping */ |
1659 | if (its->flags & ITS_FLAGS_WORKAROUND_CAVIUM_23144) { | |
1660 | struct device_node *cpu_node; | |
1661 | ||
1662 | cpu_node = of_get_cpu_node(cpu, NULL); | |
1663 | if (its->numa_node != NUMA_NO_NODE && | |
1664 | its->numa_node != of_node_to_nid(cpu_node)) | |
1665 | continue; | |
1666 | } | |
1667 | ||
1ac19ca6 MZ |
1668 | /* |
1669 | * We now have to bind each collection to its target | |
1670 | * redistributor. | |
1671 | */ | |
589ce5f4 | 1672 | if (gic_read_typer(its->base + GITS_TYPER) & GITS_TYPER_PTA) { |
1ac19ca6 MZ |
1673 | /* |
1674 | * This ITS wants the physical address of the | |
1675 | * redistributor. | |
1676 | */ | |
1677 | target = gic_data_rdist()->phys_base; | |
1678 | } else { | |
1679 | /* | |
1680 | * This ITS wants a linear CPU number. | |
1681 | */ | |
589ce5f4 | 1682 | target = gic_read_typer(gic_data_rdist_rd_base() + GICR_TYPER); |
263fcd31 | 1683 | target = GICR_TYPER_CPU_NUMBER(target) << 16; |
1ac19ca6 MZ |
1684 | } |
1685 | ||
1686 | /* Perform collection mapping */ | |
1687 | its->collections[cpu].target_address = target; | |
1688 | its->collections[cpu].col_id = cpu; | |
1689 | ||
1690 | its_send_mapc(its, &its->collections[cpu], 1); | |
1691 | its_send_invall(its, &its->collections[cpu]); | |
1692 | } | |
1693 | ||
1694 | spin_unlock(&its_lock); | |
1695 | } | |
84a6a2e7 MZ |
1696 | |
1697 | static struct its_device *its_find_device(struct its_node *its, u32 dev_id) | |
1698 | { | |
1699 | struct its_device *its_dev = NULL, *tmp; | |
3e39e8f5 | 1700 | unsigned long flags; |
84a6a2e7 | 1701 | |
3e39e8f5 | 1702 | raw_spin_lock_irqsave(&its->lock, flags); |
84a6a2e7 MZ |
1703 | |
1704 | list_for_each_entry(tmp, &its->its_device_list, entry) { | |
1705 | if (tmp->device_id == dev_id) { | |
1706 | its_dev = tmp; | |
1707 | break; | |
1708 | } | |
1709 | } | |
1710 | ||
3e39e8f5 | 1711 | raw_spin_unlock_irqrestore(&its->lock, flags); |
84a6a2e7 MZ |
1712 | |
1713 | return its_dev; | |
1714 | } | |
1715 | ||
466b7d16 SD |
1716 | static struct its_baser *its_get_baser(struct its_node *its, u32 type) |
1717 | { | |
1718 | int i; | |
1719 | ||
1720 | for (i = 0; i < GITS_BASER_NR_REGS; i++) { | |
1721 | if (GITS_BASER_TYPE(its->tables[i].val) == type) | |
1722 | return &its->tables[i]; | |
1723 | } | |
1724 | ||
1725 | return NULL; | |
1726 | } | |
1727 | ||
70cc81ed | 1728 | static bool its_alloc_table_entry(struct its_baser *baser, u32 id) |
3faf24ea | 1729 | { |
3faf24ea SD |
1730 | struct page *page; |
1731 | u32 esz, idx; | |
1732 | __le64 *table; | |
1733 | ||
3faf24ea SD |
1734 | /* Don't allow device id that exceeds single, flat table limit */ |
1735 | esz = GITS_BASER_ENTRY_SIZE(baser->val); | |
1736 | if (!(baser->val & GITS_BASER_INDIRECT)) | |
70cc81ed | 1737 | return (id < (PAGE_ORDER_TO_SIZE(baser->order) / esz)); |
3faf24ea SD |
1738 | |
1739 | /* Compute 1st level table index & check if that exceeds table limit */ | |
70cc81ed | 1740 | idx = id >> ilog2(baser->psz / esz); |
3faf24ea SD |
1741 | if (idx >= (PAGE_ORDER_TO_SIZE(baser->order) / GITS_LVL1_ENTRY_SIZE)) |
1742 | return false; | |
1743 | ||
1744 | table = baser->base; | |
1745 | ||
1746 | /* Allocate memory for 2nd level table */ | |
1747 | if (!table[idx]) { | |
1748 | page = alloc_pages(GFP_KERNEL | __GFP_ZERO, get_order(baser->psz)); | |
1749 | if (!page) | |
1750 | return false; | |
1751 | ||
1752 | /* Flush Lvl2 table to PoC if hw doesn't support coherency */ | |
1753 | if (!(baser->val & GITS_BASER_SHAREABILITY_MASK)) | |
328191c0 | 1754 | gic_flush_dcache_to_poc(page_address(page), baser->psz); |
3faf24ea SD |
1755 | |
1756 | table[idx] = cpu_to_le64(page_to_phys(page) | GITS_BASER_VALID); | |
1757 | ||
1758 | /* Flush Lvl1 entry to PoC if hw doesn't support coherency */ | |
1759 | if (!(baser->val & GITS_BASER_SHAREABILITY_MASK)) | |
328191c0 | 1760 | gic_flush_dcache_to_poc(table + idx, GITS_LVL1_ENTRY_SIZE); |
3faf24ea SD |
1761 | |
1762 | /* Ensure updated table contents are visible to ITS hardware */ | |
1763 | dsb(sy); | |
1764 | } | |
1765 | ||
1766 | return true; | |
1767 | } | |
1768 | ||
70cc81ed MZ |
1769 | static bool its_alloc_device_table(struct its_node *its, u32 dev_id) |
1770 | { | |
1771 | struct its_baser *baser; | |
1772 | ||
1773 | baser = its_get_baser(its, GITS_BASER_TYPE_DEVICE); | |
1774 | ||
1775 | /* Don't allow device id that exceeds ITS hardware limit */ | |
1776 | if (!baser) | |
1777 | return (ilog2(dev_id) < its->device_ids); | |
1778 | ||
1779 | return its_alloc_table_entry(baser, dev_id); | |
1780 | } | |
1781 | ||
84a6a2e7 MZ |
1782 | static struct its_device *its_create_device(struct its_node *its, u32 dev_id, |
1783 | int nvecs) | |
1784 | { | |
1785 | struct its_device *dev; | |
1786 | unsigned long *lpi_map; | |
3e39e8f5 | 1787 | unsigned long flags; |
591e5bec | 1788 | u16 *col_map = NULL; |
84a6a2e7 MZ |
1789 | void *itt; |
1790 | int lpi_base; | |
1791 | int nr_lpis; | |
c8481267 | 1792 | int nr_ites; |
84a6a2e7 MZ |
1793 | int sz; |
1794 | ||
3faf24ea | 1795 | if (!its_alloc_device_table(its, dev_id)) |
466b7d16 SD |
1796 | return NULL; |
1797 | ||
84a6a2e7 | 1798 | dev = kzalloc(sizeof(*dev), GFP_KERNEL); |
c8481267 MZ |
1799 | /* |
1800 | * At least one bit of EventID is being used, hence a minimum | |
1801 | * of two entries. No, the architecture doesn't let you | |
1802 | * express an ITT with a single entry. | |
1803 | */ | |
96555c47 | 1804 | nr_ites = max(2UL, roundup_pow_of_two(nvecs)); |
c8481267 | 1805 | sz = nr_ites * its->ite_size; |
84a6a2e7 | 1806 | sz = max(sz, ITS_ITT_ALIGN) + ITS_ITT_ALIGN - 1; |
6c834125 | 1807 | itt = kzalloc(sz, GFP_KERNEL); |
84a6a2e7 | 1808 | lpi_map = its_lpi_alloc_chunks(nvecs, &lpi_base, &nr_lpis); |
591e5bec MZ |
1809 | if (lpi_map) |
1810 | col_map = kzalloc(sizeof(*col_map) * nr_lpis, GFP_KERNEL); | |
84a6a2e7 | 1811 | |
591e5bec | 1812 | if (!dev || !itt || !lpi_map || !col_map) { |
84a6a2e7 MZ |
1813 | kfree(dev); |
1814 | kfree(itt); | |
1815 | kfree(lpi_map); | |
591e5bec | 1816 | kfree(col_map); |
84a6a2e7 MZ |
1817 | return NULL; |
1818 | } | |
1819 | ||
328191c0 | 1820 | gic_flush_dcache_to_poc(itt, sz); |
5a9a8915 | 1821 | |
84a6a2e7 MZ |
1822 | dev->its = its; |
1823 | dev->itt = itt; | |
c8481267 | 1824 | dev->nr_ites = nr_ites; |
591e5bec MZ |
1825 | dev->event_map.lpi_map = lpi_map; |
1826 | dev->event_map.col_map = col_map; | |
1827 | dev->event_map.lpi_base = lpi_base; | |
1828 | dev->event_map.nr_lpis = nr_lpis; | |
d011e4e6 | 1829 | mutex_init(&dev->event_map.vlpi_lock); |
84a6a2e7 MZ |
1830 | dev->device_id = dev_id; |
1831 | INIT_LIST_HEAD(&dev->entry); | |
1832 | ||
3e39e8f5 | 1833 | raw_spin_lock_irqsave(&its->lock, flags); |
84a6a2e7 | 1834 | list_add(&dev->entry, &its->its_device_list); |
3e39e8f5 | 1835 | raw_spin_unlock_irqrestore(&its->lock, flags); |
84a6a2e7 | 1836 | |
84a6a2e7 MZ |
1837 | /* Map device to its ITT */ |
1838 | its_send_mapd(dev, 1); | |
1839 | ||
1840 | return dev; | |
1841 | } | |
1842 | ||
1843 | static void its_free_device(struct its_device *its_dev) | |
1844 | { | |
3e39e8f5 MZ |
1845 | unsigned long flags; |
1846 | ||
1847 | raw_spin_lock_irqsave(&its_dev->its->lock, flags); | |
84a6a2e7 | 1848 | list_del(&its_dev->entry); |
3e39e8f5 | 1849 | raw_spin_unlock_irqrestore(&its_dev->its->lock, flags); |
84a6a2e7 MZ |
1850 | kfree(its_dev->itt); |
1851 | kfree(its_dev); | |
1852 | } | |
b48ac83d MZ |
1853 | |
1854 | static int its_alloc_device_irq(struct its_device *dev, irq_hw_number_t *hwirq) | |
1855 | { | |
1856 | int idx; | |
1857 | ||
591e5bec MZ |
1858 | idx = find_first_zero_bit(dev->event_map.lpi_map, |
1859 | dev->event_map.nr_lpis); | |
1860 | if (idx == dev->event_map.nr_lpis) | |
b48ac83d MZ |
1861 | return -ENOSPC; |
1862 | ||
591e5bec MZ |
1863 | *hwirq = dev->event_map.lpi_base + idx; |
1864 | set_bit(idx, dev->event_map.lpi_map); | |
b48ac83d | 1865 | |
b48ac83d MZ |
1866 | return 0; |
1867 | } | |
1868 | ||
54456db9 MZ |
1869 | static int its_msi_prepare(struct irq_domain *domain, struct device *dev, |
1870 | int nvec, msi_alloc_info_t *info) | |
e8137f4f | 1871 | { |
b48ac83d | 1872 | struct its_node *its; |
b48ac83d | 1873 | struct its_device *its_dev; |
54456db9 MZ |
1874 | struct msi_domain_info *msi_info; |
1875 | u32 dev_id; | |
1876 | ||
1877 | /* | |
1878 | * We ignore "dev" entierely, and rely on the dev_id that has | |
1879 | * been passed via the scratchpad. This limits this domain's | |
1880 | * usefulness to upper layers that definitely know that they | |
1881 | * are built on top of the ITS. | |
1882 | */ | |
1883 | dev_id = info->scratchpad[0].ul; | |
1884 | ||
1885 | msi_info = msi_get_domain_info(domain); | |
1886 | its = msi_info->data; | |
e8137f4f | 1887 | |
f130420e | 1888 | its_dev = its_find_device(its, dev_id); |
e8137f4f MZ |
1889 | if (its_dev) { |
1890 | /* | |
1891 | * We already have seen this ID, probably through | |
1892 | * another alias (PCI bridge of some sort). No need to | |
1893 | * create the device. | |
1894 | */ | |
f130420e | 1895 | pr_debug("Reusing ITT for devID %x\n", dev_id); |
e8137f4f MZ |
1896 | goto out; |
1897 | } | |
b48ac83d | 1898 | |
f130420e | 1899 | its_dev = its_create_device(its, dev_id, nvec); |
b48ac83d MZ |
1900 | if (!its_dev) |
1901 | return -ENOMEM; | |
1902 | ||
f130420e | 1903 | pr_debug("ITT %d entries, %d bits\n", nvec, ilog2(nvec)); |
e8137f4f | 1904 | out: |
b48ac83d | 1905 | info->scratchpad[0].ptr = its_dev; |
b48ac83d MZ |
1906 | return 0; |
1907 | } | |
1908 | ||
54456db9 MZ |
1909 | static struct msi_domain_ops its_msi_domain_ops = { |
1910 | .msi_prepare = its_msi_prepare, | |
1911 | }; | |
1912 | ||
b48ac83d MZ |
1913 | static int its_irq_gic_domain_alloc(struct irq_domain *domain, |
1914 | unsigned int virq, | |
1915 | irq_hw_number_t hwirq) | |
1916 | { | |
f833f57f MZ |
1917 | struct irq_fwspec fwspec; |
1918 | ||
1919 | if (irq_domain_get_of_node(domain->parent)) { | |
1920 | fwspec.fwnode = domain->parent->fwnode; | |
1921 | fwspec.param_count = 3; | |
1922 | fwspec.param[0] = GIC_IRQ_TYPE_LPI; | |
1923 | fwspec.param[1] = hwirq; | |
1924 | fwspec.param[2] = IRQ_TYPE_EDGE_RISING; | |
3f010cf1 TN |
1925 | } else if (is_fwnode_irqchip(domain->parent->fwnode)) { |
1926 | fwspec.fwnode = domain->parent->fwnode; | |
1927 | fwspec.param_count = 2; | |
1928 | fwspec.param[0] = hwirq; | |
1929 | fwspec.param[1] = IRQ_TYPE_EDGE_RISING; | |
f833f57f MZ |
1930 | } else { |
1931 | return -EINVAL; | |
1932 | } | |
b48ac83d | 1933 | |
f833f57f | 1934 | return irq_domain_alloc_irqs_parent(domain, virq, 1, &fwspec); |
b48ac83d MZ |
1935 | } |
1936 | ||
1937 | static int its_irq_domain_alloc(struct irq_domain *domain, unsigned int virq, | |
1938 | unsigned int nr_irqs, void *args) | |
1939 | { | |
1940 | msi_alloc_info_t *info = args; | |
1941 | struct its_device *its_dev = info->scratchpad[0].ptr; | |
1942 | irq_hw_number_t hwirq; | |
1943 | int err; | |
1944 | int i; | |
1945 | ||
1946 | for (i = 0; i < nr_irqs; i++) { | |
1947 | err = its_alloc_device_irq(its_dev, &hwirq); | |
1948 | if (err) | |
1949 | return err; | |
1950 | ||
1951 | err = its_irq_gic_domain_alloc(domain, virq + i, hwirq); | |
1952 | if (err) | |
1953 | return err; | |
1954 | ||
1955 | irq_domain_set_hwirq_and_chip(domain, virq + i, | |
1956 | hwirq, &its_irq_chip, its_dev); | |
f130420e MZ |
1957 | pr_debug("ID:%d pID:%d vID:%d\n", |
1958 | (int)(hwirq - its_dev->event_map.lpi_base), | |
1959 | (int) hwirq, virq + i); | |
b48ac83d MZ |
1960 | } |
1961 | ||
1962 | return 0; | |
1963 | } | |
1964 | ||
aca268df MZ |
1965 | static void its_irq_domain_activate(struct irq_domain *domain, |
1966 | struct irq_data *d) | |
1967 | { | |
1968 | struct its_device *its_dev = irq_data_get_irq_chip_data(d); | |
1969 | u32 event = its_get_event_id(d); | |
fbf8f40e GK |
1970 | const struct cpumask *cpu_mask = cpu_online_mask; |
1971 | ||
1972 | /* get the cpu_mask of local node */ | |
1973 | if (its_dev->its->numa_node >= 0) | |
1974 | cpu_mask = cpumask_of_node(its_dev->its->numa_node); | |
aca268df | 1975 | |
591e5bec | 1976 | /* Bind the LPI to the first possible CPU */ |
fbf8f40e | 1977 | its_dev->event_map.col_map[event] = cpumask_first(cpu_mask); |
591e5bec | 1978 | |
aca268df | 1979 | /* Map the GIC IRQ and event to the device */ |
6a25ad3a | 1980 | its_send_mapti(its_dev, d->hwirq, event); |
aca268df MZ |
1981 | } |
1982 | ||
1983 | static void its_irq_domain_deactivate(struct irq_domain *domain, | |
1984 | struct irq_data *d) | |
1985 | { | |
1986 | struct its_device *its_dev = irq_data_get_irq_chip_data(d); | |
1987 | u32 event = its_get_event_id(d); | |
1988 | ||
1989 | /* Stop the delivery of interrupts */ | |
1990 | its_send_discard(its_dev, event); | |
1991 | } | |
1992 | ||
b48ac83d MZ |
1993 | static void its_irq_domain_free(struct irq_domain *domain, unsigned int virq, |
1994 | unsigned int nr_irqs) | |
1995 | { | |
1996 | struct irq_data *d = irq_domain_get_irq_data(domain, virq); | |
1997 | struct its_device *its_dev = irq_data_get_irq_chip_data(d); | |
1998 | int i; | |
1999 | ||
2000 | for (i = 0; i < nr_irqs; i++) { | |
2001 | struct irq_data *data = irq_domain_get_irq_data(domain, | |
2002 | virq + i); | |
aca268df | 2003 | u32 event = its_get_event_id(data); |
b48ac83d MZ |
2004 | |
2005 | /* Mark interrupt index as unused */ | |
591e5bec | 2006 | clear_bit(event, its_dev->event_map.lpi_map); |
b48ac83d MZ |
2007 | |
2008 | /* Nuke the entry in the domain */ | |
2da39949 | 2009 | irq_domain_reset_irq_data(data); |
b48ac83d MZ |
2010 | } |
2011 | ||
2012 | /* If all interrupts have been freed, start mopping the floor */ | |
591e5bec MZ |
2013 | if (bitmap_empty(its_dev->event_map.lpi_map, |
2014 | its_dev->event_map.nr_lpis)) { | |
cf2be8ba MZ |
2015 | its_lpi_free_chunks(its_dev->event_map.lpi_map, |
2016 | its_dev->event_map.lpi_base, | |
2017 | its_dev->event_map.nr_lpis); | |
2018 | kfree(its_dev->event_map.col_map); | |
b48ac83d MZ |
2019 | |
2020 | /* Unmap device/itt */ | |
2021 | its_send_mapd(its_dev, 0); | |
2022 | its_free_device(its_dev); | |
2023 | } | |
2024 | ||
2025 | irq_domain_free_irqs_parent(domain, virq, nr_irqs); | |
2026 | } | |
2027 | ||
2028 | static const struct irq_domain_ops its_domain_ops = { | |
2029 | .alloc = its_irq_domain_alloc, | |
2030 | .free = its_irq_domain_free, | |
aca268df MZ |
2031 | .activate = its_irq_domain_activate, |
2032 | .deactivate = its_irq_domain_deactivate, | |
b48ac83d | 2033 | }; |
4c21f3c2 | 2034 | |
8fff27ae MZ |
2035 | static struct irq_chip its_vpe_irq_chip = { |
2036 | .name = "GICv4-vpe", | |
2037 | }; | |
2038 | ||
2039 | static const struct irq_domain_ops its_vpe_domain_ops = { | |
2040 | }; | |
2041 | ||
4559fbb3 YW |
2042 | static int its_force_quiescent(void __iomem *base) |
2043 | { | |
2044 | u32 count = 1000000; /* 1s */ | |
2045 | u32 val; | |
2046 | ||
2047 | val = readl_relaxed(base + GITS_CTLR); | |
7611da86 DD |
2048 | /* |
2049 | * GIC architecture specification requires the ITS to be both | |
2050 | * disabled and quiescent for writes to GITS_BASER<n> or | |
2051 | * GITS_CBASER to not have UNPREDICTABLE results. | |
2052 | */ | |
2053 | if ((val & GITS_CTLR_QUIESCENT) && !(val & GITS_CTLR_ENABLE)) | |
4559fbb3 YW |
2054 | return 0; |
2055 | ||
2056 | /* Disable the generation of all interrupts to this ITS */ | |
2057 | val &= ~GITS_CTLR_ENABLE; | |
2058 | writel_relaxed(val, base + GITS_CTLR); | |
2059 | ||
2060 | /* Poll GITS_CTLR and wait until ITS becomes quiescent */ | |
2061 | while (1) { | |
2062 | val = readl_relaxed(base + GITS_CTLR); | |
2063 | if (val & GITS_CTLR_QUIESCENT) | |
2064 | return 0; | |
2065 | ||
2066 | count--; | |
2067 | if (!count) | |
2068 | return -EBUSY; | |
2069 | ||
2070 | cpu_relax(); | |
2071 | udelay(1); | |
2072 | } | |
2073 | } | |
2074 | ||
94100970 RR |
2075 | static void __maybe_unused its_enable_quirk_cavium_22375(void *data) |
2076 | { | |
2077 | struct its_node *its = data; | |
2078 | ||
2079 | its->flags |= ITS_FLAGS_WORKAROUND_CAVIUM_22375; | |
2080 | } | |
2081 | ||
fbf8f40e GK |
2082 | static void __maybe_unused its_enable_quirk_cavium_23144(void *data) |
2083 | { | |
2084 | struct its_node *its = data; | |
2085 | ||
2086 | its->flags |= ITS_FLAGS_WORKAROUND_CAVIUM_23144; | |
2087 | } | |
2088 | ||
90922a2d SD |
2089 | static void __maybe_unused its_enable_quirk_qdf2400_e0065(void *data) |
2090 | { | |
2091 | struct its_node *its = data; | |
2092 | ||
2093 | /* On QDF2400, the size of the ITE is 16Bytes */ | |
2094 | its->ite_size = 16; | |
2095 | } | |
2096 | ||
67510cca | 2097 | static const struct gic_quirk its_quirks[] = { |
94100970 RR |
2098 | #ifdef CONFIG_CAVIUM_ERRATUM_22375 |
2099 | { | |
2100 | .desc = "ITS: Cavium errata 22375, 24313", | |
2101 | .iidr = 0xa100034c, /* ThunderX pass 1.x */ | |
2102 | .mask = 0xffff0fff, | |
2103 | .init = its_enable_quirk_cavium_22375, | |
2104 | }, | |
fbf8f40e GK |
2105 | #endif |
2106 | #ifdef CONFIG_CAVIUM_ERRATUM_23144 | |
2107 | { | |
2108 | .desc = "ITS: Cavium erratum 23144", | |
2109 | .iidr = 0xa100034c, /* ThunderX pass 1.x */ | |
2110 | .mask = 0xffff0fff, | |
2111 | .init = its_enable_quirk_cavium_23144, | |
2112 | }, | |
90922a2d SD |
2113 | #endif |
2114 | #ifdef CONFIG_QCOM_QDF2400_ERRATUM_0065 | |
2115 | { | |
2116 | .desc = "ITS: QDF2400 erratum 0065", | |
2117 | .iidr = 0x00001070, /* QDF2400 ITS rev 1.x */ | |
2118 | .mask = 0xffffffff, | |
2119 | .init = its_enable_quirk_qdf2400_e0065, | |
2120 | }, | |
94100970 | 2121 | #endif |
67510cca RR |
2122 | { |
2123 | } | |
2124 | }; | |
2125 | ||
2126 | static void its_enable_quirks(struct its_node *its) | |
2127 | { | |
2128 | u32 iidr = readl_relaxed(its->base + GITS_IIDR); | |
2129 | ||
2130 | gic_enable_quirks(iidr, its_quirks, its); | |
2131 | } | |
2132 | ||
db40f0a7 | 2133 | static int its_init_domain(struct fwnode_handle *handle, struct its_node *its) |
d14ae5e6 TN |
2134 | { |
2135 | struct irq_domain *inner_domain; | |
2136 | struct msi_domain_info *info; | |
2137 | ||
2138 | info = kzalloc(sizeof(*info), GFP_KERNEL); | |
2139 | if (!info) | |
2140 | return -ENOMEM; | |
2141 | ||
db40f0a7 | 2142 | inner_domain = irq_domain_create_tree(handle, &its_domain_ops, its); |
d14ae5e6 TN |
2143 | if (!inner_domain) { |
2144 | kfree(info); | |
2145 | return -ENOMEM; | |
2146 | } | |
2147 | ||
db40f0a7 | 2148 | inner_domain->parent = its_parent; |
96f0d93a | 2149 | irq_domain_update_bus_token(inner_domain, DOMAIN_BUS_NEXUS); |
59768527 | 2150 | inner_domain->flags |= IRQ_DOMAIN_FLAG_MSI_REMAP; |
d14ae5e6 TN |
2151 | info->ops = &its_msi_domain_ops; |
2152 | info->data = its; | |
2153 | inner_domain->host_data = info; | |
2154 | ||
2155 | return 0; | |
2156 | } | |
2157 | ||
8fff27ae MZ |
2158 | static int its_init_vpe_domain(void) |
2159 | { | |
2160 | return 0; | |
2161 | } | |
2162 | ||
3dfa576b MZ |
2163 | static int __init its_compute_its_list_map(struct resource *res, |
2164 | void __iomem *its_base) | |
2165 | { | |
2166 | int its_number; | |
2167 | u32 ctlr; | |
2168 | ||
2169 | /* | |
2170 | * This is assumed to be done early enough that we're | |
2171 | * guaranteed to be single-threaded, hence no | |
2172 | * locking. Should this change, we should address | |
2173 | * this. | |
2174 | */ | |
2175 | its_number = find_first_zero_bit(&its_list_map, ITS_LIST_MAX); | |
2176 | if (its_number >= ITS_LIST_MAX) { | |
2177 | pr_err("ITS@%pa: No ITSList entry available!\n", | |
2178 | &res->start); | |
2179 | return -EINVAL; | |
2180 | } | |
2181 | ||
2182 | ctlr = readl_relaxed(its_base + GITS_CTLR); | |
2183 | ctlr &= ~GITS_CTLR_ITS_NUMBER; | |
2184 | ctlr |= its_number << GITS_CTLR_ITS_NUMBER_SHIFT; | |
2185 | writel_relaxed(ctlr, its_base + GITS_CTLR); | |
2186 | ctlr = readl_relaxed(its_base + GITS_CTLR); | |
2187 | if ((ctlr & GITS_CTLR_ITS_NUMBER) != (its_number << GITS_CTLR_ITS_NUMBER_SHIFT)) { | |
2188 | its_number = ctlr & GITS_CTLR_ITS_NUMBER; | |
2189 | its_number >>= GITS_CTLR_ITS_NUMBER_SHIFT; | |
2190 | } | |
2191 | ||
2192 | if (test_and_set_bit(its_number, &its_list_map)) { | |
2193 | pr_err("ITS@%pa: Duplicate ITSList entry %d\n", | |
2194 | &res->start, its_number); | |
2195 | return -EINVAL; | |
2196 | } | |
2197 | ||
2198 | return its_number; | |
2199 | } | |
2200 | ||
db40f0a7 TN |
2201 | static int __init its_probe_one(struct resource *res, |
2202 | struct fwnode_handle *handle, int numa_node) | |
4c21f3c2 | 2203 | { |
4c21f3c2 MZ |
2204 | struct its_node *its; |
2205 | void __iomem *its_base; | |
3dfa576b MZ |
2206 | u32 val, ctlr; |
2207 | u64 baser, tmp, typer; | |
4c21f3c2 MZ |
2208 | int err; |
2209 | ||
db40f0a7 | 2210 | its_base = ioremap(res->start, resource_size(res)); |
4c21f3c2 | 2211 | if (!its_base) { |
db40f0a7 | 2212 | pr_warn("ITS@%pa: Unable to map ITS registers\n", &res->start); |
4c21f3c2 MZ |
2213 | return -ENOMEM; |
2214 | } | |
2215 | ||
2216 | val = readl_relaxed(its_base + GITS_PIDR2) & GIC_PIDR2_ARCH_MASK; | |
2217 | if (val != 0x30 && val != 0x40) { | |
db40f0a7 | 2218 | pr_warn("ITS@%pa: No ITS detected, giving up\n", &res->start); |
4c21f3c2 MZ |
2219 | err = -ENODEV; |
2220 | goto out_unmap; | |
2221 | } | |
2222 | ||
4559fbb3 YW |
2223 | err = its_force_quiescent(its_base); |
2224 | if (err) { | |
db40f0a7 | 2225 | pr_warn("ITS@%pa: Failed to quiesce, giving up\n", &res->start); |
4559fbb3 YW |
2226 | goto out_unmap; |
2227 | } | |
2228 | ||
db40f0a7 | 2229 | pr_info("ITS %pR\n", res); |
4c21f3c2 MZ |
2230 | |
2231 | its = kzalloc(sizeof(*its), GFP_KERNEL); | |
2232 | if (!its) { | |
2233 | err = -ENOMEM; | |
2234 | goto out_unmap; | |
2235 | } | |
2236 | ||
2237 | raw_spin_lock_init(&its->lock); | |
2238 | INIT_LIST_HEAD(&its->entry); | |
2239 | INIT_LIST_HEAD(&its->its_device_list); | |
3dfa576b | 2240 | typer = gic_read_typer(its_base + GITS_TYPER); |
4c21f3c2 | 2241 | its->base = its_base; |
db40f0a7 | 2242 | its->phys_base = res->start; |
3dfa576b MZ |
2243 | its->ite_size = GITS_TYPER_ITT_ENTRY_SIZE(typer); |
2244 | its->is_v4 = !!(typer & GITS_TYPER_VLPIS); | |
2245 | if (its->is_v4) { | |
2246 | if (!(typer & GITS_TYPER_VMOVP)) { | |
2247 | err = its_compute_its_list_map(res, its_base); | |
2248 | if (err < 0) | |
2249 | goto out_free_its; | |
2250 | ||
2251 | pr_info("ITS@%pa: Using ITS number %d\n", | |
2252 | &res->start, err); | |
2253 | } else { | |
2254 | pr_info("ITS@%pa: Single VMOVP capable\n", &res->start); | |
2255 | } | |
2256 | } | |
2257 | ||
db40f0a7 | 2258 | its->numa_node = numa_node; |
4c21f3c2 | 2259 | |
5bc13c2c RR |
2260 | its->cmd_base = (void *)__get_free_pages(GFP_KERNEL | __GFP_ZERO, |
2261 | get_order(ITS_CMD_QUEUE_SZ)); | |
4c21f3c2 MZ |
2262 | if (!its->cmd_base) { |
2263 | err = -ENOMEM; | |
2264 | goto out_free_its; | |
2265 | } | |
2266 | its->cmd_write = its->cmd_base; | |
2267 | ||
67510cca RR |
2268 | its_enable_quirks(its); |
2269 | ||
0e0b0f69 | 2270 | err = its_alloc_tables(its); |
4c21f3c2 MZ |
2271 | if (err) |
2272 | goto out_free_cmd; | |
2273 | ||
2274 | err = its_alloc_collections(its); | |
2275 | if (err) | |
2276 | goto out_free_tables; | |
2277 | ||
2278 | baser = (virt_to_phys(its->cmd_base) | | |
2fd632a0 | 2279 | GITS_CBASER_RaWaWb | |
4c21f3c2 MZ |
2280 | GITS_CBASER_InnerShareable | |
2281 | (ITS_CMD_QUEUE_SZ / SZ_4K - 1) | | |
2282 | GITS_CBASER_VALID); | |
2283 | ||
0968a619 VM |
2284 | gits_write_cbaser(baser, its->base + GITS_CBASER); |
2285 | tmp = gits_read_cbaser(its->base + GITS_CBASER); | |
4c21f3c2 | 2286 | |
4ad3e363 | 2287 | if ((tmp ^ baser) & GITS_CBASER_SHAREABILITY_MASK) { |
241a386c MZ |
2288 | if (!(tmp & GITS_CBASER_SHAREABILITY_MASK)) { |
2289 | /* | |
2290 | * The HW reports non-shareable, we must | |
2291 | * remove the cacheability attributes as | |
2292 | * well. | |
2293 | */ | |
2294 | baser &= ~(GITS_CBASER_SHAREABILITY_MASK | | |
2295 | GITS_CBASER_CACHEABILITY_MASK); | |
2296 | baser |= GITS_CBASER_nC; | |
0968a619 | 2297 | gits_write_cbaser(baser, its->base + GITS_CBASER); |
241a386c | 2298 | } |
4c21f3c2 MZ |
2299 | pr_info("ITS: using cache flushing for cmd queue\n"); |
2300 | its->flags |= ITS_FLAGS_CMDQ_NEEDS_FLUSHING; | |
2301 | } | |
2302 | ||
0968a619 | 2303 | gits_write_cwriter(0, its->base + GITS_CWRITER); |
3dfa576b MZ |
2304 | ctlr = readl_relaxed(its->base + GITS_CTLR); |
2305 | writel_relaxed(ctlr | GITS_CTLR_ENABLE, its->base + GITS_CTLR); | |
241a386c | 2306 | |
db40f0a7 | 2307 | err = its_init_domain(handle, its); |
d14ae5e6 TN |
2308 | if (err) |
2309 | goto out_free_tables; | |
4c21f3c2 MZ |
2310 | |
2311 | spin_lock(&its_lock); | |
2312 | list_add(&its->entry, &its_nodes); | |
2313 | spin_unlock(&its_lock); | |
2314 | ||
2315 | return 0; | |
2316 | ||
4c21f3c2 MZ |
2317 | out_free_tables: |
2318 | its_free_tables(its); | |
2319 | out_free_cmd: | |
5bc13c2c | 2320 | free_pages((unsigned long)its->cmd_base, get_order(ITS_CMD_QUEUE_SZ)); |
4c21f3c2 MZ |
2321 | out_free_its: |
2322 | kfree(its); | |
2323 | out_unmap: | |
2324 | iounmap(its_base); | |
db40f0a7 | 2325 | pr_err("ITS@%pa: failed probing (%d)\n", &res->start, err); |
4c21f3c2 MZ |
2326 | return err; |
2327 | } | |
2328 | ||
2329 | static bool gic_rdists_supports_plpis(void) | |
2330 | { | |
589ce5f4 | 2331 | return !!(gic_read_typer(gic_data_rdist_rd_base() + GICR_TYPER) & GICR_TYPER_PLPIS); |
4c21f3c2 MZ |
2332 | } |
2333 | ||
2334 | int its_cpu_init(void) | |
2335 | { | |
4c21f3c2 | 2336 | if (!list_empty(&its_nodes)) { |
16acae72 VM |
2337 | if (!gic_rdists_supports_plpis()) { |
2338 | pr_info("CPU%d: LPIs not supported\n", smp_processor_id()); | |
2339 | return -ENXIO; | |
2340 | } | |
4c21f3c2 MZ |
2341 | its_cpu_init_lpis(); |
2342 | its_cpu_init_collection(); | |
2343 | } | |
2344 | ||
2345 | return 0; | |
2346 | } | |
2347 | ||
935bba7c | 2348 | static const struct of_device_id its_device_id[] = { |
4c21f3c2 MZ |
2349 | { .compatible = "arm,gic-v3-its", }, |
2350 | {}, | |
2351 | }; | |
2352 | ||
db40f0a7 | 2353 | static int __init its_of_probe(struct device_node *node) |
4c21f3c2 MZ |
2354 | { |
2355 | struct device_node *np; | |
db40f0a7 | 2356 | struct resource res; |
4c21f3c2 MZ |
2357 | |
2358 | for (np = of_find_matching_node(node, its_device_id); np; | |
2359 | np = of_find_matching_node(np, its_device_id)) { | |
d14ae5e6 | 2360 | if (!of_property_read_bool(np, "msi-controller")) { |
e81f54c6 RH |
2361 | pr_warn("%pOF: no msi-controller property, ITS ignored\n", |
2362 | np); | |
d14ae5e6 TN |
2363 | continue; |
2364 | } | |
2365 | ||
db40f0a7 | 2366 | if (of_address_to_resource(np, 0, &res)) { |
e81f54c6 | 2367 | pr_warn("%pOF: no regs?\n", np); |
db40f0a7 TN |
2368 | continue; |
2369 | } | |
2370 | ||
2371 | its_probe_one(&res, &np->fwnode, of_node_to_nid(np)); | |
4c21f3c2 | 2372 | } |
db40f0a7 TN |
2373 | return 0; |
2374 | } | |
2375 | ||
3f010cf1 TN |
2376 | #ifdef CONFIG_ACPI |
2377 | ||
2378 | #define ACPI_GICV3_ITS_MEM_SIZE (SZ_128K) | |
2379 | ||
dbd2b826 GK |
2380 | #if defined(CONFIG_ACPI_NUMA) && (ACPI_CA_VERSION >= 0x20170531) |
2381 | struct its_srat_map { | |
2382 | /* numa node id */ | |
2383 | u32 numa_node; | |
2384 | /* GIC ITS ID */ | |
2385 | u32 its_id; | |
2386 | }; | |
2387 | ||
2388 | static struct its_srat_map its_srat_maps[MAX_NUMNODES] __initdata; | |
2389 | static int its_in_srat __initdata; | |
2390 | ||
2391 | static int __init acpi_get_its_numa_node(u32 its_id) | |
2392 | { | |
2393 | int i; | |
2394 | ||
2395 | for (i = 0; i < its_in_srat; i++) { | |
2396 | if (its_id == its_srat_maps[i].its_id) | |
2397 | return its_srat_maps[i].numa_node; | |
2398 | } | |
2399 | return NUMA_NO_NODE; | |
2400 | } | |
2401 | ||
2402 | static int __init gic_acpi_parse_srat_its(struct acpi_subtable_header *header, | |
2403 | const unsigned long end) | |
2404 | { | |
2405 | int node; | |
2406 | struct acpi_srat_gic_its_affinity *its_affinity; | |
2407 | ||
2408 | its_affinity = (struct acpi_srat_gic_its_affinity *)header; | |
2409 | if (!its_affinity) | |
2410 | return -EINVAL; | |
2411 | ||
2412 | if (its_affinity->header.length < sizeof(*its_affinity)) { | |
2413 | pr_err("SRAT: Invalid header length %d in ITS affinity\n", | |
2414 | its_affinity->header.length); | |
2415 | return -EINVAL; | |
2416 | } | |
2417 | ||
2418 | if (its_in_srat >= MAX_NUMNODES) { | |
2419 | pr_err("SRAT: ITS affinity exceeding max count[%d]\n", | |
2420 | MAX_NUMNODES); | |
2421 | return -EINVAL; | |
2422 | } | |
2423 | ||
2424 | node = acpi_map_pxm_to_node(its_affinity->proximity_domain); | |
2425 | ||
2426 | if (node == NUMA_NO_NODE || node >= MAX_NUMNODES) { | |
2427 | pr_err("SRAT: Invalid NUMA node %d in ITS affinity\n", node); | |
2428 | return 0; | |
2429 | } | |
2430 | ||
2431 | its_srat_maps[its_in_srat].numa_node = node; | |
2432 | its_srat_maps[its_in_srat].its_id = its_affinity->its_id; | |
2433 | its_in_srat++; | |
2434 | pr_info("SRAT: PXM %d -> ITS %d -> Node %d\n", | |
2435 | its_affinity->proximity_domain, its_affinity->its_id, node); | |
2436 | ||
2437 | return 0; | |
2438 | } | |
2439 | ||
2440 | static void __init acpi_table_parse_srat_its(void) | |
2441 | { | |
2442 | acpi_table_parse_entries(ACPI_SIG_SRAT, | |
2443 | sizeof(struct acpi_table_srat), | |
2444 | ACPI_SRAT_TYPE_GIC_ITS_AFFINITY, | |
2445 | gic_acpi_parse_srat_its, 0); | |
2446 | } | |
2447 | #else | |
2448 | static void __init acpi_table_parse_srat_its(void) { } | |
2449 | static int __init acpi_get_its_numa_node(u32 its_id) { return NUMA_NO_NODE; } | |
2450 | #endif | |
2451 | ||
3f010cf1 TN |
2452 | static int __init gic_acpi_parse_madt_its(struct acpi_subtable_header *header, |
2453 | const unsigned long end) | |
2454 | { | |
2455 | struct acpi_madt_generic_translator *its_entry; | |
2456 | struct fwnode_handle *dom_handle; | |
2457 | struct resource res; | |
2458 | int err; | |
2459 | ||
2460 | its_entry = (struct acpi_madt_generic_translator *)header; | |
2461 | memset(&res, 0, sizeof(res)); | |
2462 | res.start = its_entry->base_address; | |
2463 | res.end = its_entry->base_address + ACPI_GICV3_ITS_MEM_SIZE - 1; | |
2464 | res.flags = IORESOURCE_MEM; | |
2465 | ||
2466 | dom_handle = irq_domain_alloc_fwnode((void *)its_entry->base_address); | |
2467 | if (!dom_handle) { | |
2468 | pr_err("ITS@%pa: Unable to allocate GICv3 ITS domain token\n", | |
2469 | &res.start); | |
2470 | return -ENOMEM; | |
2471 | } | |
2472 | ||
2473 | err = iort_register_domain_token(its_entry->translation_id, dom_handle); | |
2474 | if (err) { | |
2475 | pr_err("ITS@%pa: Unable to register GICv3 ITS domain token (ITS ID %d) to IORT\n", | |
2476 | &res.start, its_entry->translation_id); | |
2477 | goto dom_err; | |
2478 | } | |
2479 | ||
dbd2b826 GK |
2480 | err = its_probe_one(&res, dom_handle, |
2481 | acpi_get_its_numa_node(its_entry->translation_id)); | |
3f010cf1 TN |
2482 | if (!err) |
2483 | return 0; | |
2484 | ||
2485 | iort_deregister_domain_token(its_entry->translation_id); | |
2486 | dom_err: | |
2487 | irq_domain_free_fwnode(dom_handle); | |
2488 | return err; | |
2489 | } | |
2490 | ||
2491 | static void __init its_acpi_probe(void) | |
2492 | { | |
dbd2b826 | 2493 | acpi_table_parse_srat_its(); |
3f010cf1 TN |
2494 | acpi_table_parse_madt(ACPI_MADT_TYPE_GENERIC_TRANSLATOR, |
2495 | gic_acpi_parse_madt_its, 0); | |
2496 | } | |
2497 | #else | |
2498 | static void __init its_acpi_probe(void) { } | |
2499 | #endif | |
2500 | ||
db40f0a7 TN |
2501 | int __init its_init(struct fwnode_handle *handle, struct rdists *rdists, |
2502 | struct irq_domain *parent_domain) | |
2503 | { | |
2504 | struct device_node *of_node; | |
8fff27ae MZ |
2505 | struct its_node *its; |
2506 | bool has_v4 = false; | |
2507 | int err; | |
db40f0a7 TN |
2508 | |
2509 | its_parent = parent_domain; | |
2510 | of_node = to_of_node(handle); | |
2511 | if (of_node) | |
2512 | its_of_probe(of_node); | |
2513 | else | |
3f010cf1 | 2514 | its_acpi_probe(); |
4c21f3c2 MZ |
2515 | |
2516 | if (list_empty(&its_nodes)) { | |
2517 | pr_warn("ITS: No ITS available, not enabling LPIs\n"); | |
2518 | return -ENXIO; | |
2519 | } | |
2520 | ||
2521 | gic_rdists = rdists; | |
8fff27ae MZ |
2522 | err = its_alloc_lpi_tables(); |
2523 | if (err) | |
2524 | return err; | |
2525 | ||
2526 | list_for_each_entry(its, &its_nodes, entry) | |
2527 | has_v4 |= its->is_v4; | |
2528 | ||
2529 | if (has_v4 & rdists->has_vlpis) { | |
2530 | if (its_init_vpe_domain()) { | |
2531 | rdists->has_vlpis = false; | |
2532 | pr_err("ITS: Disabling GICv4 support\n"); | |
2533 | } | |
2534 | } | |
2535 | ||
2536 | return 0; | |
4c21f3c2 | 2537 | } |