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021f6537 MZ |
1 | /* |
2 | * Copyright (C) 2013, 2014 ARM Limited, All Rights Reserved. | |
3 | * Author: Marc Zyngier <marc.zyngier@arm.com> | |
4 | * | |
5 | * This program is free software; you can redistribute it and/or modify | |
6 | * it under the terms of the GNU General Public License version 2 as | |
7 | * published by the Free Software Foundation. | |
8 | * | |
9 | * This program is distributed in the hope that it will be useful, | |
10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
12 | * GNU General Public License for more details. | |
13 | * | |
14 | * You should have received a copy of the GNU General Public License | |
15 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | |
16 | */ | |
17 | ||
ffa7d616 | 18 | #include <linux/acpi.h> |
021f6537 | 19 | #include <linux/cpu.h> |
3708d52f | 20 | #include <linux/cpu_pm.h> |
021f6537 MZ |
21 | #include <linux/delay.h> |
22 | #include <linux/interrupt.h> | |
ffa7d616 | 23 | #include <linux/irqdomain.h> |
021f6537 MZ |
24 | #include <linux/of.h> |
25 | #include <linux/of_address.h> | |
26 | #include <linux/of_irq.h> | |
27 | #include <linux/percpu.h> | |
28 | #include <linux/slab.h> | |
29 | ||
41a83e06 | 30 | #include <linux/irqchip.h> |
021f6537 | 31 | #include <linux/irqchip/arm-gic-v3.h> |
e3825ba1 | 32 | #include <linux/irqchip/irq-partition-percpu.h> |
021f6537 MZ |
33 | |
34 | #include <asm/cputype.h> | |
35 | #include <asm/exception.h> | |
36 | #include <asm/smp_plat.h> | |
0b6a3da9 | 37 | #include <asm/virt.h> |
021f6537 MZ |
38 | |
39 | #include "irq-gic-common.h" | |
021f6537 | 40 | |
f5c1434c MZ |
41 | struct redist_region { |
42 | void __iomem *redist_base; | |
43 | phys_addr_t phys_base; | |
b70fb7af | 44 | bool single_redist; |
f5c1434c MZ |
45 | }; |
46 | ||
021f6537 | 47 | struct gic_chip_data { |
e3825ba1 | 48 | struct fwnode_handle *fwnode; |
021f6537 | 49 | void __iomem *dist_base; |
f5c1434c MZ |
50 | struct redist_region *redist_regions; |
51 | struct rdists rdists; | |
021f6537 MZ |
52 | struct irq_domain *domain; |
53 | u64 redist_stride; | |
f5c1434c | 54 | u32 nr_redist_regions; |
021f6537 | 55 | unsigned int irq_nr; |
e3825ba1 | 56 | struct partition_desc *ppi_descs[16]; |
021f6537 MZ |
57 | }; |
58 | ||
59 | static struct gic_chip_data gic_data __read_mostly; | |
0b6a3da9 | 60 | static struct static_key supports_deactivate = STATIC_KEY_INIT_TRUE; |
021f6537 | 61 | |
f5c1434c MZ |
62 | #define gic_data_rdist() (this_cpu_ptr(gic_data.rdists.rdist)) |
63 | #define gic_data_rdist_rd_base() (gic_data_rdist()->rd_base) | |
021f6537 MZ |
64 | #define gic_data_rdist_sgi_base() (gic_data_rdist_rd_base() + SZ_64K) |
65 | ||
66 | /* Our default, arbitrary priority value. Linux only uses one anyway. */ | |
67 | #define DEFAULT_PMR_VALUE 0xf0 | |
68 | ||
69 | static inline unsigned int gic_irq(struct irq_data *d) | |
70 | { | |
71 | return d->hwirq; | |
72 | } | |
73 | ||
74 | static inline int gic_irq_in_rdist(struct irq_data *d) | |
75 | { | |
76 | return gic_irq(d) < 32; | |
77 | } | |
78 | ||
79 | static inline void __iomem *gic_dist_base(struct irq_data *d) | |
80 | { | |
81 | if (gic_irq_in_rdist(d)) /* SGI+PPI -> SGI_base for this CPU */ | |
82 | return gic_data_rdist_sgi_base(); | |
83 | ||
84 | if (d->hwirq <= 1023) /* SPI -> dist_base */ | |
85 | return gic_data.dist_base; | |
86 | ||
021f6537 MZ |
87 | return NULL; |
88 | } | |
89 | ||
90 | static void gic_do_wait_for_rwp(void __iomem *base) | |
91 | { | |
92 | u32 count = 1000000; /* 1s! */ | |
93 | ||
94 | while (readl_relaxed(base + GICD_CTLR) & GICD_CTLR_RWP) { | |
95 | count--; | |
96 | if (!count) { | |
97 | pr_err_ratelimited("RWP timeout, gone fishing\n"); | |
98 | return; | |
99 | } | |
100 | cpu_relax(); | |
101 | udelay(1); | |
102 | }; | |
103 | } | |
104 | ||
105 | /* Wait for completion of a distributor change */ | |
106 | static void gic_dist_wait_for_rwp(void) | |
107 | { | |
108 | gic_do_wait_for_rwp(gic_data.dist_base); | |
109 | } | |
110 | ||
111 | /* Wait for completion of a redistributor change */ | |
112 | static void gic_redist_wait_for_rwp(void) | |
113 | { | |
114 | gic_do_wait_for_rwp(gic_data_rdist_rd_base()); | |
115 | } | |
116 | ||
7936e914 | 117 | #ifdef CONFIG_ARM64 |
8ac2a170 | 118 | static DEFINE_STATIC_KEY_FALSE(is_cavium_thunderx); |
6d4e11c5 RR |
119 | |
120 | static u64 __maybe_unused gic_read_iar(void) | |
121 | { | |
8ac2a170 | 122 | if (static_branch_unlikely(&is_cavium_thunderx)) |
6d4e11c5 RR |
123 | return gic_read_iar_cavium_thunderx(); |
124 | else | |
125 | return gic_read_iar_common(); | |
126 | } | |
7936e914 | 127 | #endif |
021f6537 | 128 | |
a2c22510 | 129 | static void gic_enable_redist(bool enable) |
021f6537 MZ |
130 | { |
131 | void __iomem *rbase; | |
132 | u32 count = 1000000; /* 1s! */ | |
133 | u32 val; | |
134 | ||
135 | rbase = gic_data_rdist_rd_base(); | |
136 | ||
021f6537 | 137 | val = readl_relaxed(rbase + GICR_WAKER); |
a2c22510 SH |
138 | if (enable) |
139 | /* Wake up this CPU redistributor */ | |
140 | val &= ~GICR_WAKER_ProcessorSleep; | |
141 | else | |
142 | val |= GICR_WAKER_ProcessorSleep; | |
021f6537 MZ |
143 | writel_relaxed(val, rbase + GICR_WAKER); |
144 | ||
a2c22510 SH |
145 | if (!enable) { /* Check that GICR_WAKER is writeable */ |
146 | val = readl_relaxed(rbase + GICR_WAKER); | |
147 | if (!(val & GICR_WAKER_ProcessorSleep)) | |
148 | return; /* No PM support in this redistributor */ | |
149 | } | |
150 | ||
151 | while (count--) { | |
152 | val = readl_relaxed(rbase + GICR_WAKER); | |
153 | if (enable ^ (val & GICR_WAKER_ChildrenAsleep)) | |
154 | break; | |
021f6537 MZ |
155 | cpu_relax(); |
156 | udelay(1); | |
157 | }; | |
a2c22510 SH |
158 | if (!count) |
159 | pr_err_ratelimited("redistributor failed to %s...\n", | |
160 | enable ? "wakeup" : "sleep"); | |
021f6537 MZ |
161 | } |
162 | ||
163 | /* | |
164 | * Routines to disable, enable, EOI and route interrupts | |
165 | */ | |
b594c6e2 MZ |
166 | static int gic_peek_irq(struct irq_data *d, u32 offset) |
167 | { | |
168 | u32 mask = 1 << (gic_irq(d) % 32); | |
169 | void __iomem *base; | |
170 | ||
171 | if (gic_irq_in_rdist(d)) | |
172 | base = gic_data_rdist_sgi_base(); | |
173 | else | |
174 | base = gic_data.dist_base; | |
175 | ||
176 | return !!(readl_relaxed(base + offset + (gic_irq(d) / 32) * 4) & mask); | |
177 | } | |
178 | ||
021f6537 MZ |
179 | static void gic_poke_irq(struct irq_data *d, u32 offset) |
180 | { | |
181 | u32 mask = 1 << (gic_irq(d) % 32); | |
182 | void (*rwp_wait)(void); | |
183 | void __iomem *base; | |
184 | ||
185 | if (gic_irq_in_rdist(d)) { | |
186 | base = gic_data_rdist_sgi_base(); | |
187 | rwp_wait = gic_redist_wait_for_rwp; | |
188 | } else { | |
189 | base = gic_data.dist_base; | |
190 | rwp_wait = gic_dist_wait_for_rwp; | |
191 | } | |
192 | ||
193 | writel_relaxed(mask, base + offset + (gic_irq(d) / 32) * 4); | |
194 | rwp_wait(); | |
195 | } | |
196 | ||
021f6537 MZ |
197 | static void gic_mask_irq(struct irq_data *d) |
198 | { | |
199 | gic_poke_irq(d, GICD_ICENABLER); | |
200 | } | |
201 | ||
0b6a3da9 MZ |
202 | static void gic_eoimode1_mask_irq(struct irq_data *d) |
203 | { | |
204 | gic_mask_irq(d); | |
530bf353 MZ |
205 | /* |
206 | * When masking a forwarded interrupt, make sure it is | |
207 | * deactivated as well. | |
208 | * | |
209 | * This ensures that an interrupt that is getting | |
210 | * disabled/masked will not get "stuck", because there is | |
211 | * noone to deactivate it (guest is being terminated). | |
212 | */ | |
4df7f54d | 213 | if (irqd_is_forwarded_to_vcpu(d)) |
530bf353 | 214 | gic_poke_irq(d, GICD_ICACTIVER); |
0b6a3da9 MZ |
215 | } |
216 | ||
021f6537 MZ |
217 | static void gic_unmask_irq(struct irq_data *d) |
218 | { | |
219 | gic_poke_irq(d, GICD_ISENABLER); | |
220 | } | |
221 | ||
b594c6e2 MZ |
222 | static int gic_irq_set_irqchip_state(struct irq_data *d, |
223 | enum irqchip_irq_state which, bool val) | |
224 | { | |
225 | u32 reg; | |
226 | ||
227 | if (d->hwirq >= gic_data.irq_nr) /* PPI/SPI only */ | |
228 | return -EINVAL; | |
229 | ||
230 | switch (which) { | |
231 | case IRQCHIP_STATE_PENDING: | |
232 | reg = val ? GICD_ISPENDR : GICD_ICPENDR; | |
233 | break; | |
234 | ||
235 | case IRQCHIP_STATE_ACTIVE: | |
236 | reg = val ? GICD_ISACTIVER : GICD_ICACTIVER; | |
237 | break; | |
238 | ||
239 | case IRQCHIP_STATE_MASKED: | |
240 | reg = val ? GICD_ICENABLER : GICD_ISENABLER; | |
241 | break; | |
242 | ||
243 | default: | |
244 | return -EINVAL; | |
245 | } | |
246 | ||
247 | gic_poke_irq(d, reg); | |
248 | return 0; | |
249 | } | |
250 | ||
251 | static int gic_irq_get_irqchip_state(struct irq_data *d, | |
252 | enum irqchip_irq_state which, bool *val) | |
253 | { | |
254 | if (d->hwirq >= gic_data.irq_nr) /* PPI/SPI only */ | |
255 | return -EINVAL; | |
256 | ||
257 | switch (which) { | |
258 | case IRQCHIP_STATE_PENDING: | |
259 | *val = gic_peek_irq(d, GICD_ISPENDR); | |
260 | break; | |
261 | ||
262 | case IRQCHIP_STATE_ACTIVE: | |
263 | *val = gic_peek_irq(d, GICD_ISACTIVER); | |
264 | break; | |
265 | ||
266 | case IRQCHIP_STATE_MASKED: | |
267 | *val = !gic_peek_irq(d, GICD_ISENABLER); | |
268 | break; | |
269 | ||
270 | default: | |
271 | return -EINVAL; | |
272 | } | |
273 | ||
274 | return 0; | |
275 | } | |
276 | ||
021f6537 MZ |
277 | static void gic_eoi_irq(struct irq_data *d) |
278 | { | |
279 | gic_write_eoir(gic_irq(d)); | |
280 | } | |
281 | ||
0b6a3da9 MZ |
282 | static void gic_eoimode1_eoi_irq(struct irq_data *d) |
283 | { | |
284 | /* | |
530bf353 MZ |
285 | * No need to deactivate an LPI, or an interrupt that |
286 | * is is getting forwarded to a vcpu. | |
0b6a3da9 | 287 | */ |
4df7f54d | 288 | if (gic_irq(d) >= 8192 || irqd_is_forwarded_to_vcpu(d)) |
0b6a3da9 MZ |
289 | return; |
290 | gic_write_dir(gic_irq(d)); | |
291 | } | |
292 | ||
021f6537 MZ |
293 | static int gic_set_type(struct irq_data *d, unsigned int type) |
294 | { | |
295 | unsigned int irq = gic_irq(d); | |
296 | void (*rwp_wait)(void); | |
297 | void __iomem *base; | |
298 | ||
299 | /* Interrupt configuration for SGIs can't be changed */ | |
300 | if (irq < 16) | |
301 | return -EINVAL; | |
302 | ||
fb7e7deb LD |
303 | /* SPIs have restrictions on the supported types */ |
304 | if (irq >= 32 && type != IRQ_TYPE_LEVEL_HIGH && | |
305 | type != IRQ_TYPE_EDGE_RISING) | |
021f6537 MZ |
306 | return -EINVAL; |
307 | ||
308 | if (gic_irq_in_rdist(d)) { | |
309 | base = gic_data_rdist_sgi_base(); | |
310 | rwp_wait = gic_redist_wait_for_rwp; | |
311 | } else { | |
312 | base = gic_data.dist_base; | |
313 | rwp_wait = gic_dist_wait_for_rwp; | |
314 | } | |
315 | ||
fb7e7deb | 316 | return gic_configure_irq(irq, type, base, rwp_wait); |
021f6537 MZ |
317 | } |
318 | ||
530bf353 MZ |
319 | static int gic_irq_set_vcpu_affinity(struct irq_data *d, void *vcpu) |
320 | { | |
4df7f54d TG |
321 | if (vcpu) |
322 | irqd_set_forwarded_to_vcpu(d); | |
323 | else | |
324 | irqd_clr_forwarded_to_vcpu(d); | |
530bf353 MZ |
325 | return 0; |
326 | } | |
327 | ||
f6c86a41 | 328 | static u64 gic_mpidr_to_affinity(unsigned long mpidr) |
021f6537 MZ |
329 | { |
330 | u64 aff; | |
331 | ||
f6c86a41 | 332 | aff = ((u64)MPIDR_AFFINITY_LEVEL(mpidr, 3) << 32 | |
021f6537 MZ |
333 | MPIDR_AFFINITY_LEVEL(mpidr, 2) << 16 | |
334 | MPIDR_AFFINITY_LEVEL(mpidr, 1) << 8 | | |
335 | MPIDR_AFFINITY_LEVEL(mpidr, 0)); | |
336 | ||
337 | return aff; | |
338 | } | |
339 | ||
340 | static asmlinkage void __exception_irq_entry gic_handle_irq(struct pt_regs *regs) | |
341 | { | |
f6c86a41 | 342 | u32 irqnr; |
021f6537 MZ |
343 | |
344 | do { | |
345 | irqnr = gic_read_iar(); | |
346 | ||
da33f31d | 347 | if (likely(irqnr > 15 && irqnr < 1020) || irqnr >= 8192) { |
ebc6de00 | 348 | int err; |
0b6a3da9 MZ |
349 | |
350 | if (static_key_true(&supports_deactivate)) | |
351 | gic_write_eoir(irqnr); | |
352 | ||
ebc6de00 MZ |
353 | err = handle_domain_irq(gic_data.domain, irqnr, regs); |
354 | if (err) { | |
da33f31d | 355 | WARN_ONCE(true, "Unexpected interrupt received!\n"); |
0b6a3da9 MZ |
356 | if (static_key_true(&supports_deactivate)) { |
357 | if (irqnr < 8192) | |
358 | gic_write_dir(irqnr); | |
359 | } else { | |
360 | gic_write_eoir(irqnr); | |
361 | } | |
021f6537 | 362 | } |
ebc6de00 | 363 | continue; |
021f6537 MZ |
364 | } |
365 | if (irqnr < 16) { | |
366 | gic_write_eoir(irqnr); | |
0b6a3da9 MZ |
367 | if (static_key_true(&supports_deactivate)) |
368 | gic_write_dir(irqnr); | |
021f6537 | 369 | #ifdef CONFIG_SMP |
f86c4fbd WD |
370 | /* |
371 | * Unlike GICv2, we don't need an smp_rmb() here. | |
372 | * The control dependency from gic_read_iar to | |
373 | * the ISB in gic_write_eoir is enough to ensure | |
374 | * that any shared data read by handle_IPI will | |
375 | * be read after the ACK. | |
376 | */ | |
021f6537 MZ |
377 | handle_IPI(irqnr, regs); |
378 | #else | |
379 | WARN_ONCE(true, "Unexpected SGI received!\n"); | |
380 | #endif | |
381 | continue; | |
382 | } | |
383 | } while (irqnr != ICC_IAR1_EL1_SPURIOUS); | |
384 | } | |
385 | ||
386 | static void __init gic_dist_init(void) | |
387 | { | |
388 | unsigned int i; | |
389 | u64 affinity; | |
390 | void __iomem *base = gic_data.dist_base; | |
391 | ||
392 | /* Disable the distributor */ | |
393 | writel_relaxed(0, base + GICD_CTLR); | |
394 | gic_dist_wait_for_rwp(); | |
395 | ||
396 | gic_dist_config(base, gic_data.irq_nr, gic_dist_wait_for_rwp); | |
397 | ||
398 | /* Enable distributor with ARE, Group1 */ | |
399 | writel_relaxed(GICD_CTLR_ARE_NS | GICD_CTLR_ENABLE_G1A | GICD_CTLR_ENABLE_G1, | |
400 | base + GICD_CTLR); | |
401 | ||
402 | /* | |
403 | * Set all global interrupts to the boot CPU only. ARE must be | |
404 | * enabled. | |
405 | */ | |
406 | affinity = gic_mpidr_to_affinity(cpu_logical_map(smp_processor_id())); | |
407 | for (i = 32; i < gic_data.irq_nr; i++) | |
72c97126 | 408 | gic_write_irouter(affinity, base + GICD_IROUTER + i * 8); |
021f6537 MZ |
409 | } |
410 | ||
411 | static int gic_populate_rdist(void) | |
412 | { | |
f6c86a41 | 413 | unsigned long mpidr = cpu_logical_map(smp_processor_id()); |
021f6537 MZ |
414 | u64 typer; |
415 | u32 aff; | |
416 | int i; | |
417 | ||
418 | /* | |
419 | * Convert affinity to a 32bit value that can be matched to | |
420 | * GICR_TYPER bits [63:32]. | |
421 | */ | |
422 | aff = (MPIDR_AFFINITY_LEVEL(mpidr, 3) << 24 | | |
423 | MPIDR_AFFINITY_LEVEL(mpidr, 2) << 16 | | |
424 | MPIDR_AFFINITY_LEVEL(mpidr, 1) << 8 | | |
425 | MPIDR_AFFINITY_LEVEL(mpidr, 0)); | |
426 | ||
f5c1434c MZ |
427 | for (i = 0; i < gic_data.nr_redist_regions; i++) { |
428 | void __iomem *ptr = gic_data.redist_regions[i].redist_base; | |
021f6537 MZ |
429 | u32 reg; |
430 | ||
431 | reg = readl_relaxed(ptr + GICR_PIDR2) & GIC_PIDR2_ARCH_MASK; | |
432 | if (reg != GIC_PIDR2_ARCH_GICv3 && | |
433 | reg != GIC_PIDR2_ARCH_GICv4) { /* We're in trouble... */ | |
434 | pr_warn("No redistributor present @%p\n", ptr); | |
435 | break; | |
436 | } | |
437 | ||
438 | do { | |
72c97126 | 439 | typer = gic_read_typer(ptr + GICR_TYPER); |
021f6537 | 440 | if ((typer >> 32) == aff) { |
f5c1434c | 441 | u64 offset = ptr - gic_data.redist_regions[i].redist_base; |
021f6537 | 442 | gic_data_rdist_rd_base() = ptr; |
f5c1434c | 443 | gic_data_rdist()->phys_base = gic_data.redist_regions[i].phys_base + offset; |
f6c86a41 JPB |
444 | pr_info("CPU%d: found redistributor %lx region %d:%pa\n", |
445 | smp_processor_id(), mpidr, i, | |
446 | &gic_data_rdist()->phys_base); | |
021f6537 MZ |
447 | return 0; |
448 | } | |
449 | ||
b70fb7af TN |
450 | if (gic_data.redist_regions[i].single_redist) |
451 | break; | |
452 | ||
021f6537 MZ |
453 | if (gic_data.redist_stride) { |
454 | ptr += gic_data.redist_stride; | |
455 | } else { | |
456 | ptr += SZ_64K * 2; /* Skip RD_base + SGI_base */ | |
457 | if (typer & GICR_TYPER_VLPIS) | |
458 | ptr += SZ_64K * 2; /* Skip VLPI_base + reserved page */ | |
459 | } | |
460 | } while (!(typer & GICR_TYPER_LAST)); | |
461 | } | |
462 | ||
463 | /* We couldn't even deal with ourselves... */ | |
f6c86a41 JPB |
464 | WARN(true, "CPU%d: mpidr %lx has no re-distributor!\n", |
465 | smp_processor_id(), mpidr); | |
021f6537 MZ |
466 | return -ENODEV; |
467 | } | |
468 | ||
3708d52f SH |
469 | static void gic_cpu_sys_reg_init(void) |
470 | { | |
7cabd008 MZ |
471 | /* |
472 | * Need to check that the SRE bit has actually been set. If | |
473 | * not, it means that SRE is disabled at EL2. We're going to | |
474 | * die painfully, and there is nothing we can do about it. | |
475 | * | |
476 | * Kindly inform the luser. | |
477 | */ | |
478 | if (!gic_enable_sre()) | |
479 | pr_err("GIC: unable to set SRE (disabled at EL2), panic ahead\n"); | |
3708d52f SH |
480 | |
481 | /* Set priority mask register */ | |
482 | gic_write_pmr(DEFAULT_PMR_VALUE); | |
483 | ||
0b6a3da9 MZ |
484 | if (static_key_true(&supports_deactivate)) { |
485 | /* EOI drops priority only (mode 1) */ | |
486 | gic_write_ctlr(ICC_CTLR_EL1_EOImode_drop); | |
487 | } else { | |
488 | /* EOI deactivates interrupt too (mode 0) */ | |
489 | gic_write_ctlr(ICC_CTLR_EL1_EOImode_drop_dir); | |
490 | } | |
3708d52f SH |
491 | |
492 | /* ... and let's hit the road... */ | |
493 | gic_write_grpen1(1); | |
494 | } | |
495 | ||
da33f31d MZ |
496 | static int gic_dist_supports_lpis(void) |
497 | { | |
498 | return !!(readl_relaxed(gic_data.dist_base + GICD_TYPER) & GICD_TYPER_LPIS); | |
499 | } | |
500 | ||
021f6537 MZ |
501 | static void gic_cpu_init(void) |
502 | { | |
503 | void __iomem *rbase; | |
504 | ||
505 | /* Register ourselves with the rest of the world */ | |
506 | if (gic_populate_rdist()) | |
507 | return; | |
508 | ||
a2c22510 | 509 | gic_enable_redist(true); |
021f6537 MZ |
510 | |
511 | rbase = gic_data_rdist_sgi_base(); | |
512 | ||
513 | gic_cpu_config(rbase, gic_redist_wait_for_rwp); | |
514 | ||
da33f31d MZ |
515 | /* Give LPIs a spin */ |
516 | if (IS_ENABLED(CONFIG_ARM_GIC_V3_ITS) && gic_dist_supports_lpis()) | |
517 | its_cpu_init(); | |
518 | ||
3708d52f SH |
519 | /* initialise system registers */ |
520 | gic_cpu_sys_reg_init(); | |
021f6537 MZ |
521 | } |
522 | ||
523 | #ifdef CONFIG_SMP | |
524 | static int gic_secondary_init(struct notifier_block *nfb, | |
525 | unsigned long action, void *hcpu) | |
526 | { | |
527 | if (action == CPU_STARTING || action == CPU_STARTING_FROZEN) | |
528 | gic_cpu_init(); | |
529 | return NOTIFY_OK; | |
530 | } | |
531 | ||
532 | /* | |
533 | * Notifier for enabling the GIC CPU interface. Set an arbitrarily high | |
534 | * priority because the GIC needs to be up before the ARM generic timers. | |
535 | */ | |
536 | static struct notifier_block gic_cpu_notifier = { | |
537 | .notifier_call = gic_secondary_init, | |
538 | .priority = 100, | |
539 | }; | |
540 | ||
541 | static u16 gic_compute_target_list(int *base_cpu, const struct cpumask *mask, | |
f6c86a41 | 542 | unsigned long cluster_id) |
021f6537 MZ |
543 | { |
544 | int cpu = *base_cpu; | |
f6c86a41 | 545 | unsigned long mpidr = cpu_logical_map(cpu); |
021f6537 MZ |
546 | u16 tlist = 0; |
547 | ||
548 | while (cpu < nr_cpu_ids) { | |
549 | /* | |
550 | * If we ever get a cluster of more than 16 CPUs, just | |
551 | * scream and skip that CPU. | |
552 | */ | |
553 | if (WARN_ON((mpidr & 0xff) >= 16)) | |
554 | goto out; | |
555 | ||
556 | tlist |= 1 << (mpidr & 0xf); | |
557 | ||
558 | cpu = cpumask_next(cpu, mask); | |
614be385 | 559 | if (cpu >= nr_cpu_ids) |
021f6537 MZ |
560 | goto out; |
561 | ||
562 | mpidr = cpu_logical_map(cpu); | |
563 | ||
564 | if (cluster_id != (mpidr & ~0xffUL)) { | |
565 | cpu--; | |
566 | goto out; | |
567 | } | |
568 | } | |
569 | out: | |
570 | *base_cpu = cpu; | |
571 | return tlist; | |
572 | } | |
573 | ||
7e580278 AP |
574 | #define MPIDR_TO_SGI_AFFINITY(cluster_id, level) \ |
575 | (MPIDR_AFFINITY_LEVEL(cluster_id, level) \ | |
576 | << ICC_SGI1R_AFFINITY_## level ##_SHIFT) | |
577 | ||
021f6537 MZ |
578 | static void gic_send_sgi(u64 cluster_id, u16 tlist, unsigned int irq) |
579 | { | |
580 | u64 val; | |
581 | ||
7e580278 AP |
582 | val = (MPIDR_TO_SGI_AFFINITY(cluster_id, 3) | |
583 | MPIDR_TO_SGI_AFFINITY(cluster_id, 2) | | |
584 | irq << ICC_SGI1R_SGI_ID_SHIFT | | |
585 | MPIDR_TO_SGI_AFFINITY(cluster_id, 1) | | |
586 | tlist << ICC_SGI1R_TARGET_LIST_SHIFT); | |
021f6537 MZ |
587 | |
588 | pr_debug("CPU%d: ICC_SGI1R_EL1 %llx\n", smp_processor_id(), val); | |
589 | gic_write_sgi1r(val); | |
590 | } | |
591 | ||
592 | static void gic_raise_softirq(const struct cpumask *mask, unsigned int irq) | |
593 | { | |
594 | int cpu; | |
595 | ||
596 | if (WARN_ON(irq >= 16)) | |
597 | return; | |
598 | ||
599 | /* | |
600 | * Ensure that stores to Normal memory are visible to the | |
601 | * other CPUs before issuing the IPI. | |
602 | */ | |
603 | smp_wmb(); | |
604 | ||
f9b531fe | 605 | for_each_cpu(cpu, mask) { |
f6c86a41 | 606 | unsigned long cluster_id = cpu_logical_map(cpu) & ~0xffUL; |
021f6537 MZ |
607 | u16 tlist; |
608 | ||
609 | tlist = gic_compute_target_list(&cpu, mask, cluster_id); | |
610 | gic_send_sgi(cluster_id, tlist, irq); | |
611 | } | |
612 | ||
613 | /* Force the above writes to ICC_SGI1R_EL1 to be executed */ | |
614 | isb(); | |
615 | } | |
616 | ||
617 | static void gic_smp_init(void) | |
618 | { | |
619 | set_smp_cross_call(gic_raise_softirq); | |
620 | register_cpu_notifier(&gic_cpu_notifier); | |
621 | } | |
622 | ||
623 | static int gic_set_affinity(struct irq_data *d, const struct cpumask *mask_val, | |
624 | bool force) | |
625 | { | |
626 | unsigned int cpu = cpumask_any_and(mask_val, cpu_online_mask); | |
627 | void __iomem *reg; | |
628 | int enabled; | |
629 | u64 val; | |
630 | ||
631 | if (gic_irq_in_rdist(d)) | |
632 | return -EINVAL; | |
633 | ||
634 | /* If interrupt was enabled, disable it first */ | |
635 | enabled = gic_peek_irq(d, GICD_ISENABLER); | |
636 | if (enabled) | |
637 | gic_mask_irq(d); | |
638 | ||
639 | reg = gic_dist_base(d) + GICD_IROUTER + (gic_irq(d) * 8); | |
640 | val = gic_mpidr_to_affinity(cpu_logical_map(cpu)); | |
641 | ||
72c97126 | 642 | gic_write_irouter(val, reg); |
021f6537 MZ |
643 | |
644 | /* | |
645 | * If the interrupt was enabled, enabled it again. Otherwise, | |
646 | * just wait for the distributor to have digested our changes. | |
647 | */ | |
648 | if (enabled) | |
649 | gic_unmask_irq(d); | |
650 | else | |
651 | gic_dist_wait_for_rwp(); | |
652 | ||
0fc6fa29 | 653 | return IRQ_SET_MASK_OK_DONE; |
021f6537 MZ |
654 | } |
655 | #else | |
656 | #define gic_set_affinity NULL | |
657 | #define gic_smp_init() do { } while(0) | |
658 | #endif | |
659 | ||
3708d52f SH |
660 | #ifdef CONFIG_CPU_PM |
661 | static int gic_cpu_pm_notifier(struct notifier_block *self, | |
662 | unsigned long cmd, void *v) | |
663 | { | |
664 | if (cmd == CPU_PM_EXIT) { | |
665 | gic_enable_redist(true); | |
666 | gic_cpu_sys_reg_init(); | |
667 | } else if (cmd == CPU_PM_ENTER) { | |
668 | gic_write_grpen1(0); | |
669 | gic_enable_redist(false); | |
670 | } | |
671 | return NOTIFY_OK; | |
672 | } | |
673 | ||
674 | static struct notifier_block gic_cpu_pm_notifier_block = { | |
675 | .notifier_call = gic_cpu_pm_notifier, | |
676 | }; | |
677 | ||
678 | static void gic_cpu_pm_init(void) | |
679 | { | |
680 | cpu_pm_register_notifier(&gic_cpu_pm_notifier_block); | |
681 | } | |
682 | ||
683 | #else | |
684 | static inline void gic_cpu_pm_init(void) { } | |
685 | #endif /* CONFIG_CPU_PM */ | |
686 | ||
021f6537 MZ |
687 | static struct irq_chip gic_chip = { |
688 | .name = "GICv3", | |
689 | .irq_mask = gic_mask_irq, | |
690 | .irq_unmask = gic_unmask_irq, | |
691 | .irq_eoi = gic_eoi_irq, | |
692 | .irq_set_type = gic_set_type, | |
693 | .irq_set_affinity = gic_set_affinity, | |
b594c6e2 MZ |
694 | .irq_get_irqchip_state = gic_irq_get_irqchip_state, |
695 | .irq_set_irqchip_state = gic_irq_set_irqchip_state, | |
55963c9f | 696 | .flags = IRQCHIP_SET_TYPE_MASKED, |
021f6537 MZ |
697 | }; |
698 | ||
0b6a3da9 MZ |
699 | static struct irq_chip gic_eoimode1_chip = { |
700 | .name = "GICv3", | |
701 | .irq_mask = gic_eoimode1_mask_irq, | |
702 | .irq_unmask = gic_unmask_irq, | |
703 | .irq_eoi = gic_eoimode1_eoi_irq, | |
704 | .irq_set_type = gic_set_type, | |
705 | .irq_set_affinity = gic_set_affinity, | |
706 | .irq_get_irqchip_state = gic_irq_get_irqchip_state, | |
707 | .irq_set_irqchip_state = gic_irq_set_irqchip_state, | |
530bf353 | 708 | .irq_set_vcpu_affinity = gic_irq_set_vcpu_affinity, |
0b6a3da9 MZ |
709 | .flags = IRQCHIP_SET_TYPE_MASKED, |
710 | }; | |
711 | ||
da33f31d MZ |
712 | #define GIC_ID_NR (1U << gic_data.rdists.id_bits) |
713 | ||
021f6537 MZ |
714 | static int gic_irq_domain_map(struct irq_domain *d, unsigned int irq, |
715 | irq_hw_number_t hw) | |
716 | { | |
0b6a3da9 MZ |
717 | struct irq_chip *chip = &gic_chip; |
718 | ||
719 | if (static_key_true(&supports_deactivate)) | |
720 | chip = &gic_eoimode1_chip; | |
721 | ||
021f6537 MZ |
722 | /* SGIs are private to the core kernel */ |
723 | if (hw < 16) | |
724 | return -EPERM; | |
da33f31d MZ |
725 | /* Nothing here */ |
726 | if (hw >= gic_data.irq_nr && hw < 8192) | |
727 | return -EPERM; | |
728 | /* Off limits */ | |
729 | if (hw >= GIC_ID_NR) | |
730 | return -EPERM; | |
731 | ||
021f6537 MZ |
732 | /* PPIs */ |
733 | if (hw < 32) { | |
734 | irq_set_percpu_devid(irq); | |
0b6a3da9 | 735 | irq_domain_set_info(d, irq, hw, chip, d->host_data, |
443acc4f | 736 | handle_percpu_devid_irq, NULL, NULL); |
d17cab44 | 737 | irq_set_status_flags(irq, IRQ_NOAUTOEN); |
021f6537 MZ |
738 | } |
739 | /* SPIs */ | |
740 | if (hw >= 32 && hw < gic_data.irq_nr) { | |
0b6a3da9 | 741 | irq_domain_set_info(d, irq, hw, chip, d->host_data, |
443acc4f | 742 | handle_fasteoi_irq, NULL, NULL); |
d17cab44 | 743 | irq_set_probe(irq); |
021f6537 | 744 | } |
da33f31d MZ |
745 | /* LPIs */ |
746 | if (hw >= 8192 && hw < GIC_ID_NR) { | |
747 | if (!gic_dist_supports_lpis()) | |
748 | return -EPERM; | |
0b6a3da9 | 749 | irq_domain_set_info(d, irq, hw, chip, d->host_data, |
da33f31d | 750 | handle_fasteoi_irq, NULL, NULL); |
da33f31d MZ |
751 | } |
752 | ||
021f6537 MZ |
753 | return 0; |
754 | } | |
755 | ||
f833f57f MZ |
756 | static int gic_irq_domain_translate(struct irq_domain *d, |
757 | struct irq_fwspec *fwspec, | |
758 | unsigned long *hwirq, | |
759 | unsigned int *type) | |
021f6537 | 760 | { |
f833f57f MZ |
761 | if (is_of_node(fwspec->fwnode)) { |
762 | if (fwspec->param_count < 3) | |
763 | return -EINVAL; | |
021f6537 | 764 | |
db8c70ec MZ |
765 | switch (fwspec->param[0]) { |
766 | case 0: /* SPI */ | |
767 | *hwirq = fwspec->param[1] + 32; | |
768 | break; | |
769 | case 1: /* PPI */ | |
770 | *hwirq = fwspec->param[1] + 16; | |
771 | break; | |
772 | case GIC_IRQ_TYPE_LPI: /* LPI */ | |
773 | *hwirq = fwspec->param[1]; | |
774 | break; | |
775 | default: | |
776 | return -EINVAL; | |
777 | } | |
f833f57f MZ |
778 | |
779 | *type = fwspec->param[2] & IRQ_TYPE_SENSE_MASK; | |
780 | return 0; | |
021f6537 MZ |
781 | } |
782 | ||
ffa7d616 TN |
783 | if (is_fwnode_irqchip(fwspec->fwnode)) { |
784 | if(fwspec->param_count != 2) | |
785 | return -EINVAL; | |
786 | ||
787 | *hwirq = fwspec->param[0]; | |
788 | *type = fwspec->param[1]; | |
789 | return 0; | |
790 | } | |
791 | ||
f833f57f | 792 | return -EINVAL; |
021f6537 MZ |
793 | } |
794 | ||
443acc4f MZ |
795 | static int gic_irq_domain_alloc(struct irq_domain *domain, unsigned int virq, |
796 | unsigned int nr_irqs, void *arg) | |
797 | { | |
798 | int i, ret; | |
799 | irq_hw_number_t hwirq; | |
800 | unsigned int type = IRQ_TYPE_NONE; | |
f833f57f | 801 | struct irq_fwspec *fwspec = arg; |
443acc4f | 802 | |
f833f57f | 803 | ret = gic_irq_domain_translate(domain, fwspec, &hwirq, &type); |
443acc4f MZ |
804 | if (ret) |
805 | return ret; | |
806 | ||
807 | for (i = 0; i < nr_irqs; i++) | |
808 | gic_irq_domain_map(domain, virq + i, hwirq + i); | |
809 | ||
810 | return 0; | |
811 | } | |
812 | ||
813 | static void gic_irq_domain_free(struct irq_domain *domain, unsigned int virq, | |
814 | unsigned int nr_irqs) | |
815 | { | |
816 | int i; | |
817 | ||
818 | for (i = 0; i < nr_irqs; i++) { | |
819 | struct irq_data *d = irq_domain_get_irq_data(domain, virq + i); | |
820 | irq_set_handler(virq + i, NULL); | |
821 | irq_domain_reset_irq_data(d); | |
822 | } | |
823 | } | |
824 | ||
e3825ba1 MZ |
825 | static int gic_irq_domain_select(struct irq_domain *d, |
826 | struct irq_fwspec *fwspec, | |
827 | enum irq_domain_bus_token bus_token) | |
828 | { | |
829 | /* Not for us */ | |
830 | if (fwspec->fwnode != d->fwnode) | |
831 | return 0; | |
832 | ||
833 | /* If this is not DT, then we have a single domain */ | |
834 | if (!is_of_node(fwspec->fwnode)) | |
835 | return 1; | |
836 | ||
837 | /* | |
838 | * If this is a PPI and we have a 4th (non-null) parameter, | |
839 | * then we need to match the partition domain. | |
840 | */ | |
841 | if (fwspec->param_count >= 4 && | |
842 | fwspec->param[0] == 1 && fwspec->param[3] != 0) | |
843 | return d == partition_get_domain(gic_data.ppi_descs[fwspec->param[1]]); | |
844 | ||
845 | return d == gic_data.domain; | |
846 | } | |
847 | ||
021f6537 | 848 | static const struct irq_domain_ops gic_irq_domain_ops = { |
f833f57f | 849 | .translate = gic_irq_domain_translate, |
443acc4f MZ |
850 | .alloc = gic_irq_domain_alloc, |
851 | .free = gic_irq_domain_free, | |
e3825ba1 MZ |
852 | .select = gic_irq_domain_select, |
853 | }; | |
854 | ||
855 | static int partition_domain_translate(struct irq_domain *d, | |
856 | struct irq_fwspec *fwspec, | |
857 | unsigned long *hwirq, | |
858 | unsigned int *type) | |
859 | { | |
860 | struct device_node *np; | |
861 | int ret; | |
862 | ||
863 | np = of_find_node_by_phandle(fwspec->param[3]); | |
864 | if (WARN_ON(!np)) | |
865 | return -EINVAL; | |
866 | ||
867 | ret = partition_translate_id(gic_data.ppi_descs[fwspec->param[1]], | |
868 | of_node_to_fwnode(np)); | |
869 | if (ret < 0) | |
870 | return ret; | |
871 | ||
872 | *hwirq = ret; | |
873 | *type = fwspec->param[2] & IRQ_TYPE_SENSE_MASK; | |
874 | ||
875 | return 0; | |
876 | } | |
877 | ||
878 | static const struct irq_domain_ops partition_domain_ops = { | |
879 | .translate = partition_domain_translate, | |
880 | .select = gic_irq_domain_select, | |
021f6537 MZ |
881 | }; |
882 | ||
6d4e11c5 RR |
883 | static void gicv3_enable_quirks(void) |
884 | { | |
7936e914 | 885 | #ifdef CONFIG_ARM64 |
6d4e11c5 | 886 | if (cpus_have_cap(ARM64_WORKAROUND_CAVIUM_23154)) |
8ac2a170 | 887 | static_branch_enable(&is_cavium_thunderx); |
7936e914 | 888 | #endif |
6d4e11c5 RR |
889 | } |
890 | ||
db57d746 TN |
891 | static int __init gic_init_bases(void __iomem *dist_base, |
892 | struct redist_region *rdist_regs, | |
893 | u32 nr_redist_regions, | |
894 | u64 redist_stride, | |
895 | struct fwnode_handle *handle) | |
021f6537 | 896 | { |
db57d746 | 897 | struct device_node *node; |
f5c1434c | 898 | u32 typer; |
021f6537 MZ |
899 | int gic_irqs; |
900 | int err; | |
021f6537 | 901 | |
0b6a3da9 MZ |
902 | if (!is_hyp_mode_available()) |
903 | static_key_slow_dec(&supports_deactivate); | |
904 | ||
905 | if (static_key_true(&supports_deactivate)) | |
906 | pr_info("GIC: Using split EOI/Deactivate mode\n"); | |
907 | ||
e3825ba1 | 908 | gic_data.fwnode = handle; |
021f6537 | 909 | gic_data.dist_base = dist_base; |
f5c1434c MZ |
910 | gic_data.redist_regions = rdist_regs; |
911 | gic_data.nr_redist_regions = nr_redist_regions; | |
021f6537 MZ |
912 | gic_data.redist_stride = redist_stride; |
913 | ||
6d4e11c5 RR |
914 | gicv3_enable_quirks(); |
915 | ||
021f6537 MZ |
916 | /* |
917 | * Find out how many interrupts are supported. | |
918 | * The GIC only supports up to 1020 interrupt sources (SGI+PPI+SPI) | |
919 | */ | |
f5c1434c MZ |
920 | typer = readl_relaxed(gic_data.dist_base + GICD_TYPER); |
921 | gic_data.rdists.id_bits = GICD_TYPER_ID_BITS(typer); | |
922 | gic_irqs = GICD_TYPER_IRQS(typer); | |
021f6537 MZ |
923 | if (gic_irqs > 1020) |
924 | gic_irqs = 1020; | |
925 | gic_data.irq_nr = gic_irqs; | |
926 | ||
db57d746 TN |
927 | gic_data.domain = irq_domain_create_tree(handle, &gic_irq_domain_ops, |
928 | &gic_data); | |
f5c1434c | 929 | gic_data.rdists.rdist = alloc_percpu(typeof(*gic_data.rdists.rdist)); |
021f6537 | 930 | |
f5c1434c | 931 | if (WARN_ON(!gic_data.domain) || WARN_ON(!gic_data.rdists.rdist)) { |
021f6537 MZ |
932 | err = -ENOMEM; |
933 | goto out_free; | |
934 | } | |
935 | ||
936 | set_handle_irq(gic_handle_irq); | |
937 | ||
db57d746 TN |
938 | node = to_of_node(handle); |
939 | if (IS_ENABLED(CONFIG_ARM_GIC_V3_ITS) && gic_dist_supports_lpis() && | |
940 | node) /* Temp hack to prevent ITS init for ACPI */ | |
da33f31d MZ |
941 | its_init(node, &gic_data.rdists, gic_data.domain); |
942 | ||
021f6537 MZ |
943 | gic_smp_init(); |
944 | gic_dist_init(); | |
945 | gic_cpu_init(); | |
3708d52f | 946 | gic_cpu_pm_init(); |
021f6537 MZ |
947 | |
948 | return 0; | |
949 | ||
950 | out_free: | |
951 | if (gic_data.domain) | |
952 | irq_domain_remove(gic_data.domain); | |
f5c1434c | 953 | free_percpu(gic_data.rdists.rdist); |
db57d746 TN |
954 | return err; |
955 | } | |
956 | ||
957 | static int __init gic_validate_dist_version(void __iomem *dist_base) | |
958 | { | |
959 | u32 reg = readl_relaxed(dist_base + GICD_PIDR2) & GIC_PIDR2_ARCH_MASK; | |
960 | ||
961 | if (reg != GIC_PIDR2_ARCH_GICv3 && reg != GIC_PIDR2_ARCH_GICv4) | |
962 | return -ENODEV; | |
963 | ||
964 | return 0; | |
965 | } | |
966 | ||
e3825ba1 MZ |
967 | static int get_cpu_number(struct device_node *dn) |
968 | { | |
969 | const __be32 *cell; | |
970 | u64 hwid; | |
971 | int i; | |
972 | ||
973 | cell = of_get_property(dn, "reg", NULL); | |
974 | if (!cell) | |
975 | return -1; | |
976 | ||
977 | hwid = of_read_number(cell, of_n_addr_cells(dn)); | |
978 | ||
979 | /* | |
980 | * Non affinity bits must be set to 0 in the DT | |
981 | */ | |
982 | if (hwid & ~MPIDR_HWID_BITMASK) | |
983 | return -1; | |
984 | ||
985 | for (i = 0; i < num_possible_cpus(); i++) | |
986 | if (cpu_logical_map(i) == hwid) | |
987 | return i; | |
988 | ||
989 | return -1; | |
990 | } | |
991 | ||
992 | /* Create all possible partitions at boot time */ | |
993 | static void gic_populate_ppi_partitions(struct device_node *gic_node) | |
994 | { | |
995 | struct device_node *parts_node, *child_part; | |
996 | int part_idx = 0, i; | |
997 | int nr_parts; | |
998 | struct partition_affinity *parts; | |
999 | ||
1000 | parts_node = of_find_node_by_name(gic_node, "ppi-partitions"); | |
1001 | if (!parts_node) | |
1002 | return; | |
1003 | ||
1004 | nr_parts = of_get_child_count(parts_node); | |
1005 | ||
1006 | if (!nr_parts) | |
1007 | return; | |
1008 | ||
1009 | parts = kzalloc(sizeof(*parts) * nr_parts, GFP_KERNEL); | |
1010 | if (WARN_ON(!parts)) | |
1011 | return; | |
1012 | ||
1013 | for_each_child_of_node(parts_node, child_part) { | |
1014 | struct partition_affinity *part; | |
1015 | int n; | |
1016 | ||
1017 | part = &parts[part_idx]; | |
1018 | ||
1019 | part->partition_id = of_node_to_fwnode(child_part); | |
1020 | ||
1021 | pr_info("GIC: PPI partition %s[%d] { ", | |
1022 | child_part->name, part_idx); | |
1023 | ||
1024 | n = of_property_count_elems_of_size(child_part, "affinity", | |
1025 | sizeof(u32)); | |
1026 | WARN_ON(n <= 0); | |
1027 | ||
1028 | for (i = 0; i < n; i++) { | |
1029 | int err, cpu; | |
1030 | u32 cpu_phandle; | |
1031 | struct device_node *cpu_node; | |
1032 | ||
1033 | err = of_property_read_u32_index(child_part, "affinity", | |
1034 | i, &cpu_phandle); | |
1035 | if (WARN_ON(err)) | |
1036 | continue; | |
1037 | ||
1038 | cpu_node = of_find_node_by_phandle(cpu_phandle); | |
1039 | if (WARN_ON(!cpu_node)) | |
1040 | continue; | |
1041 | ||
1042 | cpu = get_cpu_number(cpu_node); | |
1043 | if (WARN_ON(cpu == -1)) | |
1044 | continue; | |
1045 | ||
1046 | pr_cont("%s[%d] ", cpu_node->full_name, cpu); | |
1047 | ||
1048 | cpumask_set_cpu(cpu, &part->mask); | |
1049 | } | |
1050 | ||
1051 | pr_cont("}\n"); | |
1052 | part_idx++; | |
1053 | } | |
1054 | ||
1055 | for (i = 0; i < 16; i++) { | |
1056 | unsigned int irq; | |
1057 | struct partition_desc *desc; | |
1058 | struct irq_fwspec ppi_fwspec = { | |
1059 | .fwnode = gic_data.fwnode, | |
1060 | .param_count = 3, | |
1061 | .param = { | |
1062 | [0] = 1, | |
1063 | [1] = i, | |
1064 | [2] = IRQ_TYPE_NONE, | |
1065 | }, | |
1066 | }; | |
1067 | ||
1068 | irq = irq_create_fwspec_mapping(&ppi_fwspec); | |
1069 | if (WARN_ON(!irq)) | |
1070 | continue; | |
1071 | desc = partition_create_desc(gic_data.fwnode, parts, nr_parts, | |
1072 | irq, &partition_domain_ops); | |
1073 | if (WARN_ON(!desc)) | |
1074 | continue; | |
1075 | ||
1076 | gic_data.ppi_descs[i] = desc; | |
1077 | } | |
1078 | } | |
1079 | ||
db57d746 TN |
1080 | static int __init gic_of_init(struct device_node *node, struct device_node *parent) |
1081 | { | |
1082 | void __iomem *dist_base; | |
1083 | struct redist_region *rdist_regs; | |
1084 | u64 redist_stride; | |
1085 | u32 nr_redist_regions; | |
1086 | int err, i; | |
1087 | ||
1088 | dist_base = of_iomap(node, 0); | |
1089 | if (!dist_base) { | |
1090 | pr_err("%s: unable to map gic dist registers\n", | |
1091 | node->full_name); | |
1092 | return -ENXIO; | |
1093 | } | |
1094 | ||
1095 | err = gic_validate_dist_version(dist_base); | |
1096 | if (err) { | |
1097 | pr_err("%s: no distributor detected, giving up\n", | |
1098 | node->full_name); | |
1099 | goto out_unmap_dist; | |
1100 | } | |
1101 | ||
1102 | if (of_property_read_u32(node, "#redistributor-regions", &nr_redist_regions)) | |
1103 | nr_redist_regions = 1; | |
1104 | ||
1105 | rdist_regs = kzalloc(sizeof(*rdist_regs) * nr_redist_regions, GFP_KERNEL); | |
1106 | if (!rdist_regs) { | |
1107 | err = -ENOMEM; | |
1108 | goto out_unmap_dist; | |
1109 | } | |
1110 | ||
1111 | for (i = 0; i < nr_redist_regions; i++) { | |
1112 | struct resource res; | |
1113 | int ret; | |
1114 | ||
1115 | ret = of_address_to_resource(node, 1 + i, &res); | |
1116 | rdist_regs[i].redist_base = of_iomap(node, 1 + i); | |
1117 | if (ret || !rdist_regs[i].redist_base) { | |
1118 | pr_err("%s: couldn't map region %d\n", | |
1119 | node->full_name, i); | |
1120 | err = -ENODEV; | |
1121 | goto out_unmap_rdist; | |
1122 | } | |
1123 | rdist_regs[i].phys_base = res.start; | |
1124 | } | |
1125 | ||
1126 | if (of_property_read_u64(node, "redistributor-stride", &redist_stride)) | |
1127 | redist_stride = 0; | |
1128 | ||
1129 | err = gic_init_bases(dist_base, rdist_regs, nr_redist_regions, | |
1130 | redist_stride, &node->fwnode); | |
e3825ba1 MZ |
1131 | if (err) |
1132 | goto out_unmap_rdist; | |
1133 | ||
1134 | gic_populate_ppi_partitions(node); | |
1135 | return 0; | |
db57d746 | 1136 | |
021f6537 | 1137 | out_unmap_rdist: |
f5c1434c MZ |
1138 | for (i = 0; i < nr_redist_regions; i++) |
1139 | if (rdist_regs[i].redist_base) | |
1140 | iounmap(rdist_regs[i].redist_base); | |
1141 | kfree(rdist_regs); | |
021f6537 MZ |
1142 | out_unmap_dist: |
1143 | iounmap(dist_base); | |
1144 | return err; | |
1145 | } | |
1146 | ||
1147 | IRQCHIP_DECLARE(gic_v3, "arm,gic-v3", gic_of_init); | |
ffa7d616 TN |
1148 | |
1149 | #ifdef CONFIG_ACPI | |
b70fb7af | 1150 | static void __iomem *dist_base; |
ffa7d616 TN |
1151 | static struct redist_region *redist_regs __initdata; |
1152 | static u32 nr_redist_regions __initdata; | |
b70fb7af TN |
1153 | static bool single_redist; |
1154 | ||
1155 | static void __init | |
1156 | gic_acpi_register_redist(phys_addr_t phys_base, void __iomem *redist_base) | |
1157 | { | |
1158 | static int count = 0; | |
1159 | ||
1160 | redist_regs[count].phys_base = phys_base; | |
1161 | redist_regs[count].redist_base = redist_base; | |
1162 | redist_regs[count].single_redist = single_redist; | |
1163 | count++; | |
1164 | } | |
ffa7d616 TN |
1165 | |
1166 | static int __init | |
1167 | gic_acpi_parse_madt_redist(struct acpi_subtable_header *header, | |
1168 | const unsigned long end) | |
1169 | { | |
1170 | struct acpi_madt_generic_redistributor *redist = | |
1171 | (struct acpi_madt_generic_redistributor *)header; | |
1172 | void __iomem *redist_base; | |
ffa7d616 TN |
1173 | |
1174 | redist_base = ioremap(redist->base_address, redist->length); | |
1175 | if (!redist_base) { | |
1176 | pr_err("Couldn't map GICR region @%llx\n", redist->base_address); | |
1177 | return -ENOMEM; | |
1178 | } | |
1179 | ||
b70fb7af | 1180 | gic_acpi_register_redist(redist->base_address, redist_base); |
ffa7d616 TN |
1181 | return 0; |
1182 | } | |
1183 | ||
b70fb7af TN |
1184 | static int __init |
1185 | gic_acpi_parse_madt_gicc(struct acpi_subtable_header *header, | |
1186 | const unsigned long end) | |
1187 | { | |
1188 | struct acpi_madt_generic_interrupt *gicc = | |
1189 | (struct acpi_madt_generic_interrupt *)header; | |
1190 | u32 reg = readl_relaxed(dist_base + GICD_PIDR2) & GIC_PIDR2_ARCH_MASK; | |
1191 | u32 size = reg == GIC_PIDR2_ARCH_GICv4 ? SZ_64K * 4 : SZ_64K * 2; | |
1192 | void __iomem *redist_base; | |
1193 | ||
1194 | redist_base = ioremap(gicc->gicr_base_address, size); | |
1195 | if (!redist_base) | |
1196 | return -ENOMEM; | |
1197 | ||
1198 | gic_acpi_register_redist(gicc->gicr_base_address, redist_base); | |
1199 | return 0; | |
1200 | } | |
1201 | ||
1202 | static int __init gic_acpi_collect_gicr_base(void) | |
1203 | { | |
1204 | acpi_tbl_entry_handler redist_parser; | |
1205 | enum acpi_madt_type type; | |
1206 | ||
1207 | if (single_redist) { | |
1208 | type = ACPI_MADT_TYPE_GENERIC_INTERRUPT; | |
1209 | redist_parser = gic_acpi_parse_madt_gicc; | |
1210 | } else { | |
1211 | type = ACPI_MADT_TYPE_GENERIC_REDISTRIBUTOR; | |
1212 | redist_parser = gic_acpi_parse_madt_redist; | |
1213 | } | |
1214 | ||
1215 | /* Collect redistributor base addresses in GICR entries */ | |
1216 | if (acpi_table_parse_madt(type, redist_parser, 0) > 0) | |
1217 | return 0; | |
1218 | ||
1219 | pr_info("No valid GICR entries exist\n"); | |
1220 | return -ENODEV; | |
1221 | } | |
1222 | ||
ffa7d616 TN |
1223 | static int __init gic_acpi_match_gicr(struct acpi_subtable_header *header, |
1224 | const unsigned long end) | |
1225 | { | |
1226 | /* Subtable presence means that redist exists, that's it */ | |
1227 | return 0; | |
1228 | } | |
1229 | ||
b70fb7af TN |
1230 | static int __init gic_acpi_match_gicc(struct acpi_subtable_header *header, |
1231 | const unsigned long end) | |
1232 | { | |
1233 | struct acpi_madt_generic_interrupt *gicc = | |
1234 | (struct acpi_madt_generic_interrupt *)header; | |
1235 | ||
1236 | /* | |
1237 | * If GICC is enabled and has valid gicr base address, then it means | |
1238 | * GICR base is presented via GICC | |
1239 | */ | |
1240 | if ((gicc->flags & ACPI_MADT_ENABLED) && gicc->gicr_base_address) | |
1241 | return 0; | |
1242 | ||
1243 | return -ENODEV; | |
1244 | } | |
1245 | ||
1246 | static int __init gic_acpi_count_gicr_regions(void) | |
1247 | { | |
1248 | int count; | |
1249 | ||
1250 | /* | |
1251 | * Count how many redistributor regions we have. It is not allowed | |
1252 | * to mix redistributor description, GICR and GICC subtables have to be | |
1253 | * mutually exclusive. | |
1254 | */ | |
1255 | count = acpi_table_parse_madt(ACPI_MADT_TYPE_GENERIC_REDISTRIBUTOR, | |
1256 | gic_acpi_match_gicr, 0); | |
1257 | if (count > 0) { | |
1258 | single_redist = false; | |
1259 | return count; | |
1260 | } | |
1261 | ||
1262 | count = acpi_table_parse_madt(ACPI_MADT_TYPE_GENERIC_INTERRUPT, | |
1263 | gic_acpi_match_gicc, 0); | |
1264 | if (count > 0) | |
1265 | single_redist = true; | |
1266 | ||
1267 | return count; | |
1268 | } | |
1269 | ||
ffa7d616 TN |
1270 | static bool __init acpi_validate_gic_table(struct acpi_subtable_header *header, |
1271 | struct acpi_probe_entry *ape) | |
1272 | { | |
1273 | struct acpi_madt_generic_distributor *dist; | |
1274 | int count; | |
1275 | ||
1276 | dist = (struct acpi_madt_generic_distributor *)header; | |
1277 | if (dist->version != ape->driver_data) | |
1278 | return false; | |
1279 | ||
1280 | /* We need to do that exercise anyway, the sooner the better */ | |
b70fb7af | 1281 | count = gic_acpi_count_gicr_regions(); |
ffa7d616 TN |
1282 | if (count <= 0) |
1283 | return false; | |
1284 | ||
1285 | nr_redist_regions = count; | |
1286 | return true; | |
1287 | } | |
1288 | ||
1289 | #define ACPI_GICV3_DIST_MEM_SIZE (SZ_64K) | |
1290 | ||
1291 | static int __init | |
1292 | gic_acpi_init(struct acpi_subtable_header *header, const unsigned long end) | |
1293 | { | |
1294 | struct acpi_madt_generic_distributor *dist; | |
1295 | struct fwnode_handle *domain_handle; | |
b70fb7af | 1296 | int i, err; |
ffa7d616 TN |
1297 | |
1298 | /* Get distributor base address */ | |
1299 | dist = (struct acpi_madt_generic_distributor *)header; | |
1300 | dist_base = ioremap(dist->base_address, ACPI_GICV3_DIST_MEM_SIZE); | |
1301 | if (!dist_base) { | |
1302 | pr_err("Unable to map GICD registers\n"); | |
1303 | return -ENOMEM; | |
1304 | } | |
1305 | ||
1306 | err = gic_validate_dist_version(dist_base); | |
1307 | if (err) { | |
1308 | pr_err("No distributor detected at @%p, giving up", dist_base); | |
1309 | goto out_dist_unmap; | |
1310 | } | |
1311 | ||
1312 | redist_regs = kzalloc(sizeof(*redist_regs) * nr_redist_regions, | |
1313 | GFP_KERNEL); | |
1314 | if (!redist_regs) { | |
1315 | err = -ENOMEM; | |
1316 | goto out_dist_unmap; | |
1317 | } | |
1318 | ||
b70fb7af TN |
1319 | err = gic_acpi_collect_gicr_base(); |
1320 | if (err) | |
ffa7d616 | 1321 | goto out_redist_unmap; |
ffa7d616 TN |
1322 | |
1323 | domain_handle = irq_domain_alloc_fwnode(dist_base); | |
1324 | if (!domain_handle) { | |
1325 | err = -ENOMEM; | |
1326 | goto out_redist_unmap; | |
1327 | } | |
1328 | ||
1329 | err = gic_init_bases(dist_base, redist_regs, nr_redist_regions, 0, | |
1330 | domain_handle); | |
1331 | if (err) | |
1332 | goto out_fwhandle_free; | |
1333 | ||
1334 | acpi_set_irq_model(ACPI_IRQ_MODEL_GIC, domain_handle); | |
1335 | return 0; | |
1336 | ||
1337 | out_fwhandle_free: | |
1338 | irq_domain_free_fwnode(domain_handle); | |
1339 | out_redist_unmap: | |
1340 | for (i = 0; i < nr_redist_regions; i++) | |
1341 | if (redist_regs[i].redist_base) | |
1342 | iounmap(redist_regs[i].redist_base); | |
1343 | kfree(redist_regs); | |
1344 | out_dist_unmap: | |
1345 | iounmap(dist_base); | |
1346 | return err; | |
1347 | } | |
1348 | IRQCHIP_ACPI_DECLARE(gic_v3, ACPI_MADT_TYPE_GENERIC_DISTRIBUTOR, | |
1349 | acpi_validate_gic_table, ACPI_MADT_GIC_VERSION_V3, | |
1350 | gic_acpi_init); | |
1351 | IRQCHIP_ACPI_DECLARE(gic_v4, ACPI_MADT_TYPE_GENERIC_DISTRIBUTOR, | |
1352 | acpi_validate_gic_table, ACPI_MADT_GIC_VERSION_V4, | |
1353 | gic_acpi_init); | |
1354 | IRQCHIP_ACPI_DECLARE(gic_v3_or_v4, ACPI_MADT_TYPE_GENERIC_DISTRIBUTOR, | |
1355 | acpi_validate_gic_table, ACPI_MADT_GIC_VERSION_NONE, | |
1356 | gic_acpi_init); | |
1357 | #endif |