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021f6537 MZ |
1 | /* |
2 | * Copyright (C) 2013, 2014 ARM Limited, All Rights Reserved. | |
3 | * Author: Marc Zyngier <marc.zyngier@arm.com> | |
4 | * | |
5 | * This program is free software; you can redistribute it and/or modify | |
6 | * it under the terms of the GNU General Public License version 2 as | |
7 | * published by the Free Software Foundation. | |
8 | * | |
9 | * This program is distributed in the hope that it will be useful, | |
10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
12 | * GNU General Public License for more details. | |
13 | * | |
14 | * You should have received a copy of the GNU General Public License | |
15 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | |
16 | */ | |
17 | ||
18 | #include <linux/cpu.h> | |
3708d52f | 19 | #include <linux/cpu_pm.h> |
021f6537 MZ |
20 | #include <linux/delay.h> |
21 | #include <linux/interrupt.h> | |
22 | #include <linux/of.h> | |
23 | #include <linux/of_address.h> | |
24 | #include <linux/of_irq.h> | |
25 | #include <linux/percpu.h> | |
26 | #include <linux/slab.h> | |
27 | ||
41a83e06 | 28 | #include <linux/irqchip.h> |
021f6537 MZ |
29 | #include <linux/irqchip/arm-gic-v3.h> |
30 | ||
31 | #include <asm/cputype.h> | |
32 | #include <asm/exception.h> | |
33 | #include <asm/smp_plat.h> | |
0b6a3da9 | 34 | #include <asm/virt.h> |
021f6537 MZ |
35 | |
36 | #include "irq-gic-common.h" | |
021f6537 | 37 | |
f5c1434c MZ |
38 | struct redist_region { |
39 | void __iomem *redist_base; | |
40 | phys_addr_t phys_base; | |
41 | }; | |
42 | ||
021f6537 MZ |
43 | struct gic_chip_data { |
44 | void __iomem *dist_base; | |
f5c1434c MZ |
45 | struct redist_region *redist_regions; |
46 | struct rdists rdists; | |
021f6537 MZ |
47 | struct irq_domain *domain; |
48 | u64 redist_stride; | |
f5c1434c | 49 | u32 nr_redist_regions; |
021f6537 MZ |
50 | unsigned int irq_nr; |
51 | }; | |
52 | ||
53 | static struct gic_chip_data gic_data __read_mostly; | |
0b6a3da9 | 54 | static struct static_key supports_deactivate = STATIC_KEY_INIT_TRUE; |
021f6537 | 55 | |
f5c1434c MZ |
56 | #define gic_data_rdist() (this_cpu_ptr(gic_data.rdists.rdist)) |
57 | #define gic_data_rdist_rd_base() (gic_data_rdist()->rd_base) | |
021f6537 MZ |
58 | #define gic_data_rdist_sgi_base() (gic_data_rdist_rd_base() + SZ_64K) |
59 | ||
60 | /* Our default, arbitrary priority value. Linux only uses one anyway. */ | |
61 | #define DEFAULT_PMR_VALUE 0xf0 | |
62 | ||
63 | static inline unsigned int gic_irq(struct irq_data *d) | |
64 | { | |
65 | return d->hwirq; | |
66 | } | |
67 | ||
68 | static inline int gic_irq_in_rdist(struct irq_data *d) | |
69 | { | |
70 | return gic_irq(d) < 32; | |
71 | } | |
72 | ||
73 | static inline void __iomem *gic_dist_base(struct irq_data *d) | |
74 | { | |
75 | if (gic_irq_in_rdist(d)) /* SGI+PPI -> SGI_base for this CPU */ | |
76 | return gic_data_rdist_sgi_base(); | |
77 | ||
78 | if (d->hwirq <= 1023) /* SPI -> dist_base */ | |
79 | return gic_data.dist_base; | |
80 | ||
021f6537 MZ |
81 | return NULL; |
82 | } | |
83 | ||
84 | static void gic_do_wait_for_rwp(void __iomem *base) | |
85 | { | |
86 | u32 count = 1000000; /* 1s! */ | |
87 | ||
88 | while (readl_relaxed(base + GICD_CTLR) & GICD_CTLR_RWP) { | |
89 | count--; | |
90 | if (!count) { | |
91 | pr_err_ratelimited("RWP timeout, gone fishing\n"); | |
92 | return; | |
93 | } | |
94 | cpu_relax(); | |
95 | udelay(1); | |
96 | }; | |
97 | } | |
98 | ||
99 | /* Wait for completion of a distributor change */ | |
100 | static void gic_dist_wait_for_rwp(void) | |
101 | { | |
102 | gic_do_wait_for_rwp(gic_data.dist_base); | |
103 | } | |
104 | ||
105 | /* Wait for completion of a redistributor change */ | |
106 | static void gic_redist_wait_for_rwp(void) | |
107 | { | |
108 | gic_do_wait_for_rwp(gic_data_rdist_rd_base()); | |
109 | } | |
110 | ||
111 | /* Low level accessors */ | |
c44e9d77 | 112 | static u64 __maybe_unused gic_read_iar(void) |
021f6537 MZ |
113 | { |
114 | u64 irqstat; | |
115 | ||
72c58395 | 116 | asm volatile("mrs_s %0, " __stringify(ICC_IAR1_EL1) : "=r" (irqstat)); |
021f6537 MZ |
117 | return irqstat; |
118 | } | |
119 | ||
c44e9d77 | 120 | static void __maybe_unused gic_write_pmr(u64 val) |
021f6537 | 121 | { |
72c58395 | 122 | asm volatile("msr_s " __stringify(ICC_PMR_EL1) ", %0" : : "r" (val)); |
021f6537 MZ |
123 | } |
124 | ||
c44e9d77 | 125 | static void __maybe_unused gic_write_ctlr(u64 val) |
021f6537 | 126 | { |
72c58395 | 127 | asm volatile("msr_s " __stringify(ICC_CTLR_EL1) ", %0" : : "r" (val)); |
021f6537 MZ |
128 | isb(); |
129 | } | |
130 | ||
c44e9d77 | 131 | static void __maybe_unused gic_write_grpen1(u64 val) |
021f6537 | 132 | { |
72c58395 | 133 | asm volatile("msr_s " __stringify(ICC_GRPEN1_EL1) ", %0" : : "r" (val)); |
021f6537 MZ |
134 | isb(); |
135 | } | |
136 | ||
c44e9d77 | 137 | static void __maybe_unused gic_write_sgi1r(u64 val) |
021f6537 | 138 | { |
72c58395 | 139 | asm volatile("msr_s " __stringify(ICC_SGI1R_EL1) ", %0" : : "r" (val)); |
021f6537 MZ |
140 | } |
141 | ||
142 | static void gic_enable_sre(void) | |
143 | { | |
144 | u64 val; | |
145 | ||
72c58395 | 146 | asm volatile("mrs_s %0, " __stringify(ICC_SRE_EL1) : "=r" (val)); |
021f6537 | 147 | val |= ICC_SRE_EL1_SRE; |
72c58395 | 148 | asm volatile("msr_s " __stringify(ICC_SRE_EL1) ", %0" : : "r" (val)); |
021f6537 MZ |
149 | isb(); |
150 | ||
151 | /* | |
152 | * Need to check that the SRE bit has actually been set. If | |
153 | * not, it means that SRE is disabled at EL2. We're going to | |
154 | * die painfully, and there is nothing we can do about it. | |
155 | * | |
156 | * Kindly inform the luser. | |
157 | */ | |
72c58395 | 158 | asm volatile("mrs_s %0, " __stringify(ICC_SRE_EL1) : "=r" (val)); |
021f6537 MZ |
159 | if (!(val & ICC_SRE_EL1_SRE)) |
160 | pr_err("GIC: unable to set SRE (disabled at EL2), panic ahead\n"); | |
161 | } | |
162 | ||
a2c22510 | 163 | static void gic_enable_redist(bool enable) |
021f6537 MZ |
164 | { |
165 | void __iomem *rbase; | |
166 | u32 count = 1000000; /* 1s! */ | |
167 | u32 val; | |
168 | ||
169 | rbase = gic_data_rdist_rd_base(); | |
170 | ||
021f6537 | 171 | val = readl_relaxed(rbase + GICR_WAKER); |
a2c22510 SH |
172 | if (enable) |
173 | /* Wake up this CPU redistributor */ | |
174 | val &= ~GICR_WAKER_ProcessorSleep; | |
175 | else | |
176 | val |= GICR_WAKER_ProcessorSleep; | |
021f6537 MZ |
177 | writel_relaxed(val, rbase + GICR_WAKER); |
178 | ||
a2c22510 SH |
179 | if (!enable) { /* Check that GICR_WAKER is writeable */ |
180 | val = readl_relaxed(rbase + GICR_WAKER); | |
181 | if (!(val & GICR_WAKER_ProcessorSleep)) | |
182 | return; /* No PM support in this redistributor */ | |
183 | } | |
184 | ||
185 | while (count--) { | |
186 | val = readl_relaxed(rbase + GICR_WAKER); | |
187 | if (enable ^ (val & GICR_WAKER_ChildrenAsleep)) | |
188 | break; | |
021f6537 MZ |
189 | cpu_relax(); |
190 | udelay(1); | |
191 | }; | |
a2c22510 SH |
192 | if (!count) |
193 | pr_err_ratelimited("redistributor failed to %s...\n", | |
194 | enable ? "wakeup" : "sleep"); | |
021f6537 MZ |
195 | } |
196 | ||
197 | /* | |
198 | * Routines to disable, enable, EOI and route interrupts | |
199 | */ | |
b594c6e2 MZ |
200 | static int gic_peek_irq(struct irq_data *d, u32 offset) |
201 | { | |
202 | u32 mask = 1 << (gic_irq(d) % 32); | |
203 | void __iomem *base; | |
204 | ||
205 | if (gic_irq_in_rdist(d)) | |
206 | base = gic_data_rdist_sgi_base(); | |
207 | else | |
208 | base = gic_data.dist_base; | |
209 | ||
210 | return !!(readl_relaxed(base + offset + (gic_irq(d) / 32) * 4) & mask); | |
211 | } | |
212 | ||
021f6537 MZ |
213 | static void gic_poke_irq(struct irq_data *d, u32 offset) |
214 | { | |
215 | u32 mask = 1 << (gic_irq(d) % 32); | |
216 | void (*rwp_wait)(void); | |
217 | void __iomem *base; | |
218 | ||
219 | if (gic_irq_in_rdist(d)) { | |
220 | base = gic_data_rdist_sgi_base(); | |
221 | rwp_wait = gic_redist_wait_for_rwp; | |
222 | } else { | |
223 | base = gic_data.dist_base; | |
224 | rwp_wait = gic_dist_wait_for_rwp; | |
225 | } | |
226 | ||
227 | writel_relaxed(mask, base + offset + (gic_irq(d) / 32) * 4); | |
228 | rwp_wait(); | |
229 | } | |
230 | ||
021f6537 MZ |
231 | static void gic_mask_irq(struct irq_data *d) |
232 | { | |
233 | gic_poke_irq(d, GICD_ICENABLER); | |
234 | } | |
235 | ||
0b6a3da9 MZ |
236 | static void gic_eoimode1_mask_irq(struct irq_data *d) |
237 | { | |
238 | gic_mask_irq(d); | |
530bf353 MZ |
239 | /* |
240 | * When masking a forwarded interrupt, make sure it is | |
241 | * deactivated as well. | |
242 | * | |
243 | * This ensures that an interrupt that is getting | |
244 | * disabled/masked will not get "stuck", because there is | |
245 | * noone to deactivate it (guest is being terminated). | |
246 | */ | |
4df7f54d | 247 | if (irqd_is_forwarded_to_vcpu(d)) |
530bf353 | 248 | gic_poke_irq(d, GICD_ICACTIVER); |
0b6a3da9 MZ |
249 | } |
250 | ||
021f6537 MZ |
251 | static void gic_unmask_irq(struct irq_data *d) |
252 | { | |
253 | gic_poke_irq(d, GICD_ISENABLER); | |
254 | } | |
255 | ||
b594c6e2 MZ |
256 | static int gic_irq_set_irqchip_state(struct irq_data *d, |
257 | enum irqchip_irq_state which, bool val) | |
258 | { | |
259 | u32 reg; | |
260 | ||
261 | if (d->hwirq >= gic_data.irq_nr) /* PPI/SPI only */ | |
262 | return -EINVAL; | |
263 | ||
264 | switch (which) { | |
265 | case IRQCHIP_STATE_PENDING: | |
266 | reg = val ? GICD_ISPENDR : GICD_ICPENDR; | |
267 | break; | |
268 | ||
269 | case IRQCHIP_STATE_ACTIVE: | |
270 | reg = val ? GICD_ISACTIVER : GICD_ICACTIVER; | |
271 | break; | |
272 | ||
273 | case IRQCHIP_STATE_MASKED: | |
274 | reg = val ? GICD_ICENABLER : GICD_ISENABLER; | |
275 | break; | |
276 | ||
277 | default: | |
278 | return -EINVAL; | |
279 | } | |
280 | ||
281 | gic_poke_irq(d, reg); | |
282 | return 0; | |
283 | } | |
284 | ||
285 | static int gic_irq_get_irqchip_state(struct irq_data *d, | |
286 | enum irqchip_irq_state which, bool *val) | |
287 | { | |
288 | if (d->hwirq >= gic_data.irq_nr) /* PPI/SPI only */ | |
289 | return -EINVAL; | |
290 | ||
291 | switch (which) { | |
292 | case IRQCHIP_STATE_PENDING: | |
293 | *val = gic_peek_irq(d, GICD_ISPENDR); | |
294 | break; | |
295 | ||
296 | case IRQCHIP_STATE_ACTIVE: | |
297 | *val = gic_peek_irq(d, GICD_ISACTIVER); | |
298 | break; | |
299 | ||
300 | case IRQCHIP_STATE_MASKED: | |
301 | *val = !gic_peek_irq(d, GICD_ISENABLER); | |
302 | break; | |
303 | ||
304 | default: | |
305 | return -EINVAL; | |
306 | } | |
307 | ||
308 | return 0; | |
309 | } | |
310 | ||
021f6537 MZ |
311 | static void gic_eoi_irq(struct irq_data *d) |
312 | { | |
313 | gic_write_eoir(gic_irq(d)); | |
314 | } | |
315 | ||
0b6a3da9 MZ |
316 | static void gic_eoimode1_eoi_irq(struct irq_data *d) |
317 | { | |
318 | /* | |
530bf353 MZ |
319 | * No need to deactivate an LPI, or an interrupt that |
320 | * is is getting forwarded to a vcpu. | |
0b6a3da9 | 321 | */ |
4df7f54d | 322 | if (gic_irq(d) >= 8192 || irqd_is_forwarded_to_vcpu(d)) |
0b6a3da9 MZ |
323 | return; |
324 | gic_write_dir(gic_irq(d)); | |
325 | } | |
326 | ||
021f6537 MZ |
327 | static int gic_set_type(struct irq_data *d, unsigned int type) |
328 | { | |
329 | unsigned int irq = gic_irq(d); | |
330 | void (*rwp_wait)(void); | |
331 | void __iomem *base; | |
332 | ||
333 | /* Interrupt configuration for SGIs can't be changed */ | |
334 | if (irq < 16) | |
335 | return -EINVAL; | |
336 | ||
fb7e7deb LD |
337 | /* SPIs have restrictions on the supported types */ |
338 | if (irq >= 32 && type != IRQ_TYPE_LEVEL_HIGH && | |
339 | type != IRQ_TYPE_EDGE_RISING) | |
021f6537 MZ |
340 | return -EINVAL; |
341 | ||
342 | if (gic_irq_in_rdist(d)) { | |
343 | base = gic_data_rdist_sgi_base(); | |
344 | rwp_wait = gic_redist_wait_for_rwp; | |
345 | } else { | |
346 | base = gic_data.dist_base; | |
347 | rwp_wait = gic_dist_wait_for_rwp; | |
348 | } | |
349 | ||
fb7e7deb | 350 | return gic_configure_irq(irq, type, base, rwp_wait); |
021f6537 MZ |
351 | } |
352 | ||
530bf353 MZ |
353 | static int gic_irq_set_vcpu_affinity(struct irq_data *d, void *vcpu) |
354 | { | |
4df7f54d TG |
355 | if (vcpu) |
356 | irqd_set_forwarded_to_vcpu(d); | |
357 | else | |
358 | irqd_clr_forwarded_to_vcpu(d); | |
530bf353 MZ |
359 | return 0; |
360 | } | |
361 | ||
021f6537 MZ |
362 | static u64 gic_mpidr_to_affinity(u64 mpidr) |
363 | { | |
364 | u64 aff; | |
365 | ||
366 | aff = (MPIDR_AFFINITY_LEVEL(mpidr, 3) << 32 | | |
367 | MPIDR_AFFINITY_LEVEL(mpidr, 2) << 16 | | |
368 | MPIDR_AFFINITY_LEVEL(mpidr, 1) << 8 | | |
369 | MPIDR_AFFINITY_LEVEL(mpidr, 0)); | |
370 | ||
371 | return aff; | |
372 | } | |
373 | ||
374 | static asmlinkage void __exception_irq_entry gic_handle_irq(struct pt_regs *regs) | |
375 | { | |
376 | u64 irqnr; | |
377 | ||
378 | do { | |
379 | irqnr = gic_read_iar(); | |
380 | ||
da33f31d | 381 | if (likely(irqnr > 15 && irqnr < 1020) || irqnr >= 8192) { |
ebc6de00 | 382 | int err; |
0b6a3da9 MZ |
383 | |
384 | if (static_key_true(&supports_deactivate)) | |
385 | gic_write_eoir(irqnr); | |
386 | ||
ebc6de00 MZ |
387 | err = handle_domain_irq(gic_data.domain, irqnr, regs); |
388 | if (err) { | |
da33f31d | 389 | WARN_ONCE(true, "Unexpected interrupt received!\n"); |
0b6a3da9 MZ |
390 | if (static_key_true(&supports_deactivate)) { |
391 | if (irqnr < 8192) | |
392 | gic_write_dir(irqnr); | |
393 | } else { | |
394 | gic_write_eoir(irqnr); | |
395 | } | |
021f6537 | 396 | } |
ebc6de00 | 397 | continue; |
021f6537 MZ |
398 | } |
399 | if (irqnr < 16) { | |
400 | gic_write_eoir(irqnr); | |
0b6a3da9 MZ |
401 | if (static_key_true(&supports_deactivate)) |
402 | gic_write_dir(irqnr); | |
021f6537 MZ |
403 | #ifdef CONFIG_SMP |
404 | handle_IPI(irqnr, regs); | |
405 | #else | |
406 | WARN_ONCE(true, "Unexpected SGI received!\n"); | |
407 | #endif | |
408 | continue; | |
409 | } | |
410 | } while (irqnr != ICC_IAR1_EL1_SPURIOUS); | |
411 | } | |
412 | ||
413 | static void __init gic_dist_init(void) | |
414 | { | |
415 | unsigned int i; | |
416 | u64 affinity; | |
417 | void __iomem *base = gic_data.dist_base; | |
418 | ||
419 | /* Disable the distributor */ | |
420 | writel_relaxed(0, base + GICD_CTLR); | |
421 | gic_dist_wait_for_rwp(); | |
422 | ||
423 | gic_dist_config(base, gic_data.irq_nr, gic_dist_wait_for_rwp); | |
424 | ||
425 | /* Enable distributor with ARE, Group1 */ | |
426 | writel_relaxed(GICD_CTLR_ARE_NS | GICD_CTLR_ENABLE_G1A | GICD_CTLR_ENABLE_G1, | |
427 | base + GICD_CTLR); | |
428 | ||
429 | /* | |
430 | * Set all global interrupts to the boot CPU only. ARE must be | |
431 | * enabled. | |
432 | */ | |
433 | affinity = gic_mpidr_to_affinity(cpu_logical_map(smp_processor_id())); | |
434 | for (i = 32; i < gic_data.irq_nr; i++) | |
435 | writeq_relaxed(affinity, base + GICD_IROUTER + i * 8); | |
436 | } | |
437 | ||
438 | static int gic_populate_rdist(void) | |
439 | { | |
440 | u64 mpidr = cpu_logical_map(smp_processor_id()); | |
441 | u64 typer; | |
442 | u32 aff; | |
443 | int i; | |
444 | ||
445 | /* | |
446 | * Convert affinity to a 32bit value that can be matched to | |
447 | * GICR_TYPER bits [63:32]. | |
448 | */ | |
449 | aff = (MPIDR_AFFINITY_LEVEL(mpidr, 3) << 24 | | |
450 | MPIDR_AFFINITY_LEVEL(mpidr, 2) << 16 | | |
451 | MPIDR_AFFINITY_LEVEL(mpidr, 1) << 8 | | |
452 | MPIDR_AFFINITY_LEVEL(mpidr, 0)); | |
453 | ||
f5c1434c MZ |
454 | for (i = 0; i < gic_data.nr_redist_regions; i++) { |
455 | void __iomem *ptr = gic_data.redist_regions[i].redist_base; | |
021f6537 MZ |
456 | u32 reg; |
457 | ||
458 | reg = readl_relaxed(ptr + GICR_PIDR2) & GIC_PIDR2_ARCH_MASK; | |
459 | if (reg != GIC_PIDR2_ARCH_GICv3 && | |
460 | reg != GIC_PIDR2_ARCH_GICv4) { /* We're in trouble... */ | |
461 | pr_warn("No redistributor present @%p\n", ptr); | |
462 | break; | |
463 | } | |
464 | ||
465 | do { | |
466 | typer = readq_relaxed(ptr + GICR_TYPER); | |
467 | if ((typer >> 32) == aff) { | |
f5c1434c | 468 | u64 offset = ptr - gic_data.redist_regions[i].redist_base; |
021f6537 | 469 | gic_data_rdist_rd_base() = ptr; |
f5c1434c MZ |
470 | gic_data_rdist()->phys_base = gic_data.redist_regions[i].phys_base + offset; |
471 | pr_info("CPU%d: found redistributor %llx region %d:%pa\n", | |
021f6537 | 472 | smp_processor_id(), |
f5c1434c MZ |
473 | (unsigned long long)mpidr, |
474 | i, &gic_data_rdist()->phys_base); | |
021f6537 MZ |
475 | return 0; |
476 | } | |
477 | ||
478 | if (gic_data.redist_stride) { | |
479 | ptr += gic_data.redist_stride; | |
480 | } else { | |
481 | ptr += SZ_64K * 2; /* Skip RD_base + SGI_base */ | |
482 | if (typer & GICR_TYPER_VLPIS) | |
483 | ptr += SZ_64K * 2; /* Skip VLPI_base + reserved page */ | |
484 | } | |
485 | } while (!(typer & GICR_TYPER_LAST)); | |
486 | } | |
487 | ||
488 | /* We couldn't even deal with ourselves... */ | |
489 | WARN(true, "CPU%d: mpidr %llx has no re-distributor!\n", | |
490 | smp_processor_id(), (unsigned long long)mpidr); | |
491 | return -ENODEV; | |
492 | } | |
493 | ||
3708d52f SH |
494 | static void gic_cpu_sys_reg_init(void) |
495 | { | |
496 | /* Enable system registers */ | |
497 | gic_enable_sre(); | |
498 | ||
499 | /* Set priority mask register */ | |
500 | gic_write_pmr(DEFAULT_PMR_VALUE); | |
501 | ||
0b6a3da9 MZ |
502 | if (static_key_true(&supports_deactivate)) { |
503 | /* EOI drops priority only (mode 1) */ | |
504 | gic_write_ctlr(ICC_CTLR_EL1_EOImode_drop); | |
505 | } else { | |
506 | /* EOI deactivates interrupt too (mode 0) */ | |
507 | gic_write_ctlr(ICC_CTLR_EL1_EOImode_drop_dir); | |
508 | } | |
3708d52f SH |
509 | |
510 | /* ... and let's hit the road... */ | |
511 | gic_write_grpen1(1); | |
512 | } | |
513 | ||
da33f31d MZ |
514 | static int gic_dist_supports_lpis(void) |
515 | { | |
516 | return !!(readl_relaxed(gic_data.dist_base + GICD_TYPER) & GICD_TYPER_LPIS); | |
517 | } | |
518 | ||
021f6537 MZ |
519 | static void gic_cpu_init(void) |
520 | { | |
521 | void __iomem *rbase; | |
522 | ||
523 | /* Register ourselves with the rest of the world */ | |
524 | if (gic_populate_rdist()) | |
525 | return; | |
526 | ||
a2c22510 | 527 | gic_enable_redist(true); |
021f6537 MZ |
528 | |
529 | rbase = gic_data_rdist_sgi_base(); | |
530 | ||
531 | gic_cpu_config(rbase, gic_redist_wait_for_rwp); | |
532 | ||
da33f31d MZ |
533 | /* Give LPIs a spin */ |
534 | if (IS_ENABLED(CONFIG_ARM_GIC_V3_ITS) && gic_dist_supports_lpis()) | |
535 | its_cpu_init(); | |
536 | ||
3708d52f SH |
537 | /* initialise system registers */ |
538 | gic_cpu_sys_reg_init(); | |
021f6537 MZ |
539 | } |
540 | ||
541 | #ifdef CONFIG_SMP | |
542 | static int gic_secondary_init(struct notifier_block *nfb, | |
543 | unsigned long action, void *hcpu) | |
544 | { | |
545 | if (action == CPU_STARTING || action == CPU_STARTING_FROZEN) | |
546 | gic_cpu_init(); | |
547 | return NOTIFY_OK; | |
548 | } | |
549 | ||
550 | /* | |
551 | * Notifier for enabling the GIC CPU interface. Set an arbitrarily high | |
552 | * priority because the GIC needs to be up before the ARM generic timers. | |
553 | */ | |
554 | static struct notifier_block gic_cpu_notifier = { | |
555 | .notifier_call = gic_secondary_init, | |
556 | .priority = 100, | |
557 | }; | |
558 | ||
559 | static u16 gic_compute_target_list(int *base_cpu, const struct cpumask *mask, | |
560 | u64 cluster_id) | |
561 | { | |
562 | int cpu = *base_cpu; | |
563 | u64 mpidr = cpu_logical_map(cpu); | |
564 | u16 tlist = 0; | |
565 | ||
566 | while (cpu < nr_cpu_ids) { | |
567 | /* | |
568 | * If we ever get a cluster of more than 16 CPUs, just | |
569 | * scream and skip that CPU. | |
570 | */ | |
571 | if (WARN_ON((mpidr & 0xff) >= 16)) | |
572 | goto out; | |
573 | ||
574 | tlist |= 1 << (mpidr & 0xf); | |
575 | ||
576 | cpu = cpumask_next(cpu, mask); | |
614be385 | 577 | if (cpu >= nr_cpu_ids) |
021f6537 MZ |
578 | goto out; |
579 | ||
580 | mpidr = cpu_logical_map(cpu); | |
581 | ||
582 | if (cluster_id != (mpidr & ~0xffUL)) { | |
583 | cpu--; | |
584 | goto out; | |
585 | } | |
586 | } | |
587 | out: | |
588 | *base_cpu = cpu; | |
589 | return tlist; | |
590 | } | |
591 | ||
7e580278 AP |
592 | #define MPIDR_TO_SGI_AFFINITY(cluster_id, level) \ |
593 | (MPIDR_AFFINITY_LEVEL(cluster_id, level) \ | |
594 | << ICC_SGI1R_AFFINITY_## level ##_SHIFT) | |
595 | ||
021f6537 MZ |
596 | static void gic_send_sgi(u64 cluster_id, u16 tlist, unsigned int irq) |
597 | { | |
598 | u64 val; | |
599 | ||
7e580278 AP |
600 | val = (MPIDR_TO_SGI_AFFINITY(cluster_id, 3) | |
601 | MPIDR_TO_SGI_AFFINITY(cluster_id, 2) | | |
602 | irq << ICC_SGI1R_SGI_ID_SHIFT | | |
603 | MPIDR_TO_SGI_AFFINITY(cluster_id, 1) | | |
604 | tlist << ICC_SGI1R_TARGET_LIST_SHIFT); | |
021f6537 MZ |
605 | |
606 | pr_debug("CPU%d: ICC_SGI1R_EL1 %llx\n", smp_processor_id(), val); | |
607 | gic_write_sgi1r(val); | |
608 | } | |
609 | ||
610 | static void gic_raise_softirq(const struct cpumask *mask, unsigned int irq) | |
611 | { | |
612 | int cpu; | |
613 | ||
614 | if (WARN_ON(irq >= 16)) | |
615 | return; | |
616 | ||
617 | /* | |
618 | * Ensure that stores to Normal memory are visible to the | |
619 | * other CPUs before issuing the IPI. | |
620 | */ | |
621 | smp_wmb(); | |
622 | ||
f9b531fe | 623 | for_each_cpu(cpu, mask) { |
021f6537 MZ |
624 | u64 cluster_id = cpu_logical_map(cpu) & ~0xffUL; |
625 | u16 tlist; | |
626 | ||
627 | tlist = gic_compute_target_list(&cpu, mask, cluster_id); | |
628 | gic_send_sgi(cluster_id, tlist, irq); | |
629 | } | |
630 | ||
631 | /* Force the above writes to ICC_SGI1R_EL1 to be executed */ | |
632 | isb(); | |
633 | } | |
634 | ||
635 | static void gic_smp_init(void) | |
636 | { | |
637 | set_smp_cross_call(gic_raise_softirq); | |
638 | register_cpu_notifier(&gic_cpu_notifier); | |
639 | } | |
640 | ||
641 | static int gic_set_affinity(struct irq_data *d, const struct cpumask *mask_val, | |
642 | bool force) | |
643 | { | |
644 | unsigned int cpu = cpumask_any_and(mask_val, cpu_online_mask); | |
645 | void __iomem *reg; | |
646 | int enabled; | |
647 | u64 val; | |
648 | ||
649 | if (gic_irq_in_rdist(d)) | |
650 | return -EINVAL; | |
651 | ||
652 | /* If interrupt was enabled, disable it first */ | |
653 | enabled = gic_peek_irq(d, GICD_ISENABLER); | |
654 | if (enabled) | |
655 | gic_mask_irq(d); | |
656 | ||
657 | reg = gic_dist_base(d) + GICD_IROUTER + (gic_irq(d) * 8); | |
658 | val = gic_mpidr_to_affinity(cpu_logical_map(cpu)); | |
659 | ||
660 | writeq_relaxed(val, reg); | |
661 | ||
662 | /* | |
663 | * If the interrupt was enabled, enabled it again. Otherwise, | |
664 | * just wait for the distributor to have digested our changes. | |
665 | */ | |
666 | if (enabled) | |
667 | gic_unmask_irq(d); | |
668 | else | |
669 | gic_dist_wait_for_rwp(); | |
670 | ||
671 | return IRQ_SET_MASK_OK; | |
672 | } | |
673 | #else | |
674 | #define gic_set_affinity NULL | |
675 | #define gic_smp_init() do { } while(0) | |
676 | #endif | |
677 | ||
3708d52f SH |
678 | #ifdef CONFIG_CPU_PM |
679 | static int gic_cpu_pm_notifier(struct notifier_block *self, | |
680 | unsigned long cmd, void *v) | |
681 | { | |
682 | if (cmd == CPU_PM_EXIT) { | |
683 | gic_enable_redist(true); | |
684 | gic_cpu_sys_reg_init(); | |
685 | } else if (cmd == CPU_PM_ENTER) { | |
686 | gic_write_grpen1(0); | |
687 | gic_enable_redist(false); | |
688 | } | |
689 | return NOTIFY_OK; | |
690 | } | |
691 | ||
692 | static struct notifier_block gic_cpu_pm_notifier_block = { | |
693 | .notifier_call = gic_cpu_pm_notifier, | |
694 | }; | |
695 | ||
696 | static void gic_cpu_pm_init(void) | |
697 | { | |
698 | cpu_pm_register_notifier(&gic_cpu_pm_notifier_block); | |
699 | } | |
700 | ||
701 | #else | |
702 | static inline void gic_cpu_pm_init(void) { } | |
703 | #endif /* CONFIG_CPU_PM */ | |
704 | ||
021f6537 MZ |
705 | static struct irq_chip gic_chip = { |
706 | .name = "GICv3", | |
707 | .irq_mask = gic_mask_irq, | |
708 | .irq_unmask = gic_unmask_irq, | |
709 | .irq_eoi = gic_eoi_irq, | |
710 | .irq_set_type = gic_set_type, | |
711 | .irq_set_affinity = gic_set_affinity, | |
b594c6e2 MZ |
712 | .irq_get_irqchip_state = gic_irq_get_irqchip_state, |
713 | .irq_set_irqchip_state = gic_irq_set_irqchip_state, | |
55963c9f | 714 | .flags = IRQCHIP_SET_TYPE_MASKED, |
021f6537 MZ |
715 | }; |
716 | ||
0b6a3da9 MZ |
717 | static struct irq_chip gic_eoimode1_chip = { |
718 | .name = "GICv3", | |
719 | .irq_mask = gic_eoimode1_mask_irq, | |
720 | .irq_unmask = gic_unmask_irq, | |
721 | .irq_eoi = gic_eoimode1_eoi_irq, | |
722 | .irq_set_type = gic_set_type, | |
723 | .irq_set_affinity = gic_set_affinity, | |
724 | .irq_get_irqchip_state = gic_irq_get_irqchip_state, | |
725 | .irq_set_irqchip_state = gic_irq_set_irqchip_state, | |
530bf353 | 726 | .irq_set_vcpu_affinity = gic_irq_set_vcpu_affinity, |
0b6a3da9 MZ |
727 | .flags = IRQCHIP_SET_TYPE_MASKED, |
728 | }; | |
729 | ||
da33f31d MZ |
730 | #define GIC_ID_NR (1U << gic_data.rdists.id_bits) |
731 | ||
021f6537 MZ |
732 | static int gic_irq_domain_map(struct irq_domain *d, unsigned int irq, |
733 | irq_hw_number_t hw) | |
734 | { | |
0b6a3da9 MZ |
735 | struct irq_chip *chip = &gic_chip; |
736 | ||
737 | if (static_key_true(&supports_deactivate)) | |
738 | chip = &gic_eoimode1_chip; | |
739 | ||
021f6537 MZ |
740 | /* SGIs are private to the core kernel */ |
741 | if (hw < 16) | |
742 | return -EPERM; | |
da33f31d MZ |
743 | /* Nothing here */ |
744 | if (hw >= gic_data.irq_nr && hw < 8192) | |
745 | return -EPERM; | |
746 | /* Off limits */ | |
747 | if (hw >= GIC_ID_NR) | |
748 | return -EPERM; | |
749 | ||
021f6537 MZ |
750 | /* PPIs */ |
751 | if (hw < 32) { | |
752 | irq_set_percpu_devid(irq); | |
0b6a3da9 | 753 | irq_domain_set_info(d, irq, hw, chip, d->host_data, |
443acc4f | 754 | handle_percpu_devid_irq, NULL, NULL); |
021f6537 MZ |
755 | set_irq_flags(irq, IRQF_VALID | IRQF_NOAUTOEN); |
756 | } | |
757 | /* SPIs */ | |
758 | if (hw >= 32 && hw < gic_data.irq_nr) { | |
0b6a3da9 | 759 | irq_domain_set_info(d, irq, hw, chip, d->host_data, |
443acc4f | 760 | handle_fasteoi_irq, NULL, NULL); |
021f6537 MZ |
761 | set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); |
762 | } | |
da33f31d MZ |
763 | /* LPIs */ |
764 | if (hw >= 8192 && hw < GIC_ID_NR) { | |
765 | if (!gic_dist_supports_lpis()) | |
766 | return -EPERM; | |
0b6a3da9 | 767 | irq_domain_set_info(d, irq, hw, chip, d->host_data, |
da33f31d MZ |
768 | handle_fasteoi_irq, NULL, NULL); |
769 | set_irq_flags(irq, IRQF_VALID); | |
770 | } | |
771 | ||
021f6537 MZ |
772 | return 0; |
773 | } | |
774 | ||
775 | static int gic_irq_domain_xlate(struct irq_domain *d, | |
776 | struct device_node *controller, | |
777 | const u32 *intspec, unsigned int intsize, | |
778 | unsigned long *out_hwirq, unsigned int *out_type) | |
779 | { | |
780 | if (d->of_node != controller) | |
781 | return -EINVAL; | |
782 | if (intsize < 3) | |
783 | return -EINVAL; | |
784 | ||
785 | switch(intspec[0]) { | |
786 | case 0: /* SPI */ | |
787 | *out_hwirq = intspec[1] + 32; | |
788 | break; | |
789 | case 1: /* PPI */ | |
790 | *out_hwirq = intspec[1] + 16; | |
791 | break; | |
da33f31d MZ |
792 | case GIC_IRQ_TYPE_LPI: /* LPI */ |
793 | *out_hwirq = intspec[1]; | |
794 | break; | |
021f6537 MZ |
795 | default: |
796 | return -EINVAL; | |
797 | } | |
798 | ||
799 | *out_type = intspec[2] & IRQ_TYPE_SENSE_MASK; | |
800 | return 0; | |
801 | } | |
802 | ||
443acc4f MZ |
803 | static int gic_irq_domain_alloc(struct irq_domain *domain, unsigned int virq, |
804 | unsigned int nr_irqs, void *arg) | |
805 | { | |
806 | int i, ret; | |
807 | irq_hw_number_t hwirq; | |
808 | unsigned int type = IRQ_TYPE_NONE; | |
809 | struct of_phandle_args *irq_data = arg; | |
810 | ||
811 | ret = gic_irq_domain_xlate(domain, irq_data->np, irq_data->args, | |
812 | irq_data->args_count, &hwirq, &type); | |
813 | if (ret) | |
814 | return ret; | |
815 | ||
816 | for (i = 0; i < nr_irqs; i++) | |
817 | gic_irq_domain_map(domain, virq + i, hwirq + i); | |
818 | ||
819 | return 0; | |
820 | } | |
821 | ||
822 | static void gic_irq_domain_free(struct irq_domain *domain, unsigned int virq, | |
823 | unsigned int nr_irqs) | |
824 | { | |
825 | int i; | |
826 | ||
827 | for (i = 0; i < nr_irqs; i++) { | |
828 | struct irq_data *d = irq_domain_get_irq_data(domain, virq + i); | |
829 | irq_set_handler(virq + i, NULL); | |
830 | irq_domain_reset_irq_data(d); | |
831 | } | |
832 | } | |
833 | ||
021f6537 | 834 | static const struct irq_domain_ops gic_irq_domain_ops = { |
021f6537 | 835 | .xlate = gic_irq_domain_xlate, |
443acc4f MZ |
836 | .alloc = gic_irq_domain_alloc, |
837 | .free = gic_irq_domain_free, | |
021f6537 MZ |
838 | }; |
839 | ||
840 | static int __init gic_of_init(struct device_node *node, struct device_node *parent) | |
841 | { | |
842 | void __iomem *dist_base; | |
f5c1434c | 843 | struct redist_region *rdist_regs; |
021f6537 | 844 | u64 redist_stride; |
f5c1434c MZ |
845 | u32 nr_redist_regions; |
846 | u32 typer; | |
021f6537 MZ |
847 | u32 reg; |
848 | int gic_irqs; | |
849 | int err; | |
850 | int i; | |
851 | ||
852 | dist_base = of_iomap(node, 0); | |
853 | if (!dist_base) { | |
854 | pr_err("%s: unable to map gic dist registers\n", | |
855 | node->full_name); | |
856 | return -ENXIO; | |
857 | } | |
858 | ||
859 | reg = readl_relaxed(dist_base + GICD_PIDR2) & GIC_PIDR2_ARCH_MASK; | |
860 | if (reg != GIC_PIDR2_ARCH_GICv3 && reg != GIC_PIDR2_ARCH_GICv4) { | |
861 | pr_err("%s: no distributor detected, giving up\n", | |
862 | node->full_name); | |
863 | err = -ENODEV; | |
864 | goto out_unmap_dist; | |
865 | } | |
866 | ||
f5c1434c MZ |
867 | if (of_property_read_u32(node, "#redistributor-regions", &nr_redist_regions)) |
868 | nr_redist_regions = 1; | |
021f6537 | 869 | |
f5c1434c MZ |
870 | rdist_regs = kzalloc(sizeof(*rdist_regs) * nr_redist_regions, GFP_KERNEL); |
871 | if (!rdist_regs) { | |
021f6537 MZ |
872 | err = -ENOMEM; |
873 | goto out_unmap_dist; | |
874 | } | |
875 | ||
f5c1434c MZ |
876 | for (i = 0; i < nr_redist_regions; i++) { |
877 | struct resource res; | |
878 | int ret; | |
879 | ||
880 | ret = of_address_to_resource(node, 1 + i, &res); | |
881 | rdist_regs[i].redist_base = of_iomap(node, 1 + i); | |
882 | if (ret || !rdist_regs[i].redist_base) { | |
021f6537 MZ |
883 | pr_err("%s: couldn't map region %d\n", |
884 | node->full_name, i); | |
885 | err = -ENODEV; | |
886 | goto out_unmap_rdist; | |
887 | } | |
f5c1434c | 888 | rdist_regs[i].phys_base = res.start; |
021f6537 MZ |
889 | } |
890 | ||
891 | if (of_property_read_u64(node, "redistributor-stride", &redist_stride)) | |
892 | redist_stride = 0; | |
893 | ||
0b6a3da9 MZ |
894 | if (!is_hyp_mode_available()) |
895 | static_key_slow_dec(&supports_deactivate); | |
896 | ||
897 | if (static_key_true(&supports_deactivate)) | |
898 | pr_info("GIC: Using split EOI/Deactivate mode\n"); | |
899 | ||
021f6537 | 900 | gic_data.dist_base = dist_base; |
f5c1434c MZ |
901 | gic_data.redist_regions = rdist_regs; |
902 | gic_data.nr_redist_regions = nr_redist_regions; | |
021f6537 MZ |
903 | gic_data.redist_stride = redist_stride; |
904 | ||
905 | /* | |
906 | * Find out how many interrupts are supported. | |
907 | * The GIC only supports up to 1020 interrupt sources (SGI+PPI+SPI) | |
908 | */ | |
f5c1434c MZ |
909 | typer = readl_relaxed(gic_data.dist_base + GICD_TYPER); |
910 | gic_data.rdists.id_bits = GICD_TYPER_ID_BITS(typer); | |
911 | gic_irqs = GICD_TYPER_IRQS(typer); | |
021f6537 MZ |
912 | if (gic_irqs > 1020) |
913 | gic_irqs = 1020; | |
914 | gic_data.irq_nr = gic_irqs; | |
915 | ||
916 | gic_data.domain = irq_domain_add_tree(node, &gic_irq_domain_ops, | |
917 | &gic_data); | |
f5c1434c | 918 | gic_data.rdists.rdist = alloc_percpu(typeof(*gic_data.rdists.rdist)); |
021f6537 | 919 | |
f5c1434c | 920 | if (WARN_ON(!gic_data.domain) || WARN_ON(!gic_data.rdists.rdist)) { |
021f6537 MZ |
921 | err = -ENOMEM; |
922 | goto out_free; | |
923 | } | |
924 | ||
925 | set_handle_irq(gic_handle_irq); | |
926 | ||
da33f31d MZ |
927 | if (IS_ENABLED(CONFIG_ARM_GIC_V3_ITS) && gic_dist_supports_lpis()) |
928 | its_init(node, &gic_data.rdists, gic_data.domain); | |
929 | ||
021f6537 MZ |
930 | gic_smp_init(); |
931 | gic_dist_init(); | |
932 | gic_cpu_init(); | |
3708d52f | 933 | gic_cpu_pm_init(); |
021f6537 MZ |
934 | |
935 | return 0; | |
936 | ||
937 | out_free: | |
938 | if (gic_data.domain) | |
939 | irq_domain_remove(gic_data.domain); | |
f5c1434c | 940 | free_percpu(gic_data.rdists.rdist); |
021f6537 | 941 | out_unmap_rdist: |
f5c1434c MZ |
942 | for (i = 0; i < nr_redist_regions; i++) |
943 | if (rdist_regs[i].redist_base) | |
944 | iounmap(rdist_regs[i].redist_base); | |
945 | kfree(rdist_regs); | |
021f6537 MZ |
946 | out_unmap_dist: |
947 | iounmap(dist_base); | |
948 | return err; | |
949 | } | |
950 | ||
951 | IRQCHIP_DECLARE(gic_v3, "arm,gic-v3", gic_of_init); |