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Commit | Line | Data |
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f27ecacc | 1 | /* |
f27ecacc RK |
2 | * Copyright (C) 2002 ARM Limited, All Rights Reserved. |
3 | * | |
4 | * This program is free software; you can redistribute it and/or modify | |
5 | * it under the terms of the GNU General Public License version 2 as | |
6 | * published by the Free Software Foundation. | |
7 | * | |
8 | * Interrupt architecture for the GIC: | |
9 | * | |
10 | * o There is one Interrupt Distributor, which receives interrupts | |
11 | * from system devices and sends them to the Interrupt Controllers. | |
12 | * | |
13 | * o There is one CPU Interface per CPU, which sends interrupts sent | |
14 | * by the Distributor, and interrupts generated locally, to the | |
b3a1bde4 CM |
15 | * associated CPU. The base address of the CPU interface is usually |
16 | * aliased so that the same address points to different chips depending | |
17 | * on the CPU it is accessed from. | |
f27ecacc RK |
18 | * |
19 | * Note that IRQs 0-31 are special - they are local to each CPU. | |
20 | * As such, the enable set/clear, pending set/clear and active bit | |
21 | * registers are banked per-cpu for these sources. | |
22 | */ | |
23 | #include <linux/init.h> | |
24 | #include <linux/kernel.h> | |
f37a53cc | 25 | #include <linux/err.h> |
7e1efcf5 | 26 | #include <linux/module.h> |
f27ecacc RK |
27 | #include <linux/list.h> |
28 | #include <linux/smp.h> | |
c0114709 | 29 | #include <linux/cpu.h> |
254056f3 | 30 | #include <linux/cpu_pm.h> |
dcb86e8c | 31 | #include <linux/cpumask.h> |
fced80c7 | 32 | #include <linux/io.h> |
b3f7ed03 RH |
33 | #include <linux/of.h> |
34 | #include <linux/of_address.h> | |
35 | #include <linux/of_irq.h> | |
d60fc389 | 36 | #include <linux/acpi.h> |
4294f8ba | 37 | #include <linux/irqdomain.h> |
292b293c MZ |
38 | #include <linux/interrupt.h> |
39 | #include <linux/percpu.h> | |
40 | #include <linux/slab.h> | |
41a83e06 | 41 | #include <linux/irqchip.h> |
de88cbb7 | 42 | #include <linux/irqchip/chained_irq.h> |
520f7bd7 | 43 | #include <linux/irqchip/arm-gic.h> |
f27ecacc | 44 | |
29e697b1 | 45 | #include <asm/cputype.h> |
f27ecacc | 46 | #include <asm/irq.h> |
562e0027 | 47 | #include <asm/exception.h> |
eb50439b | 48 | #include <asm/smp_plat.h> |
0b996fd3 | 49 | #include <asm/virt.h> |
f27ecacc | 50 | |
d51d0af4 | 51 | #include "irq-gic-common.h" |
f27ecacc | 52 | |
76e52dd0 MZ |
53 | #ifdef CONFIG_ARM64 |
54 | #include <asm/cpufeature.h> | |
55 | ||
56 | static void gic_check_cpu_features(void) | |
57 | { | |
58 | WARN_TAINT_ONCE(cpus_have_cap(ARM64_HAS_SYSREG_GIC_CPUIF), | |
59 | TAINT_CPU_OUT_OF_SPEC, | |
60 | "GICv3 system registers enabled, broken firmware!\n"); | |
61 | } | |
62 | #else | |
63 | #define gic_check_cpu_features() do { } while(0) | |
64 | #endif | |
65 | ||
db0d4db2 MZ |
66 | union gic_base { |
67 | void __iomem *common_base; | |
6859358e | 68 | void __percpu * __iomem *percpu_base; |
db0d4db2 MZ |
69 | }; |
70 | ||
71 | struct gic_chip_data { | |
db0d4db2 MZ |
72 | union gic_base dist_base; |
73 | union gic_base cpu_base; | |
74 | #ifdef CONFIG_CPU_PM | |
75 | u32 saved_spi_enable[DIV_ROUND_UP(1020, 32)]; | |
1c7d4dd4 | 76 | u32 saved_spi_active[DIV_ROUND_UP(1020, 32)]; |
db0d4db2 MZ |
77 | u32 saved_spi_conf[DIV_ROUND_UP(1020, 16)]; |
78 | u32 saved_spi_target[DIV_ROUND_UP(1020, 4)]; | |
79 | u32 __percpu *saved_ppi_enable; | |
1c7d4dd4 | 80 | u32 __percpu *saved_ppi_active; |
db0d4db2 MZ |
81 | u32 __percpu *saved_ppi_conf; |
82 | #endif | |
75294957 | 83 | struct irq_domain *domain; |
db0d4db2 MZ |
84 | unsigned int gic_irqs; |
85 | #ifdef CONFIG_GIC_NON_BANKED | |
86 | void __iomem *(*get_base)(union gic_base *); | |
87 | #endif | |
88 | }; | |
89 | ||
bd31b859 | 90 | static DEFINE_RAW_SPINLOCK(irq_controller_lock); |
f27ecacc | 91 | |
384a2902 NP |
92 | /* |
93 | * The GIC mapping of CPU interfaces does not necessarily match | |
94 | * the logical CPU numbering. Let's use a mapping as returned | |
95 | * by the GIC itself. | |
96 | */ | |
97 | #define NR_GIC_CPU_IF 8 | |
98 | static u8 gic_cpu_map[NR_GIC_CPU_IF] __read_mostly; | |
99 | ||
0b996fd3 MZ |
100 | static struct static_key supports_deactivate = STATIC_KEY_INIT_TRUE; |
101 | ||
b3a1bde4 CM |
102 | #ifndef MAX_GIC_NR |
103 | #define MAX_GIC_NR 1 | |
104 | #endif | |
105 | ||
bef8f9ee | 106 | static struct gic_chip_data gic_data[MAX_GIC_NR] __read_mostly; |
b3a1bde4 | 107 | |
db0d4db2 MZ |
108 | #ifdef CONFIG_GIC_NON_BANKED |
109 | static void __iomem *gic_get_percpu_base(union gic_base *base) | |
110 | { | |
513d1a28 | 111 | return raw_cpu_read(*base->percpu_base); |
db0d4db2 MZ |
112 | } |
113 | ||
114 | static void __iomem *gic_get_common_base(union gic_base *base) | |
115 | { | |
116 | return base->common_base; | |
117 | } | |
118 | ||
119 | static inline void __iomem *gic_data_dist_base(struct gic_chip_data *data) | |
120 | { | |
121 | return data->get_base(&data->dist_base); | |
122 | } | |
123 | ||
124 | static inline void __iomem *gic_data_cpu_base(struct gic_chip_data *data) | |
125 | { | |
126 | return data->get_base(&data->cpu_base); | |
127 | } | |
128 | ||
129 | static inline void gic_set_base_accessor(struct gic_chip_data *data, | |
130 | void __iomem *(*f)(union gic_base *)) | |
131 | { | |
132 | data->get_base = f; | |
133 | } | |
134 | #else | |
135 | #define gic_data_dist_base(d) ((d)->dist_base.common_base) | |
136 | #define gic_data_cpu_base(d) ((d)->cpu_base.common_base) | |
46f101df | 137 | #define gic_set_base_accessor(d, f) |
db0d4db2 MZ |
138 | #endif |
139 | ||
7d1f4288 | 140 | static inline void __iomem *gic_dist_base(struct irq_data *d) |
b3a1bde4 | 141 | { |
7d1f4288 | 142 | struct gic_chip_data *gic_data = irq_data_get_irq_chip_data(d); |
db0d4db2 | 143 | return gic_data_dist_base(gic_data); |
b3a1bde4 CM |
144 | } |
145 | ||
7d1f4288 | 146 | static inline void __iomem *gic_cpu_base(struct irq_data *d) |
b3a1bde4 | 147 | { |
7d1f4288 | 148 | struct gic_chip_data *gic_data = irq_data_get_irq_chip_data(d); |
db0d4db2 | 149 | return gic_data_cpu_base(gic_data); |
b3a1bde4 CM |
150 | } |
151 | ||
7d1f4288 | 152 | static inline unsigned int gic_irq(struct irq_data *d) |
b3a1bde4 | 153 | { |
4294f8ba | 154 | return d->hwirq; |
b3a1bde4 CM |
155 | } |
156 | ||
01f779f4 MZ |
157 | static inline bool cascading_gic_irq(struct irq_data *d) |
158 | { | |
159 | void *data = irq_data_get_irq_handler_data(d); | |
160 | ||
161 | /* | |
71466535 TG |
162 | * If handler_data is set, this is a cascading interrupt, and |
163 | * it cannot possibly be forwarded. | |
01f779f4 | 164 | */ |
71466535 | 165 | return data != NULL; |
01f779f4 MZ |
166 | } |
167 | ||
f27ecacc RK |
168 | /* |
169 | * Routines to acknowledge, disable and enable interrupts | |
f27ecacc | 170 | */ |
56717807 MZ |
171 | static void gic_poke_irq(struct irq_data *d, u32 offset) |
172 | { | |
173 | u32 mask = 1 << (gic_irq(d) % 32); | |
174 | writel_relaxed(mask, gic_dist_base(d) + offset + (gic_irq(d) / 32) * 4); | |
175 | } | |
176 | ||
177 | static int gic_peek_irq(struct irq_data *d, u32 offset) | |
f27ecacc | 178 | { |
4294f8ba | 179 | u32 mask = 1 << (gic_irq(d) % 32); |
56717807 MZ |
180 | return !!(readl_relaxed(gic_dist_base(d) + offset + (gic_irq(d) / 32) * 4) & mask); |
181 | } | |
182 | ||
183 | static void gic_mask_irq(struct irq_data *d) | |
184 | { | |
56717807 | 185 | gic_poke_irq(d, GIC_DIST_ENABLE_CLEAR); |
f27ecacc RK |
186 | } |
187 | ||
0b996fd3 MZ |
188 | static void gic_eoimode1_mask_irq(struct irq_data *d) |
189 | { | |
190 | gic_mask_irq(d); | |
01f779f4 MZ |
191 | /* |
192 | * When masking a forwarded interrupt, make sure it is | |
193 | * deactivated as well. | |
194 | * | |
195 | * This ensures that an interrupt that is getting | |
196 | * disabled/masked will not get "stuck", because there is | |
197 | * noone to deactivate it (guest is being terminated). | |
198 | */ | |
71466535 | 199 | if (irqd_is_forwarded_to_vcpu(d)) |
01f779f4 | 200 | gic_poke_irq(d, GIC_DIST_ACTIVE_CLEAR); |
0b996fd3 MZ |
201 | } |
202 | ||
7d1f4288 | 203 | static void gic_unmask_irq(struct irq_data *d) |
f27ecacc | 204 | { |
56717807 | 205 | gic_poke_irq(d, GIC_DIST_ENABLE_SET); |
f27ecacc RK |
206 | } |
207 | ||
1a01753e WD |
208 | static void gic_eoi_irq(struct irq_data *d) |
209 | { | |
6ac77e46 | 210 | writel_relaxed(gic_irq(d), gic_cpu_base(d) + GIC_CPU_EOI); |
1a01753e WD |
211 | } |
212 | ||
0b996fd3 MZ |
213 | static void gic_eoimode1_eoi_irq(struct irq_data *d) |
214 | { | |
01f779f4 | 215 | /* Do not deactivate an IRQ forwarded to a vcpu. */ |
71466535 | 216 | if (irqd_is_forwarded_to_vcpu(d)) |
01f779f4 MZ |
217 | return; |
218 | ||
0b996fd3 MZ |
219 | writel_relaxed(gic_irq(d), gic_cpu_base(d) + GIC_CPU_DEACTIVATE); |
220 | } | |
221 | ||
56717807 MZ |
222 | static int gic_irq_set_irqchip_state(struct irq_data *d, |
223 | enum irqchip_irq_state which, bool val) | |
224 | { | |
225 | u32 reg; | |
226 | ||
227 | switch (which) { | |
228 | case IRQCHIP_STATE_PENDING: | |
229 | reg = val ? GIC_DIST_PENDING_SET : GIC_DIST_PENDING_CLEAR; | |
230 | break; | |
231 | ||
232 | case IRQCHIP_STATE_ACTIVE: | |
233 | reg = val ? GIC_DIST_ACTIVE_SET : GIC_DIST_ACTIVE_CLEAR; | |
234 | break; | |
235 | ||
236 | case IRQCHIP_STATE_MASKED: | |
237 | reg = val ? GIC_DIST_ENABLE_CLEAR : GIC_DIST_ENABLE_SET; | |
238 | break; | |
239 | ||
240 | default: | |
241 | return -EINVAL; | |
242 | } | |
243 | ||
244 | gic_poke_irq(d, reg); | |
245 | return 0; | |
246 | } | |
247 | ||
248 | static int gic_irq_get_irqchip_state(struct irq_data *d, | |
249 | enum irqchip_irq_state which, bool *val) | |
250 | { | |
251 | switch (which) { | |
252 | case IRQCHIP_STATE_PENDING: | |
253 | *val = gic_peek_irq(d, GIC_DIST_PENDING_SET); | |
254 | break; | |
255 | ||
256 | case IRQCHIP_STATE_ACTIVE: | |
257 | *val = gic_peek_irq(d, GIC_DIST_ACTIVE_SET); | |
258 | break; | |
259 | ||
260 | case IRQCHIP_STATE_MASKED: | |
261 | *val = !gic_peek_irq(d, GIC_DIST_ENABLE_SET); | |
262 | break; | |
263 | ||
264 | default: | |
265 | return -EINVAL; | |
266 | } | |
267 | ||
268 | return 0; | |
269 | } | |
270 | ||
7d1f4288 | 271 | static int gic_set_type(struct irq_data *d, unsigned int type) |
5c0c1f08 | 272 | { |
7d1f4288 LB |
273 | void __iomem *base = gic_dist_base(d); |
274 | unsigned int gicirq = gic_irq(d); | |
5c0c1f08 RV |
275 | |
276 | /* Interrupt configuration for SGIs can't be changed */ | |
277 | if (gicirq < 16) | |
278 | return -EINVAL; | |
279 | ||
fb7e7deb LD |
280 | /* SPIs have restrictions on the supported types */ |
281 | if (gicirq >= 32 && type != IRQ_TYPE_LEVEL_HIGH && | |
282 | type != IRQ_TYPE_EDGE_RISING) | |
5c0c1f08 RV |
283 | return -EINVAL; |
284 | ||
1dcc73d7 | 285 | return gic_configure_irq(gicirq, type, base, NULL); |
d7ed36a4 SS |
286 | } |
287 | ||
01f779f4 MZ |
288 | static int gic_irq_set_vcpu_affinity(struct irq_data *d, void *vcpu) |
289 | { | |
290 | /* Only interrupts on the primary GIC can be forwarded to a vcpu. */ | |
291 | if (cascading_gic_irq(d)) | |
292 | return -EINVAL; | |
293 | ||
71466535 TG |
294 | if (vcpu) |
295 | irqd_set_forwarded_to_vcpu(d); | |
296 | else | |
297 | irqd_clr_forwarded_to_vcpu(d); | |
01f779f4 MZ |
298 | return 0; |
299 | } | |
300 | ||
a06f5466 | 301 | #ifdef CONFIG_SMP |
c191789c RK |
302 | static int gic_set_affinity(struct irq_data *d, const struct cpumask *mask_val, |
303 | bool force) | |
f27ecacc | 304 | { |
7d1f4288 | 305 | void __iomem *reg = gic_dist_base(d) + GIC_DIST_TARGET + (gic_irq(d) & ~3); |
ffde1de6 | 306 | unsigned int cpu, shift = (gic_irq(d) % 4) * 8; |
c191789c | 307 | u32 val, mask, bit; |
cf613871 | 308 | unsigned long flags; |
f27ecacc | 309 | |
ffde1de6 TG |
310 | if (!force) |
311 | cpu = cpumask_any_and(mask_val, cpu_online_mask); | |
312 | else | |
313 | cpu = cpumask_first(mask_val); | |
314 | ||
384a2902 | 315 | if (cpu >= NR_GIC_CPU_IF || cpu >= nr_cpu_ids) |
87507500 | 316 | return -EINVAL; |
c191789c | 317 | |
cf613871 | 318 | raw_spin_lock_irqsave(&irq_controller_lock, flags); |
c191789c | 319 | mask = 0xff << shift; |
384a2902 | 320 | bit = gic_cpu_map[cpu] << shift; |
6ac77e46 SS |
321 | val = readl_relaxed(reg) & ~mask; |
322 | writel_relaxed(val | bit, reg); | |
cf613871 | 323 | raw_spin_unlock_irqrestore(&irq_controller_lock, flags); |
d5dedd45 | 324 | |
5dfc54e0 | 325 | return IRQ_SET_MASK_OK; |
f27ecacc | 326 | } |
a06f5466 | 327 | #endif |
f27ecacc | 328 | |
8783dd3a | 329 | static void __exception_irq_entry gic_handle_irq(struct pt_regs *regs) |
562e0027 MZ |
330 | { |
331 | u32 irqstat, irqnr; | |
332 | struct gic_chip_data *gic = &gic_data[0]; | |
333 | void __iomem *cpu_base = gic_data_cpu_base(gic); | |
334 | ||
335 | do { | |
336 | irqstat = readl_relaxed(cpu_base + GIC_CPU_INTACK); | |
b8802f76 | 337 | irqnr = irqstat & GICC_IAR_INT_ID_MASK; |
562e0027 MZ |
338 | |
339 | if (likely(irqnr > 15 && irqnr < 1021)) { | |
0b996fd3 MZ |
340 | if (static_key_true(&supports_deactivate)) |
341 | writel_relaxed(irqstat, cpu_base + GIC_CPU_EOI); | |
60031b4e | 342 | handle_domain_irq(gic->domain, irqnr, regs); |
562e0027 MZ |
343 | continue; |
344 | } | |
345 | if (irqnr < 16) { | |
346 | writel_relaxed(irqstat, cpu_base + GIC_CPU_EOI); | |
0b996fd3 MZ |
347 | if (static_key_true(&supports_deactivate)) |
348 | writel_relaxed(irqstat, cpu_base + GIC_CPU_DEACTIVATE); | |
562e0027 MZ |
349 | #ifdef CONFIG_SMP |
350 | handle_IPI(irqnr, regs); | |
351 | #endif | |
352 | continue; | |
353 | } | |
354 | break; | |
355 | } while (1); | |
356 | } | |
357 | ||
bd0b9ac4 | 358 | static void gic_handle_cascade_irq(struct irq_desc *desc) |
b3a1bde4 | 359 | { |
5b29264c JL |
360 | struct gic_chip_data *chip_data = irq_desc_get_handler_data(desc); |
361 | struct irq_chip *chip = irq_desc_get_chip(desc); | |
0f347bb9 | 362 | unsigned int cascade_irq, gic_irq; |
b3a1bde4 CM |
363 | unsigned long status; |
364 | ||
1a01753e | 365 | chained_irq_enter(chip, desc); |
b3a1bde4 | 366 | |
bd31b859 | 367 | raw_spin_lock(&irq_controller_lock); |
db0d4db2 | 368 | status = readl_relaxed(gic_data_cpu_base(chip_data) + GIC_CPU_INTACK); |
bd31b859 | 369 | raw_spin_unlock(&irq_controller_lock); |
b3a1bde4 | 370 | |
e5f81539 FK |
371 | gic_irq = (status & GICC_IAR_INT_ID_MASK); |
372 | if (gic_irq == GICC_INT_SPURIOUS) | |
b3a1bde4 | 373 | goto out; |
b3a1bde4 | 374 | |
75294957 GL |
375 | cascade_irq = irq_find_mapping(chip_data->domain, gic_irq); |
376 | if (unlikely(gic_irq < 32 || gic_irq > 1020)) | |
bd0b9ac4 | 377 | handle_bad_irq(desc); |
0f347bb9 RK |
378 | else |
379 | generic_handle_irq(cascade_irq); | |
b3a1bde4 CM |
380 | |
381 | out: | |
1a01753e | 382 | chained_irq_exit(chip, desc); |
b3a1bde4 CM |
383 | } |
384 | ||
38c677cb | 385 | static struct irq_chip gic_chip = { |
7d1f4288 | 386 | .name = "GIC", |
7d1f4288 LB |
387 | .irq_mask = gic_mask_irq, |
388 | .irq_unmask = gic_unmask_irq, | |
1a01753e | 389 | .irq_eoi = gic_eoi_irq, |
7d1f4288 | 390 | .irq_set_type = gic_set_type, |
f27ecacc | 391 | #ifdef CONFIG_SMP |
c191789c | 392 | .irq_set_affinity = gic_set_affinity, |
f27ecacc | 393 | #endif |
56717807 MZ |
394 | .irq_get_irqchip_state = gic_irq_get_irqchip_state, |
395 | .irq_set_irqchip_state = gic_irq_set_irqchip_state, | |
aec89ef7 SH |
396 | .flags = IRQCHIP_SET_TYPE_MASKED | |
397 | IRQCHIP_SKIP_SET_WAKE | | |
398 | IRQCHIP_MASK_ON_SUSPEND, | |
f27ecacc RK |
399 | }; |
400 | ||
0b996fd3 MZ |
401 | static struct irq_chip gic_eoimode1_chip = { |
402 | .name = "GICv2", | |
403 | .irq_mask = gic_eoimode1_mask_irq, | |
404 | .irq_unmask = gic_unmask_irq, | |
405 | .irq_eoi = gic_eoimode1_eoi_irq, | |
406 | .irq_set_type = gic_set_type, | |
407 | #ifdef CONFIG_SMP | |
408 | .irq_set_affinity = gic_set_affinity, | |
409 | #endif | |
410 | .irq_get_irqchip_state = gic_irq_get_irqchip_state, | |
411 | .irq_set_irqchip_state = gic_irq_set_irqchip_state, | |
01f779f4 | 412 | .irq_set_vcpu_affinity = gic_irq_set_vcpu_affinity, |
0b996fd3 MZ |
413 | .flags = IRQCHIP_SET_TYPE_MASKED | |
414 | IRQCHIP_SKIP_SET_WAKE | | |
415 | IRQCHIP_MASK_ON_SUSPEND, | |
416 | }; | |
417 | ||
b3a1bde4 CM |
418 | void __init gic_cascade_irq(unsigned int gic_nr, unsigned int irq) |
419 | { | |
420 | if (gic_nr >= MAX_GIC_NR) | |
421 | BUG(); | |
4d83fcf8 TG |
422 | irq_set_chained_handler_and_data(irq, gic_handle_cascade_irq, |
423 | &gic_data[gic_nr]); | |
b3a1bde4 CM |
424 | } |
425 | ||
2bb31351 RK |
426 | static u8 gic_get_cpumask(struct gic_chip_data *gic) |
427 | { | |
428 | void __iomem *base = gic_data_dist_base(gic); | |
429 | u32 mask, i; | |
430 | ||
431 | for (i = mask = 0; i < 32; i += 4) { | |
432 | mask = readl_relaxed(base + GIC_DIST_TARGET + i); | |
433 | mask |= mask >> 16; | |
434 | mask |= mask >> 8; | |
435 | if (mask) | |
436 | break; | |
437 | } | |
438 | ||
6e3aca44 | 439 | if (!mask && num_possible_cpus() > 1) |
2bb31351 RK |
440 | pr_crit("GIC CPU mask not found - kernel will fail to boot.\n"); |
441 | ||
442 | return mask; | |
443 | } | |
444 | ||
4c2880b3 | 445 | static void gic_cpu_if_up(struct gic_chip_data *gic) |
32289506 | 446 | { |
4c2880b3 | 447 | void __iomem *cpu_base = gic_data_cpu_base(gic); |
32289506 | 448 | u32 bypass = 0; |
0b996fd3 MZ |
449 | u32 mode = 0; |
450 | ||
451 | if (static_key_true(&supports_deactivate)) | |
452 | mode = GIC_CPU_CTRL_EOImodeNS; | |
32289506 FK |
453 | |
454 | /* | |
455 | * Preserve bypass disable bits to be written back later | |
456 | */ | |
457 | bypass = readl(cpu_base + GIC_CPU_CTRL); | |
458 | bypass &= GICC_DIS_BYPASS_MASK; | |
459 | ||
0b996fd3 | 460 | writel_relaxed(bypass | mode | GICC_ENABLE, cpu_base + GIC_CPU_CTRL); |
32289506 FK |
461 | } |
462 | ||
463 | ||
4294f8ba | 464 | static void __init gic_dist_init(struct gic_chip_data *gic) |
f27ecacc | 465 | { |
75294957 | 466 | unsigned int i; |
267840f3 | 467 | u32 cpumask; |
4294f8ba | 468 | unsigned int gic_irqs = gic->gic_irqs; |
db0d4db2 | 469 | void __iomem *base = gic_data_dist_base(gic); |
f27ecacc | 470 | |
e5f81539 | 471 | writel_relaxed(GICD_DISABLE, base + GIC_DIST_CTRL); |
f27ecacc | 472 | |
f27ecacc RK |
473 | /* |
474 | * Set all global interrupts to this CPU only. | |
475 | */ | |
2bb31351 RK |
476 | cpumask = gic_get_cpumask(gic); |
477 | cpumask |= cpumask << 8; | |
478 | cpumask |= cpumask << 16; | |
e6afec9b | 479 | for (i = 32; i < gic_irqs; i += 4) |
6ac77e46 | 480 | writel_relaxed(cpumask, base + GIC_DIST_TARGET + i * 4 / 4); |
f27ecacc | 481 | |
d51d0af4 | 482 | gic_dist_config(base, gic_irqs, NULL); |
f27ecacc | 483 | |
e5f81539 | 484 | writel_relaxed(GICD_ENABLE, base + GIC_DIST_CTRL); |
f27ecacc RK |
485 | } |
486 | ||
8c37bb3a | 487 | static void gic_cpu_init(struct gic_chip_data *gic) |
f27ecacc | 488 | { |
db0d4db2 MZ |
489 | void __iomem *dist_base = gic_data_dist_base(gic); |
490 | void __iomem *base = gic_data_cpu_base(gic); | |
384a2902 | 491 | unsigned int cpu_mask, cpu = smp_processor_id(); |
9395f6ea RK |
492 | int i; |
493 | ||
384a2902 | 494 | /* |
567e5a01 JH |
495 | * Setting up the CPU map is only relevant for the primary GIC |
496 | * because any nested/secondary GICs do not directly interface | |
497 | * with the CPU(s). | |
384a2902 | 498 | */ |
567e5a01 JH |
499 | if (gic == &gic_data[0]) { |
500 | /* | |
501 | * Get what the GIC says our CPU mask is. | |
502 | */ | |
503 | BUG_ON(cpu >= NR_GIC_CPU_IF); | |
504 | cpu_mask = gic_get_cpumask(gic); | |
505 | gic_cpu_map[cpu] = cpu_mask; | |
384a2902 | 506 | |
567e5a01 JH |
507 | /* |
508 | * Clear our mask from the other map entries in case they're | |
509 | * still undefined. | |
510 | */ | |
511 | for (i = 0; i < NR_GIC_CPU_IF; i++) | |
512 | if (i != cpu) | |
513 | gic_cpu_map[i] &= ~cpu_mask; | |
514 | } | |
384a2902 | 515 | |
d51d0af4 | 516 | gic_cpu_config(dist_base, NULL); |
9395f6ea | 517 | |
e5f81539 | 518 | writel_relaxed(GICC_INT_PRI_THRESHOLD, base + GIC_CPU_PRIMASK); |
4c2880b3 | 519 | gic_cpu_if_up(gic); |
f27ecacc RK |
520 | } |
521 | ||
4c2880b3 | 522 | int gic_cpu_if_down(unsigned int gic_nr) |
10d9eb8a | 523 | { |
4c2880b3 | 524 | void __iomem *cpu_base; |
32289506 FK |
525 | u32 val = 0; |
526 | ||
4c2880b3 JH |
527 | if (gic_nr >= MAX_GIC_NR) |
528 | return -EINVAL; | |
529 | ||
530 | cpu_base = gic_data_cpu_base(&gic_data[gic_nr]); | |
32289506 FK |
531 | val = readl(cpu_base + GIC_CPU_CTRL); |
532 | val &= ~GICC_ENABLE; | |
533 | writel_relaxed(val, cpu_base + GIC_CPU_CTRL); | |
4c2880b3 JH |
534 | |
535 | return 0; | |
10d9eb8a NP |
536 | } |
537 | ||
254056f3 CC |
538 | #ifdef CONFIG_CPU_PM |
539 | /* | |
540 | * Saves the GIC distributor registers during suspend or idle. Must be called | |
541 | * with interrupts disabled but before powering down the GIC. After calling | |
542 | * this function, no interrupts will be delivered by the GIC, and another | |
543 | * platform-specific wakeup source must be enabled. | |
544 | */ | |
545 | static void gic_dist_save(unsigned int gic_nr) | |
546 | { | |
547 | unsigned int gic_irqs; | |
548 | void __iomem *dist_base; | |
549 | int i; | |
550 | ||
551 | if (gic_nr >= MAX_GIC_NR) | |
552 | BUG(); | |
553 | ||
554 | gic_irqs = gic_data[gic_nr].gic_irqs; | |
db0d4db2 | 555 | dist_base = gic_data_dist_base(&gic_data[gic_nr]); |
254056f3 CC |
556 | |
557 | if (!dist_base) | |
558 | return; | |
559 | ||
560 | for (i = 0; i < DIV_ROUND_UP(gic_irqs, 16); i++) | |
561 | gic_data[gic_nr].saved_spi_conf[i] = | |
562 | readl_relaxed(dist_base + GIC_DIST_CONFIG + i * 4); | |
563 | ||
564 | for (i = 0; i < DIV_ROUND_UP(gic_irqs, 4); i++) | |
565 | gic_data[gic_nr].saved_spi_target[i] = | |
566 | readl_relaxed(dist_base + GIC_DIST_TARGET + i * 4); | |
567 | ||
568 | for (i = 0; i < DIV_ROUND_UP(gic_irqs, 32); i++) | |
569 | gic_data[gic_nr].saved_spi_enable[i] = | |
570 | readl_relaxed(dist_base + GIC_DIST_ENABLE_SET + i * 4); | |
1c7d4dd4 MZ |
571 | |
572 | for (i = 0; i < DIV_ROUND_UP(gic_irqs, 32); i++) | |
573 | gic_data[gic_nr].saved_spi_active[i] = | |
574 | readl_relaxed(dist_base + GIC_DIST_ACTIVE_SET + i * 4); | |
254056f3 CC |
575 | } |
576 | ||
577 | /* | |
578 | * Restores the GIC distributor registers during resume or when coming out of | |
579 | * idle. Must be called before enabling interrupts. If a level interrupt | |
580 | * that occured while the GIC was suspended is still present, it will be | |
581 | * handled normally, but any edge interrupts that occured will not be seen by | |
582 | * the GIC and need to be handled by the platform-specific wakeup source. | |
583 | */ | |
584 | static void gic_dist_restore(unsigned int gic_nr) | |
585 | { | |
586 | unsigned int gic_irqs; | |
587 | unsigned int i; | |
588 | void __iomem *dist_base; | |
589 | ||
590 | if (gic_nr >= MAX_GIC_NR) | |
591 | BUG(); | |
592 | ||
593 | gic_irqs = gic_data[gic_nr].gic_irqs; | |
db0d4db2 | 594 | dist_base = gic_data_dist_base(&gic_data[gic_nr]); |
254056f3 CC |
595 | |
596 | if (!dist_base) | |
597 | return; | |
598 | ||
e5f81539 | 599 | writel_relaxed(GICD_DISABLE, dist_base + GIC_DIST_CTRL); |
254056f3 CC |
600 | |
601 | for (i = 0; i < DIV_ROUND_UP(gic_irqs, 16); i++) | |
602 | writel_relaxed(gic_data[gic_nr].saved_spi_conf[i], | |
603 | dist_base + GIC_DIST_CONFIG + i * 4); | |
604 | ||
605 | for (i = 0; i < DIV_ROUND_UP(gic_irqs, 4); i++) | |
e5f81539 | 606 | writel_relaxed(GICD_INT_DEF_PRI_X4, |
254056f3 CC |
607 | dist_base + GIC_DIST_PRI + i * 4); |
608 | ||
609 | for (i = 0; i < DIV_ROUND_UP(gic_irqs, 4); i++) | |
610 | writel_relaxed(gic_data[gic_nr].saved_spi_target[i], | |
611 | dist_base + GIC_DIST_TARGET + i * 4); | |
612 | ||
92eda4ad MZ |
613 | for (i = 0; i < DIV_ROUND_UP(gic_irqs, 32); i++) { |
614 | writel_relaxed(GICD_INT_EN_CLR_X32, | |
615 | dist_base + GIC_DIST_ENABLE_CLEAR + i * 4); | |
254056f3 CC |
616 | writel_relaxed(gic_data[gic_nr].saved_spi_enable[i], |
617 | dist_base + GIC_DIST_ENABLE_SET + i * 4); | |
92eda4ad | 618 | } |
254056f3 | 619 | |
1c7d4dd4 MZ |
620 | for (i = 0; i < DIV_ROUND_UP(gic_irqs, 32); i++) { |
621 | writel_relaxed(GICD_INT_EN_CLR_X32, | |
622 | dist_base + GIC_DIST_ACTIVE_CLEAR + i * 4); | |
623 | writel_relaxed(gic_data[gic_nr].saved_spi_active[i], | |
624 | dist_base + GIC_DIST_ACTIVE_SET + i * 4); | |
625 | } | |
626 | ||
e5f81539 | 627 | writel_relaxed(GICD_ENABLE, dist_base + GIC_DIST_CTRL); |
254056f3 CC |
628 | } |
629 | ||
630 | static void gic_cpu_save(unsigned int gic_nr) | |
631 | { | |
632 | int i; | |
633 | u32 *ptr; | |
634 | void __iomem *dist_base; | |
635 | void __iomem *cpu_base; | |
636 | ||
637 | if (gic_nr >= MAX_GIC_NR) | |
638 | BUG(); | |
639 | ||
db0d4db2 MZ |
640 | dist_base = gic_data_dist_base(&gic_data[gic_nr]); |
641 | cpu_base = gic_data_cpu_base(&gic_data[gic_nr]); | |
254056f3 CC |
642 | |
643 | if (!dist_base || !cpu_base) | |
644 | return; | |
645 | ||
532d0d06 | 646 | ptr = raw_cpu_ptr(gic_data[gic_nr].saved_ppi_enable); |
254056f3 CC |
647 | for (i = 0; i < DIV_ROUND_UP(32, 32); i++) |
648 | ptr[i] = readl_relaxed(dist_base + GIC_DIST_ENABLE_SET + i * 4); | |
649 | ||
1c7d4dd4 MZ |
650 | ptr = raw_cpu_ptr(gic_data[gic_nr].saved_ppi_active); |
651 | for (i = 0; i < DIV_ROUND_UP(32, 32); i++) | |
652 | ptr[i] = readl_relaxed(dist_base + GIC_DIST_ACTIVE_SET + i * 4); | |
653 | ||
532d0d06 | 654 | ptr = raw_cpu_ptr(gic_data[gic_nr].saved_ppi_conf); |
254056f3 CC |
655 | for (i = 0; i < DIV_ROUND_UP(32, 16); i++) |
656 | ptr[i] = readl_relaxed(dist_base + GIC_DIST_CONFIG + i * 4); | |
657 | ||
658 | } | |
659 | ||
660 | static void gic_cpu_restore(unsigned int gic_nr) | |
661 | { | |
662 | int i; | |
663 | u32 *ptr; | |
664 | void __iomem *dist_base; | |
665 | void __iomem *cpu_base; | |
666 | ||
667 | if (gic_nr >= MAX_GIC_NR) | |
668 | BUG(); | |
669 | ||
db0d4db2 MZ |
670 | dist_base = gic_data_dist_base(&gic_data[gic_nr]); |
671 | cpu_base = gic_data_cpu_base(&gic_data[gic_nr]); | |
254056f3 CC |
672 | |
673 | if (!dist_base || !cpu_base) | |
674 | return; | |
675 | ||
532d0d06 | 676 | ptr = raw_cpu_ptr(gic_data[gic_nr].saved_ppi_enable); |
92eda4ad MZ |
677 | for (i = 0; i < DIV_ROUND_UP(32, 32); i++) { |
678 | writel_relaxed(GICD_INT_EN_CLR_X32, | |
679 | dist_base + GIC_DIST_ENABLE_CLEAR + i * 4); | |
254056f3 | 680 | writel_relaxed(ptr[i], dist_base + GIC_DIST_ENABLE_SET + i * 4); |
92eda4ad | 681 | } |
254056f3 | 682 | |
1c7d4dd4 MZ |
683 | ptr = raw_cpu_ptr(gic_data[gic_nr].saved_ppi_active); |
684 | for (i = 0; i < DIV_ROUND_UP(32, 32); i++) { | |
685 | writel_relaxed(GICD_INT_EN_CLR_X32, | |
686 | dist_base + GIC_DIST_ACTIVE_CLEAR + i * 4); | |
687 | writel_relaxed(ptr[i], dist_base + GIC_DIST_ACTIVE_SET + i * 4); | |
688 | } | |
689 | ||
532d0d06 | 690 | ptr = raw_cpu_ptr(gic_data[gic_nr].saved_ppi_conf); |
254056f3 CC |
691 | for (i = 0; i < DIV_ROUND_UP(32, 16); i++) |
692 | writel_relaxed(ptr[i], dist_base + GIC_DIST_CONFIG + i * 4); | |
693 | ||
694 | for (i = 0; i < DIV_ROUND_UP(32, 4); i++) | |
e5f81539 FK |
695 | writel_relaxed(GICD_INT_DEF_PRI_X4, |
696 | dist_base + GIC_DIST_PRI + i * 4); | |
254056f3 | 697 | |
e5f81539 | 698 | writel_relaxed(GICC_INT_PRI_THRESHOLD, cpu_base + GIC_CPU_PRIMASK); |
4c2880b3 | 699 | gic_cpu_if_up(&gic_data[gic_nr]); |
254056f3 CC |
700 | } |
701 | ||
702 | static int gic_notifier(struct notifier_block *self, unsigned long cmd, void *v) | |
703 | { | |
704 | int i; | |
705 | ||
706 | for (i = 0; i < MAX_GIC_NR; i++) { | |
db0d4db2 MZ |
707 | #ifdef CONFIG_GIC_NON_BANKED |
708 | /* Skip over unused GICs */ | |
709 | if (!gic_data[i].get_base) | |
710 | continue; | |
711 | #endif | |
254056f3 CC |
712 | switch (cmd) { |
713 | case CPU_PM_ENTER: | |
714 | gic_cpu_save(i); | |
715 | break; | |
716 | case CPU_PM_ENTER_FAILED: | |
717 | case CPU_PM_EXIT: | |
718 | gic_cpu_restore(i); | |
719 | break; | |
720 | case CPU_CLUSTER_PM_ENTER: | |
721 | gic_dist_save(i); | |
722 | break; | |
723 | case CPU_CLUSTER_PM_ENTER_FAILED: | |
724 | case CPU_CLUSTER_PM_EXIT: | |
725 | gic_dist_restore(i); | |
726 | break; | |
727 | } | |
728 | } | |
729 | ||
730 | return NOTIFY_OK; | |
731 | } | |
732 | ||
733 | static struct notifier_block gic_notifier_block = { | |
734 | .notifier_call = gic_notifier, | |
735 | }; | |
736 | ||
737 | static void __init gic_pm_init(struct gic_chip_data *gic) | |
738 | { | |
739 | gic->saved_ppi_enable = __alloc_percpu(DIV_ROUND_UP(32, 32) * 4, | |
740 | sizeof(u32)); | |
741 | BUG_ON(!gic->saved_ppi_enable); | |
742 | ||
1c7d4dd4 MZ |
743 | gic->saved_ppi_active = __alloc_percpu(DIV_ROUND_UP(32, 32) * 4, |
744 | sizeof(u32)); | |
745 | BUG_ON(!gic->saved_ppi_active); | |
746 | ||
254056f3 CC |
747 | gic->saved_ppi_conf = __alloc_percpu(DIV_ROUND_UP(32, 16) * 4, |
748 | sizeof(u32)); | |
749 | BUG_ON(!gic->saved_ppi_conf); | |
750 | ||
abdd7b91 MZ |
751 | if (gic == &gic_data[0]) |
752 | cpu_pm_register_notifier(&gic_notifier_block); | |
254056f3 CC |
753 | } |
754 | #else | |
755 | static void __init gic_pm_init(struct gic_chip_data *gic) | |
756 | { | |
757 | } | |
758 | #endif | |
759 | ||
b1cffebf | 760 | #ifdef CONFIG_SMP |
6859358e | 761 | static void gic_raise_softirq(const struct cpumask *mask, unsigned int irq) |
b1cffebf RH |
762 | { |
763 | int cpu; | |
1a6b69b6 NP |
764 | unsigned long flags, map = 0; |
765 | ||
766 | raw_spin_lock_irqsave(&irq_controller_lock, flags); | |
b1cffebf RH |
767 | |
768 | /* Convert our logical CPU mask into a physical one. */ | |
769 | for_each_cpu(cpu, mask) | |
91bdf0d0 | 770 | map |= gic_cpu_map[cpu]; |
b1cffebf RH |
771 | |
772 | /* | |
773 | * Ensure that stores to Normal memory are visible to the | |
8adbf57f | 774 | * other CPUs before they observe us issuing the IPI. |
b1cffebf | 775 | */ |
8adbf57f | 776 | dmb(ishst); |
b1cffebf RH |
777 | |
778 | /* this always happens on GIC0 */ | |
779 | writel_relaxed(map << 16 | irq, gic_data_dist_base(&gic_data[0]) + GIC_DIST_SOFTINT); | |
1a6b69b6 NP |
780 | |
781 | raw_spin_unlock_irqrestore(&irq_controller_lock, flags); | |
782 | } | |
783 | #endif | |
784 | ||
785 | #ifdef CONFIG_BL_SWITCHER | |
14d2ca61 NP |
786 | /* |
787 | * gic_send_sgi - send a SGI directly to given CPU interface number | |
788 | * | |
789 | * cpu_id: the ID for the destination CPU interface | |
790 | * irq: the IPI number to send a SGI for | |
791 | */ | |
792 | void gic_send_sgi(unsigned int cpu_id, unsigned int irq) | |
793 | { | |
794 | BUG_ON(cpu_id >= NR_GIC_CPU_IF); | |
795 | cpu_id = 1 << cpu_id; | |
796 | /* this always happens on GIC0 */ | |
797 | writel_relaxed((cpu_id << 16) | irq, gic_data_dist_base(&gic_data[0]) + GIC_DIST_SOFTINT); | |
798 | } | |
799 | ||
ed96762e NP |
800 | /* |
801 | * gic_get_cpu_id - get the CPU interface ID for the specified CPU | |
802 | * | |
803 | * @cpu: the logical CPU number to get the GIC ID for. | |
804 | * | |
805 | * Return the CPU interface ID for the given logical CPU number, | |
806 | * or -1 if the CPU number is too large or the interface ID is | |
807 | * unknown (more than one bit set). | |
808 | */ | |
809 | int gic_get_cpu_id(unsigned int cpu) | |
810 | { | |
811 | unsigned int cpu_bit; | |
812 | ||
813 | if (cpu >= NR_GIC_CPU_IF) | |
814 | return -1; | |
815 | cpu_bit = gic_cpu_map[cpu]; | |
816 | if (cpu_bit & (cpu_bit - 1)) | |
817 | return -1; | |
818 | return __ffs(cpu_bit); | |
819 | } | |
820 | ||
1a6b69b6 NP |
821 | /* |
822 | * gic_migrate_target - migrate IRQs to another CPU interface | |
823 | * | |
824 | * @new_cpu_id: the CPU target ID to migrate IRQs to | |
825 | * | |
826 | * Migrate all peripheral interrupts with a target matching the current CPU | |
827 | * to the interface corresponding to @new_cpu_id. The CPU interface mapping | |
828 | * is also updated. Targets to other CPU interfaces are unchanged. | |
829 | * This must be called with IRQs locally disabled. | |
830 | */ | |
831 | void gic_migrate_target(unsigned int new_cpu_id) | |
832 | { | |
833 | unsigned int cur_cpu_id, gic_irqs, gic_nr = 0; | |
834 | void __iomem *dist_base; | |
835 | int i, ror_val, cpu = smp_processor_id(); | |
836 | u32 val, cur_target_mask, active_mask; | |
837 | ||
838 | if (gic_nr >= MAX_GIC_NR) | |
839 | BUG(); | |
840 | ||
841 | dist_base = gic_data_dist_base(&gic_data[gic_nr]); | |
842 | if (!dist_base) | |
843 | return; | |
844 | gic_irqs = gic_data[gic_nr].gic_irqs; | |
845 | ||
846 | cur_cpu_id = __ffs(gic_cpu_map[cpu]); | |
847 | cur_target_mask = 0x01010101 << cur_cpu_id; | |
848 | ror_val = (cur_cpu_id - new_cpu_id) & 31; | |
849 | ||
850 | raw_spin_lock(&irq_controller_lock); | |
851 | ||
852 | /* Update the target interface for this logical CPU */ | |
853 | gic_cpu_map[cpu] = 1 << new_cpu_id; | |
854 | ||
855 | /* | |
856 | * Find all the peripheral interrupts targetting the current | |
857 | * CPU interface and migrate them to the new CPU interface. | |
858 | * We skip DIST_TARGET 0 to 7 as they are read-only. | |
859 | */ | |
860 | for (i = 8; i < DIV_ROUND_UP(gic_irqs, 4); i++) { | |
861 | val = readl_relaxed(dist_base + GIC_DIST_TARGET + i * 4); | |
862 | active_mask = val & cur_target_mask; | |
863 | if (active_mask) { | |
864 | val &= ~active_mask; | |
865 | val |= ror32(active_mask, ror_val); | |
866 | writel_relaxed(val, dist_base + GIC_DIST_TARGET + i*4); | |
867 | } | |
868 | } | |
869 | ||
870 | raw_spin_unlock(&irq_controller_lock); | |
871 | ||
872 | /* | |
873 | * Now let's migrate and clear any potential SGIs that might be | |
874 | * pending for us (cur_cpu_id). Since GIC_DIST_SGI_PENDING_SET | |
875 | * is a banked register, we can only forward the SGI using | |
876 | * GIC_DIST_SOFTINT. The original SGI source is lost but Linux | |
877 | * doesn't use that information anyway. | |
878 | * | |
879 | * For the same reason we do not adjust SGI source information | |
880 | * for previously sent SGIs by us to other CPUs either. | |
881 | */ | |
882 | for (i = 0; i < 16; i += 4) { | |
883 | int j; | |
884 | val = readl_relaxed(dist_base + GIC_DIST_SGI_PENDING_SET + i); | |
885 | if (!val) | |
886 | continue; | |
887 | writel_relaxed(val, dist_base + GIC_DIST_SGI_PENDING_CLEAR + i); | |
888 | for (j = i; j < i + 4; j++) { | |
889 | if (val & 0xff) | |
890 | writel_relaxed((1 << (new_cpu_id + 16)) | j, | |
891 | dist_base + GIC_DIST_SOFTINT); | |
892 | val >>= 8; | |
893 | } | |
894 | } | |
b1cffebf | 895 | } |
eeb44658 NP |
896 | |
897 | /* | |
898 | * gic_get_sgir_physaddr - get the physical address for the SGI register | |
899 | * | |
900 | * REturn the physical address of the SGI register to be used | |
901 | * by some early assembly code when the kernel is not yet available. | |
902 | */ | |
903 | static unsigned long gic_dist_physaddr; | |
904 | ||
905 | unsigned long gic_get_sgir_physaddr(void) | |
906 | { | |
907 | if (!gic_dist_physaddr) | |
908 | return 0; | |
909 | return gic_dist_physaddr + GIC_DIST_SOFTINT; | |
910 | } | |
911 | ||
912 | void __init gic_init_physaddr(struct device_node *node) | |
913 | { | |
914 | struct resource res; | |
915 | if (of_address_to_resource(node, 0, &res) == 0) { | |
916 | gic_dist_physaddr = res.start; | |
917 | pr_info("GIC physical location is %#lx\n", gic_dist_physaddr); | |
918 | } | |
919 | } | |
920 | ||
921 | #else | |
922 | #define gic_init_physaddr(node) do { } while (0) | |
b1cffebf RH |
923 | #endif |
924 | ||
75294957 GL |
925 | static int gic_irq_domain_map(struct irq_domain *d, unsigned int irq, |
926 | irq_hw_number_t hw) | |
927 | { | |
0b996fd3 MZ |
928 | struct irq_chip *chip = &gic_chip; |
929 | ||
930 | if (static_key_true(&supports_deactivate)) { | |
931 | if (d->host_data == (void *)&gic_data[0]) | |
932 | chip = &gic_eoimode1_chip; | |
933 | } | |
934 | ||
75294957 GL |
935 | if (hw < 32) { |
936 | irq_set_percpu_devid(irq); | |
0b996fd3 | 937 | irq_domain_set_info(d, irq, hw, chip, d->host_data, |
9a1091ef | 938 | handle_percpu_devid_irq, NULL, NULL); |
d17cab44 | 939 | irq_set_status_flags(irq, IRQ_NOAUTOEN); |
75294957 | 940 | } else { |
0b996fd3 | 941 | irq_domain_set_info(d, irq, hw, chip, d->host_data, |
9a1091ef | 942 | handle_fasteoi_irq, NULL, NULL); |
d17cab44 | 943 | irq_set_probe(irq); |
75294957 | 944 | } |
75294957 GL |
945 | return 0; |
946 | } | |
947 | ||
006e983b S |
948 | static void gic_irq_domain_unmap(struct irq_domain *d, unsigned int irq) |
949 | { | |
006e983b S |
950 | } |
951 | ||
f833f57f MZ |
952 | static int gic_irq_domain_translate(struct irq_domain *d, |
953 | struct irq_fwspec *fwspec, | |
954 | unsigned long *hwirq, | |
955 | unsigned int *type) | |
956 | { | |
957 | if (is_of_node(fwspec->fwnode)) { | |
958 | if (fwspec->param_count < 3) | |
959 | return -EINVAL; | |
960 | ||
961 | /* Get the interrupt number and add 16 to skip over SGIs */ | |
962 | *hwirq = fwspec->param[1] + 16; | |
963 | ||
964 | /* | |
965 | * For SPIs, we need to add 16 more to get the GIC irq | |
966 | * ID number | |
967 | */ | |
968 | if (!fwspec->param[0]) | |
969 | *hwirq += 16; | |
970 | ||
971 | *type = fwspec->param[2] & IRQ_TYPE_SENSE_MASK; | |
972 | return 0; | |
973 | } | |
974 | ||
891ae769 MZ |
975 | if (fwspec->fwnode->type == FWNODE_IRQCHIP) { |
976 | if(fwspec->param_count != 2) | |
977 | return -EINVAL; | |
978 | ||
979 | *hwirq = fwspec->param[0]; | |
980 | *type = fwspec->param[1]; | |
981 | return 0; | |
982 | } | |
983 | ||
f833f57f MZ |
984 | return -EINVAL; |
985 | } | |
986 | ||
c0114709 | 987 | #ifdef CONFIG_SMP |
8c37bb3a PG |
988 | static int gic_secondary_init(struct notifier_block *nfb, unsigned long action, |
989 | void *hcpu) | |
c0114709 | 990 | { |
8b6fd652 | 991 | if (action == CPU_STARTING || action == CPU_STARTING_FROZEN) |
c0114709 CM |
992 | gic_cpu_init(&gic_data[0]); |
993 | return NOTIFY_OK; | |
994 | } | |
995 | ||
996 | /* | |
997 | * Notifier for enabling the GIC CPU interface. Set an arbitrarily high | |
998 | * priority because the GIC needs to be up before the ARM generic timers. | |
999 | */ | |
8c37bb3a | 1000 | static struct notifier_block gic_cpu_notifier = { |
c0114709 CM |
1001 | .notifier_call = gic_secondary_init, |
1002 | .priority = 100, | |
1003 | }; | |
1004 | #endif | |
1005 | ||
9a1091ef YC |
1006 | static int gic_irq_domain_alloc(struct irq_domain *domain, unsigned int virq, |
1007 | unsigned int nr_irqs, void *arg) | |
1008 | { | |
1009 | int i, ret; | |
1010 | irq_hw_number_t hwirq; | |
1011 | unsigned int type = IRQ_TYPE_NONE; | |
f833f57f | 1012 | struct irq_fwspec *fwspec = arg; |
9a1091ef | 1013 | |
f833f57f | 1014 | ret = gic_irq_domain_translate(domain, fwspec, &hwirq, &type); |
9a1091ef YC |
1015 | if (ret) |
1016 | return ret; | |
1017 | ||
1018 | for (i = 0; i < nr_irqs; i++) | |
1019 | gic_irq_domain_map(domain, virq + i, hwirq + i); | |
1020 | ||
1021 | return 0; | |
1022 | } | |
1023 | ||
1024 | static const struct irq_domain_ops gic_irq_domain_hierarchy_ops = { | |
f833f57f | 1025 | .translate = gic_irq_domain_translate, |
9a1091ef YC |
1026 | .alloc = gic_irq_domain_alloc, |
1027 | .free = irq_domain_free_irqs_top, | |
1028 | }; | |
1029 | ||
6859358e | 1030 | static const struct irq_domain_ops gic_irq_domain_ops = { |
75294957 | 1031 | .map = gic_irq_domain_map, |
006e983b | 1032 | .unmap = gic_irq_domain_unmap, |
4294f8ba RH |
1033 | }; |
1034 | ||
4a6ac304 | 1035 | static void __init __gic_init_bases(unsigned int gic_nr, int irq_start, |
db0d4db2 | 1036 | void __iomem *dist_base, void __iomem *cpu_base, |
891ae769 | 1037 | u32 percpu_offset, struct fwnode_handle *handle) |
b580b899 | 1038 | { |
75294957 | 1039 | irq_hw_number_t hwirq_base; |
bef8f9ee | 1040 | struct gic_chip_data *gic; |
384a2902 | 1041 | int gic_irqs, irq_base, i; |
bef8f9ee RK |
1042 | |
1043 | BUG_ON(gic_nr >= MAX_GIC_NR); | |
1044 | ||
76e52dd0 MZ |
1045 | gic_check_cpu_features(); |
1046 | ||
bef8f9ee | 1047 | gic = &gic_data[gic_nr]; |
db0d4db2 MZ |
1048 | #ifdef CONFIG_GIC_NON_BANKED |
1049 | if (percpu_offset) { /* Frankein-GIC without banked registers... */ | |
1050 | unsigned int cpu; | |
1051 | ||
1052 | gic->dist_base.percpu_base = alloc_percpu(void __iomem *); | |
1053 | gic->cpu_base.percpu_base = alloc_percpu(void __iomem *); | |
1054 | if (WARN_ON(!gic->dist_base.percpu_base || | |
1055 | !gic->cpu_base.percpu_base)) { | |
1056 | free_percpu(gic->dist_base.percpu_base); | |
1057 | free_percpu(gic->cpu_base.percpu_base); | |
1058 | return; | |
1059 | } | |
1060 | ||
1061 | for_each_possible_cpu(cpu) { | |
29e697b1 TF |
1062 | u32 mpidr = cpu_logical_map(cpu); |
1063 | u32 core_id = MPIDR_AFFINITY_LEVEL(mpidr, 0); | |
1064 | unsigned long offset = percpu_offset * core_id; | |
db0d4db2 MZ |
1065 | *per_cpu_ptr(gic->dist_base.percpu_base, cpu) = dist_base + offset; |
1066 | *per_cpu_ptr(gic->cpu_base.percpu_base, cpu) = cpu_base + offset; | |
1067 | } | |
1068 | ||
1069 | gic_set_base_accessor(gic, gic_get_percpu_base); | |
1070 | } else | |
1071 | #endif | |
1072 | { /* Normal, sane GIC... */ | |
1073 | WARN(percpu_offset, | |
1074 | "GIC_NON_BANKED not enabled, ignoring %08x offset!", | |
1075 | percpu_offset); | |
1076 | gic->dist_base.common_base = dist_base; | |
1077 | gic->cpu_base.common_base = cpu_base; | |
1078 | gic_set_base_accessor(gic, gic_get_common_base); | |
1079 | } | |
bef8f9ee | 1080 | |
4294f8ba RH |
1081 | /* |
1082 | * Find out how many interrupts are supported. | |
1083 | * The GIC only supports up to 1020 interrupt sources. | |
1084 | */ | |
db0d4db2 | 1085 | gic_irqs = readl_relaxed(gic_data_dist_base(gic) + GIC_DIST_CTR) & 0x1f; |
4294f8ba RH |
1086 | gic_irqs = (gic_irqs + 1) * 32; |
1087 | if (gic_irqs > 1020) | |
1088 | gic_irqs = 1020; | |
1089 | gic->gic_irqs = gic_irqs; | |
1090 | ||
891ae769 MZ |
1091 | if (handle) { /* DT/ACPI */ |
1092 | gic->domain = irq_domain_create_linear(handle, gic_irqs, | |
1093 | &gic_irq_domain_hierarchy_ops, | |
1094 | gic); | |
1095 | } else { /* Legacy support */ | |
9a1091ef YC |
1096 | /* |
1097 | * For primary GICs, skip over SGIs. | |
1098 | * For secondary GICs, skip over PPIs, too. | |
1099 | */ | |
1100 | if (gic_nr == 0 && (irq_start & 31) > 0) { | |
1101 | hwirq_base = 16; | |
1102 | if (irq_start != -1) | |
1103 | irq_start = (irq_start & ~31) + 16; | |
1104 | } else { | |
1105 | hwirq_base = 32; | |
1106 | } | |
1107 | ||
1108 | gic_irqs -= hwirq_base; /* calculate # of irqs to allocate */ | |
006e983b | 1109 | |
006e983b S |
1110 | irq_base = irq_alloc_descs(irq_start, 16, gic_irqs, |
1111 | numa_node_id()); | |
1112 | if (IS_ERR_VALUE(irq_base)) { | |
1113 | WARN(1, "Cannot allocate irq_descs @ IRQ%d, assuming pre-allocated\n", | |
1114 | irq_start); | |
1115 | irq_base = irq_start; | |
1116 | } | |
1117 | ||
891ae769 | 1118 | gic->domain = irq_domain_add_legacy(NULL, gic_irqs, irq_base, |
006e983b | 1119 | hwirq_base, &gic_irq_domain_ops, gic); |
f37a53cc | 1120 | } |
006e983b | 1121 | |
75294957 GL |
1122 | if (WARN_ON(!gic->domain)) |
1123 | return; | |
bef8f9ee | 1124 | |
08332dff | 1125 | if (gic_nr == 0) { |
567e5a01 JH |
1126 | /* |
1127 | * Initialize the CPU interface map to all CPUs. | |
1128 | * It will be refined as each CPU probes its ID. | |
1129 | * This is only necessary for the primary GIC. | |
1130 | */ | |
1131 | for (i = 0; i < NR_GIC_CPU_IF; i++) | |
1132 | gic_cpu_map[i] = 0xff; | |
b1cffebf | 1133 | #ifdef CONFIG_SMP |
08332dff MR |
1134 | set_smp_cross_call(gic_raise_softirq); |
1135 | register_cpu_notifier(&gic_cpu_notifier); | |
b1cffebf | 1136 | #endif |
08332dff | 1137 | set_handle_irq(gic_handle_irq); |
0b996fd3 MZ |
1138 | if (static_key_true(&supports_deactivate)) |
1139 | pr_info("GIC: Using split EOI/Deactivate mode\n"); | |
08332dff | 1140 | } |
cfed7d60 | 1141 | |
4294f8ba | 1142 | gic_dist_init(gic); |
bef8f9ee | 1143 | gic_cpu_init(gic); |
254056f3 | 1144 | gic_pm_init(gic); |
b580b899 RK |
1145 | } |
1146 | ||
e81a7cd9 MZ |
1147 | void __init gic_init(unsigned int gic_nr, int irq_start, |
1148 | void __iomem *dist_base, void __iomem *cpu_base) | |
4a6ac304 MZ |
1149 | { |
1150 | /* | |
1151 | * Non-DT/ACPI systems won't run a hypervisor, so let's not | |
1152 | * bother with these... | |
1153 | */ | |
1154 | static_key_slow_dec(&supports_deactivate); | |
e81a7cd9 | 1155 | __gic_init_bases(gic_nr, irq_start, dist_base, cpu_base, 0, NULL); |
4a6ac304 MZ |
1156 | } |
1157 | ||
b3f7ed03 | 1158 | #ifdef CONFIG_OF |
46f101df | 1159 | static int gic_cnt __initdata; |
b3f7ed03 | 1160 | |
12e14066 MZ |
1161 | static bool gic_check_eoimode(struct device_node *node, void __iomem **base) |
1162 | { | |
1163 | struct resource cpuif_res; | |
1164 | ||
1165 | of_address_to_resource(node, 1, &cpuif_res); | |
1166 | ||
1167 | if (!is_hyp_mode_available()) | |
1168 | return false; | |
1169 | if (resource_size(&cpuif_res) < SZ_8K) | |
1170 | return false; | |
1171 | if (resource_size(&cpuif_res) == SZ_128K) { | |
1172 | u32 val_low, val_high; | |
1173 | ||
1174 | /* | |
1175 | * Verify that we have the first 4kB of a GIC400 | |
1176 | * aliased over the first 64kB by checking the | |
1177 | * GICC_IIDR register on both ends. | |
1178 | */ | |
1179 | val_low = readl_relaxed(*base + GIC_CPU_IDENT); | |
1180 | val_high = readl_relaxed(*base + GIC_CPU_IDENT + 0xf000); | |
1181 | if ((val_low & 0xffff0fff) != 0x0202043B || | |
1182 | val_low != val_high) | |
1183 | return false; | |
1184 | ||
1185 | /* | |
1186 | * Move the base up by 60kB, so that we have a 8kB | |
1187 | * contiguous region, which allows us to use GICC_DIR | |
1188 | * at its normal offset. Please pass me that bucket. | |
1189 | */ | |
1190 | *base += 0xf000; | |
1191 | cpuif_res.start += 0xf000; | |
1192 | pr_warn("GIC: Adjusting CPU interface base to %pa", | |
1193 | &cpuif_res.start); | |
1194 | } | |
1195 | ||
1196 | return true; | |
1197 | } | |
1198 | ||
6859358e SB |
1199 | static int __init |
1200 | gic_of_init(struct device_node *node, struct device_node *parent) | |
b3f7ed03 RH |
1201 | { |
1202 | void __iomem *cpu_base; | |
1203 | void __iomem *dist_base; | |
db0d4db2 | 1204 | u32 percpu_offset; |
b3f7ed03 | 1205 | int irq; |
b3f7ed03 RH |
1206 | |
1207 | if (WARN_ON(!node)) | |
1208 | return -ENODEV; | |
1209 | ||
1210 | dist_base = of_iomap(node, 0); | |
1211 | WARN(!dist_base, "unable to map gic dist registers\n"); | |
1212 | ||
1213 | cpu_base = of_iomap(node, 1); | |
1214 | WARN(!cpu_base, "unable to map gic cpu registers\n"); | |
1215 | ||
0b996fd3 MZ |
1216 | /* |
1217 | * Disable split EOI/Deactivate if either HYP is not available | |
1218 | * or the CPU interface is too small. | |
1219 | */ | |
12e14066 | 1220 | if (gic_cnt == 0 && !gic_check_eoimode(node, &cpu_base)) |
0b996fd3 MZ |
1221 | static_key_slow_dec(&supports_deactivate); |
1222 | ||
db0d4db2 MZ |
1223 | if (of_property_read_u32(node, "cpu-offset", &percpu_offset)) |
1224 | percpu_offset = 0; | |
1225 | ||
891ae769 MZ |
1226 | __gic_init_bases(gic_cnt, -1, dist_base, cpu_base, percpu_offset, |
1227 | &node->fwnode); | |
eeb44658 NP |
1228 | if (!gic_cnt) |
1229 | gic_init_physaddr(node); | |
b3f7ed03 RH |
1230 | |
1231 | if (parent) { | |
1232 | irq = irq_of_parse_and_map(node, 0); | |
1233 | gic_cascade_irq(gic_cnt, irq); | |
1234 | } | |
853a33ce SS |
1235 | |
1236 | if (IS_ENABLED(CONFIG_ARM_GIC_V2M)) | |
1237 | gicv2m_of_init(node, gic_data[gic_cnt].domain); | |
1238 | ||
b3f7ed03 RH |
1239 | gic_cnt++; |
1240 | return 0; | |
1241 | } | |
144cb088 | 1242 | IRQCHIP_DECLARE(gic_400, "arm,gic-400", gic_of_init); |
fa6e2eec LW |
1243 | IRQCHIP_DECLARE(arm11mp_gic, "arm,arm11mp-gic", gic_of_init); |
1244 | IRQCHIP_DECLARE(arm1176jzf_dc_gic, "arm,arm1176jzf-devchip-gic", gic_of_init); | |
81243e44 RH |
1245 | IRQCHIP_DECLARE(cortex_a15_gic, "arm,cortex-a15-gic", gic_of_init); |
1246 | IRQCHIP_DECLARE(cortex_a9_gic, "arm,cortex-a9-gic", gic_of_init); | |
a97e8027 | 1247 | IRQCHIP_DECLARE(cortex_a7_gic, "arm,cortex-a7-gic", gic_of_init); |
81243e44 RH |
1248 | IRQCHIP_DECLARE(msm_8660_qgic, "qcom,msm-8660-qgic", gic_of_init); |
1249 | IRQCHIP_DECLARE(msm_qgic2, "qcom,msm-qgic2", gic_of_init); | |
8709b9eb | 1250 | IRQCHIP_DECLARE(pl390, "arm,pl390", gic_of_init); |
81243e44 | 1251 | |
b3f7ed03 | 1252 | #endif |
d60fc389 TN |
1253 | |
1254 | #ifdef CONFIG_ACPI | |
f26527b1 | 1255 | static phys_addr_t cpu_phy_base __initdata; |
d60fc389 TN |
1256 | |
1257 | static int __init | |
1258 | gic_acpi_parse_madt_cpu(struct acpi_subtable_header *header, | |
1259 | const unsigned long end) | |
1260 | { | |
1261 | struct acpi_madt_generic_interrupt *processor; | |
1262 | phys_addr_t gic_cpu_base; | |
1263 | static int cpu_base_assigned; | |
1264 | ||
1265 | processor = (struct acpi_madt_generic_interrupt *)header; | |
1266 | ||
99e3e3ae | 1267 | if (BAD_MADT_GICC_ENTRY(processor, end)) |
d60fc389 TN |
1268 | return -EINVAL; |
1269 | ||
1270 | /* | |
1271 | * There is no support for non-banked GICv1/2 register in ACPI spec. | |
1272 | * All CPU interface addresses have to be the same. | |
1273 | */ | |
1274 | gic_cpu_base = processor->base_address; | |
1275 | if (cpu_base_assigned && gic_cpu_base != cpu_phy_base) | |
1276 | return -EINVAL; | |
1277 | ||
1278 | cpu_phy_base = gic_cpu_base; | |
1279 | cpu_base_assigned = 1; | |
1280 | return 0; | |
1281 | } | |
1282 | ||
f26527b1 MZ |
1283 | /* The things you have to do to just *count* something... */ |
1284 | static int __init acpi_dummy_func(struct acpi_subtable_header *header, | |
1285 | const unsigned long end) | |
d60fc389 | 1286 | { |
f26527b1 MZ |
1287 | return 0; |
1288 | } | |
d60fc389 | 1289 | |
f26527b1 MZ |
1290 | static bool __init acpi_gic_redist_is_present(void) |
1291 | { | |
1292 | return acpi_table_parse_madt(ACPI_MADT_TYPE_GENERIC_REDISTRIBUTOR, | |
1293 | acpi_dummy_func, 0) > 0; | |
1294 | } | |
d60fc389 | 1295 | |
f26527b1 MZ |
1296 | static bool __init gic_validate_dist(struct acpi_subtable_header *header, |
1297 | struct acpi_probe_entry *ape) | |
1298 | { | |
1299 | struct acpi_madt_generic_distributor *dist; | |
1300 | dist = (struct acpi_madt_generic_distributor *)header; | |
d60fc389 | 1301 | |
f26527b1 MZ |
1302 | return (dist->version == ape->driver_data && |
1303 | (dist->version != ACPI_MADT_GIC_VERSION_NONE || | |
1304 | !acpi_gic_redist_is_present())); | |
d60fc389 TN |
1305 | } |
1306 | ||
f26527b1 MZ |
1307 | #define ACPI_GICV2_DIST_MEM_SIZE (SZ_4K) |
1308 | #define ACPI_GIC_CPU_IF_MEM_SIZE (SZ_8K) | |
1309 | ||
1310 | static int __init gic_v2_acpi_init(struct acpi_subtable_header *header, | |
1311 | const unsigned long end) | |
d60fc389 | 1312 | { |
f26527b1 | 1313 | struct acpi_madt_generic_distributor *dist; |
d60fc389 | 1314 | void __iomem *cpu_base, *dist_base; |
891ae769 | 1315 | struct fwnode_handle *domain_handle; |
d60fc389 TN |
1316 | int count; |
1317 | ||
1318 | /* Collect CPU base addresses */ | |
f26527b1 MZ |
1319 | count = acpi_table_parse_madt(ACPI_MADT_TYPE_GENERIC_INTERRUPT, |
1320 | gic_acpi_parse_madt_cpu, 0); | |
d60fc389 TN |
1321 | if (count <= 0) { |
1322 | pr_err("No valid GICC entries exist\n"); | |
1323 | return -EINVAL; | |
1324 | } | |
1325 | ||
d60fc389 TN |
1326 | cpu_base = ioremap(cpu_phy_base, ACPI_GIC_CPU_IF_MEM_SIZE); |
1327 | if (!cpu_base) { | |
1328 | pr_err("Unable to map GICC registers\n"); | |
1329 | return -ENOMEM; | |
1330 | } | |
1331 | ||
f26527b1 MZ |
1332 | dist = (struct acpi_madt_generic_distributor *)header; |
1333 | dist_base = ioremap(dist->base_address, ACPI_GICV2_DIST_MEM_SIZE); | |
d60fc389 TN |
1334 | if (!dist_base) { |
1335 | pr_err("Unable to map GICD registers\n"); | |
1336 | iounmap(cpu_base); | |
1337 | return -ENOMEM; | |
1338 | } | |
1339 | ||
0b996fd3 MZ |
1340 | /* |
1341 | * Disable split EOI/Deactivate if HYP is not available. ACPI | |
1342 | * guarantees that we'll always have a GICv2, so the CPU | |
1343 | * interface will always be the right size. | |
1344 | */ | |
1345 | if (!is_hyp_mode_available()) | |
1346 | static_key_slow_dec(&supports_deactivate); | |
1347 | ||
d60fc389 | 1348 | /* |
891ae769 | 1349 | * Initialize GIC instance zero (no multi-GIC support). |
d60fc389 | 1350 | */ |
891ae769 MZ |
1351 | domain_handle = irq_domain_alloc_fwnode(dist_base); |
1352 | if (!domain_handle) { | |
1353 | pr_err("Unable to allocate domain handle\n"); | |
1354 | iounmap(cpu_base); | |
1355 | iounmap(dist_base); | |
1356 | return -ENOMEM; | |
1357 | } | |
1358 | ||
1359 | __gic_init_bases(0, -1, dist_base, cpu_base, 0, domain_handle); | |
d8f4f161 | 1360 | |
891ae769 | 1361 | acpi_set_irq_model(ACPI_IRQ_MODEL_GIC, domain_handle); |
d60fc389 TN |
1362 | return 0; |
1363 | } | |
f26527b1 MZ |
1364 | IRQCHIP_ACPI_DECLARE(gic_v2, ACPI_MADT_TYPE_GENERIC_DISTRIBUTOR, |
1365 | gic_validate_dist, ACPI_MADT_GIC_VERSION_V2, | |
1366 | gic_v2_acpi_init); | |
1367 | IRQCHIP_ACPI_DECLARE(gic_v2_maybe, ACPI_MADT_TYPE_GENERIC_DISTRIBUTOR, | |
1368 | gic_validate_dist, ACPI_MADT_GIC_VERSION_NONE, | |
1369 | gic_v2_acpi_init); | |
d60fc389 | 1370 | #endif |