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b2441318 | 1 | // SPDX-License-Identifier: GPL-2.0 |
b6ef9161 JH |
2 | /* |
3 | * IMG PowerDown Controller (PDC) | |
4 | * | |
5 | * Copyright 2010-2013 Imagination Technologies Ltd. | |
6 | * | |
7 | * Exposes the syswake and PDC peripheral wake interrupts to the system. | |
8 | * | |
9 | */ | |
10 | ||
11 | #include <linux/bitops.h> | |
12 | #include <linux/interrupt.h> | |
13 | #include <linux/irqdomain.h> | |
14 | #include <linux/io.h> | |
15 | #include <linux/kernel.h> | |
16 | #include <linux/of.h> | |
17 | #include <linux/platform_device.h> | |
18 | #include <linux/spinlock.h> | |
19 | ||
20 | /* PDC interrupt register numbers */ | |
21 | ||
22 | #define PDC_IRQ_STATUS 0x310 | |
23 | #define PDC_IRQ_ENABLE 0x314 | |
24 | #define PDC_IRQ_CLEAR 0x318 | |
25 | #define PDC_IRQ_ROUTE 0x31c | |
26 | #define PDC_SYS_WAKE_BASE 0x330 | |
27 | #define PDC_SYS_WAKE_STRIDE 0x8 | |
28 | #define PDC_SYS_WAKE_CONFIG_BASE 0x334 | |
29 | #define PDC_SYS_WAKE_CONFIG_STRIDE 0x8 | |
30 | ||
31 | /* PDC interrupt register field masks */ | |
32 | ||
33 | #define PDC_IRQ_SYS3 0x08 | |
34 | #define PDC_IRQ_SYS2 0x04 | |
35 | #define PDC_IRQ_SYS1 0x02 | |
36 | #define PDC_IRQ_SYS0 0x01 | |
37 | #define PDC_IRQ_ROUTE_WU_EN_SYS3 0x08000000 | |
38 | #define PDC_IRQ_ROUTE_WU_EN_SYS2 0x04000000 | |
39 | #define PDC_IRQ_ROUTE_WU_EN_SYS1 0x02000000 | |
40 | #define PDC_IRQ_ROUTE_WU_EN_SYS0 0x01000000 | |
41 | #define PDC_IRQ_ROUTE_WU_EN_WD 0x00040000 | |
42 | #define PDC_IRQ_ROUTE_WU_EN_IR 0x00020000 | |
43 | #define PDC_IRQ_ROUTE_WU_EN_RTC 0x00010000 | |
44 | #define PDC_IRQ_ROUTE_EXT_EN_SYS3 0x00000800 | |
45 | #define PDC_IRQ_ROUTE_EXT_EN_SYS2 0x00000400 | |
46 | #define PDC_IRQ_ROUTE_EXT_EN_SYS1 0x00000200 | |
47 | #define PDC_IRQ_ROUTE_EXT_EN_SYS0 0x00000100 | |
48 | #define PDC_IRQ_ROUTE_EXT_EN_WD 0x00000004 | |
49 | #define PDC_IRQ_ROUTE_EXT_EN_IR 0x00000002 | |
50 | #define PDC_IRQ_ROUTE_EXT_EN_RTC 0x00000001 | |
51 | #define PDC_SYS_WAKE_RESET 0x00000010 | |
52 | #define PDC_SYS_WAKE_INT_MODE 0x0000000e | |
53 | #define PDC_SYS_WAKE_INT_MODE_SHIFT 1 | |
54 | #define PDC_SYS_WAKE_PIN_VAL 0x00000001 | |
55 | ||
56 | /* PDC interrupt constants */ | |
57 | ||
58 | #define PDC_SYS_WAKE_INT_LOW 0x0 | |
59 | #define PDC_SYS_WAKE_INT_HIGH 0x1 | |
60 | #define PDC_SYS_WAKE_INT_DOWN 0x2 | |
61 | #define PDC_SYS_WAKE_INT_UP 0x3 | |
62 | #define PDC_SYS_WAKE_INT_CHANGE 0x6 | |
63 | #define PDC_SYS_WAKE_INT_NONE 0x4 | |
64 | ||
65 | /** | |
66 | * struct pdc_intc_priv - private pdc interrupt data. | |
67 | * @nr_perips: Number of peripheral interrupt signals. | |
68 | * @nr_syswakes: Number of syswake signals. | |
69 | * @perip_irqs: List of peripheral IRQ numbers handled. | |
70 | * @syswake_irq: Shared PDC syswake IRQ number. | |
71 | * @domain: IRQ domain for PDC peripheral and syswake IRQs. | |
72 | * @pdc_base: Base of PDC registers. | |
73 | * @irq_route: Cached version of PDC_IRQ_ROUTE register. | |
74 | * @lock: Lock to protect the PDC syswake registers and the cached | |
75 | * values of those registers in this struct. | |
76 | */ | |
77 | struct pdc_intc_priv { | |
78 | unsigned int nr_perips; | |
79 | unsigned int nr_syswakes; | |
80 | unsigned int *perip_irqs; | |
81 | unsigned int syswake_irq; | |
82 | struct irq_domain *domain; | |
83 | void __iomem *pdc_base; | |
84 | ||
85 | u32 irq_route; | |
86 | raw_spinlock_t lock; | |
87 | }; | |
88 | ||
89 | static void pdc_write(struct pdc_intc_priv *priv, unsigned int reg_offs, | |
90 | unsigned int data) | |
91 | { | |
92 | iowrite32(data, priv->pdc_base + reg_offs); | |
93 | } | |
94 | ||
95 | static unsigned int pdc_read(struct pdc_intc_priv *priv, | |
96 | unsigned int reg_offs) | |
97 | { | |
98 | return ioread32(priv->pdc_base + reg_offs); | |
99 | } | |
100 | ||
101 | /* Generic IRQ callbacks */ | |
102 | ||
103 | #define SYS0_HWIRQ 8 | |
104 | ||
105 | static unsigned int hwirq_is_syswake(irq_hw_number_t hw) | |
106 | { | |
107 | return hw >= SYS0_HWIRQ; | |
108 | } | |
109 | ||
110 | static unsigned int hwirq_to_syswake(irq_hw_number_t hw) | |
111 | { | |
112 | return hw - SYS0_HWIRQ; | |
113 | } | |
114 | ||
115 | static irq_hw_number_t syswake_to_hwirq(unsigned int syswake) | |
116 | { | |
117 | return SYS0_HWIRQ + syswake; | |
118 | } | |
119 | ||
120 | static struct pdc_intc_priv *irqd_to_priv(struct irq_data *data) | |
121 | { | |
122 | return (struct pdc_intc_priv *)data->domain->host_data; | |
123 | } | |
124 | ||
125 | /* | |
126 | * perip_irq_mask() and perip_irq_unmask() use IRQ_ROUTE which also contains | |
127 | * wake bits, therefore we cannot use the generic irqchip mask callbacks as they | |
128 | * cache the mask. | |
129 | */ | |
130 | ||
131 | static void perip_irq_mask(struct irq_data *data) | |
132 | { | |
133 | struct pdc_intc_priv *priv = irqd_to_priv(data); | |
134 | ||
135 | raw_spin_lock(&priv->lock); | |
136 | priv->irq_route &= ~data->mask; | |
137 | pdc_write(priv, PDC_IRQ_ROUTE, priv->irq_route); | |
138 | raw_spin_unlock(&priv->lock); | |
139 | } | |
140 | ||
141 | static void perip_irq_unmask(struct irq_data *data) | |
142 | { | |
143 | struct pdc_intc_priv *priv = irqd_to_priv(data); | |
144 | ||
145 | raw_spin_lock(&priv->lock); | |
146 | priv->irq_route |= data->mask; | |
147 | pdc_write(priv, PDC_IRQ_ROUTE, priv->irq_route); | |
148 | raw_spin_unlock(&priv->lock); | |
149 | } | |
150 | ||
151 | static int syswake_irq_set_type(struct irq_data *data, unsigned int flow_type) | |
152 | { | |
153 | struct pdc_intc_priv *priv = irqd_to_priv(data); | |
154 | unsigned int syswake = hwirq_to_syswake(data->hwirq); | |
155 | unsigned int irq_mode; | |
156 | unsigned int soc_sys_wake_regoff, soc_sys_wake; | |
157 | ||
158 | /* translate to syswake IRQ mode */ | |
159 | switch (flow_type) { | |
160 | case IRQ_TYPE_EDGE_BOTH: | |
161 | irq_mode = PDC_SYS_WAKE_INT_CHANGE; | |
162 | break; | |
163 | case IRQ_TYPE_EDGE_RISING: | |
164 | irq_mode = PDC_SYS_WAKE_INT_UP; | |
165 | break; | |
166 | case IRQ_TYPE_EDGE_FALLING: | |
167 | irq_mode = PDC_SYS_WAKE_INT_DOWN; | |
168 | break; | |
169 | case IRQ_TYPE_LEVEL_HIGH: | |
170 | irq_mode = PDC_SYS_WAKE_INT_HIGH; | |
171 | break; | |
172 | case IRQ_TYPE_LEVEL_LOW: | |
173 | irq_mode = PDC_SYS_WAKE_INT_LOW; | |
174 | break; | |
175 | default: | |
176 | return -EINVAL; | |
177 | } | |
178 | ||
179 | raw_spin_lock(&priv->lock); | |
180 | ||
181 | /* set the IRQ mode */ | |
182 | soc_sys_wake_regoff = PDC_SYS_WAKE_BASE + syswake*PDC_SYS_WAKE_STRIDE; | |
183 | soc_sys_wake = pdc_read(priv, soc_sys_wake_regoff); | |
184 | soc_sys_wake &= ~PDC_SYS_WAKE_INT_MODE; | |
185 | soc_sys_wake |= irq_mode << PDC_SYS_WAKE_INT_MODE_SHIFT; | |
186 | pdc_write(priv, soc_sys_wake_regoff, soc_sys_wake); | |
187 | ||
188 | /* and update the handler */ | |
189 | irq_setup_alt_chip(data, flow_type); | |
190 | ||
191 | raw_spin_unlock(&priv->lock); | |
192 | ||
193 | return 0; | |
194 | } | |
195 | ||
196 | /* applies to both peripheral and syswake interrupts */ | |
197 | static int pdc_irq_set_wake(struct irq_data *data, unsigned int on) | |
198 | { | |
199 | struct pdc_intc_priv *priv = irqd_to_priv(data); | |
200 | irq_hw_number_t hw = data->hwirq; | |
201 | unsigned int mask = (1 << 16) << hw; | |
202 | unsigned int dst_irq; | |
203 | ||
204 | raw_spin_lock(&priv->lock); | |
205 | if (on) | |
206 | priv->irq_route |= mask; | |
207 | else | |
208 | priv->irq_route &= ~mask; | |
209 | pdc_write(priv, PDC_IRQ_ROUTE, priv->irq_route); | |
210 | raw_spin_unlock(&priv->lock); | |
211 | ||
212 | /* control the destination IRQ wakeup too for standby mode */ | |
213 | if (hwirq_is_syswake(hw)) | |
214 | dst_irq = priv->syswake_irq; | |
215 | else | |
216 | dst_irq = priv->perip_irqs[hw]; | |
217 | irq_set_irq_wake(dst_irq, on); | |
218 | ||
219 | return 0; | |
220 | } | |
221 | ||
bd0b9ac4 | 222 | static void pdc_intc_perip_isr(struct irq_desc *desc) |
b6ef9161 | 223 | { |
99705f99 | 224 | unsigned int irq = irq_desc_get_irq(desc); |
b6ef9161 JH |
225 | struct pdc_intc_priv *priv; |
226 | unsigned int i, irq_no; | |
227 | ||
228 | priv = (struct pdc_intc_priv *)irq_desc_get_handler_data(desc); | |
229 | ||
230 | /* find the peripheral number */ | |
231 | for (i = 0; i < priv->nr_perips; ++i) | |
232 | if (irq == priv->perip_irqs[i]) | |
233 | goto found; | |
234 | ||
235 | /* should never get here */ | |
236 | return; | |
237 | found: | |
238 | ||
239 | /* pass on the interrupt */ | |
240 | irq_no = irq_linear_revmap(priv->domain, i); | |
241 | generic_handle_irq(irq_no); | |
242 | } | |
243 | ||
bd0b9ac4 | 244 | static void pdc_intc_syswake_isr(struct irq_desc *desc) |
b6ef9161 JH |
245 | { |
246 | struct pdc_intc_priv *priv; | |
247 | unsigned int syswake, irq_no; | |
248 | unsigned int status; | |
249 | ||
250 | priv = (struct pdc_intc_priv *)irq_desc_get_handler_data(desc); | |
251 | ||
252 | status = pdc_read(priv, PDC_IRQ_STATUS) & | |
253 | pdc_read(priv, PDC_IRQ_ENABLE); | |
254 | status &= (1 << priv->nr_syswakes) - 1; | |
255 | ||
256 | for (syswake = 0; status; status >>= 1, ++syswake) { | |
257 | /* Has this sys_wake triggered? */ | |
258 | if (!(status & 1)) | |
259 | continue; | |
260 | ||
261 | irq_no = irq_linear_revmap(priv->domain, | |
262 | syswake_to_hwirq(syswake)); | |
263 | generic_handle_irq(irq_no); | |
264 | } | |
265 | } | |
266 | ||
267 | static void pdc_intc_setup(struct pdc_intc_priv *priv) | |
268 | { | |
269 | int i; | |
270 | unsigned int soc_sys_wake_regoff; | |
271 | unsigned int soc_sys_wake; | |
272 | ||
273 | /* | |
274 | * Mask all syswake interrupts before routing, or we could receive an | |
275 | * interrupt before we're ready to handle it. | |
276 | */ | |
277 | pdc_write(priv, PDC_IRQ_ENABLE, 0); | |
278 | ||
279 | /* | |
280 | * Enable routing of all syswakes | |
281 | * Disable all wake sources | |
282 | */ | |
283 | priv->irq_route = ((PDC_IRQ_ROUTE_EXT_EN_SYS0 << priv->nr_syswakes) - | |
284 | PDC_IRQ_ROUTE_EXT_EN_SYS0); | |
285 | pdc_write(priv, PDC_IRQ_ROUTE, priv->irq_route); | |
286 | ||
287 | /* Initialise syswake IRQ */ | |
288 | for (i = 0; i < priv->nr_syswakes; ++i) { | |
289 | /* set the IRQ mode to none */ | |
290 | soc_sys_wake_regoff = PDC_SYS_WAKE_BASE + i*PDC_SYS_WAKE_STRIDE; | |
291 | soc_sys_wake = PDC_SYS_WAKE_INT_NONE | |
292 | << PDC_SYS_WAKE_INT_MODE_SHIFT; | |
293 | pdc_write(priv, soc_sys_wake_regoff, soc_sys_wake); | |
294 | } | |
295 | } | |
296 | ||
297 | static int pdc_intc_probe(struct platform_device *pdev) | |
298 | { | |
299 | struct pdc_intc_priv *priv; | |
300 | struct device_node *node = pdev->dev.of_node; | |
301 | struct resource *res_regs; | |
302 | struct irq_chip_generic *gc; | |
303 | unsigned int i; | |
304 | int irq, ret; | |
305 | u32 val; | |
306 | ||
307 | if (!node) | |
308 | return -ENOENT; | |
309 | ||
310 | /* Get registers */ | |
311 | res_regs = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
312 | if (res_regs == NULL) { | |
313 | dev_err(&pdev->dev, "cannot find registers resource\n"); | |
314 | return -ENOENT; | |
315 | } | |
316 | ||
317 | /* Allocate driver data */ | |
318 | priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL); | |
319 | if (!priv) { | |
320 | dev_err(&pdev->dev, "cannot allocate device data\n"); | |
321 | return -ENOMEM; | |
322 | } | |
323 | raw_spin_lock_init(&priv->lock); | |
324 | platform_set_drvdata(pdev, priv); | |
325 | ||
326 | /* Ioremap the registers */ | |
327 | priv->pdc_base = devm_ioremap(&pdev->dev, res_regs->start, | |
328bf1b2 | 328 | resource_size(res_regs)); |
b6ef9161 JH |
329 | if (!priv->pdc_base) |
330 | return -EIO; | |
331 | ||
332 | /* Get number of peripherals */ | |
333 | ret = of_property_read_u32(node, "num-perips", &val); | |
334 | if (ret) { | |
335 | dev_err(&pdev->dev, "No num-perips node property found\n"); | |
336 | return -EINVAL; | |
337 | } | |
338 | if (val > SYS0_HWIRQ) { | |
339 | dev_err(&pdev->dev, "num-perips (%u) out of range\n", val); | |
340 | return -EINVAL; | |
341 | } | |
342 | priv->nr_perips = val; | |
343 | ||
344 | /* Get number of syswakes */ | |
345 | ret = of_property_read_u32(node, "num-syswakes", &val); | |
346 | if (ret) { | |
347 | dev_err(&pdev->dev, "No num-syswakes node property found\n"); | |
348 | return -EINVAL; | |
349 | } | |
350 | if (val > SYS0_HWIRQ) { | |
351 | dev_err(&pdev->dev, "num-syswakes (%u) out of range\n", val); | |
352 | return -EINVAL; | |
353 | } | |
354 | priv->nr_syswakes = val; | |
355 | ||
356 | /* Get peripheral IRQ numbers */ | |
357 | priv->perip_irqs = devm_kzalloc(&pdev->dev, 4 * priv->nr_perips, | |
358 | GFP_KERNEL); | |
359 | if (!priv->perip_irqs) { | |
360 | dev_err(&pdev->dev, "cannot allocate perip IRQ list\n"); | |
361 | return -ENOMEM; | |
362 | } | |
363 | for (i = 0; i < priv->nr_perips; ++i) { | |
364 | irq = platform_get_irq(pdev, 1 + i); | |
365 | if (irq < 0) { | |
366 | dev_err(&pdev->dev, "cannot find perip IRQ #%u\n", i); | |
367 | return irq; | |
368 | } | |
369 | priv->perip_irqs[i] = irq; | |
370 | } | |
371 | /* check if too many were provided */ | |
372 | if (platform_get_irq(pdev, 1 + i) >= 0) { | |
373 | dev_err(&pdev->dev, "surplus perip IRQs detected\n"); | |
374 | return -EINVAL; | |
375 | } | |
376 | ||
377 | /* Get syswake IRQ number */ | |
378 | irq = platform_get_irq(pdev, 0); | |
379 | if (irq < 0) { | |
380 | dev_err(&pdev->dev, "cannot find syswake IRQ\n"); | |
381 | return irq; | |
382 | } | |
383 | priv->syswake_irq = irq; | |
384 | ||
385 | /* Set up an IRQ domain */ | |
386 | priv->domain = irq_domain_add_linear(node, 16, &irq_generic_chip_ops, | |
387 | priv); | |
388 | if (unlikely(!priv->domain)) { | |
389 | dev_err(&pdev->dev, "cannot add IRQ domain\n"); | |
390 | return -ENOMEM; | |
391 | } | |
392 | ||
393 | /* | |
394 | * Set up 2 generic irq chips with 2 chip types. | |
395 | * The first one for peripheral irqs (only 1 chip type used) | |
396 | * The second one for syswake irqs (edge and level chip types) | |
397 | */ | |
398 | ret = irq_alloc_domain_generic_chips(priv->domain, 8, 2, "pdc", | |
399 | handle_level_irq, 0, 0, | |
400 | IRQ_GC_INIT_NESTED_LOCK); | |
401 | if (ret) | |
402 | goto err_generic; | |
403 | ||
404 | /* peripheral interrupt chip */ | |
405 | ||
406 | gc = irq_get_domain_generic_chip(priv->domain, 0); | |
407 | gc->unused = ~(BIT(priv->nr_perips) - 1); | |
408 | gc->reg_base = priv->pdc_base; | |
409 | /* | |
410 | * IRQ_ROUTE contains wake bits, so we can't use the generic versions as | |
411 | * they cache the mask | |
412 | */ | |
413 | gc->chip_types[0].regs.mask = PDC_IRQ_ROUTE; | |
414 | gc->chip_types[0].chip.irq_mask = perip_irq_mask; | |
415 | gc->chip_types[0].chip.irq_unmask = perip_irq_unmask; | |
416 | gc->chip_types[0].chip.irq_set_wake = pdc_irq_set_wake; | |
417 | ||
418 | /* syswake interrupt chip */ | |
419 | ||
420 | gc = irq_get_domain_generic_chip(priv->domain, 8); | |
421 | gc->unused = ~(BIT(priv->nr_syswakes) - 1); | |
422 | gc->reg_base = priv->pdc_base; | |
423 | ||
424 | /* edge interrupts */ | |
425 | gc->chip_types[0].type = IRQ_TYPE_EDGE_BOTH; | |
426 | gc->chip_types[0].handler = handle_edge_irq; | |
427 | gc->chip_types[0].regs.ack = PDC_IRQ_CLEAR; | |
428 | gc->chip_types[0].regs.mask = PDC_IRQ_ENABLE; | |
429 | gc->chip_types[0].chip.irq_ack = irq_gc_ack_set_bit; | |
430 | gc->chip_types[0].chip.irq_mask = irq_gc_mask_clr_bit; | |
431 | gc->chip_types[0].chip.irq_unmask = irq_gc_mask_set_bit; | |
432 | gc->chip_types[0].chip.irq_set_type = syswake_irq_set_type; | |
433 | gc->chip_types[0].chip.irq_set_wake = pdc_irq_set_wake; | |
434 | /* for standby we pass on to the shared syswake IRQ */ | |
435 | gc->chip_types[0].chip.flags = IRQCHIP_MASK_ON_SUSPEND; | |
436 | ||
437 | /* level interrupts */ | |
438 | gc->chip_types[1].type = IRQ_TYPE_LEVEL_MASK; | |
439 | gc->chip_types[1].handler = handle_level_irq; | |
440 | gc->chip_types[1].regs.ack = PDC_IRQ_CLEAR; | |
441 | gc->chip_types[1].regs.mask = PDC_IRQ_ENABLE; | |
442 | gc->chip_types[1].chip.irq_ack = irq_gc_ack_set_bit; | |
443 | gc->chip_types[1].chip.irq_mask = irq_gc_mask_clr_bit; | |
444 | gc->chip_types[1].chip.irq_unmask = irq_gc_mask_set_bit; | |
445 | gc->chip_types[1].chip.irq_set_type = syswake_irq_set_type; | |
446 | gc->chip_types[1].chip.irq_set_wake = pdc_irq_set_wake; | |
447 | /* for standby we pass on to the shared syswake IRQ */ | |
448 | gc->chip_types[1].chip.flags = IRQCHIP_MASK_ON_SUSPEND; | |
449 | ||
450 | /* Set up the hardware to enable interrupt routing */ | |
451 | pdc_intc_setup(priv); | |
452 | ||
453 | /* Setup chained handlers for the peripheral IRQs */ | |
454 | for (i = 0; i < priv->nr_perips; ++i) { | |
455 | irq = priv->perip_irqs[i]; | |
bc4d2c07 TG |
456 | irq_set_chained_handler_and_data(irq, pdc_intc_perip_isr, |
457 | priv); | |
b6ef9161 JH |
458 | } |
459 | ||
460 | /* Setup chained handler for the syswake IRQ */ | |
bc4d2c07 TG |
461 | irq_set_chained_handler_and_data(priv->syswake_irq, |
462 | pdc_intc_syswake_isr, priv); | |
b6ef9161 JH |
463 | |
464 | dev_info(&pdev->dev, | |
465 | "PDC IRQ controller initialised (%u perip IRQs, %u syswake IRQs)\n", | |
466 | priv->nr_perips, | |
467 | priv->nr_syswakes); | |
468 | ||
469 | return 0; | |
470 | err_generic: | |
471 | irq_domain_remove(priv->domain); | |
472 | return ret; | |
473 | } | |
474 | ||
475 | static int pdc_intc_remove(struct platform_device *pdev) | |
476 | { | |
477 | struct pdc_intc_priv *priv = platform_get_drvdata(pdev); | |
478 | ||
479 | irq_domain_remove(priv->domain); | |
480 | return 0; | |
481 | } | |
482 | ||
483 | static const struct of_device_id pdc_intc_match[] = { | |
484 | { .compatible = "img,pdc-intc" }, | |
485 | {} | |
486 | }; | |
487 | ||
488 | static struct platform_driver pdc_intc_driver = { | |
489 | .driver = { | |
490 | .name = "pdc-intc", | |
491 | .of_match_table = pdc_intc_match, | |
492 | }, | |
493 | .probe = pdc_intc_probe, | |
494 | .remove = pdc_intc_remove, | |
495 | }; | |
496 | ||
497 | static int __init pdc_intc_init(void) | |
498 | { | |
499 | return platform_driver_register(&pdc_intc_driver); | |
500 | } | |
501 | core_initcall(pdc_intc_init); |