[mirror_ubuntu-jammy-kernel.git] / drivers / irqchip / irq-loongson-liointc.c

// SPDX-License-Identifier: GPL-2.0
/*
 *  Copyright (C) 2020, Jiaxun Yang <jiaxun.yang@flygoat.com>
 *  Loongson Local IO Interrupt Controller support
 */

#include <linux/errno.h>
#include <linux/init.h>
#include <linux/types.h>
#include <linux/interrupt.h>
#include <linux/ioport.h>
#include <linux/irqchip.h>
#include <linux/of_address.h>
#include <linux/of_irq.h>
#include <linux/io.h>
#include <linux/smp.h>
#include <linux/irqchip/chained_irq.h>

#include <boot_param.h>

#define LIOINTC_CHIP_IRQ	32
#define LIOINTC_NUM_PARENT 4

#define LIOINTC_INTC_CHIP_START	0x20

#define LIOINTC_REG_INTC_STATUS	(LIOINTC_INTC_CHIP_START + 0x20)
#define LIOINTC_REG_INTC_EN_STATUS	(LIOINTC_INTC_CHIP_START + 0x04)
#define LIOINTC_REG_INTC_ENABLE	(LIOINTC_INTC_CHIP_START + 0x08)
#define LIOINTC_REG_INTC_DISABLE	(LIOINTC_INTC_CHIP_START + 0x0c)
#define LIOINTC_REG_INTC_POL	(LIOINTC_INTC_CHIP_START + 0x10)
#define LIOINTC_REG_INTC_EDGE	(LIOINTC_INTC_CHIP_START + 0x14)

#define LIOINTC_SHIFT_INTx	4

#define LIOINTC_ERRATA_IRQ	10

struct liointc_handler_data {
	struct liointc_priv	*priv;
	u32			parent_int_map;
};

struct liointc_priv {
	struct irq_chip_generic		*gc;
	struct liointc_handler_data	handler[LIOINTC_NUM_PARENT];
	u8				map_cache[LIOINTC_CHIP_IRQ];
	bool				has_lpc_irq_errata;
};

static void liointc_chained_handle_irq(struct irq_desc *desc)
{
	struct liointc_handler_data *handler = irq_desc_get_handler_data(desc);
	struct irq_chip *chip = irq_desc_get_chip(desc);
	struct irq_chip_generic *gc = handler->priv->gc;
	u32 pending;

	chained_irq_enter(chip, desc);

	pending = readl(gc->reg_base + LIOINTC_REG_INTC_STATUS);

	if (!pending) {
		/* Always blame LPC IRQ if we have that bug */
		if (handler->priv->has_lpc_irq_errata &&
			(handler->parent_int_map & ~gc->mask_cache &
			BIT(LIOINTC_ERRATA_IRQ)))
			pending = BIT(LIOINTC_ERRATA_IRQ);
		else
			spurious_interrupt();
	}

	while (pending) {
		int bit = __ffs(pending);

		generic_handle_irq(irq_find_mapping(gc->domain, bit));
		pending &= ~BIT(bit);
	}

	chained_irq_exit(chip, desc);
}

static void liointc_set_bit(struct irq_chip_generic *gc,
				unsigned int offset,
				u32 mask, bool set)
{
	if (set)
		writel(readl(gc->reg_base + offset) | mask,
				gc->reg_base + offset);
	else
		writel(readl(gc->reg_base + offset) & ~mask,
				gc->reg_base + offset);
}

static int liointc_set_type(struct irq_data *data, unsigned int type)
{
	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(data);
	u32 mask = data->mask;
	unsigned long flags;

	irq_gc_lock_irqsave(gc, flags);
	switch (type) {
	case IRQ_TYPE_LEVEL_HIGH:
		liointc_set_bit(gc, LIOINTC_REG_INTC_EDGE, mask, false);
		liointc_set_bit(gc, LIOINTC_REG_INTC_POL, mask, true);
		break;
	case IRQ_TYPE_LEVEL_LOW:
		liointc_set_bit(gc, LIOINTC_REG_INTC_EDGE, mask, false);
		liointc_set_bit(gc, LIOINTC_REG_INTC_POL, mask, false);
		break;
	case IRQ_TYPE_EDGE_RISING:
		liointc_set_bit(gc, LIOINTC_REG_INTC_EDGE, mask, true);
		liointc_set_bit(gc, LIOINTC_REG_INTC_POL, mask, true);
		break;
	case IRQ_TYPE_EDGE_FALLING:
		liointc_set_bit(gc, LIOINTC_REG_INTC_EDGE, mask, true);
		liointc_set_bit(gc, LIOINTC_REG_INTC_POL, mask, false);
		break;
	default:
		return -EINVAL;
	}
	irq_gc_unlock_irqrestore(gc, flags);

	irqd_set_trigger_type(data, type);
	return 0;
}

static void liointc_resume(struct irq_chip_generic *gc)
{
	struct liointc_priv *priv = gc->private;
	unsigned long flags;
	int i;

	irq_gc_lock_irqsave(gc, flags);
	/* Disable all at first */
	writel(0xffffffff, gc->reg_base + LIOINTC_REG_INTC_DISABLE);
	/* Revert map cache */
	for (i = 0; i < LIOINTC_CHIP_IRQ; i++)
		writeb(priv->map_cache[i], gc->reg_base + i);
	/* Revert mask cache */
	writel(~gc->mask_cache, gc->reg_base + LIOINTC_REG_INTC_ENABLE);
	irq_gc_unlock_irqrestore(gc, flags);
}

static const char * const parent_names[] = {"int0", "int1", "int2", "int3"};

int __init liointc_of_init(struct device_node *node,
				struct device_node *parent)
{
	struct irq_chip_generic *gc;
	struct irq_domain *domain;
	struct irq_chip_type *ct;
	struct liointc_priv *priv;
	void __iomem *base;
	u32 of_parent_int_map[LIOINTC_NUM_PARENT];
	int parent_irq[LIOINTC_NUM_PARENT];
	bool have_parent = FALSE;
	int sz, i, err = 0;

	priv = kzalloc(sizeof(*priv), GFP_KERNEL);
	if (!priv)
		return -ENOMEM;

	base = of_iomap(node, 0);
	if (!base) {
		err = -ENODEV;
		goto out_free_priv;
	}

	for (i = 0; i < LIOINTC_NUM_PARENT; i++) {
		parent_irq[i] = of_irq_get_byname(node, parent_names[i]);
		if (parent_irq[i] > 0)
			have_parent = TRUE;
	}
	if (!have_parent) {
		err = -ENODEV;
		goto out_iounmap;
	}

	sz = of_property_read_variable_u32_array(node,
						"loongson,parent_int_map",
						&of_parent_int_map[0],
						LIOINTC_NUM_PARENT,
						LIOINTC_NUM_PARENT);
	if (sz < 4) {
		pr_err("loongson-liointc: No parent_int_map\n");
		err = -ENODEV;
		goto out_iounmap;
	}

	for (i = 0; i < LIOINTC_NUM_PARENT; i++)
		priv->handler[i].parent_int_map = of_parent_int_map[i];

	/* Setup IRQ domain */
	domain = irq_domain_add_linear(node, 32,
					&irq_generic_chip_ops, priv);
	if (!domain) {
		pr_err("loongson-liointc: cannot add IRQ domain\n");
		err = -EINVAL;
		goto out_iounmap;
	}

	err = irq_alloc_domain_generic_chips(domain, 32, 1,
					node->full_name, handle_level_irq,
					IRQ_NOPROBE, 0, 0);
	if (err) {
		pr_err("loongson-liointc: unable to register IRQ domain\n");
		goto out_free_domain;
	}


	/* Disable all IRQs */
	writel(0xffffffff, base + LIOINTC_REG_INTC_DISABLE);
	/* Set to level triggered */
	writel(0x0, base + LIOINTC_REG_INTC_EDGE);

	/* Generate parent INT part of map cache */
	for (i = 0; i < LIOINTC_NUM_PARENT; i++) {
		u32 pending = priv->handler[i].parent_int_map;

		while (pending) {
			int bit = __ffs(pending);

			priv->map_cache[bit] = BIT(i) << LIOINTC_SHIFT_INTx;
			pending &= ~BIT(bit);
		}
	}

	for (i = 0; i < LIOINTC_CHIP_IRQ; i++) {
		/* Generate core part of map cache */
		priv->map_cache[i] |= BIT(loongson_sysconf.boot_cpu_id);
		writeb(priv->map_cache[i], base + i);
	}

	gc = irq_get_domain_generic_chip(domain, 0);
	gc->private = priv;
	gc->reg_base = base;
	gc->domain = domain;
	gc->resume = liointc_resume;

	ct = gc->chip_types;
	ct->regs.enable = LIOINTC_REG_INTC_ENABLE;
	ct->regs.disable = LIOINTC_REG_INTC_DISABLE;
	ct->chip.irq_unmask = irq_gc_unmask_enable_reg;
	ct->chip.irq_mask = irq_gc_mask_disable_reg;
	ct->chip.irq_mask_ack = irq_gc_mask_disable_reg;
	ct->chip.irq_set_type = liointc_set_type;

	gc->mask_cache = 0xffffffff;
	priv->gc = gc;

	for (i = 0; i < LIOINTC_NUM_PARENT; i++) {
		if (parent_irq[i] <= 0)
			continue;

		priv->handler[i].priv = priv;
		irq_set_chained_handler_and_data(parent_irq[i],
				liointc_chained_handle_irq, &priv->handler[i]);
	}

	return 0;

out_free_domain:
	irq_domain_remove(domain);
out_iounmap:
	iounmap(base);
out_free_priv:
	kfree(priv);

	return err;
}

IRQCHIP_DECLARE(loongson_liointc_1_0, "loongson,liointc-1.0", liointc_of_init);
IRQCHIP_DECLARE(loongson_liointc_1_0a, "loongson,liointc-1.0a", liointc_of_init);
Commit	Line	Data
dbb15226 JY	1	// SPDX-License-Identifier: GPL-2.0
	2	/*
	3	* Copyright (C) 2020, Jiaxun Yang <jiaxun.yang@flygoat.com>
	4	* Loongson Local IO Interrupt Controller support
	5	*/
	6
	7	#include <linux/errno.h>
	8	#include <linux/init.h>
	9	#include <linux/types.h>
	10	#include <linux/interrupt.h>
	11	#include <linux/ioport.h>
	12	#include <linux/irqchip.h>
	13	#include <linux/of_address.h>
	14	#include <linux/of_irq.h>
	15	#include <linux/io.h>
	16	#include <linux/smp.h>
	17	#include <linux/irqchip/chained_irq.h>
	18
	19	#include <boot_param.h>
	20
	21	#define LIOINTC_CHIP_IRQ 32
	22	#define LIOINTC_NUM_PARENT 4
	23
	24	#define LIOINTC_INTC_CHIP_START 0x20
	25
	26	#define LIOINTC_REG_INTC_STATUS (LIOINTC_INTC_CHIP_START + 0x20)
	27	#define LIOINTC_REG_INTC_EN_STATUS (LIOINTC_INTC_CHIP_START + 0x04)
	28	#define LIOINTC_REG_INTC_ENABLE (LIOINTC_INTC_CHIP_START + 0x08)
	29	#define LIOINTC_REG_INTC_DISABLE (LIOINTC_INTC_CHIP_START + 0x0c)
	30	#define LIOINTC_REG_INTC_POL (LIOINTC_INTC_CHIP_START + 0x10)
	31	#define LIOINTC_REG_INTC_EDGE (LIOINTC_INTC_CHIP_START + 0x14)
	32
	33	#define LIOINTC_SHIFT_INTx 4
	34
be09ef09 JY	35	#define LIOINTC_ERRATA_IRQ 10
be09ef09 JY	36
dbb15226 JY	37	struct liointc_handler_data {
	38	struct liointc_priv *priv;
	39	u32 parent_int_map;
	40	};
	41
	42	struct liointc_priv {
	43	struct irq_chip_generic *gc;
	44	struct liointc_handler_data handler[LIOINTC_NUM_PARENT];
	45	u8 map_cache[LIOINTC_CHIP_IRQ];
be09ef09	46	bool has_lpc_irq_errata;
dbb15226 JY	47	};
	48
	49	static void liointc_chained_handle_irq(struct irq_desc *desc)
	50	{
	51	struct liointc_handler_data *handler = irq_desc_get_handler_data(desc);
	52	struct irq_chip *chip = irq_desc_get_chip(desc);
	53	struct irq_chip_generic *gc = handler->priv->gc;
	54	u32 pending;
	55
	56	chained_irq_enter(chip, desc);
	57
	58	pending = readl(gc->reg_base + LIOINTC_REG_INTC_STATUS);
	59
be09ef09 JY	60	if (!pending) {
	61	/* Always blame LPC IRQ if we have that bug */
	62	if (handler->priv->has_lpc_irq_errata &&
	63	(handler->parent_int_map & ~gc->mask_cache &
	64	BIT(LIOINTC_ERRATA_IRQ)))
	65	pending = BIT(LIOINTC_ERRATA_IRQ);
	66	else
	67	spurious_interrupt();
	68	}
dbb15226 JY	69
	70	while (pending) {
	71	int bit = __ffs(pending);
	72
	73	generic_handle_irq(irq_find_mapping(gc->domain, bit));
	74	pending &= ~BIT(bit);
	75	}
	76
	77	chained_irq_exit(chip, desc);
	78	}
	79
	80	static void liointc_set_bit(struct irq_chip_generic *gc,
	81	unsigned int offset,
	82	u32 mask, bool set)
	83	{
	84	if (set)
	85	writel(readl(gc->reg_base + offset) \| mask,
	86	gc->reg_base + offset);
	87	else
	88	writel(readl(gc->reg_base + offset) & ~mask,
	89	gc->reg_base + offset);
	90	}
	91
	92	static int liointc_set_type(struct irq_data *data, unsigned int type)
	93	{
	94	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(data);
	95	u32 mask = data->mask;
	96	unsigned long flags;
	97
	98	irq_gc_lock_irqsave(gc, flags);
	99	switch (type) {
	100	case IRQ_TYPE_LEVEL_HIGH:
	101	liointc_set_bit(gc, LIOINTC_REG_INTC_EDGE, mask, false);
	102	liointc_set_bit(gc, LIOINTC_REG_INTC_POL, mask, true);
	103	break;
	104	case IRQ_TYPE_LEVEL_LOW:
	105	liointc_set_bit(gc, LIOINTC_REG_INTC_EDGE, mask, false);
	106	liointc_set_bit(gc, LIOINTC_REG_INTC_POL, mask, false);
	107	break;
	108	case IRQ_TYPE_EDGE_RISING:
	109	liointc_set_bit(gc, LIOINTC_REG_INTC_EDGE, mask, true);
	110	liointc_set_bit(gc, LIOINTC_REG_INTC_POL, mask, true);
	111	break;
	112	case IRQ_TYPE_EDGE_FALLING:
	113	liointc_set_bit(gc, LIOINTC_REG_INTC_EDGE, mask, true);
	114	liointc_set_bit(gc, LIOINTC_REG_INTC_POL, mask, false);
	115	break;
	116	default:
	117	return -EINVAL;
	118	}
	119	irq_gc_unlock_irqrestore(gc, flags);
	120
	121	irqd_set_trigger_type(data, type);
	122	return 0;
	123	}
	124
	125	static void liointc_resume(struct irq_chip_generic *gc)
	126	{
	127	struct liointc_priv *priv = gc->private;
	128	unsigned long flags;
	129	int i;
	130
	131	irq_gc_lock_irqsave(gc, flags);
	132	/* Disable all at first */
133	writel(0xffffffff, gc->reg_base + LIOINTC_REG_INTC_DISABLE);
134	/* Revert map cache */
135	for (i = 0; i < LIOINTC_CHIP_IRQ; i++)
136	writeb(priv->map_cache[i], gc->reg_base + i);
137	/* Revert mask cache */
138	writel(~gc->mask_cache, gc->reg_base + LIOINTC_REG_INTC_ENABLE);
139	irq_gc_unlock_irqrestore(gc, flags);
140	}
141
142	static const char * const parent_names[] = {"int0", "int1", "int2", "int3"};
143
144	int __init liointc_of_init(struct device_node *node,
145	struct device_node *parent)
146	{
147	struct irq_chip_generic *gc;
148	struct irq_domain *domain;
149	struct irq_chip_type *ct;
150	struct liointc_priv *priv;
151	void __iomem *base;
152	u32 of_parent_int_map[LIOINTC_NUM_PARENT];
153	int parent_irq[LIOINTC_NUM_PARENT];
154	bool have_parent = FALSE;
155	int sz, i, err = 0;
156
157	priv = kzalloc(sizeof(*priv), GFP_KERNEL);
158	if (!priv)
159	return -ENOMEM;
160
161	base = of_iomap(node, 0);
162	if (!base) {
163	err = -ENODEV;
164	goto out_free_priv;
165	}
166
167	for (i = 0; i < LIOINTC_NUM_PARENT; i++) {
168	parent_irq[i] = of_irq_get_byname(node, parent_names[i]);
169	if (parent_irq[i] > 0)
170	have_parent = TRUE;
171	}
172	if (!have_parent) {
173	err = -ENODEV;
174	goto out_iounmap;
175	}
176
177	sz = of_property_read_variable_u32_array(node,
178	"loongson,parent_int_map",
179	&of_parent_int_map[0],
180	LIOINTC_NUM_PARENT,
181	LIOINTC_NUM_PARENT);
182	if (sz < 4) {
183	pr_err("loongson-liointc: No parent_int_map\n");
184	err = -ENODEV;
185	goto out_iounmap;
186	}
187
188	for (i = 0; i < LIOINTC_NUM_PARENT; i++)
189	priv->handler[i].parent_int_map = of_parent_int_map[i];
190
191	/* Setup IRQ domain */
192	domain = irq_domain_add_linear(node, 32,
193	&irq_generic_chip_ops, priv);
194	if (!domain) {
195	pr_err("loongson-liointc: cannot add IRQ domain\n");
196	err = -EINVAL;
197	goto out_iounmap;
198	}
199
200	err = irq_alloc_domain_generic_chips(domain, 32, 1,
201	node->full_name, handle_level_irq,
202	IRQ_NOPROBE, 0, 0);
203	if (err) {
204	pr_err("loongson-liointc: unable to register IRQ domain\n");
205	goto out_free_domain;
206	}
207
208
209	/* Disable all IRQs */
210	writel(0xffffffff, base + LIOINTC_REG_INTC_DISABLE);
211	/* Set to level triggered */
212	writel(0x0, base + LIOINTC_REG_INTC_EDGE);
213
214	/* Generate parent INT part of map cache */
215	for (i = 0; i < LIOINTC_NUM_PARENT; i++) {
216	u32 pending = priv->handler[i].parent_int_map;
217
218	while (pending) {
219	int bit = __ffs(pending);
220
221	priv->map_cache[bit] = BIT(i) << LIOINTC_SHIFT_INTx;
222	pending &= ~BIT(bit);
223	}
224	}
225
226	for (i = 0; i < LIOINTC_CHIP_IRQ; i++) {
227	/* Generate core part of map cache */
228	priv->map_cache[i] \|= BIT(loongson_sysconf.boot_cpu_id);
229	writeb(priv->map_cache[i], base + i);
230	}
231
232	gc = irq_get_domain_generic_chip(domain, 0);
233	gc->private = priv;
234	gc->reg_base = base;
235	gc->domain = domain;
236	gc->resume = liointc_resume;
237
238	ct = gc->chip_types;
239	ct->regs.enable = LIOINTC_REG_INTC_ENABLE;
240	ct->regs.disable = LIOINTC_REG_INTC_DISABLE;
241	ct->chip.irq_unmask = irq_gc_unmask_enable_reg;
242	ct->chip.irq_mask = irq_gc_mask_disable_reg;
243	ct->chip.irq_mask_ack = irq_gc_mask_disable_reg;
244	ct->chip.irq_set_type = liointc_set_type;
245
246	gc->mask_cache = 0xffffffff;
247	priv->gc = gc;
248
249	for (i = 0; i < LIOINTC_NUM_PARENT; i++) {
250	if (parent_irq[i] <= 0)
251	continue;
252
253	priv->handler[i].priv = priv;
254	irq_set_chained_handler_and_data(parent_irq[i],
255	liointc_chained_handle_irq, &priv->handler[i]);
256	}
257
258	return 0;
259
260	out_free_domain:
261	irq_domain_remove(domain);
262	out_iounmap:
263	iounmap(base);
264	out_free_priv:
265	kfree(priv);
266
267	return err;
268	}
269
270	IRQCHIP_DECLARE(loongson_liointc_1_0, "loongson,liointc-1.0", liointc_of_init);
271	IRQCHIP_DECLARE(loongson_liointc_1_0a, "loongson,liointc-1.0a", liointc_of_init);