[mirror_ubuntu-hirsute-kernel.git] / drivers / irqchip / irq-loongson-liointc.c

// SPDX-License-Identifier: GPL-2.0
/*
 *  Copyright (C) 2020, Jiaxun Yang <jiaxun.yang@flygoat.com>
 *  Loongson Local IO Interrupt Controller support
 */

#include <linux/errno.h>
#include <linux/init.h>
#include <linux/types.h>
#include <linux/interrupt.h>
#include <linux/ioport.h>
#include <linux/irqchip.h>
#include <linux/of_address.h>
#include <linux/of_irq.h>
#include <linux/io.h>
#include <linux/smp.h>
#include <linux/irqchip/chained_irq.h>

#include <boot_param.h>

#define LIOINTC_CHIP_IRQ	32
#define LIOINTC_NUM_PARENT 4

#define LIOINTC_INTC_CHIP_START	0x20

#define LIOINTC_REG_INTC_STATUS	(LIOINTC_INTC_CHIP_START + 0x20)
#define LIOINTC_REG_INTC_EN_STATUS	(LIOINTC_INTC_CHIP_START + 0x04)
#define LIOINTC_REG_INTC_ENABLE	(LIOINTC_INTC_CHIP_START + 0x08)
#define LIOINTC_REG_INTC_DISABLE	(LIOINTC_INTC_CHIP_START + 0x0c)
#define LIOINTC_REG_INTC_POL	(LIOINTC_INTC_CHIP_START + 0x10)
#define LIOINTC_REG_INTC_EDGE	(LIOINTC_INTC_CHIP_START + 0x14)

#define LIOINTC_SHIFT_INTx	4

struct liointc_handler_data {
	struct liointc_priv	*priv;
	u32			parent_int_map;
};

struct liointc_priv {
	struct irq_chip_generic		*gc;
	struct liointc_handler_data	handler[LIOINTC_NUM_PARENT];
	u8				map_cache[LIOINTC_CHIP_IRQ];
};

static void liointc_chained_handle_irq(struct irq_desc *desc)
{
	struct liointc_handler_data *handler = irq_desc_get_handler_data(desc);
	struct irq_chip *chip = irq_desc_get_chip(desc);
	struct irq_chip_generic *gc = handler->priv->gc;
	u32 pending;

	chained_irq_enter(chip, desc);

	pending = readl(gc->reg_base + LIOINTC_REG_INTC_STATUS);

	if (!pending)
		spurious_interrupt();

	while (pending) {
		int bit = __ffs(pending);

		generic_handle_irq(irq_find_mapping(gc->domain, bit));
		pending &= ~BIT(bit);
	}

	chained_irq_exit(chip, desc);
}

static void liointc_set_bit(struct irq_chip_generic *gc,
				unsigned int offset,
				u32 mask, bool set)
{
	if (set)
		writel(readl(gc->reg_base + offset) | mask,
				gc->reg_base + offset);
	else
		writel(readl(gc->reg_base + offset) & ~mask,
				gc->reg_base + offset);
}

static int liointc_set_type(struct irq_data *data, unsigned int type)
{
	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(data);
	u32 mask = data->mask;
	unsigned long flags;

	irq_gc_lock_irqsave(gc, flags);
	switch (type) {
	case IRQ_TYPE_LEVEL_HIGH:
		liointc_set_bit(gc, LIOINTC_REG_INTC_EDGE, mask, false);
		liointc_set_bit(gc, LIOINTC_REG_INTC_POL, mask, true);
		break;
	case IRQ_TYPE_LEVEL_LOW:
		liointc_set_bit(gc, LIOINTC_REG_INTC_EDGE, mask, false);
		liointc_set_bit(gc, LIOINTC_REG_INTC_POL, mask, false);
		break;
	case IRQ_TYPE_EDGE_RISING:
		liointc_set_bit(gc, LIOINTC_REG_INTC_EDGE, mask, true);
		liointc_set_bit(gc, LIOINTC_REG_INTC_POL, mask, true);
		break;
	case IRQ_TYPE_EDGE_FALLING:
		liointc_set_bit(gc, LIOINTC_REG_INTC_EDGE, mask, true);
		liointc_set_bit(gc, LIOINTC_REG_INTC_POL, mask, false);
		break;
	default:
		return -EINVAL;
	}
	irq_gc_unlock_irqrestore(gc, flags);

	irqd_set_trigger_type(data, type);
	return 0;
}

static void liointc_resume(struct irq_chip_generic *gc)
{
	struct liointc_priv *priv = gc->private;
	unsigned long flags;
	int i;

	irq_gc_lock_irqsave(gc, flags);
	/* Disable all at first */
	writel(0xffffffff, gc->reg_base + LIOINTC_REG_INTC_DISABLE);
	/* Revert map cache */
	for (i = 0; i < LIOINTC_CHIP_IRQ; i++)
		writeb(priv->map_cache[i], gc->reg_base + i);
	/* Revert mask cache */
	writel(~gc->mask_cache, gc->reg_base + LIOINTC_REG_INTC_ENABLE);
	irq_gc_unlock_irqrestore(gc, flags);
}

static const char * const parent_names[] = {"int0", "int1", "int2", "int3"};

int __init liointc_of_init(struct device_node *node,
				struct device_node *parent)
{
	struct irq_chip_generic *gc;
	struct irq_domain *domain;
	struct irq_chip_type *ct;
	struct liointc_priv *priv;
	void __iomem *base;
	u32 of_parent_int_map[LIOINTC_NUM_PARENT];
	int parent_irq[LIOINTC_NUM_PARENT];
	bool have_parent = FALSE;
	int sz, i, err = 0;

	priv = kzalloc(sizeof(*priv), GFP_KERNEL);
	if (!priv)
		return -ENOMEM;

	base = of_iomap(node, 0);
	if (!base) {
		err = -ENODEV;
		goto out_free_priv;
	}

	for (i = 0; i < LIOINTC_NUM_PARENT; i++) {
		parent_irq[i] = of_irq_get_byname(node, parent_names[i]);
		if (parent_irq[i] > 0)
			have_parent = TRUE;
	}
	if (!have_parent) {
		err = -ENODEV;
		goto out_iounmap;
	}

	sz = of_property_read_variable_u32_array(node,
						"loongson,parent_int_map",
						&of_parent_int_map[0],
						LIOINTC_NUM_PARENT,
						LIOINTC_NUM_PARENT);
	if (sz < 4) {
		pr_err("loongson-liointc: No parent_int_map\n");
		err = -ENODEV;
		goto out_iounmap;
	}

	for (i = 0; i < LIOINTC_NUM_PARENT; i++)
		priv->handler[i].parent_int_map = of_parent_int_map[i];

	/* Setup IRQ domain */
	domain = irq_domain_add_linear(node, 32,
					&irq_generic_chip_ops, priv);
	if (!domain) {
		pr_err("loongson-liointc: cannot add IRQ domain\n");
		err = -EINVAL;
		goto out_iounmap;
	}

	err = irq_alloc_domain_generic_chips(domain, 32, 1,
					node->full_name, handle_level_irq,
					IRQ_NOPROBE, 0, 0);
	if (err) {
		pr_err("loongson-liointc: unable to register IRQ domain\n");
		goto out_free_domain;
	}


	/* Disable all IRQs */
	writel(0xffffffff, base + LIOINTC_REG_INTC_DISABLE);
	/* Set to level triggered */
	writel(0x0, base + LIOINTC_REG_INTC_EDGE);

	/* Generate parent INT part of map cache */
	for (i = 0; i < LIOINTC_NUM_PARENT; i++) {
		u32 pending = priv->handler[i].parent_int_map;

		while (pending) {
			int bit = __ffs(pending);

			priv->map_cache[bit] = BIT(i) << LIOINTC_SHIFT_INTx;
			pending &= ~BIT(bit);
		}
	}

	for (i = 0; i < LIOINTC_CHIP_IRQ; i++) {
		/* Generate core part of map cache */
		priv->map_cache[i] |= BIT(loongson_sysconf.boot_cpu_id);
		writeb(priv->map_cache[i], base + i);
	}

	gc = irq_get_domain_generic_chip(domain, 0);
	gc->private = priv;
	gc->reg_base = base;
	gc->domain = domain;
	gc->resume = liointc_resume;

	ct = gc->chip_types;
	ct->regs.enable = LIOINTC_REG_INTC_ENABLE;
	ct->regs.disable = LIOINTC_REG_INTC_DISABLE;
	ct->chip.irq_unmask = irq_gc_unmask_enable_reg;
	ct->chip.irq_mask = irq_gc_mask_disable_reg;
	ct->chip.irq_mask_ack = irq_gc_mask_disable_reg;
	ct->chip.irq_set_type = liointc_set_type;

	gc->mask_cache = 0xffffffff;
	priv->gc = gc;

	for (i = 0; i < LIOINTC_NUM_PARENT; i++) {
		if (parent_irq[i] <= 0)
			continue;

		priv->handler[i].priv = priv;
		irq_set_chained_handler_and_data(parent_irq[i],
				liointc_chained_handle_irq, &priv->handler[i]);
	}

	return 0;

out_free_domain:
	irq_domain_remove(domain);
out_iounmap:
	iounmap(base);
out_free_priv:
	kfree(priv);

	return err;
}

IRQCHIP_DECLARE(loongson_liointc_1_0, "loongson,liointc-1.0", liointc_of_init);
IRQCHIP_DECLARE(loongson_liointc_1_0a, "loongson,liointc-1.0a", liointc_of_init);
Commit	Line	Data
dbb15226 JY	1	// SPDX-License-Identifier: GPL-2.0
	2	/*
	3	* Copyright (C) 2020, Jiaxun Yang <jiaxun.yang@flygoat.com>
	4	* Loongson Local IO Interrupt Controller support
	5	*/
	6
	7	#include <linux/errno.h>
	8	#include <linux/init.h>
	9	#include <linux/types.h>
	10	#include <linux/interrupt.h>
	11	#include <linux/ioport.h>
	12	#include <linux/irqchip.h>
	13	#include <linux/of_address.h>
	14	#include <linux/of_irq.h>
	15	#include <linux/io.h>
	16	#include <linux/smp.h>
	17	#include <linux/irqchip/chained_irq.h>
	18
	19	#include <boot_param.h>
	20
	21	#define LIOINTC_CHIP_IRQ 32
	22	#define LIOINTC_NUM_PARENT 4
	23
	24	#define LIOINTC_INTC_CHIP_START 0x20
	25
	26	#define LIOINTC_REG_INTC_STATUS (LIOINTC_INTC_CHIP_START + 0x20)
	27	#define LIOINTC_REG_INTC_EN_STATUS (LIOINTC_INTC_CHIP_START + 0x04)
	28	#define LIOINTC_REG_INTC_ENABLE (LIOINTC_INTC_CHIP_START + 0x08)
	29	#define LIOINTC_REG_INTC_DISABLE (LIOINTC_INTC_CHIP_START + 0x0c)
	30	#define LIOINTC_REG_INTC_POL (LIOINTC_INTC_CHIP_START + 0x10)
	31	#define LIOINTC_REG_INTC_EDGE (LIOINTC_INTC_CHIP_START + 0x14)
	32
	33	#define LIOINTC_SHIFT_INTx 4
	34
	35	struct liointc_handler_data {
	36	struct liointc_priv *priv;
	37	u32 parent_int_map;
	38	};
	39
	40	struct liointc_priv {
	41	struct irq_chip_generic *gc;
	42	struct liointc_handler_data handler[LIOINTC_NUM_PARENT];
	43	u8 map_cache[LIOINTC_CHIP_IRQ];
	44	};
	45
	46	static void liointc_chained_handle_irq(struct irq_desc *desc)
	47	{
	48	struct liointc_handler_data *handler = irq_desc_get_handler_data(desc);
	49	struct irq_chip *chip = irq_desc_get_chip(desc);
	50	struct irq_chip_generic *gc = handler->priv->gc;
	51	u32 pending;
	52
	53	chained_irq_enter(chip, desc);
	54
	55	pending = readl(gc->reg_base + LIOINTC_REG_INTC_STATUS);
	56
	57	if (!pending)
	58	spurious_interrupt();
	59
	60	while (pending) {
	61	int bit = __ffs(pending);
	62
	63	generic_handle_irq(irq_find_mapping(gc->domain, bit));
	64	pending &= ~BIT(bit);
65	}
66
67	chained_irq_exit(chip, desc);
68	}
69
70	static void liointc_set_bit(struct irq_chip_generic *gc,
71	unsigned int offset,
72	u32 mask, bool set)
73	{
74	if (set)
75	writel(readl(gc->reg_base + offset) \| mask,
76	gc->reg_base + offset);
77	else
78	writel(readl(gc->reg_base + offset) & ~mask,
79	gc->reg_base + offset);
80	}
81
82	static int liointc_set_type(struct irq_data *data, unsigned int type)
83	{
84	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(data);
85	u32 mask = data->mask;
86	unsigned long flags;
87
88	irq_gc_lock_irqsave(gc, flags);
89	switch (type) {
90	case IRQ_TYPE_LEVEL_HIGH:
91	liointc_set_bit(gc, LIOINTC_REG_INTC_EDGE, mask, false);
92	liointc_set_bit(gc, LIOINTC_REG_INTC_POL, mask, true);
93	break;
94	case IRQ_TYPE_LEVEL_LOW:
95	liointc_set_bit(gc, LIOINTC_REG_INTC_EDGE, mask, false);
96	liointc_set_bit(gc, LIOINTC_REG_INTC_POL, mask, false);
97	break;
98	case IRQ_TYPE_EDGE_RISING:
99	liointc_set_bit(gc, LIOINTC_REG_INTC_EDGE, mask, true);
100	liointc_set_bit(gc, LIOINTC_REG_INTC_POL, mask, true);
101	break;
102	case IRQ_TYPE_EDGE_FALLING:
103	liointc_set_bit(gc, LIOINTC_REG_INTC_EDGE, mask, true);
104	liointc_set_bit(gc, LIOINTC_REG_INTC_POL, mask, false);
105	break;
106	default:
107	return -EINVAL;
108	}
109	irq_gc_unlock_irqrestore(gc, flags);
110
111	irqd_set_trigger_type(data, type);
112	return 0;
113	}
114
115	static void liointc_resume(struct irq_chip_generic *gc)
116	{
117	struct liointc_priv *priv = gc->private;
118	unsigned long flags;
119	int i;
120
121	irq_gc_lock_irqsave(gc, flags);
122	/* Disable all at first */
123	writel(0xffffffff, gc->reg_base + LIOINTC_REG_INTC_DISABLE);
124	/* Revert map cache */
125	for (i = 0; i < LIOINTC_CHIP_IRQ; i++)
126	writeb(priv->map_cache[i], gc->reg_base + i);
127	/* Revert mask cache */
128	writel(~gc->mask_cache, gc->reg_base + LIOINTC_REG_INTC_ENABLE);
129	irq_gc_unlock_irqrestore(gc, flags);
130	}
131
132	static const char * const parent_names[] = {"int0", "int1", "int2", "int3"};
133
134	int __init liointc_of_init(struct device_node *node,
135	struct device_node *parent)
136	{
137	struct irq_chip_generic *gc;
138	struct irq_domain *domain;
139	struct irq_chip_type *ct;
140	struct liointc_priv *priv;
141	void __iomem *base;
142	u32 of_parent_int_map[LIOINTC_NUM_PARENT];
143	int parent_irq[LIOINTC_NUM_PARENT];
144	bool have_parent = FALSE;
145	int sz, i, err = 0;
146
147	priv = kzalloc(sizeof(*priv), GFP_KERNEL);
148	if (!priv)
149	return -ENOMEM;
150
151	base = of_iomap(node, 0);
152	if (!base) {
153	err = -ENODEV;
154	goto out_free_priv;
155	}
156
157	for (i = 0; i < LIOINTC_NUM_PARENT; i++) {
158	parent_irq[i] = of_irq_get_byname(node, parent_names[i]);
159	if (parent_irq[i] > 0)
160	have_parent = TRUE;
161	}
162	if (!have_parent) {
163	err = -ENODEV;
164	goto out_iounmap;
165	}
166
167	sz = of_property_read_variable_u32_array(node,
168	"loongson,parent_int_map",
169	&of_parent_int_map[0],
170	LIOINTC_NUM_PARENT,
171	LIOINTC_NUM_PARENT);
172	if (sz < 4) {
173	pr_err("loongson-liointc: No parent_int_map\n");
174	err = -ENODEV;
175	goto out_iounmap;
176	}
177
178	for (i = 0; i < LIOINTC_NUM_PARENT; i++)
179	priv->handler[i].parent_int_map = of_parent_int_map[i];
180
181	/* Setup IRQ domain */
182	domain = irq_domain_add_linear(node, 32,
183	&irq_generic_chip_ops, priv);
184	if (!domain) {
185	pr_err("loongson-liointc: cannot add IRQ domain\n");
186	err = -EINVAL;
187	goto out_iounmap;
188	}
189
190	err = irq_alloc_domain_generic_chips(domain, 32, 1,
191	node->full_name, handle_level_irq,
192	IRQ_NOPROBE, 0, 0);
193	if (err) {
194	pr_err("loongson-liointc: unable to register IRQ domain\n");
195	goto out_free_domain;
196	}
197
198
199	/* Disable all IRQs */
200	writel(0xffffffff, base + LIOINTC_REG_INTC_DISABLE);
201	/* Set to level triggered */
202	writel(0x0, base + LIOINTC_REG_INTC_EDGE);
203
204	/* Generate parent INT part of map cache */
205	for (i = 0; i < LIOINTC_NUM_PARENT; i++) {
206	u32 pending = priv->handler[i].parent_int_map;
207
208	while (pending) {
209	int bit = __ffs(pending);
210
211	priv->map_cache[bit] = BIT(i) << LIOINTC_SHIFT_INTx;
212	pending &= ~BIT(bit);
213	}
214	}
215
216	for (i = 0; i < LIOINTC_CHIP_IRQ; i++) {
217	/* Generate core part of map cache */
218	priv->map_cache[i] \|= BIT(loongson_sysconf.boot_cpu_id);
219	writeb(priv->map_cache[i], base + i);
220	}
221
222	gc = irq_get_domain_generic_chip(domain, 0);
223	gc->private = priv;
224	gc->reg_base = base;
225	gc->domain = domain;
226	gc->resume = liointc_resume;
227
228	ct = gc->chip_types;
229	ct->regs.enable = LIOINTC_REG_INTC_ENABLE;
230	ct->regs.disable = LIOINTC_REG_INTC_DISABLE;
231	ct->chip.irq_unmask = irq_gc_unmask_enable_reg;
232	ct->chip.irq_mask = irq_gc_mask_disable_reg;
233	ct->chip.irq_mask_ack = irq_gc_mask_disable_reg;
234	ct->chip.irq_set_type = liointc_set_type;
235
236	gc->mask_cache = 0xffffffff;
237	priv->gc = gc;
238
239	for (i = 0; i < LIOINTC_NUM_PARENT; i++) {
240	if (parent_irq[i] <= 0)
241	continue;
242
243	priv->handler[i].priv = priv;
244	irq_set_chained_handler_and_data(parent_irq[i],
245	liointc_chained_handle_irq, &priv->handler[i]);
246	}
247
248	return 0;
249
250	out_free_domain:
251	irq_domain_remove(domain);
252	out_iounmap:
253	iounmap(base);
254	out_free_priv:
255	kfree(priv);
256
257	return err;
258	}
259
260	IRQCHIP_DECLARE(loongson_liointc_1_0, "loongson,liointc-1.0", liointc_of_init);
261	IRQCHIP_DECLARE(loongson_liointc_1_0a, "loongson,liointc-1.0a", liointc_of_init);