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caab277b | 1 | // SPDX-License-Identifier: GPL-2.0-only |
717c3dbc MJ |
2 | /* |
3 | * Copyright (C) 2015 Hisilicon Limited, All Rights Reserved. | |
4 | * Author: Jun Ma <majun258@huawei.com> | |
5 | * Author: Yun Wu <wuyun.wu@huawei.com> | |
717c3dbc MJ |
6 | */ |
7 | ||
f907c515 | 8 | #include <linux/acpi.h> |
9650c60e MJ |
9 | #include <linux/interrupt.h> |
10 | #include <linux/irqchip.h> | |
717c3dbc | 11 | #include <linux/module.h> |
9650c60e | 12 | #include <linux/msi.h> |
717c3dbc MJ |
13 | #include <linux/of_address.h> |
14 | #include <linux/of_irq.h> | |
15 | #include <linux/of_platform.h> | |
16 | #include <linux/platform_device.h> | |
17 | #include <linux/slab.h> | |
18 | ||
9650c60e MJ |
19 | /* Interrupt numbers per mbigen node supported */ |
20 | #define IRQS_PER_MBIGEN_NODE 128 | |
21 | ||
22 | /* 64 irqs (Pin0-pin63) are reserved for each mbigen chip */ | |
23 | #define RESERVED_IRQ_PER_MBIGEN_CHIP 64 | |
24 | ||
25 | /* The maximum IRQ pin number of mbigen chip(start from 0) */ | |
26 | #define MAXIMUM_IRQ_PIN_NUM 1407 | |
27 | ||
28 | /** | |
29 | * In mbigen vector register | |
30 | * bit[21:12]: event id value | |
31 | * bit[11:0]: device id | |
32 | */ | |
33 | #define IRQ_EVENT_ID_SHIFT 12 | |
34 | #define IRQ_EVENT_ID_MASK 0x3ff | |
35 | ||
36 | /* register range of each mbigen node */ | |
37 | #define MBIGEN_NODE_OFFSET 0x1000 | |
38 | ||
39 | /* offset of vector register in mbigen node */ | |
40 | #define REG_MBIGEN_VEC_OFFSET 0x200 | |
41 | ||
a6c2f87b MJ |
42 | /** |
43 | * offset of clear register in mbigen node | |
44 | * This register is used to clear the status | |
45 | * of interrupt | |
46 | */ | |
47 | #define REG_MBIGEN_CLEAR_OFFSET 0xa000 | |
48 | ||
49 | /** | |
50 | * offset of interrupt type register | |
51 | * This register is used to configure interrupt | |
52 | * trigger type | |
53 | */ | |
54 | #define REG_MBIGEN_TYPE_OFFSET 0x0 | |
55 | ||
717c3dbc MJ |
56 | /** |
57 | * struct mbigen_device - holds the information of mbigen device. | |
58 | * | |
59 | * @pdev: pointer to the platform device structure of mbigen chip. | |
60 | * @base: mapped address of this mbigen chip. | |
61 | */ | |
62 | struct mbigen_device { | |
63 | struct platform_device *pdev; | |
64 | void __iomem *base; | |
65 | }; | |
66 | ||
9650c60e MJ |
67 | static inline unsigned int get_mbigen_vec_reg(irq_hw_number_t hwirq) |
68 | { | |
69 | unsigned int nid, pin; | |
70 | ||
71 | hwirq -= RESERVED_IRQ_PER_MBIGEN_CHIP; | |
72 | nid = hwirq / IRQS_PER_MBIGEN_NODE + 1; | |
73 | pin = hwirq % IRQS_PER_MBIGEN_NODE; | |
74 | ||
75 | return pin * 4 + nid * MBIGEN_NODE_OFFSET | |
76 | + REG_MBIGEN_VEC_OFFSET; | |
77 | } | |
78 | ||
a6c2f87b MJ |
79 | static inline void get_mbigen_type_reg(irq_hw_number_t hwirq, |
80 | u32 *mask, u32 *addr) | |
81 | { | |
82 | unsigned int nid, irq_ofst, ofst; | |
83 | ||
84 | hwirq -= RESERVED_IRQ_PER_MBIGEN_CHIP; | |
85 | nid = hwirq / IRQS_PER_MBIGEN_NODE + 1; | |
86 | irq_ofst = hwirq % IRQS_PER_MBIGEN_NODE; | |
87 | ||
88 | *mask = 1 << (irq_ofst % 32); | |
89 | ofst = irq_ofst / 32 * 4; | |
90 | ||
91 | *addr = ofst + nid * MBIGEN_NODE_OFFSET | |
92 | + REG_MBIGEN_TYPE_OFFSET; | |
93 | } | |
94 | ||
95 | static inline void get_mbigen_clear_reg(irq_hw_number_t hwirq, | |
96 | u32 *mask, u32 *addr) | |
97 | { | |
9459a04b | 98 | unsigned int ofst = (hwirq / 32) * 4; |
a6c2f87b MJ |
99 | |
100 | *mask = 1 << (hwirq % 32); | |
101 | *addr = ofst + REG_MBIGEN_CLEAR_OFFSET; | |
102 | } | |
103 | ||
104 | static void mbigen_eoi_irq(struct irq_data *data) | |
105 | { | |
106 | void __iomem *base = data->chip_data; | |
107 | u32 mask, addr; | |
108 | ||
109 | get_mbigen_clear_reg(data->hwirq, &mask, &addr); | |
110 | ||
111 | writel_relaxed(mask, base + addr); | |
112 | ||
113 | irq_chip_eoi_parent(data); | |
114 | } | |
115 | ||
116 | static int mbigen_set_type(struct irq_data *data, unsigned int type) | |
117 | { | |
118 | void __iomem *base = data->chip_data; | |
119 | u32 mask, addr, val; | |
120 | ||
121 | if (type != IRQ_TYPE_LEVEL_HIGH && type != IRQ_TYPE_EDGE_RISING) | |
122 | return -EINVAL; | |
123 | ||
124 | get_mbigen_type_reg(data->hwirq, &mask, &addr); | |
125 | ||
126 | val = readl_relaxed(base + addr); | |
127 | ||
128 | if (type == IRQ_TYPE_LEVEL_HIGH) | |
129 | val |= mask; | |
130 | else | |
131 | val &= ~mask; | |
132 | ||
133 | writel_relaxed(val, base + addr); | |
134 | ||
135 | return 0; | |
136 | } | |
137 | ||
9650c60e MJ |
138 | static struct irq_chip mbigen_irq_chip = { |
139 | .name = "mbigen-v2", | |
a6c2f87b MJ |
140 | .irq_mask = irq_chip_mask_parent, |
141 | .irq_unmask = irq_chip_unmask_parent, | |
142 | .irq_eoi = mbigen_eoi_irq, | |
143 | .irq_set_type = mbigen_set_type, | |
144 | .irq_set_affinity = irq_chip_set_affinity_parent, | |
9650c60e MJ |
145 | }; |
146 | ||
147 | static void mbigen_write_msg(struct msi_desc *desc, struct msi_msg *msg) | |
148 | { | |
149 | struct irq_data *d = irq_get_irq_data(desc->irq); | |
150 | void __iomem *base = d->chip_data; | |
151 | u32 val; | |
152 | ||
fca269f2 JC |
153 | if (!msg->address_lo && !msg->address_hi) |
154 | return; | |
155 | ||
9650c60e MJ |
156 | base += get_mbigen_vec_reg(d->hwirq); |
157 | val = readl_relaxed(base); | |
158 | ||
159 | val &= ~(IRQ_EVENT_ID_MASK << IRQ_EVENT_ID_SHIFT); | |
160 | val |= (msg->data << IRQ_EVENT_ID_SHIFT); | |
161 | ||
162 | /* The address of doorbell is encoded in mbigen register by default | |
163 | * So,we don't need to program the doorbell address at here | |
164 | */ | |
165 | writel_relaxed(val, base); | |
166 | } | |
167 | ||
168 | static int mbigen_domain_translate(struct irq_domain *d, | |
169 | struct irq_fwspec *fwspec, | |
170 | unsigned long *hwirq, | |
171 | unsigned int *type) | |
172 | { | |
f907c515 | 173 | if (is_of_node(fwspec->fwnode) || is_acpi_device_node(fwspec->fwnode)) { |
9650c60e MJ |
174 | if (fwspec->param_count != 2) |
175 | return -EINVAL; | |
176 | ||
177 | if ((fwspec->param[0] > MAXIMUM_IRQ_PIN_NUM) || | |
178 | (fwspec->param[0] < RESERVED_IRQ_PER_MBIGEN_CHIP)) | |
179 | return -EINVAL; | |
180 | else | |
181 | *hwirq = fwspec->param[0]; | |
182 | ||
183 | /* If there is no valid irq type, just use the default type */ | |
184 | if ((fwspec->param[1] == IRQ_TYPE_EDGE_RISING) || | |
185 | (fwspec->param[1] == IRQ_TYPE_LEVEL_HIGH)) | |
186 | *type = fwspec->param[1]; | |
187 | else | |
188 | return -EINVAL; | |
189 | ||
190 | return 0; | |
191 | } | |
192 | return -EINVAL; | |
193 | } | |
194 | ||
195 | static int mbigen_irq_domain_alloc(struct irq_domain *domain, | |
196 | unsigned int virq, | |
197 | unsigned int nr_irqs, | |
198 | void *args) | |
199 | { | |
200 | struct irq_fwspec *fwspec = args; | |
201 | irq_hw_number_t hwirq; | |
202 | unsigned int type; | |
203 | struct mbigen_device *mgn_chip; | |
204 | int i, err; | |
205 | ||
206 | err = mbigen_domain_translate(domain, fwspec, &hwirq, &type); | |
207 | if (err) | |
208 | return err; | |
209 | ||
210 | err = platform_msi_domain_alloc(domain, virq, nr_irqs); | |
211 | if (err) | |
212 | return err; | |
213 | ||
214 | mgn_chip = platform_msi_get_host_data(domain); | |
215 | ||
216 | for (i = 0; i < nr_irqs; i++) | |
217 | irq_domain_set_hwirq_and_chip(domain, virq + i, hwirq + i, | |
218 | &mbigen_irq_chip, mgn_chip->base); | |
219 | ||
220 | return 0; | |
221 | } | |
222 | ||
e183c2a3 | 223 | static const struct irq_domain_ops mbigen_domain_ops = { |
9650c60e MJ |
224 | .translate = mbigen_domain_translate, |
225 | .alloc = mbigen_irq_domain_alloc, | |
226 | .free = irq_domain_free_irqs_common, | |
227 | }; | |
228 | ||
76e1f77f KW |
229 | static int mbigen_of_create_domain(struct platform_device *pdev, |
230 | struct mbigen_device *mgn_chip) | |
717c3dbc | 231 | { |
76e1f77f | 232 | struct device *parent; |
ed2a1002 | 233 | struct platform_device *child; |
9650c60e | 234 | struct irq_domain *domain; |
ed2a1002 | 235 | struct device_node *np; |
9650c60e | 236 | u32 num_pins; |
717c3dbc | 237 | |
ed2a1002 M |
238 | for_each_child_of_node(pdev->dev.of_node, np) { |
239 | if (!of_property_read_bool(np, "interrupt-controller")) | |
240 | continue; | |
9650c60e | 241 | |
ed2a1002 M |
242 | parent = platform_bus_type.dev_root; |
243 | child = of_platform_device_create(np, NULL, parent); | |
321275f0 ND |
244 | if (!child) { |
245 | of_node_put(np); | |
086eec2d | 246 | return -ENOMEM; |
321275f0 | 247 | } |
9650c60e | 248 | |
ed2a1002 M |
249 | if (of_property_read_u32(child->dev.of_node, "num-pins", |
250 | &num_pins) < 0) { | |
251 | dev_err(&pdev->dev, "No num-pins property\n"); | |
321275f0 | 252 | of_node_put(np); |
ed2a1002 M |
253 | return -EINVAL; |
254 | } | |
255 | ||
256 | domain = platform_msi_create_device_domain(&child->dev, num_pins, | |
257 | mbigen_write_msg, | |
258 | &mbigen_domain_ops, | |
259 | mgn_chip); | |
321275f0 ND |
260 | if (!domain) { |
261 | of_node_put(np); | |
ed2a1002 | 262 | return -ENOMEM; |
321275f0 | 263 | } |
ed2a1002 | 264 | } |
9650c60e | 265 | |
76e1f77f KW |
266 | return 0; |
267 | } | |
268 | ||
f907c515 HG |
269 | #ifdef CONFIG_ACPI |
270 | static int mbigen_acpi_create_domain(struct platform_device *pdev, | |
271 | struct mbigen_device *mgn_chip) | |
272 | { | |
273 | struct irq_domain *domain; | |
274 | u32 num_pins = 0; | |
275 | int ret; | |
276 | ||
277 | /* | |
278 | * "num-pins" is the total number of interrupt pins implemented in | |
279 | * this mbigen instance, and mbigen is an interrupt controller | |
280 | * connected to ITS converting wired interrupts into MSI, so we | |
281 | * use "num-pins" to alloc MSI vectors which are needed by client | |
282 | * devices connected to it. | |
283 | * | |
284 | * Here is the DSDT device node used for mbigen in firmware: | |
285 | * Device(MBI0) { | |
286 | * Name(_HID, "HISI0152") | |
287 | * Name(_UID, Zero) | |
288 | * Name(_CRS, ResourceTemplate() { | |
289 | * Memory32Fixed(ReadWrite, 0xa0080000, 0x10000) | |
290 | * }) | |
291 | * | |
292 | * Name(_DSD, Package () { | |
293 | * ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), | |
294 | * Package () { | |
295 | * Package () {"num-pins", 378} | |
296 | * } | |
297 | * }) | |
298 | * } | |
299 | */ | |
300 | ret = device_property_read_u32(&pdev->dev, "num-pins", &num_pins); | |
301 | if (ret || num_pins == 0) | |
302 | return -EINVAL; | |
303 | ||
304 | domain = platform_msi_create_device_domain(&pdev->dev, num_pins, | |
305 | mbigen_write_msg, | |
306 | &mbigen_domain_ops, | |
307 | mgn_chip); | |
308 | if (!domain) | |
309 | return -ENOMEM; | |
310 | ||
311 | return 0; | |
312 | } | |
313 | #else | |
314 | static inline int mbigen_acpi_create_domain(struct platform_device *pdev, | |
315 | struct mbigen_device *mgn_chip) | |
316 | { | |
317 | return -ENODEV; | |
318 | } | |
319 | #endif | |
320 | ||
76e1f77f KW |
321 | static int mbigen_device_probe(struct platform_device *pdev) |
322 | { | |
323 | struct mbigen_device *mgn_chip; | |
324 | struct resource *res; | |
325 | int err; | |
326 | ||
327 | mgn_chip = devm_kzalloc(&pdev->dev, sizeof(*mgn_chip), GFP_KERNEL); | |
328 | if (!mgn_chip) | |
329 | return -ENOMEM; | |
330 | ||
331 | mgn_chip->pdev = pdev; | |
332 | ||
333 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
ad7cc3c0 HG |
334 | if (!res) |
335 | return -EINVAL; | |
336 | ||
5ba9b0a1 HG |
337 | mgn_chip->base = devm_ioremap(&pdev->dev, res->start, |
338 | resource_size(res)); | |
339 | if (!mgn_chip->base) { | |
340 | dev_err(&pdev->dev, "failed to ioremap %pR\n", res); | |
341 | return -ENOMEM; | |
342 | } | |
76e1f77f | 343 | |
f907c515 HG |
344 | if (IS_ENABLED(CONFIG_OF) && pdev->dev.of_node) |
345 | err = mbigen_of_create_domain(pdev, mgn_chip); | |
346 | else if (ACPI_COMPANION(&pdev->dev)) | |
347 | err = mbigen_acpi_create_domain(pdev, mgn_chip); | |
348 | else | |
349 | err = -EINVAL; | |
350 | ||
351 | if (err) { | |
0bdd0047 | 352 | dev_err(&pdev->dev, "Failed to create mbi-gen irqdomain\n"); |
76e1f77f | 353 | return err; |
f907c515 | 354 | } |
76e1f77f | 355 | |
717c3dbc | 356 | platform_set_drvdata(pdev, mgn_chip); |
717c3dbc MJ |
357 | return 0; |
358 | } | |
359 | ||
360 | static const struct of_device_id mbigen_of_match[] = { | |
361 | { .compatible = "hisilicon,mbigen-v2" }, | |
362 | { /* END */ } | |
363 | }; | |
364 | MODULE_DEVICE_TABLE(of, mbigen_of_match); | |
365 | ||
f907c515 HG |
366 | static const struct acpi_device_id mbigen_acpi_match[] = { |
367 | { "HISI0152", 0 }, | |
368 | {} | |
369 | }; | |
370 | MODULE_DEVICE_TABLE(acpi, mbigen_acpi_match); | |
371 | ||
717c3dbc MJ |
372 | static struct platform_driver mbigen_platform_driver = { |
373 | .driver = { | |
374 | .name = "Hisilicon MBIGEN-V2", | |
717c3dbc | 375 | .of_match_table = mbigen_of_match, |
f907c515 | 376 | .acpi_match_table = ACPI_PTR(mbigen_acpi_match), |
d6152e6e | 377 | .suppress_bind_attrs = true, |
717c3dbc MJ |
378 | }, |
379 | .probe = mbigen_device_probe, | |
380 | }; | |
381 | ||
382 | module_platform_driver(mbigen_platform_driver); | |
383 | ||
384 | MODULE_AUTHOR("Jun Ma <majun258@huawei.com>"); | |
385 | MODULE_AUTHOR("Yun Wu <wuyun.wu@huawei.com>"); | |
386 | MODULE_LICENSE("GPL"); | |
387 | MODULE_DESCRIPTION("Hisilicon MBI Generator driver"); |