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Commit | Line | Data |
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2299c49d SH |
1 | /* |
2 | * This file is subject to the terms and conditions of the GNU General Public | |
3 | * License. See the file "COPYING" in the main directory of this archive | |
4 | * for more details. | |
5 | * | |
6 | * Copyright (C) 2008 Ralf Baechle (ralf@linux-mips.org) | |
7 | * Copyright (C) 2012 MIPS Technologies, Inc. All rights reserved. | |
8 | */ | |
39b8d525 | 9 | #include <linux/bitmap.h> |
fb8f7be1 | 10 | #include <linux/clocksource.h> |
39b8d525 | 11 | #include <linux/init.h> |
18743d27 | 12 | #include <linux/interrupt.h> |
fb8f7be1 | 13 | #include <linux/irq.h> |
4060bbe9 | 14 | #include <linux/irqchip/mips-gic.h> |
a7057270 | 15 | #include <linux/of_address.h> |
18743d27 | 16 | #include <linux/sched.h> |
631330f5 | 17 | #include <linux/smp.h> |
39b8d525 | 18 | |
a7057270 | 19 | #include <asm/mips-cm.h> |
98b67c37 SH |
20 | #include <asm/setup.h> |
21 | #include <asm/traps.h> | |
39b8d525 | 22 | |
a7057270 AB |
23 | #include <dt-bindings/interrupt-controller/mips-gic.h> |
24 | ||
25 | #include "irqchip.h" | |
26 | ||
ff86714f | 27 | unsigned int gic_present; |
98b67c37 | 28 | |
822350bc | 29 | struct gic_pcpu_mask { |
fbd55241 | 30 | DECLARE_BITMAP(pcpu_mask, GIC_MAX_INTRS); |
822350bc JD |
31 | }; |
32 | ||
5f68fea0 | 33 | static void __iomem *gic_base; |
0b271f56 | 34 | static struct gic_pcpu_mask pcpu_masks[NR_CPUS]; |
95150ae8 | 35 | static DEFINE_SPINLOCK(gic_lock); |
c49581a4 | 36 | static struct irq_domain *gic_irq_domain; |
fbd55241 | 37 | static int gic_shared_intrs; |
e9de688d | 38 | static int gic_vpes; |
3263d085 | 39 | static unsigned int gic_cpu_pin; |
1b6af71a | 40 | static unsigned int timer_cpu_pin; |
4a6a3ea3 | 41 | static struct irq_chip gic_level_irq_controller, gic_edge_irq_controller; |
39b8d525 | 42 | |
18743d27 AB |
43 | static void __gic_irq_dispatch(void); |
44 | ||
5f68fea0 AB |
45 | static inline unsigned int gic_read(unsigned int reg) |
46 | { | |
47 | return __raw_readl(gic_base + reg); | |
48 | } | |
49 | ||
50 | static inline void gic_write(unsigned int reg, unsigned int val) | |
51 | { | |
52 | __raw_writel(val, gic_base + reg); | |
53 | } | |
54 | ||
55 | static inline void gic_update_bits(unsigned int reg, unsigned int mask, | |
56 | unsigned int val) | |
57 | { | |
58 | unsigned int regval; | |
59 | ||
60 | regval = gic_read(reg); | |
61 | regval &= ~mask; | |
62 | regval |= val; | |
63 | gic_write(reg, regval); | |
64 | } | |
65 | ||
66 | static inline void gic_reset_mask(unsigned int intr) | |
67 | { | |
68 | gic_write(GIC_REG(SHARED, GIC_SH_RMASK) + GIC_INTR_OFS(intr), | |
69 | 1 << GIC_INTR_BIT(intr)); | |
70 | } | |
71 | ||
72 | static inline void gic_set_mask(unsigned int intr) | |
73 | { | |
74 | gic_write(GIC_REG(SHARED, GIC_SH_SMASK) + GIC_INTR_OFS(intr), | |
75 | 1 << GIC_INTR_BIT(intr)); | |
76 | } | |
77 | ||
78 | static inline void gic_set_polarity(unsigned int intr, unsigned int pol) | |
79 | { | |
80 | gic_update_bits(GIC_REG(SHARED, GIC_SH_SET_POLARITY) + | |
81 | GIC_INTR_OFS(intr), 1 << GIC_INTR_BIT(intr), | |
82 | pol << GIC_INTR_BIT(intr)); | |
83 | } | |
84 | ||
85 | static inline void gic_set_trigger(unsigned int intr, unsigned int trig) | |
86 | { | |
87 | gic_update_bits(GIC_REG(SHARED, GIC_SH_SET_TRIGGER) + | |
88 | GIC_INTR_OFS(intr), 1 << GIC_INTR_BIT(intr), | |
89 | trig << GIC_INTR_BIT(intr)); | |
90 | } | |
91 | ||
92 | static inline void gic_set_dual_edge(unsigned int intr, unsigned int dual) | |
93 | { | |
94 | gic_update_bits(GIC_REG(SHARED, GIC_SH_SET_DUAL) + GIC_INTR_OFS(intr), | |
95 | 1 << GIC_INTR_BIT(intr), | |
96 | dual << GIC_INTR_BIT(intr)); | |
97 | } | |
98 | ||
99 | static inline void gic_map_to_pin(unsigned int intr, unsigned int pin) | |
100 | { | |
101 | gic_write(GIC_REG(SHARED, GIC_SH_INTR_MAP_TO_PIN_BASE) + | |
102 | GIC_SH_MAP_TO_PIN(intr), GIC_MAP_TO_PIN_MSK | pin); | |
103 | } | |
104 | ||
105 | static inline void gic_map_to_vpe(unsigned int intr, unsigned int vpe) | |
106 | { | |
107 | gic_write(GIC_REG(SHARED, GIC_SH_INTR_MAP_TO_VPE_BASE) + | |
108 | GIC_SH_MAP_TO_VPE_REG_OFF(intr, vpe), | |
109 | GIC_SH_MAP_TO_VPE_REG_BIT(vpe)); | |
110 | } | |
111 | ||
a331ce63 | 112 | #ifdef CONFIG_CLKSRC_MIPS_GIC |
dfa762e1 SH |
113 | cycle_t gic_read_count(void) |
114 | { | |
115 | unsigned int hi, hi2, lo; | |
116 | ||
117 | do { | |
5f68fea0 AB |
118 | hi = gic_read(GIC_REG(SHARED, GIC_SH_COUNTER_63_32)); |
119 | lo = gic_read(GIC_REG(SHARED, GIC_SH_COUNTER_31_00)); | |
120 | hi2 = gic_read(GIC_REG(SHARED, GIC_SH_COUNTER_63_32)); | |
dfa762e1 SH |
121 | } while (hi2 != hi); |
122 | ||
123 | return (((cycle_t) hi) << 32) + lo; | |
124 | } | |
0ab2b7d0 | 125 | |
387904ff AB |
126 | unsigned int gic_get_count_width(void) |
127 | { | |
128 | unsigned int bits, config; | |
129 | ||
5f68fea0 | 130 | config = gic_read(GIC_REG(SHARED, GIC_SH_CONFIG)); |
387904ff AB |
131 | bits = 32 + 4 * ((config & GIC_SH_CONFIG_COUNTBITS_MSK) >> |
132 | GIC_SH_CONFIG_COUNTBITS_SHF); | |
133 | ||
134 | return bits; | |
135 | } | |
136 | ||
0ab2b7d0 RG |
137 | void gic_write_compare(cycle_t cnt) |
138 | { | |
5f68fea0 | 139 | gic_write(GIC_REG(VPE_LOCAL, GIC_VPE_COMPARE_HI), |
0ab2b7d0 | 140 | (int)(cnt >> 32)); |
5f68fea0 | 141 | gic_write(GIC_REG(VPE_LOCAL, GIC_VPE_COMPARE_LO), |
0ab2b7d0 RG |
142 | (int)(cnt & 0xffffffff)); |
143 | } | |
144 | ||
414408d0 PB |
145 | void gic_write_cpu_compare(cycle_t cnt, int cpu) |
146 | { | |
147 | unsigned long flags; | |
148 | ||
149 | local_irq_save(flags); | |
150 | ||
5f68fea0 AB |
151 | gic_write(GIC_REG(VPE_LOCAL, GIC_VPE_OTHER_ADDR), cpu); |
152 | gic_write(GIC_REG(VPE_OTHER, GIC_VPE_COMPARE_HI), | |
414408d0 | 153 | (int)(cnt >> 32)); |
5f68fea0 | 154 | gic_write(GIC_REG(VPE_OTHER, GIC_VPE_COMPARE_LO), |
414408d0 PB |
155 | (int)(cnt & 0xffffffff)); |
156 | ||
157 | local_irq_restore(flags); | |
158 | } | |
159 | ||
0ab2b7d0 RG |
160 | cycle_t gic_read_compare(void) |
161 | { | |
162 | unsigned int hi, lo; | |
163 | ||
5f68fea0 AB |
164 | hi = gic_read(GIC_REG(VPE_LOCAL, GIC_VPE_COMPARE_HI)); |
165 | lo = gic_read(GIC_REG(VPE_LOCAL, GIC_VPE_COMPARE_LO)); | |
0ab2b7d0 RG |
166 | |
167 | return (((cycle_t) hi) << 32) + lo; | |
168 | } | |
dfa762e1 SH |
169 | #endif |
170 | ||
e9de688d AB |
171 | static bool gic_local_irq_is_routable(int intr) |
172 | { | |
173 | u32 vpe_ctl; | |
174 | ||
175 | /* All local interrupts are routable in EIC mode. */ | |
176 | if (cpu_has_veic) | |
177 | return true; | |
178 | ||
5f68fea0 | 179 | vpe_ctl = gic_read(GIC_REG(VPE_LOCAL, GIC_VPE_CTL)); |
e9de688d AB |
180 | switch (intr) { |
181 | case GIC_LOCAL_INT_TIMER: | |
182 | return vpe_ctl & GIC_VPE_CTL_TIMER_RTBL_MSK; | |
183 | case GIC_LOCAL_INT_PERFCTR: | |
184 | return vpe_ctl & GIC_VPE_CTL_PERFCNT_RTBL_MSK; | |
185 | case GIC_LOCAL_INT_FDC: | |
186 | return vpe_ctl & GIC_VPE_CTL_FDC_RTBL_MSK; | |
187 | case GIC_LOCAL_INT_SWINT0: | |
188 | case GIC_LOCAL_INT_SWINT1: | |
189 | return vpe_ctl & GIC_VPE_CTL_SWINT_RTBL_MSK; | |
190 | default: | |
191 | return true; | |
192 | } | |
193 | } | |
194 | ||
98b67c37 SH |
195 | unsigned int gic_get_timer_pending(void) |
196 | { | |
197 | unsigned int vpe_pending; | |
198 | ||
5f68fea0 | 199 | vpe_pending = gic_read(GIC_REG(VPE_LOCAL, GIC_VPE_PEND)); |
635c9907 | 200 | return vpe_pending & GIC_VPE_PEND_TIMER_MSK; |
98b67c37 SH |
201 | } |
202 | ||
3263d085 | 203 | static void gic_bind_eic_interrupt(int irq, int set) |
98b67c37 SH |
204 | { |
205 | /* Convert irq vector # to hw int # */ | |
206 | irq -= GIC_PIN_TO_VEC_OFFSET; | |
207 | ||
208 | /* Set irq to use shadow set */ | |
5f68fea0 AB |
209 | gic_write(GIC_REG(VPE_LOCAL, GIC_VPE_EIC_SHADOW_SET_BASE) + |
210 | GIC_VPE_EIC_SS(irq), set); | |
98b67c37 SH |
211 | } |
212 | ||
39b8d525 RB |
213 | void gic_send_ipi(unsigned int intr) |
214 | { | |
53a7bc81 | 215 | gic_write(GIC_REG(SHARED, GIC_SH_WEDGE), GIC_SH_WEDGE_SET(intr)); |
39b8d525 RB |
216 | } |
217 | ||
e9de688d AB |
218 | int gic_get_c0_compare_int(void) |
219 | { | |
220 | if (!gic_local_irq_is_routable(GIC_LOCAL_INT_TIMER)) | |
221 | return MIPS_CPU_IRQ_BASE + cp0_compare_irq; | |
222 | return irq_create_mapping(gic_irq_domain, | |
223 | GIC_LOCAL_TO_HWIRQ(GIC_LOCAL_INT_TIMER)); | |
224 | } | |
225 | ||
226 | int gic_get_c0_perfcount_int(void) | |
227 | { | |
228 | if (!gic_local_irq_is_routable(GIC_LOCAL_INT_PERFCTR)) { | |
229 | /* Is the erformance counter shared with the timer? */ | |
230 | if (cp0_perfcount_irq < 0) | |
231 | return -1; | |
232 | return MIPS_CPU_IRQ_BASE + cp0_perfcount_irq; | |
233 | } | |
234 | return irq_create_mapping(gic_irq_domain, | |
235 | GIC_LOCAL_TO_HWIRQ(GIC_LOCAL_INT_PERFCTR)); | |
236 | } | |
237 | ||
d7eb4f2e | 238 | static void gic_handle_shared_int(void) |
39b8d525 | 239 | { |
d7eb4f2e | 240 | unsigned int i, intr, virq; |
8f5ee79c | 241 | unsigned long *pcpu_mask; |
5f68fea0 | 242 | unsigned long pending_reg, intrmask_reg; |
8f5ee79c AB |
243 | DECLARE_BITMAP(pending, GIC_MAX_INTRS); |
244 | DECLARE_BITMAP(intrmask, GIC_MAX_INTRS); | |
39b8d525 RB |
245 | |
246 | /* Get per-cpu bitmaps */ | |
39b8d525 RB |
247 | pcpu_mask = pcpu_masks[smp_processor_id()].pcpu_mask; |
248 | ||
824f3f7f AB |
249 | pending_reg = GIC_REG(SHARED, GIC_SH_PEND); |
250 | intrmask_reg = GIC_REG(SHARED, GIC_SH_MASK); | |
39b8d525 | 251 | |
fbd55241 | 252 | for (i = 0; i < BITS_TO_LONGS(gic_shared_intrs); i++) { |
5f68fea0 AB |
253 | pending[i] = gic_read(pending_reg); |
254 | intrmask[i] = gic_read(intrmask_reg); | |
255 | pending_reg += 0x4; | |
256 | intrmask_reg += 0x4; | |
39b8d525 RB |
257 | } |
258 | ||
fbd55241 AB |
259 | bitmap_and(pending, pending, intrmask, gic_shared_intrs); |
260 | bitmap_and(pending, pending, pcpu_mask, gic_shared_intrs); | |
39b8d525 | 261 | |
d7eb4f2e QY |
262 | intr = find_first_bit(pending, gic_shared_intrs); |
263 | while (intr != gic_shared_intrs) { | |
264 | virq = irq_linear_revmap(gic_irq_domain, | |
265 | GIC_SHARED_TO_HWIRQ(intr)); | |
266 | do_IRQ(virq); | |
267 | ||
268 | /* go to next pending bit */ | |
269 | bitmap_clear(pending, intr, 1); | |
270 | intr = find_first_bit(pending, gic_shared_intrs); | |
271 | } | |
39b8d525 RB |
272 | } |
273 | ||
161d049e | 274 | static void gic_mask_irq(struct irq_data *d) |
39b8d525 | 275 | { |
5f68fea0 | 276 | gic_reset_mask(GIC_HWIRQ_TO_SHARED(d->hwirq)); |
39b8d525 RB |
277 | } |
278 | ||
161d049e | 279 | static void gic_unmask_irq(struct irq_data *d) |
39b8d525 | 280 | { |
5f68fea0 | 281 | gic_set_mask(GIC_HWIRQ_TO_SHARED(d->hwirq)); |
39b8d525 RB |
282 | } |
283 | ||
5561c9e4 AB |
284 | static void gic_ack_irq(struct irq_data *d) |
285 | { | |
e9de688d | 286 | unsigned int irq = GIC_HWIRQ_TO_SHARED(d->hwirq); |
c49581a4 | 287 | |
53a7bc81 | 288 | gic_write(GIC_REG(SHARED, GIC_SH_WEDGE), GIC_SH_WEDGE_CLR(irq)); |
5561c9e4 AB |
289 | } |
290 | ||
95150ae8 AB |
291 | static int gic_set_type(struct irq_data *d, unsigned int type) |
292 | { | |
e9de688d | 293 | unsigned int irq = GIC_HWIRQ_TO_SHARED(d->hwirq); |
95150ae8 AB |
294 | unsigned long flags; |
295 | bool is_edge; | |
296 | ||
297 | spin_lock_irqsave(&gic_lock, flags); | |
298 | switch (type & IRQ_TYPE_SENSE_MASK) { | |
299 | case IRQ_TYPE_EDGE_FALLING: | |
5f68fea0 AB |
300 | gic_set_polarity(irq, GIC_POL_NEG); |
301 | gic_set_trigger(irq, GIC_TRIG_EDGE); | |
302 | gic_set_dual_edge(irq, GIC_TRIG_DUAL_DISABLE); | |
95150ae8 AB |
303 | is_edge = true; |
304 | break; | |
305 | case IRQ_TYPE_EDGE_RISING: | |
5f68fea0 AB |
306 | gic_set_polarity(irq, GIC_POL_POS); |
307 | gic_set_trigger(irq, GIC_TRIG_EDGE); | |
308 | gic_set_dual_edge(irq, GIC_TRIG_DUAL_DISABLE); | |
95150ae8 AB |
309 | is_edge = true; |
310 | break; | |
311 | case IRQ_TYPE_EDGE_BOTH: | |
312 | /* polarity is irrelevant in this case */ | |
5f68fea0 AB |
313 | gic_set_trigger(irq, GIC_TRIG_EDGE); |
314 | gic_set_dual_edge(irq, GIC_TRIG_DUAL_ENABLE); | |
95150ae8 AB |
315 | is_edge = true; |
316 | break; | |
317 | case IRQ_TYPE_LEVEL_LOW: | |
5f68fea0 AB |
318 | gic_set_polarity(irq, GIC_POL_NEG); |
319 | gic_set_trigger(irq, GIC_TRIG_LEVEL); | |
320 | gic_set_dual_edge(irq, GIC_TRIG_DUAL_DISABLE); | |
95150ae8 AB |
321 | is_edge = false; |
322 | break; | |
323 | case IRQ_TYPE_LEVEL_HIGH: | |
324 | default: | |
5f68fea0 AB |
325 | gic_set_polarity(irq, GIC_POL_POS); |
326 | gic_set_trigger(irq, GIC_TRIG_LEVEL); | |
327 | gic_set_dual_edge(irq, GIC_TRIG_DUAL_DISABLE); | |
95150ae8 AB |
328 | is_edge = false; |
329 | break; | |
330 | } | |
331 | ||
332 | if (is_edge) { | |
4a6a3ea3 AB |
333 | __irq_set_chip_handler_name_locked(d->irq, |
334 | &gic_edge_irq_controller, | |
335 | handle_edge_irq, NULL); | |
95150ae8 | 336 | } else { |
4a6a3ea3 AB |
337 | __irq_set_chip_handler_name_locked(d->irq, |
338 | &gic_level_irq_controller, | |
339 | handle_level_irq, NULL); | |
95150ae8 AB |
340 | } |
341 | spin_unlock_irqrestore(&gic_lock, flags); | |
39b8d525 | 342 | |
95150ae8 AB |
343 | return 0; |
344 | } | |
345 | ||
346 | #ifdef CONFIG_SMP | |
161d049e TG |
347 | static int gic_set_affinity(struct irq_data *d, const struct cpumask *cpumask, |
348 | bool force) | |
39b8d525 | 349 | { |
e9de688d | 350 | unsigned int irq = GIC_HWIRQ_TO_SHARED(d->hwirq); |
39b8d525 RB |
351 | cpumask_t tmp = CPU_MASK_NONE; |
352 | unsigned long flags; | |
353 | int i; | |
354 | ||
0de26520 | 355 | cpumask_and(&tmp, cpumask, cpu_online_mask); |
39b8d525 | 356 | if (cpus_empty(tmp)) |
14d160ab | 357 | return -EINVAL; |
39b8d525 RB |
358 | |
359 | /* Assumption : cpumask refers to a single CPU */ | |
360 | spin_lock_irqsave(&gic_lock, flags); | |
39b8d525 | 361 | |
c214c035 | 362 | /* Re-route this IRQ */ |
5f68fea0 | 363 | gic_map_to_vpe(irq, first_cpu(tmp)); |
c214c035 TW |
364 | |
365 | /* Update the pcpu_masks */ | |
366 | for (i = 0; i < NR_CPUS; i++) | |
367 | clear_bit(irq, pcpu_masks[i].pcpu_mask); | |
368 | set_bit(irq, pcpu_masks[first_cpu(tmp)].pcpu_mask); | |
39b8d525 | 369 | |
161d049e | 370 | cpumask_copy(d->affinity, cpumask); |
39b8d525 RB |
371 | spin_unlock_irqrestore(&gic_lock, flags); |
372 | ||
161d049e | 373 | return IRQ_SET_MASK_OK_NOCOPY; |
39b8d525 RB |
374 | } |
375 | #endif | |
376 | ||
4a6a3ea3 AB |
377 | static struct irq_chip gic_level_irq_controller = { |
378 | .name = "MIPS GIC", | |
379 | .irq_mask = gic_mask_irq, | |
380 | .irq_unmask = gic_unmask_irq, | |
381 | .irq_set_type = gic_set_type, | |
382 | #ifdef CONFIG_SMP | |
383 | .irq_set_affinity = gic_set_affinity, | |
384 | #endif | |
385 | }; | |
386 | ||
387 | static struct irq_chip gic_edge_irq_controller = { | |
161d049e | 388 | .name = "MIPS GIC", |
5561c9e4 | 389 | .irq_ack = gic_ack_irq, |
161d049e | 390 | .irq_mask = gic_mask_irq, |
161d049e | 391 | .irq_unmask = gic_unmask_irq, |
95150ae8 | 392 | .irq_set_type = gic_set_type, |
39b8d525 | 393 | #ifdef CONFIG_SMP |
161d049e | 394 | .irq_set_affinity = gic_set_affinity, |
39b8d525 RB |
395 | #endif |
396 | }; | |
397 | ||
d7eb4f2e | 398 | static void gic_handle_local_int(void) |
e9de688d AB |
399 | { |
400 | unsigned long pending, masked; | |
d7eb4f2e | 401 | unsigned int intr, virq; |
e9de688d | 402 | |
5f68fea0 AB |
403 | pending = gic_read(GIC_REG(VPE_LOCAL, GIC_VPE_PEND)); |
404 | masked = gic_read(GIC_REG(VPE_LOCAL, GIC_VPE_MASK)); | |
e9de688d AB |
405 | |
406 | bitmap_and(&pending, &pending, &masked, GIC_NUM_LOCAL_INTRS); | |
407 | ||
d7eb4f2e QY |
408 | intr = find_first_bit(&pending, GIC_NUM_LOCAL_INTRS); |
409 | while (intr != GIC_NUM_LOCAL_INTRS) { | |
410 | virq = irq_linear_revmap(gic_irq_domain, | |
411 | GIC_LOCAL_TO_HWIRQ(intr)); | |
412 | do_IRQ(virq); | |
413 | ||
414 | /* go to next pending bit */ | |
415 | bitmap_clear(&pending, intr, 1); | |
416 | intr = find_first_bit(&pending, GIC_NUM_LOCAL_INTRS); | |
417 | } | |
e9de688d AB |
418 | } |
419 | ||
420 | static void gic_mask_local_irq(struct irq_data *d) | |
421 | { | |
422 | int intr = GIC_HWIRQ_TO_LOCAL(d->hwirq); | |
423 | ||
5f68fea0 | 424 | gic_write(GIC_REG(VPE_LOCAL, GIC_VPE_RMASK), 1 << intr); |
e9de688d AB |
425 | } |
426 | ||
427 | static void gic_unmask_local_irq(struct irq_data *d) | |
428 | { | |
429 | int intr = GIC_HWIRQ_TO_LOCAL(d->hwirq); | |
430 | ||
5f68fea0 | 431 | gic_write(GIC_REG(VPE_LOCAL, GIC_VPE_SMASK), 1 << intr); |
e9de688d AB |
432 | } |
433 | ||
434 | static struct irq_chip gic_local_irq_controller = { | |
435 | .name = "MIPS GIC Local", | |
436 | .irq_mask = gic_mask_local_irq, | |
437 | .irq_unmask = gic_unmask_local_irq, | |
438 | }; | |
439 | ||
440 | static void gic_mask_local_irq_all_vpes(struct irq_data *d) | |
441 | { | |
442 | int intr = GIC_HWIRQ_TO_LOCAL(d->hwirq); | |
443 | int i; | |
444 | unsigned long flags; | |
445 | ||
446 | spin_lock_irqsave(&gic_lock, flags); | |
447 | for (i = 0; i < gic_vpes; i++) { | |
5f68fea0 AB |
448 | gic_write(GIC_REG(VPE_LOCAL, GIC_VPE_OTHER_ADDR), i); |
449 | gic_write(GIC_REG(VPE_OTHER, GIC_VPE_RMASK), 1 << intr); | |
e9de688d AB |
450 | } |
451 | spin_unlock_irqrestore(&gic_lock, flags); | |
452 | } | |
453 | ||
454 | static void gic_unmask_local_irq_all_vpes(struct irq_data *d) | |
455 | { | |
456 | int intr = GIC_HWIRQ_TO_LOCAL(d->hwirq); | |
457 | int i; | |
458 | unsigned long flags; | |
459 | ||
460 | spin_lock_irqsave(&gic_lock, flags); | |
461 | for (i = 0; i < gic_vpes; i++) { | |
5f68fea0 AB |
462 | gic_write(GIC_REG(VPE_LOCAL, GIC_VPE_OTHER_ADDR), i); |
463 | gic_write(GIC_REG(VPE_OTHER, GIC_VPE_SMASK), 1 << intr); | |
e9de688d AB |
464 | } |
465 | spin_unlock_irqrestore(&gic_lock, flags); | |
466 | } | |
467 | ||
468 | static struct irq_chip gic_all_vpes_local_irq_controller = { | |
469 | .name = "MIPS GIC Local", | |
470 | .irq_mask = gic_mask_local_irq_all_vpes, | |
471 | .irq_unmask = gic_unmask_local_irq_all_vpes, | |
472 | }; | |
473 | ||
18743d27 | 474 | static void __gic_irq_dispatch(void) |
39b8d525 | 475 | { |
d7eb4f2e QY |
476 | gic_handle_local_int(); |
477 | gic_handle_shared_int(); | |
18743d27 | 478 | } |
39b8d525 | 479 | |
18743d27 AB |
480 | static void gic_irq_dispatch(unsigned int irq, struct irq_desc *desc) |
481 | { | |
482 | __gic_irq_dispatch(); | |
483 | } | |
484 | ||
485 | #ifdef CONFIG_MIPS_GIC_IPI | |
486 | static int gic_resched_int_base; | |
487 | static int gic_call_int_base; | |
488 | ||
489 | unsigned int plat_ipi_resched_int_xlate(unsigned int cpu) | |
490 | { | |
491 | return gic_resched_int_base + cpu; | |
492 | } | |
39b8d525 | 493 | |
18743d27 AB |
494 | unsigned int plat_ipi_call_int_xlate(unsigned int cpu) |
495 | { | |
496 | return gic_call_int_base + cpu; | |
497 | } | |
39b8d525 | 498 | |
18743d27 AB |
499 | static irqreturn_t ipi_resched_interrupt(int irq, void *dev_id) |
500 | { | |
501 | scheduler_ipi(); | |
502 | ||
503 | return IRQ_HANDLED; | |
504 | } | |
505 | ||
506 | static irqreturn_t ipi_call_interrupt(int irq, void *dev_id) | |
507 | { | |
508 | smp_call_function_interrupt(); | |
509 | ||
510 | return IRQ_HANDLED; | |
511 | } | |
b0a88ae5 | 512 | |
18743d27 AB |
513 | static struct irqaction irq_resched = { |
514 | .handler = ipi_resched_interrupt, | |
515 | .flags = IRQF_PERCPU, | |
516 | .name = "IPI resched" | |
517 | }; | |
518 | ||
519 | static struct irqaction irq_call = { | |
520 | .handler = ipi_call_interrupt, | |
521 | .flags = IRQF_PERCPU, | |
522 | .name = "IPI call" | |
523 | }; | |
524 | ||
525 | static __init void gic_ipi_init_one(unsigned int intr, int cpu, | |
526 | struct irqaction *action) | |
527 | { | |
e9de688d AB |
528 | int virq = irq_create_mapping(gic_irq_domain, |
529 | GIC_SHARED_TO_HWIRQ(intr)); | |
18743d27 AB |
530 | int i; |
531 | ||
5f68fea0 | 532 | gic_map_to_vpe(intr, cpu); |
c49581a4 AB |
533 | for (i = 0; i < NR_CPUS; i++) |
534 | clear_bit(intr, pcpu_masks[i].pcpu_mask); | |
b0a88ae5 JD |
535 | set_bit(intr, pcpu_masks[cpu].pcpu_mask); |
536 | ||
18743d27 AB |
537 | irq_set_irq_type(virq, IRQ_TYPE_EDGE_RISING); |
538 | ||
539 | irq_set_handler(virq, handle_percpu_irq); | |
540 | setup_irq(virq, action); | |
39b8d525 RB |
541 | } |
542 | ||
18743d27 | 543 | static __init void gic_ipi_init(void) |
39b8d525 | 544 | { |
18743d27 AB |
545 | int i; |
546 | ||
547 | /* Use last 2 * NR_CPUS interrupts as IPIs */ | |
fbd55241 | 548 | gic_resched_int_base = gic_shared_intrs - nr_cpu_ids; |
18743d27 AB |
549 | gic_call_int_base = gic_resched_int_base - nr_cpu_ids; |
550 | ||
551 | for (i = 0; i < nr_cpu_ids; i++) { | |
552 | gic_ipi_init_one(gic_call_int_base + i, i, &irq_call); | |
553 | gic_ipi_init_one(gic_resched_int_base + i, i, &irq_resched); | |
554 | } | |
555 | } | |
556 | #else | |
557 | static inline void gic_ipi_init(void) | |
558 | { | |
559 | } | |
560 | #endif | |
561 | ||
e9de688d | 562 | static void __init gic_basic_init(void) |
18743d27 AB |
563 | { |
564 | unsigned int i; | |
98b67c37 SH |
565 | |
566 | board_bind_eic_interrupt = &gic_bind_eic_interrupt; | |
39b8d525 RB |
567 | |
568 | /* Setup defaults */ | |
fbd55241 | 569 | for (i = 0; i < gic_shared_intrs; i++) { |
5f68fea0 AB |
570 | gic_set_polarity(i, GIC_POL_POS); |
571 | gic_set_trigger(i, GIC_TRIG_LEVEL); | |
572 | gic_reset_mask(i); | |
39b8d525 RB |
573 | } |
574 | ||
e9de688d AB |
575 | for (i = 0; i < gic_vpes; i++) { |
576 | unsigned int j; | |
577 | ||
5f68fea0 | 578 | gic_write(GIC_REG(VPE_LOCAL, GIC_VPE_OTHER_ADDR), i); |
e9de688d AB |
579 | for (j = 0; j < GIC_NUM_LOCAL_INTRS; j++) { |
580 | if (!gic_local_irq_is_routable(j)) | |
581 | continue; | |
5f68fea0 | 582 | gic_write(GIC_REG(VPE_OTHER, GIC_VPE_RMASK), 1 << j); |
e9de688d AB |
583 | } |
584 | } | |
39b8d525 RB |
585 | } |
586 | ||
e9de688d AB |
587 | static int gic_local_irq_domain_map(struct irq_domain *d, unsigned int virq, |
588 | irq_hw_number_t hw) | |
c49581a4 | 589 | { |
e9de688d AB |
590 | int intr = GIC_HWIRQ_TO_LOCAL(hw); |
591 | int ret = 0; | |
592 | int i; | |
593 | unsigned long flags; | |
594 | ||
595 | if (!gic_local_irq_is_routable(intr)) | |
596 | return -EPERM; | |
597 | ||
598 | /* | |
599 | * HACK: These are all really percpu interrupts, but the rest | |
600 | * of the MIPS kernel code does not use the percpu IRQ API for | |
601 | * the CP0 timer and performance counter interrupts. | |
602 | */ | |
603 | if (intr != GIC_LOCAL_INT_TIMER && intr != GIC_LOCAL_INT_PERFCTR) { | |
604 | irq_set_chip_and_handler(virq, | |
605 | &gic_local_irq_controller, | |
606 | handle_percpu_devid_irq); | |
607 | irq_set_percpu_devid(virq); | |
608 | } else { | |
609 | irq_set_chip_and_handler(virq, | |
610 | &gic_all_vpes_local_irq_controller, | |
611 | handle_percpu_irq); | |
612 | } | |
613 | ||
614 | spin_lock_irqsave(&gic_lock, flags); | |
615 | for (i = 0; i < gic_vpes; i++) { | |
616 | u32 val = GIC_MAP_TO_PIN_MSK | gic_cpu_pin; | |
617 | ||
5f68fea0 | 618 | gic_write(GIC_REG(VPE_LOCAL, GIC_VPE_OTHER_ADDR), i); |
e9de688d AB |
619 | |
620 | switch (intr) { | |
621 | case GIC_LOCAL_INT_WD: | |
5f68fea0 | 622 | gic_write(GIC_REG(VPE_OTHER, GIC_VPE_WD_MAP), val); |
e9de688d AB |
623 | break; |
624 | case GIC_LOCAL_INT_COMPARE: | |
5f68fea0 | 625 | gic_write(GIC_REG(VPE_OTHER, GIC_VPE_COMPARE_MAP), val); |
e9de688d AB |
626 | break; |
627 | case GIC_LOCAL_INT_TIMER: | |
1b6af71a JH |
628 | /* CONFIG_MIPS_CMP workaround (see __gic_init) */ |
629 | val = GIC_MAP_TO_PIN_MSK | timer_cpu_pin; | |
5f68fea0 | 630 | gic_write(GIC_REG(VPE_OTHER, GIC_VPE_TIMER_MAP), val); |
e9de688d AB |
631 | break; |
632 | case GIC_LOCAL_INT_PERFCTR: | |
5f68fea0 | 633 | gic_write(GIC_REG(VPE_OTHER, GIC_VPE_PERFCTR_MAP), val); |
e9de688d AB |
634 | break; |
635 | case GIC_LOCAL_INT_SWINT0: | |
5f68fea0 | 636 | gic_write(GIC_REG(VPE_OTHER, GIC_VPE_SWINT0_MAP), val); |
e9de688d AB |
637 | break; |
638 | case GIC_LOCAL_INT_SWINT1: | |
5f68fea0 | 639 | gic_write(GIC_REG(VPE_OTHER, GIC_VPE_SWINT1_MAP), val); |
e9de688d AB |
640 | break; |
641 | case GIC_LOCAL_INT_FDC: | |
5f68fea0 | 642 | gic_write(GIC_REG(VPE_OTHER, GIC_VPE_FDC_MAP), val); |
e9de688d AB |
643 | break; |
644 | default: | |
645 | pr_err("Invalid local IRQ %d\n", intr); | |
646 | ret = -EINVAL; | |
647 | break; | |
648 | } | |
649 | } | |
650 | spin_unlock_irqrestore(&gic_lock, flags); | |
651 | ||
652 | return ret; | |
653 | } | |
654 | ||
655 | static int gic_shared_irq_domain_map(struct irq_domain *d, unsigned int virq, | |
656 | irq_hw_number_t hw) | |
657 | { | |
658 | int intr = GIC_HWIRQ_TO_SHARED(hw); | |
c49581a4 AB |
659 | unsigned long flags; |
660 | ||
4a6a3ea3 AB |
661 | irq_set_chip_and_handler(virq, &gic_level_irq_controller, |
662 | handle_level_irq); | |
c49581a4 AB |
663 | |
664 | spin_lock_irqsave(&gic_lock, flags); | |
5f68fea0 | 665 | gic_map_to_pin(intr, gic_cpu_pin); |
c49581a4 | 666 | /* Map to VPE 0 by default */ |
5f68fea0 | 667 | gic_map_to_vpe(intr, 0); |
e9de688d | 668 | set_bit(intr, pcpu_masks[0].pcpu_mask); |
c49581a4 AB |
669 | spin_unlock_irqrestore(&gic_lock, flags); |
670 | ||
671 | return 0; | |
672 | } | |
673 | ||
e9de688d AB |
674 | static int gic_irq_domain_map(struct irq_domain *d, unsigned int virq, |
675 | irq_hw_number_t hw) | |
676 | { | |
677 | if (GIC_HWIRQ_TO_LOCAL(hw) < GIC_NUM_LOCAL_INTRS) | |
678 | return gic_local_irq_domain_map(d, virq, hw); | |
679 | return gic_shared_irq_domain_map(d, virq, hw); | |
680 | } | |
681 | ||
a7057270 AB |
682 | static int gic_irq_domain_xlate(struct irq_domain *d, struct device_node *ctrlr, |
683 | const u32 *intspec, unsigned int intsize, | |
684 | irq_hw_number_t *out_hwirq, | |
685 | unsigned int *out_type) | |
686 | { | |
687 | if (intsize != 3) | |
688 | return -EINVAL; | |
689 | ||
690 | if (intspec[0] == GIC_SHARED) | |
691 | *out_hwirq = GIC_SHARED_TO_HWIRQ(intspec[1]); | |
692 | else if (intspec[0] == GIC_LOCAL) | |
693 | *out_hwirq = GIC_LOCAL_TO_HWIRQ(intspec[1]); | |
694 | else | |
695 | return -EINVAL; | |
696 | *out_type = intspec[2] & IRQ_TYPE_SENSE_MASK; | |
697 | ||
698 | return 0; | |
699 | } | |
700 | ||
c49581a4 AB |
701 | static struct irq_domain_ops gic_irq_domain_ops = { |
702 | .map = gic_irq_domain_map, | |
a7057270 | 703 | .xlate = gic_irq_domain_xlate, |
c49581a4 AB |
704 | }; |
705 | ||
a7057270 AB |
706 | static void __init __gic_init(unsigned long gic_base_addr, |
707 | unsigned long gic_addrspace_size, | |
708 | unsigned int cpu_vec, unsigned int irqbase, | |
709 | struct device_node *node) | |
39b8d525 RB |
710 | { |
711 | unsigned int gicconfig; | |
712 | ||
5f68fea0 | 713 | gic_base = ioremap_nocache(gic_base_addr, gic_addrspace_size); |
39b8d525 | 714 | |
5f68fea0 | 715 | gicconfig = gic_read(GIC_REG(SHARED, GIC_SH_CONFIG)); |
fbd55241 | 716 | gic_shared_intrs = (gicconfig & GIC_SH_CONFIG_NUMINTRS_MSK) >> |
39b8d525 | 717 | GIC_SH_CONFIG_NUMINTRS_SHF; |
fbd55241 | 718 | gic_shared_intrs = ((gic_shared_intrs + 1) * 8); |
39b8d525 | 719 | |
e9de688d | 720 | gic_vpes = (gicconfig & GIC_SH_CONFIG_NUMVPES_MSK) >> |
39b8d525 | 721 | GIC_SH_CONFIG_NUMVPES_SHF; |
e9de688d | 722 | gic_vpes = gic_vpes + 1; |
39b8d525 | 723 | |
18743d27 AB |
724 | if (cpu_has_veic) { |
725 | /* Always use vector 1 in EIC mode */ | |
726 | gic_cpu_pin = 0; | |
1b6af71a | 727 | timer_cpu_pin = gic_cpu_pin; |
18743d27 AB |
728 | set_vi_handler(gic_cpu_pin + GIC_PIN_TO_VEC_OFFSET, |
729 | __gic_irq_dispatch); | |
730 | } else { | |
731 | gic_cpu_pin = cpu_vec - GIC_CPU_PIN_OFFSET; | |
732 | irq_set_chained_handler(MIPS_CPU_IRQ_BASE + cpu_vec, | |
733 | gic_irq_dispatch); | |
1b6af71a JH |
734 | /* |
735 | * With the CMP implementation of SMP (deprecated), other CPUs | |
736 | * are started by the bootloader and put into a timer based | |
737 | * waiting poll loop. We must not re-route those CPU's local | |
738 | * timer interrupts as the wait instruction will never finish, | |
739 | * so just handle whatever CPU interrupt it is routed to by | |
740 | * default. | |
741 | * | |
742 | * This workaround should be removed when CMP support is | |
743 | * dropped. | |
744 | */ | |
745 | if (IS_ENABLED(CONFIG_MIPS_CMP) && | |
746 | gic_local_irq_is_routable(GIC_LOCAL_INT_TIMER)) { | |
747 | timer_cpu_pin = gic_read(GIC_REG(VPE_LOCAL, | |
748 | GIC_VPE_TIMER_MAP)) & | |
749 | GIC_MAP_MSK; | |
750 | irq_set_chained_handler(MIPS_CPU_IRQ_BASE + | |
751 | GIC_CPU_PIN_OFFSET + | |
752 | timer_cpu_pin, | |
753 | gic_irq_dispatch); | |
754 | } else { | |
755 | timer_cpu_pin = gic_cpu_pin; | |
756 | } | |
18743d27 AB |
757 | } |
758 | ||
a7057270 | 759 | gic_irq_domain = irq_domain_add_simple(node, GIC_NUM_LOCAL_INTRS + |
e9de688d | 760 | gic_shared_intrs, irqbase, |
c49581a4 AB |
761 | &gic_irq_domain_ops, NULL); |
762 | if (!gic_irq_domain) | |
763 | panic("Failed to add GIC IRQ domain"); | |
0b271f56 | 764 | |
e9de688d | 765 | gic_basic_init(); |
18743d27 AB |
766 | |
767 | gic_ipi_init(); | |
39b8d525 | 768 | } |
a7057270 AB |
769 | |
770 | void __init gic_init(unsigned long gic_base_addr, | |
771 | unsigned long gic_addrspace_size, | |
772 | unsigned int cpu_vec, unsigned int irqbase) | |
773 | { | |
774 | __gic_init(gic_base_addr, gic_addrspace_size, cpu_vec, irqbase, NULL); | |
775 | } | |
776 | ||
777 | static int __init gic_of_init(struct device_node *node, | |
778 | struct device_node *parent) | |
779 | { | |
780 | struct resource res; | |
781 | unsigned int cpu_vec, i = 0, reserved = 0; | |
782 | phys_addr_t gic_base; | |
783 | size_t gic_len; | |
784 | ||
785 | /* Find the first available CPU vector. */ | |
786 | while (!of_property_read_u32_index(node, "mti,reserved-cpu-vectors", | |
787 | i++, &cpu_vec)) | |
788 | reserved |= BIT(cpu_vec); | |
789 | for (cpu_vec = 2; cpu_vec < 8; cpu_vec++) { | |
790 | if (!(reserved & BIT(cpu_vec))) | |
791 | break; | |
792 | } | |
793 | if (cpu_vec == 8) { | |
794 | pr_err("No CPU vectors available for GIC\n"); | |
795 | return -ENODEV; | |
796 | } | |
797 | ||
798 | if (of_address_to_resource(node, 0, &res)) { | |
799 | /* | |
800 | * Probe the CM for the GIC base address if not specified | |
801 | * in the device-tree. | |
802 | */ | |
803 | if (mips_cm_present()) { | |
804 | gic_base = read_gcr_gic_base() & | |
805 | ~CM_GCR_GIC_BASE_GICEN_MSK; | |
806 | gic_len = 0x20000; | |
807 | } else { | |
808 | pr_err("Failed to get GIC memory range\n"); | |
809 | return -ENODEV; | |
810 | } | |
811 | } else { | |
812 | gic_base = res.start; | |
813 | gic_len = resource_size(&res); | |
814 | } | |
815 | ||
816 | if (mips_cm_present()) | |
817 | write_gcr_gic_base(gic_base | CM_GCR_GIC_BASE_GICEN_MSK); | |
818 | gic_present = true; | |
819 | ||
820 | __gic_init(gic_base, gic_len, cpu_vec, 0, node); | |
821 | ||
822 | return 0; | |
823 | } | |
824 | IRQCHIP_DECLARE(mips_gic, "mti,gic", gic_of_init); |