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Commit | Line | Data |
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2299c49d SH |
1 | /* |
2 | * This file is subject to the terms and conditions of the GNU General Public | |
3 | * License. See the file "COPYING" in the main directory of this archive | |
4 | * for more details. | |
5 | * | |
6 | * Copyright (C) 2008 Ralf Baechle (ralf@linux-mips.org) | |
7 | * Copyright (C) 2012 MIPS Technologies, Inc. All rights reserved. | |
8 | */ | |
39b8d525 | 9 | #include <linux/bitmap.h> |
fb8f7be1 | 10 | #include <linux/clocksource.h> |
39b8d525 | 11 | #include <linux/init.h> |
18743d27 | 12 | #include <linux/interrupt.h> |
fb8f7be1 | 13 | #include <linux/irq.h> |
41a83e06 | 14 | #include <linux/irqchip.h> |
4060bbe9 | 15 | #include <linux/irqchip/mips-gic.h> |
a7057270 | 16 | #include <linux/of_address.h> |
18743d27 | 17 | #include <linux/sched.h> |
631330f5 | 18 | #include <linux/smp.h> |
39b8d525 | 19 | |
a7057270 | 20 | #include <asm/mips-cm.h> |
98b67c37 SH |
21 | #include <asm/setup.h> |
22 | #include <asm/traps.h> | |
39b8d525 | 23 | |
a7057270 AB |
24 | #include <dt-bindings/interrupt-controller/mips-gic.h> |
25 | ||
ff86714f | 26 | unsigned int gic_present; |
98b67c37 | 27 | |
822350bc | 28 | struct gic_pcpu_mask { |
fbd55241 | 29 | DECLARE_BITMAP(pcpu_mask, GIC_MAX_INTRS); |
822350bc JD |
30 | }; |
31 | ||
2af70a96 QY |
32 | struct gic_irq_spec { |
33 | enum { | |
34 | GIC_DEVICE, | |
35 | GIC_IPI | |
36 | } type; | |
37 | ||
38 | union { | |
39 | struct cpumask *ipimask; | |
40 | unsigned int hwirq; | |
41 | }; | |
42 | }; | |
43 | ||
c0a9f72c | 44 | static unsigned long __gic_base_addr; |
2af70a96 | 45 | |
5f68fea0 | 46 | static void __iomem *gic_base; |
0b271f56 | 47 | static struct gic_pcpu_mask pcpu_masks[NR_CPUS]; |
95150ae8 | 48 | static DEFINE_SPINLOCK(gic_lock); |
c49581a4 | 49 | static struct irq_domain *gic_irq_domain; |
2af70a96 | 50 | static struct irq_domain *gic_ipi_domain; |
fbd55241 | 51 | static int gic_shared_intrs; |
e9de688d | 52 | static int gic_vpes; |
3263d085 | 53 | static unsigned int gic_cpu_pin; |
1b6af71a | 54 | static unsigned int timer_cpu_pin; |
4a6a3ea3 | 55 | static struct irq_chip gic_level_irq_controller, gic_edge_irq_controller; |
2af70a96 | 56 | DECLARE_BITMAP(ipi_resrv, GIC_MAX_INTRS); |
39b8d525 | 57 | |
18743d27 AB |
58 | static void __gic_irq_dispatch(void); |
59 | ||
c3f57f02 | 60 | static inline u32 gic_read32(unsigned int reg) |
5f68fea0 AB |
61 | { |
62 | return __raw_readl(gic_base + reg); | |
63 | } | |
64 | ||
c3f57f02 | 65 | static inline u64 gic_read64(unsigned int reg) |
5f68fea0 | 66 | { |
c3f57f02 | 67 | return __raw_readq(gic_base + reg); |
5f68fea0 AB |
68 | } |
69 | ||
c3f57f02 | 70 | static inline unsigned long gic_read(unsigned int reg) |
5f68fea0 | 71 | { |
c3f57f02 MC |
72 | if (!mips_cm_is64) |
73 | return gic_read32(reg); | |
74 | else | |
75 | return gic_read64(reg); | |
76 | } | |
77 | ||
78 | static inline void gic_write32(unsigned int reg, u32 val) | |
79 | { | |
80 | return __raw_writel(val, gic_base + reg); | |
81 | } | |
82 | ||
83 | static inline void gic_write64(unsigned int reg, u64 val) | |
84 | { | |
85 | return __raw_writeq(val, gic_base + reg); | |
86 | } | |
87 | ||
88 | static inline void gic_write(unsigned int reg, unsigned long val) | |
89 | { | |
90 | if (!mips_cm_is64) | |
91 | return gic_write32(reg, (u32)val); | |
92 | else | |
93 | return gic_write64(reg, (u64)val); | |
94 | } | |
95 | ||
96 | static inline void gic_update_bits(unsigned int reg, unsigned long mask, | |
97 | unsigned long val) | |
98 | { | |
99 | unsigned long regval; | |
5f68fea0 AB |
100 | |
101 | regval = gic_read(reg); | |
102 | regval &= ~mask; | |
103 | regval |= val; | |
104 | gic_write(reg, regval); | |
105 | } | |
106 | ||
107 | static inline void gic_reset_mask(unsigned int intr) | |
108 | { | |
109 | gic_write(GIC_REG(SHARED, GIC_SH_RMASK) + GIC_INTR_OFS(intr), | |
c3f57f02 | 110 | 1ul << GIC_INTR_BIT(intr)); |
5f68fea0 AB |
111 | } |
112 | ||
113 | static inline void gic_set_mask(unsigned int intr) | |
114 | { | |
115 | gic_write(GIC_REG(SHARED, GIC_SH_SMASK) + GIC_INTR_OFS(intr), | |
c3f57f02 | 116 | 1ul << GIC_INTR_BIT(intr)); |
5f68fea0 AB |
117 | } |
118 | ||
119 | static inline void gic_set_polarity(unsigned int intr, unsigned int pol) | |
120 | { | |
121 | gic_update_bits(GIC_REG(SHARED, GIC_SH_SET_POLARITY) + | |
c3f57f02 MC |
122 | GIC_INTR_OFS(intr), 1ul << GIC_INTR_BIT(intr), |
123 | (unsigned long)pol << GIC_INTR_BIT(intr)); | |
5f68fea0 AB |
124 | } |
125 | ||
126 | static inline void gic_set_trigger(unsigned int intr, unsigned int trig) | |
127 | { | |
128 | gic_update_bits(GIC_REG(SHARED, GIC_SH_SET_TRIGGER) + | |
c3f57f02 MC |
129 | GIC_INTR_OFS(intr), 1ul << GIC_INTR_BIT(intr), |
130 | (unsigned long)trig << GIC_INTR_BIT(intr)); | |
5f68fea0 AB |
131 | } |
132 | ||
133 | static inline void gic_set_dual_edge(unsigned int intr, unsigned int dual) | |
134 | { | |
135 | gic_update_bits(GIC_REG(SHARED, GIC_SH_SET_DUAL) + GIC_INTR_OFS(intr), | |
c3f57f02 MC |
136 | 1ul << GIC_INTR_BIT(intr), |
137 | (unsigned long)dual << GIC_INTR_BIT(intr)); | |
5f68fea0 AB |
138 | } |
139 | ||
140 | static inline void gic_map_to_pin(unsigned int intr, unsigned int pin) | |
141 | { | |
c3f57f02 MC |
142 | gic_write32(GIC_REG(SHARED, GIC_SH_INTR_MAP_TO_PIN_BASE) + |
143 | GIC_SH_MAP_TO_PIN(intr), GIC_MAP_TO_PIN_MSK | pin); | |
5f68fea0 AB |
144 | } |
145 | ||
146 | static inline void gic_map_to_vpe(unsigned int intr, unsigned int vpe) | |
147 | { | |
148 | gic_write(GIC_REG(SHARED, GIC_SH_INTR_MAP_TO_VPE_BASE) + | |
149 | GIC_SH_MAP_TO_VPE_REG_OFF(intr, vpe), | |
150 | GIC_SH_MAP_TO_VPE_REG_BIT(vpe)); | |
151 | } | |
152 | ||
a331ce63 | 153 | #ifdef CONFIG_CLKSRC_MIPS_GIC |
dfa762e1 SH |
154 | cycle_t gic_read_count(void) |
155 | { | |
156 | unsigned int hi, hi2, lo; | |
157 | ||
6f50c835 MC |
158 | if (mips_cm_is64) |
159 | return (cycle_t)gic_read(GIC_REG(SHARED, GIC_SH_COUNTER)); | |
160 | ||
dfa762e1 | 161 | do { |
c3f57f02 MC |
162 | hi = gic_read32(GIC_REG(SHARED, GIC_SH_COUNTER_63_32)); |
163 | lo = gic_read32(GIC_REG(SHARED, GIC_SH_COUNTER_31_00)); | |
164 | hi2 = gic_read32(GIC_REG(SHARED, GIC_SH_COUNTER_63_32)); | |
dfa762e1 SH |
165 | } while (hi2 != hi); |
166 | ||
167 | return (((cycle_t) hi) << 32) + lo; | |
168 | } | |
0ab2b7d0 | 169 | |
387904ff AB |
170 | unsigned int gic_get_count_width(void) |
171 | { | |
172 | unsigned int bits, config; | |
173 | ||
5f68fea0 | 174 | config = gic_read(GIC_REG(SHARED, GIC_SH_CONFIG)); |
387904ff AB |
175 | bits = 32 + 4 * ((config & GIC_SH_CONFIG_COUNTBITS_MSK) >> |
176 | GIC_SH_CONFIG_COUNTBITS_SHF); | |
177 | ||
178 | return bits; | |
179 | } | |
180 | ||
0ab2b7d0 RG |
181 | void gic_write_compare(cycle_t cnt) |
182 | { | |
6f50c835 MC |
183 | if (mips_cm_is64) { |
184 | gic_write(GIC_REG(VPE_LOCAL, GIC_VPE_COMPARE), cnt); | |
185 | } else { | |
186 | gic_write32(GIC_REG(VPE_LOCAL, GIC_VPE_COMPARE_HI), | |
187 | (int)(cnt >> 32)); | |
188 | gic_write32(GIC_REG(VPE_LOCAL, GIC_VPE_COMPARE_LO), | |
189 | (int)(cnt & 0xffffffff)); | |
190 | } | |
0ab2b7d0 RG |
191 | } |
192 | ||
414408d0 PB |
193 | void gic_write_cpu_compare(cycle_t cnt, int cpu) |
194 | { | |
195 | unsigned long flags; | |
196 | ||
197 | local_irq_save(flags); | |
198 | ||
5f68fea0 | 199 | gic_write(GIC_REG(VPE_LOCAL, GIC_VPE_OTHER_ADDR), cpu); |
6f50c835 MC |
200 | |
201 | if (mips_cm_is64) { | |
202 | gic_write(GIC_REG(VPE_OTHER, GIC_VPE_COMPARE), cnt); | |
203 | } else { | |
204 | gic_write32(GIC_REG(VPE_OTHER, GIC_VPE_COMPARE_HI), | |
205 | (int)(cnt >> 32)); | |
206 | gic_write32(GIC_REG(VPE_OTHER, GIC_VPE_COMPARE_LO), | |
207 | (int)(cnt & 0xffffffff)); | |
208 | } | |
414408d0 PB |
209 | |
210 | local_irq_restore(flags); | |
211 | } | |
212 | ||
0ab2b7d0 RG |
213 | cycle_t gic_read_compare(void) |
214 | { | |
215 | unsigned int hi, lo; | |
216 | ||
6f50c835 MC |
217 | if (mips_cm_is64) |
218 | return (cycle_t)gic_read(GIC_REG(VPE_LOCAL, GIC_VPE_COMPARE)); | |
219 | ||
c3f57f02 MC |
220 | hi = gic_read32(GIC_REG(VPE_LOCAL, GIC_VPE_COMPARE_HI)); |
221 | lo = gic_read32(GIC_REG(VPE_LOCAL, GIC_VPE_COMPARE_LO)); | |
0ab2b7d0 RG |
222 | |
223 | return (((cycle_t) hi) << 32) + lo; | |
224 | } | |
8fa4b930 MC |
225 | |
226 | void gic_start_count(void) | |
227 | { | |
228 | u32 gicconfig; | |
229 | ||
230 | /* Start the counter */ | |
231 | gicconfig = gic_read(GIC_REG(SHARED, GIC_SH_CONFIG)); | |
232 | gicconfig &= ~(1 << GIC_SH_CONFIG_COUNTSTOP_SHF); | |
233 | gic_write(GIC_REG(SHARED, GIC_SH_CONFIG), gicconfig); | |
234 | } | |
235 | ||
236 | void gic_stop_count(void) | |
237 | { | |
238 | u32 gicconfig; | |
239 | ||
240 | /* Stop the counter */ | |
241 | gicconfig = gic_read(GIC_REG(SHARED, GIC_SH_CONFIG)); | |
242 | gicconfig |= 1 << GIC_SH_CONFIG_COUNTSTOP_SHF; | |
243 | gic_write(GIC_REG(SHARED, GIC_SH_CONFIG), gicconfig); | |
244 | } | |
245 | ||
dfa762e1 SH |
246 | #endif |
247 | ||
e9de688d AB |
248 | static bool gic_local_irq_is_routable(int intr) |
249 | { | |
250 | u32 vpe_ctl; | |
251 | ||
252 | /* All local interrupts are routable in EIC mode. */ | |
253 | if (cpu_has_veic) | |
254 | return true; | |
255 | ||
c3f57f02 | 256 | vpe_ctl = gic_read32(GIC_REG(VPE_LOCAL, GIC_VPE_CTL)); |
e9de688d AB |
257 | switch (intr) { |
258 | case GIC_LOCAL_INT_TIMER: | |
259 | return vpe_ctl & GIC_VPE_CTL_TIMER_RTBL_MSK; | |
260 | case GIC_LOCAL_INT_PERFCTR: | |
261 | return vpe_ctl & GIC_VPE_CTL_PERFCNT_RTBL_MSK; | |
262 | case GIC_LOCAL_INT_FDC: | |
263 | return vpe_ctl & GIC_VPE_CTL_FDC_RTBL_MSK; | |
264 | case GIC_LOCAL_INT_SWINT0: | |
265 | case GIC_LOCAL_INT_SWINT1: | |
266 | return vpe_ctl & GIC_VPE_CTL_SWINT_RTBL_MSK; | |
267 | default: | |
268 | return true; | |
269 | } | |
270 | } | |
271 | ||
3263d085 | 272 | static void gic_bind_eic_interrupt(int irq, int set) |
98b67c37 SH |
273 | { |
274 | /* Convert irq vector # to hw int # */ | |
275 | irq -= GIC_PIN_TO_VEC_OFFSET; | |
276 | ||
277 | /* Set irq to use shadow set */ | |
5f68fea0 AB |
278 | gic_write(GIC_REG(VPE_LOCAL, GIC_VPE_EIC_SHADOW_SET_BASE) + |
279 | GIC_VPE_EIC_SS(irq), set); | |
98b67c37 SH |
280 | } |
281 | ||
39b8d525 RB |
282 | void gic_send_ipi(unsigned int intr) |
283 | { | |
53a7bc81 | 284 | gic_write(GIC_REG(SHARED, GIC_SH_WEDGE), GIC_SH_WEDGE_SET(intr)); |
39b8d525 RB |
285 | } |
286 | ||
e9de688d AB |
287 | int gic_get_c0_compare_int(void) |
288 | { | |
289 | if (!gic_local_irq_is_routable(GIC_LOCAL_INT_TIMER)) | |
290 | return MIPS_CPU_IRQ_BASE + cp0_compare_irq; | |
291 | return irq_create_mapping(gic_irq_domain, | |
292 | GIC_LOCAL_TO_HWIRQ(GIC_LOCAL_INT_TIMER)); | |
293 | } | |
294 | ||
295 | int gic_get_c0_perfcount_int(void) | |
296 | { | |
297 | if (!gic_local_irq_is_routable(GIC_LOCAL_INT_PERFCTR)) { | |
7e3e6cb2 | 298 | /* Is the performance counter shared with the timer? */ |
e9de688d AB |
299 | if (cp0_perfcount_irq < 0) |
300 | return -1; | |
301 | return MIPS_CPU_IRQ_BASE + cp0_perfcount_irq; | |
302 | } | |
303 | return irq_create_mapping(gic_irq_domain, | |
304 | GIC_LOCAL_TO_HWIRQ(GIC_LOCAL_INT_PERFCTR)); | |
305 | } | |
306 | ||
6429e2b6 JH |
307 | int gic_get_c0_fdc_int(void) |
308 | { | |
309 | if (!gic_local_irq_is_routable(GIC_LOCAL_INT_FDC)) { | |
310 | /* Is the FDC IRQ even present? */ | |
311 | if (cp0_fdc_irq < 0) | |
312 | return -1; | |
313 | return MIPS_CPU_IRQ_BASE + cp0_fdc_irq; | |
314 | } | |
315 | ||
6429e2b6 JH |
316 | return irq_create_mapping(gic_irq_domain, |
317 | GIC_LOCAL_TO_HWIRQ(GIC_LOCAL_INT_FDC)); | |
318 | } | |
319 | ||
c0a9f72c AS |
320 | int gic_get_usm_range(struct resource *gic_usm_res) |
321 | { | |
322 | if (!gic_present) | |
323 | return -1; | |
324 | ||
325 | gic_usm_res->start = __gic_base_addr + USM_VISIBLE_SECTION_OFS; | |
326 | gic_usm_res->end = gic_usm_res->start + (USM_VISIBLE_SECTION_SIZE - 1); | |
327 | ||
328 | return 0; | |
329 | } | |
330 | ||
1b3ed367 | 331 | static void gic_handle_shared_int(bool chained) |
39b8d525 | 332 | { |
c3f57f02 | 333 | unsigned int i, intr, virq, gic_reg_step = mips_cm_is64 ? 8 : 4; |
8f5ee79c | 334 | unsigned long *pcpu_mask; |
5f68fea0 | 335 | unsigned long pending_reg, intrmask_reg; |
8f5ee79c AB |
336 | DECLARE_BITMAP(pending, GIC_MAX_INTRS); |
337 | DECLARE_BITMAP(intrmask, GIC_MAX_INTRS); | |
39b8d525 RB |
338 | |
339 | /* Get per-cpu bitmaps */ | |
39b8d525 RB |
340 | pcpu_mask = pcpu_masks[smp_processor_id()].pcpu_mask; |
341 | ||
824f3f7f AB |
342 | pending_reg = GIC_REG(SHARED, GIC_SH_PEND); |
343 | intrmask_reg = GIC_REG(SHARED, GIC_SH_MASK); | |
39b8d525 | 344 | |
fbd55241 | 345 | for (i = 0; i < BITS_TO_LONGS(gic_shared_intrs); i++) { |
5f68fea0 AB |
346 | pending[i] = gic_read(pending_reg); |
347 | intrmask[i] = gic_read(intrmask_reg); | |
c3f57f02 MC |
348 | pending_reg += gic_reg_step; |
349 | intrmask_reg += gic_reg_step; | |
d77d5ac9 PB |
350 | |
351 | if (!config_enabled(CONFIG_64BIT) || mips_cm_is64) | |
352 | continue; | |
353 | ||
354 | pending[i] |= (u64)gic_read(pending_reg) << 32; | |
355 | intrmask[i] |= (u64)gic_read(intrmask_reg) << 32; | |
356 | pending_reg += gic_reg_step; | |
357 | intrmask_reg += gic_reg_step; | |
39b8d525 RB |
358 | } |
359 | ||
fbd55241 AB |
360 | bitmap_and(pending, pending, intrmask, gic_shared_intrs); |
361 | bitmap_and(pending, pending, pcpu_mask, gic_shared_intrs); | |
39b8d525 | 362 | |
d7eb4f2e QY |
363 | intr = find_first_bit(pending, gic_shared_intrs); |
364 | while (intr != gic_shared_intrs) { | |
365 | virq = irq_linear_revmap(gic_irq_domain, | |
366 | GIC_SHARED_TO_HWIRQ(intr)); | |
1b3ed367 RV |
367 | if (chained) |
368 | generic_handle_irq(virq); | |
369 | else | |
370 | do_IRQ(virq); | |
d7eb4f2e QY |
371 | |
372 | /* go to next pending bit */ | |
373 | bitmap_clear(pending, intr, 1); | |
374 | intr = find_first_bit(pending, gic_shared_intrs); | |
375 | } | |
39b8d525 RB |
376 | } |
377 | ||
161d049e | 378 | static void gic_mask_irq(struct irq_data *d) |
39b8d525 | 379 | { |
5f68fea0 | 380 | gic_reset_mask(GIC_HWIRQ_TO_SHARED(d->hwirq)); |
39b8d525 RB |
381 | } |
382 | ||
161d049e | 383 | static void gic_unmask_irq(struct irq_data *d) |
39b8d525 | 384 | { |
5f68fea0 | 385 | gic_set_mask(GIC_HWIRQ_TO_SHARED(d->hwirq)); |
39b8d525 RB |
386 | } |
387 | ||
5561c9e4 AB |
388 | static void gic_ack_irq(struct irq_data *d) |
389 | { | |
e9de688d | 390 | unsigned int irq = GIC_HWIRQ_TO_SHARED(d->hwirq); |
c49581a4 | 391 | |
53a7bc81 | 392 | gic_write(GIC_REG(SHARED, GIC_SH_WEDGE), GIC_SH_WEDGE_CLR(irq)); |
5561c9e4 AB |
393 | } |
394 | ||
95150ae8 AB |
395 | static int gic_set_type(struct irq_data *d, unsigned int type) |
396 | { | |
e9de688d | 397 | unsigned int irq = GIC_HWIRQ_TO_SHARED(d->hwirq); |
95150ae8 AB |
398 | unsigned long flags; |
399 | bool is_edge; | |
400 | ||
401 | spin_lock_irqsave(&gic_lock, flags); | |
402 | switch (type & IRQ_TYPE_SENSE_MASK) { | |
403 | case IRQ_TYPE_EDGE_FALLING: | |
5f68fea0 AB |
404 | gic_set_polarity(irq, GIC_POL_NEG); |
405 | gic_set_trigger(irq, GIC_TRIG_EDGE); | |
406 | gic_set_dual_edge(irq, GIC_TRIG_DUAL_DISABLE); | |
95150ae8 AB |
407 | is_edge = true; |
408 | break; | |
409 | case IRQ_TYPE_EDGE_RISING: | |
5f68fea0 AB |
410 | gic_set_polarity(irq, GIC_POL_POS); |
411 | gic_set_trigger(irq, GIC_TRIG_EDGE); | |
412 | gic_set_dual_edge(irq, GIC_TRIG_DUAL_DISABLE); | |
95150ae8 AB |
413 | is_edge = true; |
414 | break; | |
415 | case IRQ_TYPE_EDGE_BOTH: | |
416 | /* polarity is irrelevant in this case */ | |
5f68fea0 AB |
417 | gic_set_trigger(irq, GIC_TRIG_EDGE); |
418 | gic_set_dual_edge(irq, GIC_TRIG_DUAL_ENABLE); | |
95150ae8 AB |
419 | is_edge = true; |
420 | break; | |
421 | case IRQ_TYPE_LEVEL_LOW: | |
5f68fea0 AB |
422 | gic_set_polarity(irq, GIC_POL_NEG); |
423 | gic_set_trigger(irq, GIC_TRIG_LEVEL); | |
424 | gic_set_dual_edge(irq, GIC_TRIG_DUAL_DISABLE); | |
95150ae8 AB |
425 | is_edge = false; |
426 | break; | |
427 | case IRQ_TYPE_LEVEL_HIGH: | |
428 | default: | |
5f68fea0 AB |
429 | gic_set_polarity(irq, GIC_POL_POS); |
430 | gic_set_trigger(irq, GIC_TRIG_LEVEL); | |
431 | gic_set_dual_edge(irq, GIC_TRIG_DUAL_DISABLE); | |
95150ae8 AB |
432 | is_edge = false; |
433 | break; | |
434 | } | |
435 | ||
a595fc51 TG |
436 | if (is_edge) |
437 | irq_set_chip_handler_name_locked(d, &gic_edge_irq_controller, | |
438 | handle_edge_irq, NULL); | |
439 | else | |
440 | irq_set_chip_handler_name_locked(d, &gic_level_irq_controller, | |
441 | handle_level_irq, NULL); | |
95150ae8 | 442 | spin_unlock_irqrestore(&gic_lock, flags); |
39b8d525 | 443 | |
95150ae8 AB |
444 | return 0; |
445 | } | |
446 | ||
447 | #ifdef CONFIG_SMP | |
161d049e TG |
448 | static int gic_set_affinity(struct irq_data *d, const struct cpumask *cpumask, |
449 | bool force) | |
39b8d525 | 450 | { |
e9de688d | 451 | unsigned int irq = GIC_HWIRQ_TO_SHARED(d->hwirq); |
39b8d525 RB |
452 | cpumask_t tmp = CPU_MASK_NONE; |
453 | unsigned long flags; | |
454 | int i; | |
455 | ||
0de26520 | 456 | cpumask_and(&tmp, cpumask, cpu_online_mask); |
f9b531fe | 457 | if (cpumask_empty(&tmp)) |
14d160ab | 458 | return -EINVAL; |
39b8d525 RB |
459 | |
460 | /* Assumption : cpumask refers to a single CPU */ | |
461 | spin_lock_irqsave(&gic_lock, flags); | |
39b8d525 | 462 | |
c214c035 | 463 | /* Re-route this IRQ */ |
ab41f6c8 | 464 | gic_map_to_vpe(irq, mips_cm_vp_id(cpumask_first(&tmp))); |
c214c035 TW |
465 | |
466 | /* Update the pcpu_masks */ | |
467 | for (i = 0; i < NR_CPUS; i++) | |
468 | clear_bit(irq, pcpu_masks[i].pcpu_mask); | |
f9b531fe | 469 | set_bit(irq, pcpu_masks[cpumask_first(&tmp)].pcpu_mask); |
39b8d525 | 470 | |
72f86db4 | 471 | cpumask_copy(irq_data_get_affinity_mask(d), cpumask); |
39b8d525 RB |
472 | spin_unlock_irqrestore(&gic_lock, flags); |
473 | ||
161d049e | 474 | return IRQ_SET_MASK_OK_NOCOPY; |
39b8d525 RB |
475 | } |
476 | #endif | |
477 | ||
4a6a3ea3 AB |
478 | static struct irq_chip gic_level_irq_controller = { |
479 | .name = "MIPS GIC", | |
480 | .irq_mask = gic_mask_irq, | |
481 | .irq_unmask = gic_unmask_irq, | |
482 | .irq_set_type = gic_set_type, | |
483 | #ifdef CONFIG_SMP | |
484 | .irq_set_affinity = gic_set_affinity, | |
485 | #endif | |
486 | }; | |
487 | ||
488 | static struct irq_chip gic_edge_irq_controller = { | |
161d049e | 489 | .name = "MIPS GIC", |
5561c9e4 | 490 | .irq_ack = gic_ack_irq, |
161d049e | 491 | .irq_mask = gic_mask_irq, |
161d049e | 492 | .irq_unmask = gic_unmask_irq, |
95150ae8 | 493 | .irq_set_type = gic_set_type, |
39b8d525 | 494 | #ifdef CONFIG_SMP |
161d049e | 495 | .irq_set_affinity = gic_set_affinity, |
39b8d525 RB |
496 | #endif |
497 | }; | |
498 | ||
1b3ed367 | 499 | static void gic_handle_local_int(bool chained) |
e9de688d AB |
500 | { |
501 | unsigned long pending, masked; | |
d7eb4f2e | 502 | unsigned int intr, virq; |
e9de688d | 503 | |
c3f57f02 MC |
504 | pending = gic_read32(GIC_REG(VPE_LOCAL, GIC_VPE_PEND)); |
505 | masked = gic_read32(GIC_REG(VPE_LOCAL, GIC_VPE_MASK)); | |
e9de688d AB |
506 | |
507 | bitmap_and(&pending, &pending, &masked, GIC_NUM_LOCAL_INTRS); | |
508 | ||
d7eb4f2e QY |
509 | intr = find_first_bit(&pending, GIC_NUM_LOCAL_INTRS); |
510 | while (intr != GIC_NUM_LOCAL_INTRS) { | |
511 | virq = irq_linear_revmap(gic_irq_domain, | |
512 | GIC_LOCAL_TO_HWIRQ(intr)); | |
1b3ed367 RV |
513 | if (chained) |
514 | generic_handle_irq(virq); | |
515 | else | |
516 | do_IRQ(virq); | |
d7eb4f2e QY |
517 | |
518 | /* go to next pending bit */ | |
519 | bitmap_clear(&pending, intr, 1); | |
520 | intr = find_first_bit(&pending, GIC_NUM_LOCAL_INTRS); | |
521 | } | |
e9de688d AB |
522 | } |
523 | ||
524 | static void gic_mask_local_irq(struct irq_data *d) | |
525 | { | |
526 | int intr = GIC_HWIRQ_TO_LOCAL(d->hwirq); | |
527 | ||
c3f57f02 | 528 | gic_write32(GIC_REG(VPE_LOCAL, GIC_VPE_RMASK), 1 << intr); |
e9de688d AB |
529 | } |
530 | ||
531 | static void gic_unmask_local_irq(struct irq_data *d) | |
532 | { | |
533 | int intr = GIC_HWIRQ_TO_LOCAL(d->hwirq); | |
534 | ||
c3f57f02 | 535 | gic_write32(GIC_REG(VPE_LOCAL, GIC_VPE_SMASK), 1 << intr); |
e9de688d AB |
536 | } |
537 | ||
538 | static struct irq_chip gic_local_irq_controller = { | |
539 | .name = "MIPS GIC Local", | |
540 | .irq_mask = gic_mask_local_irq, | |
541 | .irq_unmask = gic_unmask_local_irq, | |
542 | }; | |
543 | ||
544 | static void gic_mask_local_irq_all_vpes(struct irq_data *d) | |
545 | { | |
546 | int intr = GIC_HWIRQ_TO_LOCAL(d->hwirq); | |
547 | int i; | |
548 | unsigned long flags; | |
549 | ||
550 | spin_lock_irqsave(&gic_lock, flags); | |
551 | for (i = 0; i < gic_vpes; i++) { | |
5f68fea0 | 552 | gic_write(GIC_REG(VPE_LOCAL, GIC_VPE_OTHER_ADDR), i); |
c3f57f02 | 553 | gic_write32(GIC_REG(VPE_OTHER, GIC_VPE_RMASK), 1 << intr); |
e9de688d AB |
554 | } |
555 | spin_unlock_irqrestore(&gic_lock, flags); | |
556 | } | |
557 | ||
558 | static void gic_unmask_local_irq_all_vpes(struct irq_data *d) | |
559 | { | |
560 | int intr = GIC_HWIRQ_TO_LOCAL(d->hwirq); | |
561 | int i; | |
562 | unsigned long flags; | |
563 | ||
564 | spin_lock_irqsave(&gic_lock, flags); | |
565 | for (i = 0; i < gic_vpes; i++) { | |
5f68fea0 | 566 | gic_write(GIC_REG(VPE_LOCAL, GIC_VPE_OTHER_ADDR), i); |
c3f57f02 | 567 | gic_write32(GIC_REG(VPE_OTHER, GIC_VPE_SMASK), 1 << intr); |
e9de688d AB |
568 | } |
569 | spin_unlock_irqrestore(&gic_lock, flags); | |
570 | } | |
571 | ||
572 | static struct irq_chip gic_all_vpes_local_irq_controller = { | |
573 | .name = "MIPS GIC Local", | |
574 | .irq_mask = gic_mask_local_irq_all_vpes, | |
575 | .irq_unmask = gic_unmask_local_irq_all_vpes, | |
576 | }; | |
577 | ||
18743d27 | 578 | static void __gic_irq_dispatch(void) |
39b8d525 | 579 | { |
1b3ed367 RV |
580 | gic_handle_local_int(false); |
581 | gic_handle_shared_int(false); | |
18743d27 | 582 | } |
39b8d525 | 583 | |
bd0b9ac4 | 584 | static void gic_irq_dispatch(struct irq_desc *desc) |
18743d27 | 585 | { |
1b3ed367 RV |
586 | gic_handle_local_int(true); |
587 | gic_handle_shared_int(true); | |
18743d27 AB |
588 | } |
589 | ||
590 | #ifdef CONFIG_MIPS_GIC_IPI | |
591 | static int gic_resched_int_base; | |
592 | static int gic_call_int_base; | |
593 | ||
594 | unsigned int plat_ipi_resched_int_xlate(unsigned int cpu) | |
595 | { | |
596 | return gic_resched_int_base + cpu; | |
597 | } | |
39b8d525 | 598 | |
18743d27 AB |
599 | unsigned int plat_ipi_call_int_xlate(unsigned int cpu) |
600 | { | |
601 | return gic_call_int_base + cpu; | |
602 | } | |
39b8d525 | 603 | |
18743d27 AB |
604 | static irqreturn_t ipi_resched_interrupt(int irq, void *dev_id) |
605 | { | |
606 | scheduler_ipi(); | |
607 | ||
608 | return IRQ_HANDLED; | |
609 | } | |
610 | ||
611 | static irqreturn_t ipi_call_interrupt(int irq, void *dev_id) | |
612 | { | |
4ace6139 | 613 | generic_smp_call_function_interrupt(); |
18743d27 AB |
614 | |
615 | return IRQ_HANDLED; | |
616 | } | |
b0a88ae5 | 617 | |
18743d27 AB |
618 | static struct irqaction irq_resched = { |
619 | .handler = ipi_resched_interrupt, | |
620 | .flags = IRQF_PERCPU, | |
621 | .name = "IPI resched" | |
622 | }; | |
623 | ||
624 | static struct irqaction irq_call = { | |
625 | .handler = ipi_call_interrupt, | |
626 | .flags = IRQF_PERCPU, | |
627 | .name = "IPI call" | |
628 | }; | |
629 | ||
630 | static __init void gic_ipi_init_one(unsigned int intr, int cpu, | |
631 | struct irqaction *action) | |
632 | { | |
e9de688d AB |
633 | int virq = irq_create_mapping(gic_irq_domain, |
634 | GIC_SHARED_TO_HWIRQ(intr)); | |
18743d27 AB |
635 | int i; |
636 | ||
ab41f6c8 | 637 | gic_map_to_vpe(intr, mips_cm_vp_id(cpu)); |
c49581a4 AB |
638 | for (i = 0; i < NR_CPUS; i++) |
639 | clear_bit(intr, pcpu_masks[i].pcpu_mask); | |
b0a88ae5 JD |
640 | set_bit(intr, pcpu_masks[cpu].pcpu_mask); |
641 | ||
18743d27 AB |
642 | irq_set_irq_type(virq, IRQ_TYPE_EDGE_RISING); |
643 | ||
644 | irq_set_handler(virq, handle_percpu_irq); | |
645 | setup_irq(virq, action); | |
39b8d525 RB |
646 | } |
647 | ||
18743d27 | 648 | static __init void gic_ipi_init(void) |
39b8d525 | 649 | { |
18743d27 AB |
650 | int i; |
651 | ||
652 | /* Use last 2 * NR_CPUS interrupts as IPIs */ | |
fbd55241 | 653 | gic_resched_int_base = gic_shared_intrs - nr_cpu_ids; |
18743d27 AB |
654 | gic_call_int_base = gic_resched_int_base - nr_cpu_ids; |
655 | ||
656 | for (i = 0; i < nr_cpu_ids; i++) { | |
657 | gic_ipi_init_one(gic_call_int_base + i, i, &irq_call); | |
658 | gic_ipi_init_one(gic_resched_int_base + i, i, &irq_resched); | |
659 | } | |
660 | } | |
661 | #else | |
662 | static inline void gic_ipi_init(void) | |
663 | { | |
664 | } | |
665 | #endif | |
666 | ||
e9de688d | 667 | static void __init gic_basic_init(void) |
18743d27 AB |
668 | { |
669 | unsigned int i; | |
98b67c37 SH |
670 | |
671 | board_bind_eic_interrupt = &gic_bind_eic_interrupt; | |
39b8d525 RB |
672 | |
673 | /* Setup defaults */ | |
fbd55241 | 674 | for (i = 0; i < gic_shared_intrs; i++) { |
5f68fea0 AB |
675 | gic_set_polarity(i, GIC_POL_POS); |
676 | gic_set_trigger(i, GIC_TRIG_LEVEL); | |
677 | gic_reset_mask(i); | |
39b8d525 RB |
678 | } |
679 | ||
e9de688d AB |
680 | for (i = 0; i < gic_vpes; i++) { |
681 | unsigned int j; | |
682 | ||
5f68fea0 | 683 | gic_write(GIC_REG(VPE_LOCAL, GIC_VPE_OTHER_ADDR), i); |
e9de688d AB |
684 | for (j = 0; j < GIC_NUM_LOCAL_INTRS; j++) { |
685 | if (!gic_local_irq_is_routable(j)) | |
686 | continue; | |
c3f57f02 | 687 | gic_write32(GIC_REG(VPE_OTHER, GIC_VPE_RMASK), 1 << j); |
e9de688d AB |
688 | } |
689 | } | |
39b8d525 RB |
690 | } |
691 | ||
e9de688d AB |
692 | static int gic_local_irq_domain_map(struct irq_domain *d, unsigned int virq, |
693 | irq_hw_number_t hw) | |
c49581a4 | 694 | { |
e9de688d AB |
695 | int intr = GIC_HWIRQ_TO_LOCAL(hw); |
696 | int ret = 0; | |
697 | int i; | |
698 | unsigned long flags; | |
699 | ||
700 | if (!gic_local_irq_is_routable(intr)) | |
701 | return -EPERM; | |
702 | ||
703 | /* | |
704 | * HACK: These are all really percpu interrupts, but the rest | |
705 | * of the MIPS kernel code does not use the percpu IRQ API for | |
706 | * the CP0 timer and performance counter interrupts. | |
707 | */ | |
b720fd8b JH |
708 | switch (intr) { |
709 | case GIC_LOCAL_INT_TIMER: | |
710 | case GIC_LOCAL_INT_PERFCTR: | |
711 | case GIC_LOCAL_INT_FDC: | |
712 | irq_set_chip_and_handler(virq, | |
713 | &gic_all_vpes_local_irq_controller, | |
714 | handle_percpu_irq); | |
715 | break; | |
716 | default: | |
e9de688d AB |
717 | irq_set_chip_and_handler(virq, |
718 | &gic_local_irq_controller, | |
719 | handle_percpu_devid_irq); | |
720 | irq_set_percpu_devid(virq); | |
b720fd8b | 721 | break; |
e9de688d AB |
722 | } |
723 | ||
724 | spin_lock_irqsave(&gic_lock, flags); | |
725 | for (i = 0; i < gic_vpes; i++) { | |
726 | u32 val = GIC_MAP_TO_PIN_MSK | gic_cpu_pin; | |
727 | ||
5f68fea0 | 728 | gic_write(GIC_REG(VPE_LOCAL, GIC_VPE_OTHER_ADDR), i); |
e9de688d AB |
729 | |
730 | switch (intr) { | |
731 | case GIC_LOCAL_INT_WD: | |
c3f57f02 | 732 | gic_write32(GIC_REG(VPE_OTHER, GIC_VPE_WD_MAP), val); |
e9de688d AB |
733 | break; |
734 | case GIC_LOCAL_INT_COMPARE: | |
c3f57f02 MC |
735 | gic_write32(GIC_REG(VPE_OTHER, GIC_VPE_COMPARE_MAP), |
736 | val); | |
e9de688d AB |
737 | break; |
738 | case GIC_LOCAL_INT_TIMER: | |
1b6af71a JH |
739 | /* CONFIG_MIPS_CMP workaround (see __gic_init) */ |
740 | val = GIC_MAP_TO_PIN_MSK | timer_cpu_pin; | |
c3f57f02 MC |
741 | gic_write32(GIC_REG(VPE_OTHER, GIC_VPE_TIMER_MAP), |
742 | val); | |
e9de688d AB |
743 | break; |
744 | case GIC_LOCAL_INT_PERFCTR: | |
c3f57f02 MC |
745 | gic_write32(GIC_REG(VPE_OTHER, GIC_VPE_PERFCTR_MAP), |
746 | val); | |
e9de688d AB |
747 | break; |
748 | case GIC_LOCAL_INT_SWINT0: | |
c3f57f02 MC |
749 | gic_write32(GIC_REG(VPE_OTHER, GIC_VPE_SWINT0_MAP), |
750 | val); | |
e9de688d AB |
751 | break; |
752 | case GIC_LOCAL_INT_SWINT1: | |
c3f57f02 MC |
753 | gic_write32(GIC_REG(VPE_OTHER, GIC_VPE_SWINT1_MAP), |
754 | val); | |
e9de688d AB |
755 | break; |
756 | case GIC_LOCAL_INT_FDC: | |
c3f57f02 | 757 | gic_write32(GIC_REG(VPE_OTHER, GIC_VPE_FDC_MAP), val); |
e9de688d AB |
758 | break; |
759 | default: | |
760 | pr_err("Invalid local IRQ %d\n", intr); | |
761 | ret = -EINVAL; | |
762 | break; | |
763 | } | |
764 | } | |
765 | spin_unlock_irqrestore(&gic_lock, flags); | |
766 | ||
767 | return ret; | |
768 | } | |
769 | ||
770 | static int gic_shared_irq_domain_map(struct irq_domain *d, unsigned int virq, | |
2af70a96 | 771 | irq_hw_number_t hw, unsigned int vpe) |
e9de688d AB |
772 | { |
773 | int intr = GIC_HWIRQ_TO_SHARED(hw); | |
c49581a4 AB |
774 | unsigned long flags; |
775 | ||
4a6a3ea3 AB |
776 | irq_set_chip_and_handler(virq, &gic_level_irq_controller, |
777 | handle_level_irq); | |
c49581a4 AB |
778 | |
779 | spin_lock_irqsave(&gic_lock, flags); | |
5f68fea0 | 780 | gic_map_to_pin(intr, gic_cpu_pin); |
2af70a96 QY |
781 | gic_map_to_vpe(intr, vpe); |
782 | set_bit(intr, pcpu_masks[vpe].pcpu_mask); | |
c49581a4 AB |
783 | spin_unlock_irqrestore(&gic_lock, flags); |
784 | ||
785 | return 0; | |
786 | } | |
787 | ||
e9de688d AB |
788 | static int gic_irq_domain_map(struct irq_domain *d, unsigned int virq, |
789 | irq_hw_number_t hw) | |
790 | { | |
791 | if (GIC_HWIRQ_TO_LOCAL(hw) < GIC_NUM_LOCAL_INTRS) | |
792 | return gic_local_irq_domain_map(d, virq, hw); | |
2af70a96 | 793 | return gic_shared_irq_domain_map(d, virq, hw, 0); |
e9de688d AB |
794 | } |
795 | ||
a7057270 AB |
796 | static int gic_irq_domain_xlate(struct irq_domain *d, struct device_node *ctrlr, |
797 | const u32 *intspec, unsigned int intsize, | |
798 | irq_hw_number_t *out_hwirq, | |
799 | unsigned int *out_type) | |
800 | { | |
801 | if (intsize != 3) | |
802 | return -EINVAL; | |
803 | ||
804 | if (intspec[0] == GIC_SHARED) | |
805 | *out_hwirq = GIC_SHARED_TO_HWIRQ(intspec[1]); | |
806 | else if (intspec[0] == GIC_LOCAL) | |
807 | *out_hwirq = GIC_LOCAL_TO_HWIRQ(intspec[1]); | |
808 | else | |
809 | return -EINVAL; | |
810 | *out_type = intspec[2] & IRQ_TYPE_SENSE_MASK; | |
811 | ||
812 | return 0; | |
813 | } | |
814 | ||
2af70a96 QY |
815 | static int gic_irq_domain_alloc(struct irq_domain *d, unsigned int virq, |
816 | unsigned int nr_irqs, void *arg) | |
817 | { | |
818 | struct gic_irq_spec *spec = arg; | |
819 | irq_hw_number_t hwirq, base_hwirq; | |
820 | int cpu, ret, i; | |
821 | ||
822 | if (spec->type == GIC_DEVICE) { | |
823 | /* verify that it doesn't conflict with an IPI irq */ | |
824 | if (test_bit(spec->hwirq, ipi_resrv)) | |
825 | return -EBUSY; | |
826 | } else { | |
827 | base_hwirq = find_first_bit(ipi_resrv, gic_shared_intrs); | |
828 | if (base_hwirq == gic_shared_intrs) { | |
829 | return -ENOMEM; | |
830 | } | |
831 | ||
832 | /* check that we have enough space */ | |
833 | for (i = base_hwirq; i < nr_irqs; i++) { | |
834 | if (!test_bit(i, ipi_resrv)) | |
835 | return -EBUSY; | |
836 | } | |
837 | bitmap_clear(ipi_resrv, base_hwirq, nr_irqs); | |
838 | ||
839 | /* map the hwirq for each cpu consecutively */ | |
840 | i = 0; | |
841 | for_each_cpu(cpu, spec->ipimask) { | |
842 | hwirq = GIC_SHARED_TO_HWIRQ(base_hwirq + i); | |
843 | ||
844 | ret = irq_domain_set_hwirq_and_chip(d, virq + i, hwirq, | |
845 | &gic_edge_irq_controller, | |
846 | NULL); | |
847 | if (ret) | |
848 | goto error; | |
849 | ||
850 | ret = gic_shared_irq_domain_map(d, virq + i, hwirq, cpu); | |
851 | if (ret) | |
852 | goto error; | |
853 | ||
854 | i++; | |
855 | } | |
856 | ||
857 | /* | |
858 | * tell the parent about the base hwirq we allocated so it can | |
859 | * set its own domain data | |
860 | */ | |
861 | spec->hwirq = base_hwirq; | |
862 | } | |
863 | ||
864 | return 0; | |
865 | error: | |
866 | bitmap_set(ipi_resrv, base_hwirq, nr_irqs); | |
867 | return ret; | |
868 | } | |
869 | ||
870 | void gic_irq_domain_free(struct irq_domain *d, unsigned int virq, | |
871 | unsigned int nr_irqs) | |
872 | { | |
873 | irq_hw_number_t base_hwirq; | |
874 | struct irq_data *data; | |
875 | ||
876 | data = irq_get_irq_data(virq); | |
877 | if (!data) | |
878 | return; | |
879 | ||
880 | base_hwirq = GIC_HWIRQ_TO_SHARED(irqd_to_hwirq(data)); | |
881 | bitmap_set(ipi_resrv, base_hwirq, nr_irqs); | |
882 | } | |
883 | ||
96009736 | 884 | static const struct irq_domain_ops gic_irq_domain_ops = { |
c49581a4 | 885 | .map = gic_irq_domain_map, |
a7057270 | 886 | .xlate = gic_irq_domain_xlate, |
2af70a96 QY |
887 | .alloc = gic_irq_domain_alloc, |
888 | .free = gic_irq_domain_free, | |
889 | }; | |
890 | ||
891 | static int gic_ipi_domain_xlate(struct irq_domain *d, struct device_node *ctrlr, | |
892 | const u32 *intspec, unsigned int intsize, | |
893 | irq_hw_number_t *out_hwirq, | |
894 | unsigned int *out_type) | |
895 | { | |
896 | /* | |
897 | * There's nothing to translate here. hwirq is dynamically allocated and | |
898 | * the irq type is always edge triggered. | |
899 | * */ | |
900 | *out_hwirq = 0; | |
901 | *out_type = IRQ_TYPE_EDGE_RISING; | |
902 | ||
903 | return 0; | |
904 | } | |
905 | ||
906 | static int gic_ipi_domain_alloc(struct irq_domain *d, unsigned int virq, | |
907 | unsigned int nr_irqs, void *arg) | |
908 | { | |
909 | struct cpumask *ipimask = arg; | |
910 | struct gic_irq_spec spec = { | |
911 | .type = GIC_IPI, | |
912 | .ipimask = ipimask | |
913 | }; | |
914 | int ret, i; | |
915 | ||
916 | ret = irq_domain_alloc_irqs_parent(d, virq, nr_irqs, &spec); | |
917 | if (ret) | |
918 | return ret; | |
919 | ||
920 | /* the parent should have set spec.hwirq to the base_hwirq it allocated */ | |
921 | for (i = 0; i < nr_irqs; i++) { | |
922 | ret = irq_domain_set_hwirq_and_chip(d, virq + i, | |
923 | GIC_SHARED_TO_HWIRQ(spec.hwirq + i), | |
924 | &gic_edge_irq_controller, | |
925 | NULL); | |
926 | if (ret) | |
927 | goto error; | |
928 | ||
929 | ret = irq_set_irq_type(virq + i, IRQ_TYPE_EDGE_RISING); | |
930 | if (ret) | |
931 | goto error; | |
932 | } | |
933 | ||
934 | return 0; | |
935 | error: | |
936 | irq_domain_free_irqs_parent(d, virq, nr_irqs); | |
937 | return ret; | |
938 | } | |
939 | ||
940 | void gic_ipi_domain_free(struct irq_domain *d, unsigned int virq, | |
941 | unsigned int nr_irqs) | |
942 | { | |
943 | irq_domain_free_irqs_parent(d, virq, nr_irqs); | |
944 | } | |
945 | ||
946 | int gic_ipi_domain_match(struct irq_domain *d, struct device_node *node, | |
947 | enum irq_domain_bus_token bus_token) | |
948 | { | |
949 | bool is_ipi; | |
950 | ||
951 | switch (bus_token) { | |
952 | case DOMAIN_BUS_IPI: | |
953 | is_ipi = d->bus_token == bus_token; | |
954 | return to_of_node(d->fwnode) == node && is_ipi; | |
955 | break; | |
956 | default: | |
957 | return 0; | |
958 | } | |
959 | } | |
960 | ||
961 | static struct irq_domain_ops gic_ipi_domain_ops = { | |
962 | .xlate = gic_ipi_domain_xlate, | |
963 | .alloc = gic_ipi_domain_alloc, | |
964 | .free = gic_ipi_domain_free, | |
965 | .match = gic_ipi_domain_match, | |
c49581a4 AB |
966 | }; |
967 | ||
a7057270 AB |
968 | static void __init __gic_init(unsigned long gic_base_addr, |
969 | unsigned long gic_addrspace_size, | |
970 | unsigned int cpu_vec, unsigned int irqbase, | |
971 | struct device_node *node) | |
39b8d525 RB |
972 | { |
973 | unsigned int gicconfig; | |
974 | ||
c0a9f72c AS |
975 | __gic_base_addr = gic_base_addr; |
976 | ||
5f68fea0 | 977 | gic_base = ioremap_nocache(gic_base_addr, gic_addrspace_size); |
39b8d525 | 978 | |
5f68fea0 | 979 | gicconfig = gic_read(GIC_REG(SHARED, GIC_SH_CONFIG)); |
fbd55241 | 980 | gic_shared_intrs = (gicconfig & GIC_SH_CONFIG_NUMINTRS_MSK) >> |
39b8d525 | 981 | GIC_SH_CONFIG_NUMINTRS_SHF; |
fbd55241 | 982 | gic_shared_intrs = ((gic_shared_intrs + 1) * 8); |
39b8d525 | 983 | |
e9de688d | 984 | gic_vpes = (gicconfig & GIC_SH_CONFIG_NUMVPES_MSK) >> |
39b8d525 | 985 | GIC_SH_CONFIG_NUMVPES_SHF; |
e9de688d | 986 | gic_vpes = gic_vpes + 1; |
39b8d525 | 987 | |
18743d27 AB |
988 | if (cpu_has_veic) { |
989 | /* Always use vector 1 in EIC mode */ | |
990 | gic_cpu_pin = 0; | |
1b6af71a | 991 | timer_cpu_pin = gic_cpu_pin; |
18743d27 AB |
992 | set_vi_handler(gic_cpu_pin + GIC_PIN_TO_VEC_OFFSET, |
993 | __gic_irq_dispatch); | |
994 | } else { | |
995 | gic_cpu_pin = cpu_vec - GIC_CPU_PIN_OFFSET; | |
996 | irq_set_chained_handler(MIPS_CPU_IRQ_BASE + cpu_vec, | |
997 | gic_irq_dispatch); | |
1b6af71a JH |
998 | /* |
999 | * With the CMP implementation of SMP (deprecated), other CPUs | |
1000 | * are started by the bootloader and put into a timer based | |
1001 | * waiting poll loop. We must not re-route those CPU's local | |
1002 | * timer interrupts as the wait instruction will never finish, | |
1003 | * so just handle whatever CPU interrupt it is routed to by | |
1004 | * default. | |
1005 | * | |
1006 | * This workaround should be removed when CMP support is | |
1007 | * dropped. | |
1008 | */ | |
1009 | if (IS_ENABLED(CONFIG_MIPS_CMP) && | |
1010 | gic_local_irq_is_routable(GIC_LOCAL_INT_TIMER)) { | |
c3f57f02 | 1011 | timer_cpu_pin = gic_read32(GIC_REG(VPE_LOCAL, |
1b6af71a JH |
1012 | GIC_VPE_TIMER_MAP)) & |
1013 | GIC_MAP_MSK; | |
1014 | irq_set_chained_handler(MIPS_CPU_IRQ_BASE + | |
1015 | GIC_CPU_PIN_OFFSET + | |
1016 | timer_cpu_pin, | |
1017 | gic_irq_dispatch); | |
1018 | } else { | |
1019 | timer_cpu_pin = gic_cpu_pin; | |
1020 | } | |
18743d27 AB |
1021 | } |
1022 | ||
a7057270 | 1023 | gic_irq_domain = irq_domain_add_simple(node, GIC_NUM_LOCAL_INTRS + |
e9de688d | 1024 | gic_shared_intrs, irqbase, |
c49581a4 AB |
1025 | &gic_irq_domain_ops, NULL); |
1026 | if (!gic_irq_domain) | |
1027 | panic("Failed to add GIC IRQ domain"); | |
0b271f56 | 1028 | |
2af70a96 QY |
1029 | gic_ipi_domain = irq_domain_add_hierarchy(gic_irq_domain, |
1030 | IRQ_DOMAIN_FLAG_IPI_PER_CPU, | |
1031 | GIC_NUM_LOCAL_INTRS + gic_shared_intrs, | |
1032 | node, &gic_ipi_domain_ops, NULL); | |
1033 | if (!gic_ipi_domain) | |
1034 | panic("Failed to add GIC IPI domain"); | |
1035 | ||
1036 | gic_ipi_domain->bus_token = DOMAIN_BUS_IPI; | |
1037 | ||
1038 | /* Make the last 2 * NR_CPUS available for IPIs */ | |
1039 | bitmap_set(ipi_resrv, gic_shared_intrs - 2 * NR_CPUS, 2 * NR_CPUS); | |
1040 | ||
e9de688d | 1041 | gic_basic_init(); |
18743d27 AB |
1042 | |
1043 | gic_ipi_init(); | |
39b8d525 | 1044 | } |
a7057270 AB |
1045 | |
1046 | void __init gic_init(unsigned long gic_base_addr, | |
1047 | unsigned long gic_addrspace_size, | |
1048 | unsigned int cpu_vec, unsigned int irqbase) | |
1049 | { | |
1050 | __gic_init(gic_base_addr, gic_addrspace_size, cpu_vec, irqbase, NULL); | |
1051 | } | |
1052 | ||
1053 | static int __init gic_of_init(struct device_node *node, | |
1054 | struct device_node *parent) | |
1055 | { | |
1056 | struct resource res; | |
1057 | unsigned int cpu_vec, i = 0, reserved = 0; | |
1058 | phys_addr_t gic_base; | |
1059 | size_t gic_len; | |
1060 | ||
1061 | /* Find the first available CPU vector. */ | |
1062 | while (!of_property_read_u32_index(node, "mti,reserved-cpu-vectors", | |
1063 | i++, &cpu_vec)) | |
1064 | reserved |= BIT(cpu_vec); | |
1065 | for (cpu_vec = 2; cpu_vec < 8; cpu_vec++) { | |
1066 | if (!(reserved & BIT(cpu_vec))) | |
1067 | break; | |
1068 | } | |
1069 | if (cpu_vec == 8) { | |
1070 | pr_err("No CPU vectors available for GIC\n"); | |
1071 | return -ENODEV; | |
1072 | } | |
1073 | ||
1074 | if (of_address_to_resource(node, 0, &res)) { | |
1075 | /* | |
1076 | * Probe the CM for the GIC base address if not specified | |
1077 | * in the device-tree. | |
1078 | */ | |
1079 | if (mips_cm_present()) { | |
1080 | gic_base = read_gcr_gic_base() & | |
1081 | ~CM_GCR_GIC_BASE_GICEN_MSK; | |
1082 | gic_len = 0x20000; | |
1083 | } else { | |
1084 | pr_err("Failed to get GIC memory range\n"); | |
1085 | return -ENODEV; | |
1086 | } | |
1087 | } else { | |
1088 | gic_base = res.start; | |
1089 | gic_len = resource_size(&res); | |
1090 | } | |
1091 | ||
1092 | if (mips_cm_present()) | |
1093 | write_gcr_gic_base(gic_base | CM_GCR_GIC_BASE_GICEN_MSK); | |
1094 | gic_present = true; | |
1095 | ||
1096 | __gic_init(gic_base, gic_len, cpu_vec, 0, node); | |
1097 | ||
1098 | return 0; | |
1099 | } | |
1100 | IRQCHIP_DECLARE(mips_gic, "mti,gic", gic_of_init); |