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Commit | Line | Data |
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2299c49d SH |
1 | /* |
2 | * This file is subject to the terms and conditions of the GNU General Public | |
3 | * License. See the file "COPYING" in the main directory of this archive | |
4 | * for more details. | |
5 | * | |
6 | * Copyright (C) 2008 Ralf Baechle (ralf@linux-mips.org) | |
7 | * Copyright (C) 2012 MIPS Technologies, Inc. All rights reserved. | |
8 | */ | |
39b8d525 | 9 | #include <linux/bitmap.h> |
fb8f7be1 | 10 | #include <linux/clocksource.h> |
39b8d525 | 11 | #include <linux/init.h> |
18743d27 | 12 | #include <linux/interrupt.h> |
fb8f7be1 | 13 | #include <linux/irq.h> |
41a83e06 | 14 | #include <linux/irqchip.h> |
4060bbe9 | 15 | #include <linux/irqchip/mips-gic.h> |
a7057270 | 16 | #include <linux/of_address.h> |
18743d27 | 17 | #include <linux/sched.h> |
631330f5 | 18 | #include <linux/smp.h> |
39b8d525 | 19 | |
a7057270 | 20 | #include <asm/mips-cm.h> |
98b67c37 SH |
21 | #include <asm/setup.h> |
22 | #include <asm/traps.h> | |
39b8d525 | 23 | |
a7057270 AB |
24 | #include <dt-bindings/interrupt-controller/mips-gic.h> |
25 | ||
ff86714f | 26 | unsigned int gic_present; |
98b67c37 | 27 | |
822350bc | 28 | struct gic_pcpu_mask { |
fbd55241 | 29 | DECLARE_BITMAP(pcpu_mask, GIC_MAX_INTRS); |
822350bc JD |
30 | }; |
31 | ||
5f68fea0 | 32 | static void __iomem *gic_base; |
0b271f56 | 33 | static struct gic_pcpu_mask pcpu_masks[NR_CPUS]; |
95150ae8 | 34 | static DEFINE_SPINLOCK(gic_lock); |
c49581a4 | 35 | static struct irq_domain *gic_irq_domain; |
fbd55241 | 36 | static int gic_shared_intrs; |
e9de688d | 37 | static int gic_vpes; |
3263d085 | 38 | static unsigned int gic_cpu_pin; |
1b6af71a | 39 | static unsigned int timer_cpu_pin; |
4a6a3ea3 | 40 | static struct irq_chip gic_level_irq_controller, gic_edge_irq_controller; |
39b8d525 | 41 | |
18743d27 AB |
42 | static void __gic_irq_dispatch(void); |
43 | ||
5f68fea0 AB |
44 | static inline unsigned int gic_read(unsigned int reg) |
45 | { | |
46 | return __raw_readl(gic_base + reg); | |
47 | } | |
48 | ||
49 | static inline void gic_write(unsigned int reg, unsigned int val) | |
50 | { | |
51 | __raw_writel(val, gic_base + reg); | |
52 | } | |
53 | ||
54 | static inline void gic_update_bits(unsigned int reg, unsigned int mask, | |
55 | unsigned int val) | |
56 | { | |
57 | unsigned int regval; | |
58 | ||
59 | regval = gic_read(reg); | |
60 | regval &= ~mask; | |
61 | regval |= val; | |
62 | gic_write(reg, regval); | |
63 | } | |
64 | ||
65 | static inline void gic_reset_mask(unsigned int intr) | |
66 | { | |
67 | gic_write(GIC_REG(SHARED, GIC_SH_RMASK) + GIC_INTR_OFS(intr), | |
68 | 1 << GIC_INTR_BIT(intr)); | |
69 | } | |
70 | ||
71 | static inline void gic_set_mask(unsigned int intr) | |
72 | { | |
73 | gic_write(GIC_REG(SHARED, GIC_SH_SMASK) + GIC_INTR_OFS(intr), | |
74 | 1 << GIC_INTR_BIT(intr)); | |
75 | } | |
76 | ||
77 | static inline void gic_set_polarity(unsigned int intr, unsigned int pol) | |
78 | { | |
79 | gic_update_bits(GIC_REG(SHARED, GIC_SH_SET_POLARITY) + | |
80 | GIC_INTR_OFS(intr), 1 << GIC_INTR_BIT(intr), | |
81 | pol << GIC_INTR_BIT(intr)); | |
82 | } | |
83 | ||
84 | static inline void gic_set_trigger(unsigned int intr, unsigned int trig) | |
85 | { | |
86 | gic_update_bits(GIC_REG(SHARED, GIC_SH_SET_TRIGGER) + | |
87 | GIC_INTR_OFS(intr), 1 << GIC_INTR_BIT(intr), | |
88 | trig << GIC_INTR_BIT(intr)); | |
89 | } | |
90 | ||
91 | static inline void gic_set_dual_edge(unsigned int intr, unsigned int dual) | |
92 | { | |
93 | gic_update_bits(GIC_REG(SHARED, GIC_SH_SET_DUAL) + GIC_INTR_OFS(intr), | |
94 | 1 << GIC_INTR_BIT(intr), | |
95 | dual << GIC_INTR_BIT(intr)); | |
96 | } | |
97 | ||
98 | static inline void gic_map_to_pin(unsigned int intr, unsigned int pin) | |
99 | { | |
100 | gic_write(GIC_REG(SHARED, GIC_SH_INTR_MAP_TO_PIN_BASE) + | |
101 | GIC_SH_MAP_TO_PIN(intr), GIC_MAP_TO_PIN_MSK | pin); | |
102 | } | |
103 | ||
104 | static inline void gic_map_to_vpe(unsigned int intr, unsigned int vpe) | |
105 | { | |
106 | gic_write(GIC_REG(SHARED, GIC_SH_INTR_MAP_TO_VPE_BASE) + | |
107 | GIC_SH_MAP_TO_VPE_REG_OFF(intr, vpe), | |
108 | GIC_SH_MAP_TO_VPE_REG_BIT(vpe)); | |
109 | } | |
110 | ||
a331ce63 | 111 | #ifdef CONFIG_CLKSRC_MIPS_GIC |
dfa762e1 SH |
112 | cycle_t gic_read_count(void) |
113 | { | |
114 | unsigned int hi, hi2, lo; | |
115 | ||
116 | do { | |
5f68fea0 AB |
117 | hi = gic_read(GIC_REG(SHARED, GIC_SH_COUNTER_63_32)); |
118 | lo = gic_read(GIC_REG(SHARED, GIC_SH_COUNTER_31_00)); | |
119 | hi2 = gic_read(GIC_REG(SHARED, GIC_SH_COUNTER_63_32)); | |
dfa762e1 SH |
120 | } while (hi2 != hi); |
121 | ||
122 | return (((cycle_t) hi) << 32) + lo; | |
123 | } | |
0ab2b7d0 | 124 | |
387904ff AB |
125 | unsigned int gic_get_count_width(void) |
126 | { | |
127 | unsigned int bits, config; | |
128 | ||
5f68fea0 | 129 | config = gic_read(GIC_REG(SHARED, GIC_SH_CONFIG)); |
387904ff AB |
130 | bits = 32 + 4 * ((config & GIC_SH_CONFIG_COUNTBITS_MSK) >> |
131 | GIC_SH_CONFIG_COUNTBITS_SHF); | |
132 | ||
133 | return bits; | |
134 | } | |
135 | ||
0ab2b7d0 RG |
136 | void gic_write_compare(cycle_t cnt) |
137 | { | |
5f68fea0 | 138 | gic_write(GIC_REG(VPE_LOCAL, GIC_VPE_COMPARE_HI), |
0ab2b7d0 | 139 | (int)(cnt >> 32)); |
5f68fea0 | 140 | gic_write(GIC_REG(VPE_LOCAL, GIC_VPE_COMPARE_LO), |
0ab2b7d0 RG |
141 | (int)(cnt & 0xffffffff)); |
142 | } | |
143 | ||
414408d0 PB |
144 | void gic_write_cpu_compare(cycle_t cnt, int cpu) |
145 | { | |
146 | unsigned long flags; | |
147 | ||
148 | local_irq_save(flags); | |
149 | ||
5f68fea0 AB |
150 | gic_write(GIC_REG(VPE_LOCAL, GIC_VPE_OTHER_ADDR), cpu); |
151 | gic_write(GIC_REG(VPE_OTHER, GIC_VPE_COMPARE_HI), | |
414408d0 | 152 | (int)(cnt >> 32)); |
5f68fea0 | 153 | gic_write(GIC_REG(VPE_OTHER, GIC_VPE_COMPARE_LO), |
414408d0 PB |
154 | (int)(cnt & 0xffffffff)); |
155 | ||
156 | local_irq_restore(flags); | |
157 | } | |
158 | ||
0ab2b7d0 RG |
159 | cycle_t gic_read_compare(void) |
160 | { | |
161 | unsigned int hi, lo; | |
162 | ||
5f68fea0 AB |
163 | hi = gic_read(GIC_REG(VPE_LOCAL, GIC_VPE_COMPARE_HI)); |
164 | lo = gic_read(GIC_REG(VPE_LOCAL, GIC_VPE_COMPARE_LO)); | |
0ab2b7d0 RG |
165 | |
166 | return (((cycle_t) hi) << 32) + lo; | |
167 | } | |
8fa4b930 MC |
168 | |
169 | void gic_start_count(void) | |
170 | { | |
171 | u32 gicconfig; | |
172 | ||
173 | /* Start the counter */ | |
174 | gicconfig = gic_read(GIC_REG(SHARED, GIC_SH_CONFIG)); | |
175 | gicconfig &= ~(1 << GIC_SH_CONFIG_COUNTSTOP_SHF); | |
176 | gic_write(GIC_REG(SHARED, GIC_SH_CONFIG), gicconfig); | |
177 | } | |
178 | ||
179 | void gic_stop_count(void) | |
180 | { | |
181 | u32 gicconfig; | |
182 | ||
183 | /* Stop the counter */ | |
184 | gicconfig = gic_read(GIC_REG(SHARED, GIC_SH_CONFIG)); | |
185 | gicconfig |= 1 << GIC_SH_CONFIG_COUNTSTOP_SHF; | |
186 | gic_write(GIC_REG(SHARED, GIC_SH_CONFIG), gicconfig); | |
187 | } | |
188 | ||
dfa762e1 SH |
189 | #endif |
190 | ||
e9de688d AB |
191 | static bool gic_local_irq_is_routable(int intr) |
192 | { | |
193 | u32 vpe_ctl; | |
194 | ||
195 | /* All local interrupts are routable in EIC mode. */ | |
196 | if (cpu_has_veic) | |
197 | return true; | |
198 | ||
5f68fea0 | 199 | vpe_ctl = gic_read(GIC_REG(VPE_LOCAL, GIC_VPE_CTL)); |
e9de688d AB |
200 | switch (intr) { |
201 | case GIC_LOCAL_INT_TIMER: | |
202 | return vpe_ctl & GIC_VPE_CTL_TIMER_RTBL_MSK; | |
203 | case GIC_LOCAL_INT_PERFCTR: | |
204 | return vpe_ctl & GIC_VPE_CTL_PERFCNT_RTBL_MSK; | |
205 | case GIC_LOCAL_INT_FDC: | |
206 | return vpe_ctl & GIC_VPE_CTL_FDC_RTBL_MSK; | |
207 | case GIC_LOCAL_INT_SWINT0: | |
208 | case GIC_LOCAL_INT_SWINT1: | |
209 | return vpe_ctl & GIC_VPE_CTL_SWINT_RTBL_MSK; | |
210 | default: | |
211 | return true; | |
212 | } | |
213 | } | |
214 | ||
3263d085 | 215 | static void gic_bind_eic_interrupt(int irq, int set) |
98b67c37 SH |
216 | { |
217 | /* Convert irq vector # to hw int # */ | |
218 | irq -= GIC_PIN_TO_VEC_OFFSET; | |
219 | ||
220 | /* Set irq to use shadow set */ | |
5f68fea0 AB |
221 | gic_write(GIC_REG(VPE_LOCAL, GIC_VPE_EIC_SHADOW_SET_BASE) + |
222 | GIC_VPE_EIC_SS(irq), set); | |
98b67c37 SH |
223 | } |
224 | ||
39b8d525 RB |
225 | void gic_send_ipi(unsigned int intr) |
226 | { | |
53a7bc81 | 227 | gic_write(GIC_REG(SHARED, GIC_SH_WEDGE), GIC_SH_WEDGE_SET(intr)); |
39b8d525 RB |
228 | } |
229 | ||
e9de688d AB |
230 | int gic_get_c0_compare_int(void) |
231 | { | |
232 | if (!gic_local_irq_is_routable(GIC_LOCAL_INT_TIMER)) | |
233 | return MIPS_CPU_IRQ_BASE + cp0_compare_irq; | |
234 | return irq_create_mapping(gic_irq_domain, | |
235 | GIC_LOCAL_TO_HWIRQ(GIC_LOCAL_INT_TIMER)); | |
236 | } | |
237 | ||
238 | int gic_get_c0_perfcount_int(void) | |
239 | { | |
240 | if (!gic_local_irq_is_routable(GIC_LOCAL_INT_PERFCTR)) { | |
7e3e6cb2 | 241 | /* Is the performance counter shared with the timer? */ |
e9de688d AB |
242 | if (cp0_perfcount_irq < 0) |
243 | return -1; | |
244 | return MIPS_CPU_IRQ_BASE + cp0_perfcount_irq; | |
245 | } | |
246 | return irq_create_mapping(gic_irq_domain, | |
247 | GIC_LOCAL_TO_HWIRQ(GIC_LOCAL_INT_PERFCTR)); | |
248 | } | |
249 | ||
6429e2b6 JH |
250 | int gic_get_c0_fdc_int(void) |
251 | { | |
252 | if (!gic_local_irq_is_routable(GIC_LOCAL_INT_FDC)) { | |
253 | /* Is the FDC IRQ even present? */ | |
254 | if (cp0_fdc_irq < 0) | |
255 | return -1; | |
256 | return MIPS_CPU_IRQ_BASE + cp0_fdc_irq; | |
257 | } | |
258 | ||
6429e2b6 JH |
259 | return irq_create_mapping(gic_irq_domain, |
260 | GIC_LOCAL_TO_HWIRQ(GIC_LOCAL_INT_FDC)); | |
261 | } | |
262 | ||
1b3ed367 | 263 | static void gic_handle_shared_int(bool chained) |
39b8d525 | 264 | { |
d7eb4f2e | 265 | unsigned int i, intr, virq; |
8f5ee79c | 266 | unsigned long *pcpu_mask; |
5f68fea0 | 267 | unsigned long pending_reg, intrmask_reg; |
8f5ee79c AB |
268 | DECLARE_BITMAP(pending, GIC_MAX_INTRS); |
269 | DECLARE_BITMAP(intrmask, GIC_MAX_INTRS); | |
39b8d525 RB |
270 | |
271 | /* Get per-cpu bitmaps */ | |
39b8d525 RB |
272 | pcpu_mask = pcpu_masks[smp_processor_id()].pcpu_mask; |
273 | ||
824f3f7f AB |
274 | pending_reg = GIC_REG(SHARED, GIC_SH_PEND); |
275 | intrmask_reg = GIC_REG(SHARED, GIC_SH_MASK); | |
39b8d525 | 276 | |
fbd55241 | 277 | for (i = 0; i < BITS_TO_LONGS(gic_shared_intrs); i++) { |
5f68fea0 AB |
278 | pending[i] = gic_read(pending_reg); |
279 | intrmask[i] = gic_read(intrmask_reg); | |
280 | pending_reg += 0x4; | |
281 | intrmask_reg += 0x4; | |
39b8d525 RB |
282 | } |
283 | ||
fbd55241 AB |
284 | bitmap_and(pending, pending, intrmask, gic_shared_intrs); |
285 | bitmap_and(pending, pending, pcpu_mask, gic_shared_intrs); | |
39b8d525 | 286 | |
d7eb4f2e QY |
287 | intr = find_first_bit(pending, gic_shared_intrs); |
288 | while (intr != gic_shared_intrs) { | |
289 | virq = irq_linear_revmap(gic_irq_domain, | |
290 | GIC_SHARED_TO_HWIRQ(intr)); | |
1b3ed367 RV |
291 | if (chained) |
292 | generic_handle_irq(virq); | |
293 | else | |
294 | do_IRQ(virq); | |
d7eb4f2e QY |
295 | |
296 | /* go to next pending bit */ | |
297 | bitmap_clear(pending, intr, 1); | |
298 | intr = find_first_bit(pending, gic_shared_intrs); | |
299 | } | |
39b8d525 RB |
300 | } |
301 | ||
161d049e | 302 | static void gic_mask_irq(struct irq_data *d) |
39b8d525 | 303 | { |
5f68fea0 | 304 | gic_reset_mask(GIC_HWIRQ_TO_SHARED(d->hwirq)); |
39b8d525 RB |
305 | } |
306 | ||
161d049e | 307 | static void gic_unmask_irq(struct irq_data *d) |
39b8d525 | 308 | { |
5f68fea0 | 309 | gic_set_mask(GIC_HWIRQ_TO_SHARED(d->hwirq)); |
39b8d525 RB |
310 | } |
311 | ||
5561c9e4 AB |
312 | static void gic_ack_irq(struct irq_data *d) |
313 | { | |
e9de688d | 314 | unsigned int irq = GIC_HWIRQ_TO_SHARED(d->hwirq); |
c49581a4 | 315 | |
53a7bc81 | 316 | gic_write(GIC_REG(SHARED, GIC_SH_WEDGE), GIC_SH_WEDGE_CLR(irq)); |
5561c9e4 AB |
317 | } |
318 | ||
95150ae8 AB |
319 | static int gic_set_type(struct irq_data *d, unsigned int type) |
320 | { | |
e9de688d | 321 | unsigned int irq = GIC_HWIRQ_TO_SHARED(d->hwirq); |
95150ae8 AB |
322 | unsigned long flags; |
323 | bool is_edge; | |
324 | ||
325 | spin_lock_irqsave(&gic_lock, flags); | |
326 | switch (type & IRQ_TYPE_SENSE_MASK) { | |
327 | case IRQ_TYPE_EDGE_FALLING: | |
5f68fea0 AB |
328 | gic_set_polarity(irq, GIC_POL_NEG); |
329 | gic_set_trigger(irq, GIC_TRIG_EDGE); | |
330 | gic_set_dual_edge(irq, GIC_TRIG_DUAL_DISABLE); | |
95150ae8 AB |
331 | is_edge = true; |
332 | break; | |
333 | case IRQ_TYPE_EDGE_RISING: | |
5f68fea0 AB |
334 | gic_set_polarity(irq, GIC_POL_POS); |
335 | gic_set_trigger(irq, GIC_TRIG_EDGE); | |
336 | gic_set_dual_edge(irq, GIC_TRIG_DUAL_DISABLE); | |
95150ae8 AB |
337 | is_edge = true; |
338 | break; | |
339 | case IRQ_TYPE_EDGE_BOTH: | |
340 | /* polarity is irrelevant in this case */ | |
5f68fea0 AB |
341 | gic_set_trigger(irq, GIC_TRIG_EDGE); |
342 | gic_set_dual_edge(irq, GIC_TRIG_DUAL_ENABLE); | |
95150ae8 AB |
343 | is_edge = true; |
344 | break; | |
345 | case IRQ_TYPE_LEVEL_LOW: | |
5f68fea0 AB |
346 | gic_set_polarity(irq, GIC_POL_NEG); |
347 | gic_set_trigger(irq, GIC_TRIG_LEVEL); | |
348 | gic_set_dual_edge(irq, GIC_TRIG_DUAL_DISABLE); | |
95150ae8 AB |
349 | is_edge = false; |
350 | break; | |
351 | case IRQ_TYPE_LEVEL_HIGH: | |
352 | default: | |
5f68fea0 AB |
353 | gic_set_polarity(irq, GIC_POL_POS); |
354 | gic_set_trigger(irq, GIC_TRIG_LEVEL); | |
355 | gic_set_dual_edge(irq, GIC_TRIG_DUAL_DISABLE); | |
95150ae8 AB |
356 | is_edge = false; |
357 | break; | |
358 | } | |
359 | ||
a595fc51 TG |
360 | if (is_edge) |
361 | irq_set_chip_handler_name_locked(d, &gic_edge_irq_controller, | |
362 | handle_edge_irq, NULL); | |
363 | else | |
364 | irq_set_chip_handler_name_locked(d, &gic_level_irq_controller, | |
365 | handle_level_irq, NULL); | |
95150ae8 | 366 | spin_unlock_irqrestore(&gic_lock, flags); |
39b8d525 | 367 | |
95150ae8 AB |
368 | return 0; |
369 | } | |
370 | ||
371 | #ifdef CONFIG_SMP | |
161d049e TG |
372 | static int gic_set_affinity(struct irq_data *d, const struct cpumask *cpumask, |
373 | bool force) | |
39b8d525 | 374 | { |
e9de688d | 375 | unsigned int irq = GIC_HWIRQ_TO_SHARED(d->hwirq); |
39b8d525 RB |
376 | cpumask_t tmp = CPU_MASK_NONE; |
377 | unsigned long flags; | |
378 | int i; | |
379 | ||
0de26520 | 380 | cpumask_and(&tmp, cpumask, cpu_online_mask); |
f9b531fe | 381 | if (cpumask_empty(&tmp)) |
14d160ab | 382 | return -EINVAL; |
39b8d525 RB |
383 | |
384 | /* Assumption : cpumask refers to a single CPU */ | |
385 | spin_lock_irqsave(&gic_lock, flags); | |
39b8d525 | 386 | |
c214c035 | 387 | /* Re-route this IRQ */ |
f9b531fe | 388 | gic_map_to_vpe(irq, cpumask_first(&tmp)); |
c214c035 TW |
389 | |
390 | /* Update the pcpu_masks */ | |
391 | for (i = 0; i < NR_CPUS; i++) | |
392 | clear_bit(irq, pcpu_masks[i].pcpu_mask); | |
f9b531fe | 393 | set_bit(irq, pcpu_masks[cpumask_first(&tmp)].pcpu_mask); |
39b8d525 | 394 | |
72f86db4 | 395 | cpumask_copy(irq_data_get_affinity_mask(d), cpumask); |
39b8d525 RB |
396 | spin_unlock_irqrestore(&gic_lock, flags); |
397 | ||
161d049e | 398 | return IRQ_SET_MASK_OK_NOCOPY; |
39b8d525 RB |
399 | } |
400 | #endif | |
401 | ||
4a6a3ea3 AB |
402 | static struct irq_chip gic_level_irq_controller = { |
403 | .name = "MIPS GIC", | |
404 | .irq_mask = gic_mask_irq, | |
405 | .irq_unmask = gic_unmask_irq, | |
406 | .irq_set_type = gic_set_type, | |
407 | #ifdef CONFIG_SMP | |
408 | .irq_set_affinity = gic_set_affinity, | |
409 | #endif | |
410 | }; | |
411 | ||
412 | static struct irq_chip gic_edge_irq_controller = { | |
161d049e | 413 | .name = "MIPS GIC", |
5561c9e4 | 414 | .irq_ack = gic_ack_irq, |
161d049e | 415 | .irq_mask = gic_mask_irq, |
161d049e | 416 | .irq_unmask = gic_unmask_irq, |
95150ae8 | 417 | .irq_set_type = gic_set_type, |
39b8d525 | 418 | #ifdef CONFIG_SMP |
161d049e | 419 | .irq_set_affinity = gic_set_affinity, |
39b8d525 RB |
420 | #endif |
421 | }; | |
422 | ||
1b3ed367 | 423 | static void gic_handle_local_int(bool chained) |
e9de688d AB |
424 | { |
425 | unsigned long pending, masked; | |
d7eb4f2e | 426 | unsigned int intr, virq; |
e9de688d | 427 | |
5f68fea0 AB |
428 | pending = gic_read(GIC_REG(VPE_LOCAL, GIC_VPE_PEND)); |
429 | masked = gic_read(GIC_REG(VPE_LOCAL, GIC_VPE_MASK)); | |
e9de688d AB |
430 | |
431 | bitmap_and(&pending, &pending, &masked, GIC_NUM_LOCAL_INTRS); | |
432 | ||
d7eb4f2e QY |
433 | intr = find_first_bit(&pending, GIC_NUM_LOCAL_INTRS); |
434 | while (intr != GIC_NUM_LOCAL_INTRS) { | |
435 | virq = irq_linear_revmap(gic_irq_domain, | |
436 | GIC_LOCAL_TO_HWIRQ(intr)); | |
1b3ed367 RV |
437 | if (chained) |
438 | generic_handle_irq(virq); | |
439 | else | |
440 | do_IRQ(virq); | |
d7eb4f2e QY |
441 | |
442 | /* go to next pending bit */ | |
443 | bitmap_clear(&pending, intr, 1); | |
444 | intr = find_first_bit(&pending, GIC_NUM_LOCAL_INTRS); | |
445 | } | |
e9de688d AB |
446 | } |
447 | ||
448 | static void gic_mask_local_irq(struct irq_data *d) | |
449 | { | |
450 | int intr = GIC_HWIRQ_TO_LOCAL(d->hwirq); | |
451 | ||
5f68fea0 | 452 | gic_write(GIC_REG(VPE_LOCAL, GIC_VPE_RMASK), 1 << intr); |
e9de688d AB |
453 | } |
454 | ||
455 | static void gic_unmask_local_irq(struct irq_data *d) | |
456 | { | |
457 | int intr = GIC_HWIRQ_TO_LOCAL(d->hwirq); | |
458 | ||
5f68fea0 | 459 | gic_write(GIC_REG(VPE_LOCAL, GIC_VPE_SMASK), 1 << intr); |
e9de688d AB |
460 | } |
461 | ||
462 | static struct irq_chip gic_local_irq_controller = { | |
463 | .name = "MIPS GIC Local", | |
464 | .irq_mask = gic_mask_local_irq, | |
465 | .irq_unmask = gic_unmask_local_irq, | |
466 | }; | |
467 | ||
468 | static void gic_mask_local_irq_all_vpes(struct irq_data *d) | |
469 | { | |
470 | int intr = GIC_HWIRQ_TO_LOCAL(d->hwirq); | |
471 | int i; | |
472 | unsigned long flags; | |
473 | ||
474 | spin_lock_irqsave(&gic_lock, flags); | |
475 | for (i = 0; i < gic_vpes; i++) { | |
5f68fea0 AB |
476 | gic_write(GIC_REG(VPE_LOCAL, GIC_VPE_OTHER_ADDR), i); |
477 | gic_write(GIC_REG(VPE_OTHER, GIC_VPE_RMASK), 1 << intr); | |
e9de688d AB |
478 | } |
479 | spin_unlock_irqrestore(&gic_lock, flags); | |
480 | } | |
481 | ||
482 | static void gic_unmask_local_irq_all_vpes(struct irq_data *d) | |
483 | { | |
484 | int intr = GIC_HWIRQ_TO_LOCAL(d->hwirq); | |
485 | int i; | |
486 | unsigned long flags; | |
487 | ||
488 | spin_lock_irqsave(&gic_lock, flags); | |
489 | for (i = 0; i < gic_vpes; i++) { | |
5f68fea0 AB |
490 | gic_write(GIC_REG(VPE_LOCAL, GIC_VPE_OTHER_ADDR), i); |
491 | gic_write(GIC_REG(VPE_OTHER, GIC_VPE_SMASK), 1 << intr); | |
e9de688d AB |
492 | } |
493 | spin_unlock_irqrestore(&gic_lock, flags); | |
494 | } | |
495 | ||
496 | static struct irq_chip gic_all_vpes_local_irq_controller = { | |
497 | .name = "MIPS GIC Local", | |
498 | .irq_mask = gic_mask_local_irq_all_vpes, | |
499 | .irq_unmask = gic_unmask_local_irq_all_vpes, | |
500 | }; | |
501 | ||
18743d27 | 502 | static void __gic_irq_dispatch(void) |
39b8d525 | 503 | { |
1b3ed367 RV |
504 | gic_handle_local_int(false); |
505 | gic_handle_shared_int(false); | |
18743d27 | 506 | } |
39b8d525 | 507 | |
18743d27 AB |
508 | static void gic_irq_dispatch(unsigned int irq, struct irq_desc *desc) |
509 | { | |
1b3ed367 RV |
510 | gic_handle_local_int(true); |
511 | gic_handle_shared_int(true); | |
18743d27 AB |
512 | } |
513 | ||
514 | #ifdef CONFIG_MIPS_GIC_IPI | |
515 | static int gic_resched_int_base; | |
516 | static int gic_call_int_base; | |
517 | ||
518 | unsigned int plat_ipi_resched_int_xlate(unsigned int cpu) | |
519 | { | |
520 | return gic_resched_int_base + cpu; | |
521 | } | |
39b8d525 | 522 | |
18743d27 AB |
523 | unsigned int plat_ipi_call_int_xlate(unsigned int cpu) |
524 | { | |
525 | return gic_call_int_base + cpu; | |
526 | } | |
39b8d525 | 527 | |
18743d27 AB |
528 | static irqreturn_t ipi_resched_interrupt(int irq, void *dev_id) |
529 | { | |
530 | scheduler_ipi(); | |
531 | ||
532 | return IRQ_HANDLED; | |
533 | } | |
534 | ||
535 | static irqreturn_t ipi_call_interrupt(int irq, void *dev_id) | |
536 | { | |
4ace6139 | 537 | generic_smp_call_function_interrupt(); |
18743d27 AB |
538 | |
539 | return IRQ_HANDLED; | |
540 | } | |
b0a88ae5 | 541 | |
18743d27 AB |
542 | static struct irqaction irq_resched = { |
543 | .handler = ipi_resched_interrupt, | |
544 | .flags = IRQF_PERCPU, | |
545 | .name = "IPI resched" | |
546 | }; | |
547 | ||
548 | static struct irqaction irq_call = { | |
549 | .handler = ipi_call_interrupt, | |
550 | .flags = IRQF_PERCPU, | |
551 | .name = "IPI call" | |
552 | }; | |
553 | ||
554 | static __init void gic_ipi_init_one(unsigned int intr, int cpu, | |
555 | struct irqaction *action) | |
556 | { | |
e9de688d AB |
557 | int virq = irq_create_mapping(gic_irq_domain, |
558 | GIC_SHARED_TO_HWIRQ(intr)); | |
18743d27 AB |
559 | int i; |
560 | ||
5f68fea0 | 561 | gic_map_to_vpe(intr, cpu); |
c49581a4 AB |
562 | for (i = 0; i < NR_CPUS; i++) |
563 | clear_bit(intr, pcpu_masks[i].pcpu_mask); | |
b0a88ae5 JD |
564 | set_bit(intr, pcpu_masks[cpu].pcpu_mask); |
565 | ||
18743d27 AB |
566 | irq_set_irq_type(virq, IRQ_TYPE_EDGE_RISING); |
567 | ||
568 | irq_set_handler(virq, handle_percpu_irq); | |
569 | setup_irq(virq, action); | |
39b8d525 RB |
570 | } |
571 | ||
18743d27 | 572 | static __init void gic_ipi_init(void) |
39b8d525 | 573 | { |
18743d27 AB |
574 | int i; |
575 | ||
576 | /* Use last 2 * NR_CPUS interrupts as IPIs */ | |
fbd55241 | 577 | gic_resched_int_base = gic_shared_intrs - nr_cpu_ids; |
18743d27 AB |
578 | gic_call_int_base = gic_resched_int_base - nr_cpu_ids; |
579 | ||
580 | for (i = 0; i < nr_cpu_ids; i++) { | |
581 | gic_ipi_init_one(gic_call_int_base + i, i, &irq_call); | |
582 | gic_ipi_init_one(gic_resched_int_base + i, i, &irq_resched); | |
583 | } | |
584 | } | |
585 | #else | |
586 | static inline void gic_ipi_init(void) | |
587 | { | |
588 | } | |
589 | #endif | |
590 | ||
e9de688d | 591 | static void __init gic_basic_init(void) |
18743d27 AB |
592 | { |
593 | unsigned int i; | |
98b67c37 SH |
594 | |
595 | board_bind_eic_interrupt = &gic_bind_eic_interrupt; | |
39b8d525 RB |
596 | |
597 | /* Setup defaults */ | |
fbd55241 | 598 | for (i = 0; i < gic_shared_intrs; i++) { |
5f68fea0 AB |
599 | gic_set_polarity(i, GIC_POL_POS); |
600 | gic_set_trigger(i, GIC_TRIG_LEVEL); | |
601 | gic_reset_mask(i); | |
39b8d525 RB |
602 | } |
603 | ||
e9de688d AB |
604 | for (i = 0; i < gic_vpes; i++) { |
605 | unsigned int j; | |
606 | ||
5f68fea0 | 607 | gic_write(GIC_REG(VPE_LOCAL, GIC_VPE_OTHER_ADDR), i); |
e9de688d AB |
608 | for (j = 0; j < GIC_NUM_LOCAL_INTRS; j++) { |
609 | if (!gic_local_irq_is_routable(j)) | |
610 | continue; | |
5f68fea0 | 611 | gic_write(GIC_REG(VPE_OTHER, GIC_VPE_RMASK), 1 << j); |
e9de688d AB |
612 | } |
613 | } | |
39b8d525 RB |
614 | } |
615 | ||
e9de688d AB |
616 | static int gic_local_irq_domain_map(struct irq_domain *d, unsigned int virq, |
617 | irq_hw_number_t hw) | |
c49581a4 | 618 | { |
e9de688d AB |
619 | int intr = GIC_HWIRQ_TO_LOCAL(hw); |
620 | int ret = 0; | |
621 | int i; | |
622 | unsigned long flags; | |
623 | ||
624 | if (!gic_local_irq_is_routable(intr)) | |
625 | return -EPERM; | |
626 | ||
627 | /* | |
628 | * HACK: These are all really percpu interrupts, but the rest | |
629 | * of the MIPS kernel code does not use the percpu IRQ API for | |
630 | * the CP0 timer and performance counter interrupts. | |
631 | */ | |
b720fd8b JH |
632 | switch (intr) { |
633 | case GIC_LOCAL_INT_TIMER: | |
634 | case GIC_LOCAL_INT_PERFCTR: | |
635 | case GIC_LOCAL_INT_FDC: | |
636 | irq_set_chip_and_handler(virq, | |
637 | &gic_all_vpes_local_irq_controller, | |
638 | handle_percpu_irq); | |
639 | break; | |
640 | default: | |
e9de688d AB |
641 | irq_set_chip_and_handler(virq, |
642 | &gic_local_irq_controller, | |
643 | handle_percpu_devid_irq); | |
644 | irq_set_percpu_devid(virq); | |
b720fd8b | 645 | break; |
e9de688d AB |
646 | } |
647 | ||
648 | spin_lock_irqsave(&gic_lock, flags); | |
649 | for (i = 0; i < gic_vpes; i++) { | |
650 | u32 val = GIC_MAP_TO_PIN_MSK | gic_cpu_pin; | |
651 | ||
5f68fea0 | 652 | gic_write(GIC_REG(VPE_LOCAL, GIC_VPE_OTHER_ADDR), i); |
e9de688d AB |
653 | |
654 | switch (intr) { | |
655 | case GIC_LOCAL_INT_WD: | |
5f68fea0 | 656 | gic_write(GIC_REG(VPE_OTHER, GIC_VPE_WD_MAP), val); |
e9de688d AB |
657 | break; |
658 | case GIC_LOCAL_INT_COMPARE: | |
5f68fea0 | 659 | gic_write(GIC_REG(VPE_OTHER, GIC_VPE_COMPARE_MAP), val); |
e9de688d AB |
660 | break; |
661 | case GIC_LOCAL_INT_TIMER: | |
1b6af71a JH |
662 | /* CONFIG_MIPS_CMP workaround (see __gic_init) */ |
663 | val = GIC_MAP_TO_PIN_MSK | timer_cpu_pin; | |
5f68fea0 | 664 | gic_write(GIC_REG(VPE_OTHER, GIC_VPE_TIMER_MAP), val); |
e9de688d AB |
665 | break; |
666 | case GIC_LOCAL_INT_PERFCTR: | |
5f68fea0 | 667 | gic_write(GIC_REG(VPE_OTHER, GIC_VPE_PERFCTR_MAP), val); |
e9de688d AB |
668 | break; |
669 | case GIC_LOCAL_INT_SWINT0: | |
5f68fea0 | 670 | gic_write(GIC_REG(VPE_OTHER, GIC_VPE_SWINT0_MAP), val); |
e9de688d AB |
671 | break; |
672 | case GIC_LOCAL_INT_SWINT1: | |
5f68fea0 | 673 | gic_write(GIC_REG(VPE_OTHER, GIC_VPE_SWINT1_MAP), val); |
e9de688d AB |
674 | break; |
675 | case GIC_LOCAL_INT_FDC: | |
5f68fea0 | 676 | gic_write(GIC_REG(VPE_OTHER, GIC_VPE_FDC_MAP), val); |
e9de688d AB |
677 | break; |
678 | default: | |
679 | pr_err("Invalid local IRQ %d\n", intr); | |
680 | ret = -EINVAL; | |
681 | break; | |
682 | } | |
683 | } | |
684 | spin_unlock_irqrestore(&gic_lock, flags); | |
685 | ||
686 | return ret; | |
687 | } | |
688 | ||
689 | static int gic_shared_irq_domain_map(struct irq_domain *d, unsigned int virq, | |
690 | irq_hw_number_t hw) | |
691 | { | |
692 | int intr = GIC_HWIRQ_TO_SHARED(hw); | |
c49581a4 AB |
693 | unsigned long flags; |
694 | ||
4a6a3ea3 AB |
695 | irq_set_chip_and_handler(virq, &gic_level_irq_controller, |
696 | handle_level_irq); | |
c49581a4 AB |
697 | |
698 | spin_lock_irqsave(&gic_lock, flags); | |
5f68fea0 | 699 | gic_map_to_pin(intr, gic_cpu_pin); |
c49581a4 | 700 | /* Map to VPE 0 by default */ |
5f68fea0 | 701 | gic_map_to_vpe(intr, 0); |
e9de688d | 702 | set_bit(intr, pcpu_masks[0].pcpu_mask); |
c49581a4 AB |
703 | spin_unlock_irqrestore(&gic_lock, flags); |
704 | ||
705 | return 0; | |
706 | } | |
707 | ||
e9de688d AB |
708 | static int gic_irq_domain_map(struct irq_domain *d, unsigned int virq, |
709 | irq_hw_number_t hw) | |
710 | { | |
711 | if (GIC_HWIRQ_TO_LOCAL(hw) < GIC_NUM_LOCAL_INTRS) | |
712 | return gic_local_irq_domain_map(d, virq, hw); | |
713 | return gic_shared_irq_domain_map(d, virq, hw); | |
714 | } | |
715 | ||
a7057270 AB |
716 | static int gic_irq_domain_xlate(struct irq_domain *d, struct device_node *ctrlr, |
717 | const u32 *intspec, unsigned int intsize, | |
718 | irq_hw_number_t *out_hwirq, | |
719 | unsigned int *out_type) | |
720 | { | |
721 | if (intsize != 3) | |
722 | return -EINVAL; | |
723 | ||
724 | if (intspec[0] == GIC_SHARED) | |
725 | *out_hwirq = GIC_SHARED_TO_HWIRQ(intspec[1]); | |
726 | else if (intspec[0] == GIC_LOCAL) | |
727 | *out_hwirq = GIC_LOCAL_TO_HWIRQ(intspec[1]); | |
728 | else | |
729 | return -EINVAL; | |
730 | *out_type = intspec[2] & IRQ_TYPE_SENSE_MASK; | |
731 | ||
732 | return 0; | |
733 | } | |
734 | ||
96009736 | 735 | static const struct irq_domain_ops gic_irq_domain_ops = { |
c49581a4 | 736 | .map = gic_irq_domain_map, |
a7057270 | 737 | .xlate = gic_irq_domain_xlate, |
c49581a4 AB |
738 | }; |
739 | ||
a7057270 AB |
740 | static void __init __gic_init(unsigned long gic_base_addr, |
741 | unsigned long gic_addrspace_size, | |
742 | unsigned int cpu_vec, unsigned int irqbase, | |
743 | struct device_node *node) | |
39b8d525 RB |
744 | { |
745 | unsigned int gicconfig; | |
746 | ||
5f68fea0 | 747 | gic_base = ioremap_nocache(gic_base_addr, gic_addrspace_size); |
39b8d525 | 748 | |
5f68fea0 | 749 | gicconfig = gic_read(GIC_REG(SHARED, GIC_SH_CONFIG)); |
fbd55241 | 750 | gic_shared_intrs = (gicconfig & GIC_SH_CONFIG_NUMINTRS_MSK) >> |
39b8d525 | 751 | GIC_SH_CONFIG_NUMINTRS_SHF; |
fbd55241 | 752 | gic_shared_intrs = ((gic_shared_intrs + 1) * 8); |
39b8d525 | 753 | |
e9de688d | 754 | gic_vpes = (gicconfig & GIC_SH_CONFIG_NUMVPES_MSK) >> |
39b8d525 | 755 | GIC_SH_CONFIG_NUMVPES_SHF; |
e9de688d | 756 | gic_vpes = gic_vpes + 1; |
39b8d525 | 757 | |
18743d27 AB |
758 | if (cpu_has_veic) { |
759 | /* Always use vector 1 in EIC mode */ | |
760 | gic_cpu_pin = 0; | |
1b6af71a | 761 | timer_cpu_pin = gic_cpu_pin; |
18743d27 AB |
762 | set_vi_handler(gic_cpu_pin + GIC_PIN_TO_VEC_OFFSET, |
763 | __gic_irq_dispatch); | |
764 | } else { | |
765 | gic_cpu_pin = cpu_vec - GIC_CPU_PIN_OFFSET; | |
766 | irq_set_chained_handler(MIPS_CPU_IRQ_BASE + cpu_vec, | |
767 | gic_irq_dispatch); | |
1b6af71a JH |
768 | /* |
769 | * With the CMP implementation of SMP (deprecated), other CPUs | |
770 | * are started by the bootloader and put into a timer based | |
771 | * waiting poll loop. We must not re-route those CPU's local | |
772 | * timer interrupts as the wait instruction will never finish, | |
773 | * so just handle whatever CPU interrupt it is routed to by | |
774 | * default. | |
775 | * | |
776 | * This workaround should be removed when CMP support is | |
777 | * dropped. | |
778 | */ | |
779 | if (IS_ENABLED(CONFIG_MIPS_CMP) && | |
780 | gic_local_irq_is_routable(GIC_LOCAL_INT_TIMER)) { | |
781 | timer_cpu_pin = gic_read(GIC_REG(VPE_LOCAL, | |
782 | GIC_VPE_TIMER_MAP)) & | |
783 | GIC_MAP_MSK; | |
784 | irq_set_chained_handler(MIPS_CPU_IRQ_BASE + | |
785 | GIC_CPU_PIN_OFFSET + | |
786 | timer_cpu_pin, | |
787 | gic_irq_dispatch); | |
788 | } else { | |
789 | timer_cpu_pin = gic_cpu_pin; | |
790 | } | |
18743d27 AB |
791 | } |
792 | ||
a7057270 | 793 | gic_irq_domain = irq_domain_add_simple(node, GIC_NUM_LOCAL_INTRS + |
e9de688d | 794 | gic_shared_intrs, irqbase, |
c49581a4 AB |
795 | &gic_irq_domain_ops, NULL); |
796 | if (!gic_irq_domain) | |
797 | panic("Failed to add GIC IRQ domain"); | |
0b271f56 | 798 | |
e9de688d | 799 | gic_basic_init(); |
18743d27 AB |
800 | |
801 | gic_ipi_init(); | |
39b8d525 | 802 | } |
a7057270 AB |
803 | |
804 | void __init gic_init(unsigned long gic_base_addr, | |
805 | unsigned long gic_addrspace_size, | |
806 | unsigned int cpu_vec, unsigned int irqbase) | |
807 | { | |
808 | __gic_init(gic_base_addr, gic_addrspace_size, cpu_vec, irqbase, NULL); | |
809 | } | |
810 | ||
811 | static int __init gic_of_init(struct device_node *node, | |
812 | struct device_node *parent) | |
813 | { | |
814 | struct resource res; | |
815 | unsigned int cpu_vec, i = 0, reserved = 0; | |
816 | phys_addr_t gic_base; | |
817 | size_t gic_len; | |
818 | ||
819 | /* Find the first available CPU vector. */ | |
820 | while (!of_property_read_u32_index(node, "mti,reserved-cpu-vectors", | |
821 | i++, &cpu_vec)) | |
822 | reserved |= BIT(cpu_vec); | |
823 | for (cpu_vec = 2; cpu_vec < 8; cpu_vec++) { | |
824 | if (!(reserved & BIT(cpu_vec))) | |
825 | break; | |
826 | } | |
827 | if (cpu_vec == 8) { | |
828 | pr_err("No CPU vectors available for GIC\n"); | |
829 | return -ENODEV; | |
830 | } | |
831 | ||
832 | if (of_address_to_resource(node, 0, &res)) { | |
833 | /* | |
834 | * Probe the CM for the GIC base address if not specified | |
835 | * in the device-tree. | |
836 | */ | |
837 | if (mips_cm_present()) { | |
838 | gic_base = read_gcr_gic_base() & | |
839 | ~CM_GCR_GIC_BASE_GICEN_MSK; | |
840 | gic_len = 0x20000; | |
841 | } else { | |
842 | pr_err("Failed to get GIC memory range\n"); | |
843 | return -ENODEV; | |
844 | } | |
845 | } else { | |
846 | gic_base = res.start; | |
847 | gic_len = resource_size(&res); | |
848 | } | |
849 | ||
850 | if (mips_cm_present()) | |
851 | write_gcr_gic_base(gic_base | CM_GCR_GIC_BASE_GICEN_MSK); | |
852 | gic_present = true; | |
853 | ||
854 | __gic_init(gic_base, gic_len, cpu_vec, 0, node); | |
855 | ||
856 | return 0; | |
857 | } | |
858 | IRQCHIP_DECLARE(mips_gic, "mti,gic", gic_of_init); |