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Commit | Line | Data |
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2299c49d SH |
1 | /* |
2 | * This file is subject to the terms and conditions of the GNU General Public | |
3 | * License. See the file "COPYING" in the main directory of this archive | |
4 | * for more details. | |
5 | * | |
6 | * Copyright (C) 2008 Ralf Baechle (ralf@linux-mips.org) | |
7 | * Copyright (C) 2012 MIPS Technologies, Inc. All rights reserved. | |
8 | */ | |
39b8d525 | 9 | #include <linux/bitmap.h> |
fb8f7be1 | 10 | #include <linux/clocksource.h> |
39b8d525 | 11 | #include <linux/init.h> |
18743d27 | 12 | #include <linux/interrupt.h> |
fb8f7be1 | 13 | #include <linux/irq.h> |
4060bbe9 | 14 | #include <linux/irqchip/mips-gic.h> |
a7057270 | 15 | #include <linux/of_address.h> |
18743d27 | 16 | #include <linux/sched.h> |
631330f5 | 17 | #include <linux/smp.h> |
39b8d525 | 18 | |
a7057270 | 19 | #include <asm/mips-cm.h> |
98b67c37 SH |
20 | #include <asm/setup.h> |
21 | #include <asm/traps.h> | |
39b8d525 | 22 | |
a7057270 AB |
23 | #include <dt-bindings/interrupt-controller/mips-gic.h> |
24 | ||
25 | #include "irqchip.h" | |
26 | ||
ff86714f | 27 | unsigned int gic_present; |
98b67c37 | 28 | |
822350bc | 29 | struct gic_pcpu_mask { |
fbd55241 | 30 | DECLARE_BITMAP(pcpu_mask, GIC_MAX_INTRS); |
822350bc JD |
31 | }; |
32 | ||
5f68fea0 | 33 | static void __iomem *gic_base; |
0b271f56 | 34 | static struct gic_pcpu_mask pcpu_masks[NR_CPUS]; |
95150ae8 | 35 | static DEFINE_SPINLOCK(gic_lock); |
c49581a4 | 36 | static struct irq_domain *gic_irq_domain; |
fbd55241 | 37 | static int gic_shared_intrs; |
e9de688d | 38 | static int gic_vpes; |
3263d085 | 39 | static unsigned int gic_cpu_pin; |
1b6af71a | 40 | static unsigned int timer_cpu_pin; |
4a6a3ea3 | 41 | static struct irq_chip gic_level_irq_controller, gic_edge_irq_controller; |
39b8d525 | 42 | |
18743d27 AB |
43 | static void __gic_irq_dispatch(void); |
44 | ||
c3f57f02 | 45 | static inline u32 gic_read32(unsigned int reg) |
5f68fea0 AB |
46 | { |
47 | return __raw_readl(gic_base + reg); | |
48 | } | |
49 | ||
c3f57f02 | 50 | static inline u64 gic_read64(unsigned int reg) |
5f68fea0 | 51 | { |
c3f57f02 | 52 | return __raw_readq(gic_base + reg); |
5f68fea0 AB |
53 | } |
54 | ||
c3f57f02 | 55 | static inline unsigned long gic_read(unsigned int reg) |
5f68fea0 | 56 | { |
c3f57f02 MC |
57 | if (!mips_cm_is64) |
58 | return gic_read32(reg); | |
59 | else | |
60 | return gic_read64(reg); | |
61 | } | |
62 | ||
63 | static inline void gic_write32(unsigned int reg, u32 val) | |
64 | { | |
65 | return __raw_writel(val, gic_base + reg); | |
66 | } | |
67 | ||
68 | static inline void gic_write64(unsigned int reg, u64 val) | |
69 | { | |
70 | return __raw_writeq(val, gic_base + reg); | |
71 | } | |
72 | ||
73 | static inline void gic_write(unsigned int reg, unsigned long val) | |
74 | { | |
75 | if (!mips_cm_is64) | |
76 | return gic_write32(reg, (u32)val); | |
77 | else | |
78 | return gic_write64(reg, (u64)val); | |
79 | } | |
80 | ||
81 | static inline void gic_update_bits(unsigned int reg, unsigned long mask, | |
82 | unsigned long val) | |
83 | { | |
84 | unsigned long regval; | |
5f68fea0 AB |
85 | |
86 | regval = gic_read(reg); | |
87 | regval &= ~mask; | |
88 | regval |= val; | |
89 | gic_write(reg, regval); | |
90 | } | |
91 | ||
92 | static inline void gic_reset_mask(unsigned int intr) | |
93 | { | |
94 | gic_write(GIC_REG(SHARED, GIC_SH_RMASK) + GIC_INTR_OFS(intr), | |
c3f57f02 | 95 | 1ul << GIC_INTR_BIT(intr)); |
5f68fea0 AB |
96 | } |
97 | ||
98 | static inline void gic_set_mask(unsigned int intr) | |
99 | { | |
100 | gic_write(GIC_REG(SHARED, GIC_SH_SMASK) + GIC_INTR_OFS(intr), | |
c3f57f02 | 101 | 1ul << GIC_INTR_BIT(intr)); |
5f68fea0 AB |
102 | } |
103 | ||
104 | static inline void gic_set_polarity(unsigned int intr, unsigned int pol) | |
105 | { | |
106 | gic_update_bits(GIC_REG(SHARED, GIC_SH_SET_POLARITY) + | |
c3f57f02 MC |
107 | GIC_INTR_OFS(intr), 1ul << GIC_INTR_BIT(intr), |
108 | (unsigned long)pol << GIC_INTR_BIT(intr)); | |
5f68fea0 AB |
109 | } |
110 | ||
111 | static inline void gic_set_trigger(unsigned int intr, unsigned int trig) | |
112 | { | |
113 | gic_update_bits(GIC_REG(SHARED, GIC_SH_SET_TRIGGER) + | |
c3f57f02 MC |
114 | GIC_INTR_OFS(intr), 1ul << GIC_INTR_BIT(intr), |
115 | (unsigned long)trig << GIC_INTR_BIT(intr)); | |
5f68fea0 AB |
116 | } |
117 | ||
118 | static inline void gic_set_dual_edge(unsigned int intr, unsigned int dual) | |
119 | { | |
120 | gic_update_bits(GIC_REG(SHARED, GIC_SH_SET_DUAL) + GIC_INTR_OFS(intr), | |
c3f57f02 MC |
121 | 1ul << GIC_INTR_BIT(intr), |
122 | (unsigned long)dual << GIC_INTR_BIT(intr)); | |
5f68fea0 AB |
123 | } |
124 | ||
125 | static inline void gic_map_to_pin(unsigned int intr, unsigned int pin) | |
126 | { | |
c3f57f02 MC |
127 | gic_write32(GIC_REG(SHARED, GIC_SH_INTR_MAP_TO_PIN_BASE) + |
128 | GIC_SH_MAP_TO_PIN(intr), GIC_MAP_TO_PIN_MSK | pin); | |
5f68fea0 AB |
129 | } |
130 | ||
131 | static inline void gic_map_to_vpe(unsigned int intr, unsigned int vpe) | |
132 | { | |
133 | gic_write(GIC_REG(SHARED, GIC_SH_INTR_MAP_TO_VPE_BASE) + | |
134 | GIC_SH_MAP_TO_VPE_REG_OFF(intr, vpe), | |
135 | GIC_SH_MAP_TO_VPE_REG_BIT(vpe)); | |
136 | } | |
137 | ||
a331ce63 | 138 | #ifdef CONFIG_CLKSRC_MIPS_GIC |
dfa762e1 SH |
139 | cycle_t gic_read_count(void) |
140 | { | |
141 | unsigned int hi, hi2, lo; | |
142 | ||
143 | do { | |
c3f57f02 MC |
144 | hi = gic_read32(GIC_REG(SHARED, GIC_SH_COUNTER_63_32)); |
145 | lo = gic_read32(GIC_REG(SHARED, GIC_SH_COUNTER_31_00)); | |
146 | hi2 = gic_read32(GIC_REG(SHARED, GIC_SH_COUNTER_63_32)); | |
dfa762e1 SH |
147 | } while (hi2 != hi); |
148 | ||
149 | return (((cycle_t) hi) << 32) + lo; | |
150 | } | |
0ab2b7d0 | 151 | |
387904ff AB |
152 | unsigned int gic_get_count_width(void) |
153 | { | |
154 | unsigned int bits, config; | |
155 | ||
5f68fea0 | 156 | config = gic_read(GIC_REG(SHARED, GIC_SH_CONFIG)); |
387904ff AB |
157 | bits = 32 + 4 * ((config & GIC_SH_CONFIG_COUNTBITS_MSK) >> |
158 | GIC_SH_CONFIG_COUNTBITS_SHF); | |
159 | ||
160 | return bits; | |
161 | } | |
162 | ||
0ab2b7d0 RG |
163 | void gic_write_compare(cycle_t cnt) |
164 | { | |
c3f57f02 | 165 | gic_write32(GIC_REG(VPE_LOCAL, GIC_VPE_COMPARE_HI), |
0ab2b7d0 | 166 | (int)(cnt >> 32)); |
c3f57f02 | 167 | gic_write32(GIC_REG(VPE_LOCAL, GIC_VPE_COMPARE_LO), |
0ab2b7d0 RG |
168 | (int)(cnt & 0xffffffff)); |
169 | } | |
170 | ||
414408d0 PB |
171 | void gic_write_cpu_compare(cycle_t cnt, int cpu) |
172 | { | |
173 | unsigned long flags; | |
174 | ||
175 | local_irq_save(flags); | |
176 | ||
c3f57f02 MC |
177 | gic_write32(GIC_REG(VPE_LOCAL, GIC_VPE_OTHER_ADDR), cpu); |
178 | gic_write32(GIC_REG(VPE_OTHER, GIC_VPE_COMPARE_HI), | |
414408d0 | 179 | (int)(cnt >> 32)); |
c3f57f02 | 180 | gic_write32(GIC_REG(VPE_OTHER, GIC_VPE_COMPARE_LO), |
414408d0 PB |
181 | (int)(cnt & 0xffffffff)); |
182 | ||
183 | local_irq_restore(flags); | |
184 | } | |
185 | ||
0ab2b7d0 RG |
186 | cycle_t gic_read_compare(void) |
187 | { | |
188 | unsigned int hi, lo; | |
189 | ||
c3f57f02 MC |
190 | hi = gic_read32(GIC_REG(VPE_LOCAL, GIC_VPE_COMPARE_HI)); |
191 | lo = gic_read32(GIC_REG(VPE_LOCAL, GIC_VPE_COMPARE_LO)); | |
0ab2b7d0 RG |
192 | |
193 | return (((cycle_t) hi) << 32) + lo; | |
194 | } | |
8fa4b930 MC |
195 | |
196 | void gic_start_count(void) | |
197 | { | |
198 | u32 gicconfig; | |
199 | ||
200 | /* Start the counter */ | |
201 | gicconfig = gic_read(GIC_REG(SHARED, GIC_SH_CONFIG)); | |
202 | gicconfig &= ~(1 << GIC_SH_CONFIG_COUNTSTOP_SHF); | |
203 | gic_write(GIC_REG(SHARED, GIC_SH_CONFIG), gicconfig); | |
204 | } | |
205 | ||
206 | void gic_stop_count(void) | |
207 | { | |
208 | u32 gicconfig; | |
209 | ||
210 | /* Stop the counter */ | |
211 | gicconfig = gic_read(GIC_REG(SHARED, GIC_SH_CONFIG)); | |
212 | gicconfig |= 1 << GIC_SH_CONFIG_COUNTSTOP_SHF; | |
213 | gic_write(GIC_REG(SHARED, GIC_SH_CONFIG), gicconfig); | |
214 | } | |
215 | ||
dfa762e1 SH |
216 | #endif |
217 | ||
e9de688d AB |
218 | static bool gic_local_irq_is_routable(int intr) |
219 | { | |
220 | u32 vpe_ctl; | |
221 | ||
222 | /* All local interrupts are routable in EIC mode. */ | |
223 | if (cpu_has_veic) | |
224 | return true; | |
225 | ||
c3f57f02 | 226 | vpe_ctl = gic_read32(GIC_REG(VPE_LOCAL, GIC_VPE_CTL)); |
e9de688d AB |
227 | switch (intr) { |
228 | case GIC_LOCAL_INT_TIMER: | |
229 | return vpe_ctl & GIC_VPE_CTL_TIMER_RTBL_MSK; | |
230 | case GIC_LOCAL_INT_PERFCTR: | |
231 | return vpe_ctl & GIC_VPE_CTL_PERFCNT_RTBL_MSK; | |
232 | case GIC_LOCAL_INT_FDC: | |
233 | return vpe_ctl & GIC_VPE_CTL_FDC_RTBL_MSK; | |
234 | case GIC_LOCAL_INT_SWINT0: | |
235 | case GIC_LOCAL_INT_SWINT1: | |
236 | return vpe_ctl & GIC_VPE_CTL_SWINT_RTBL_MSK; | |
237 | default: | |
238 | return true; | |
239 | } | |
240 | } | |
241 | ||
3263d085 | 242 | static void gic_bind_eic_interrupt(int irq, int set) |
98b67c37 SH |
243 | { |
244 | /* Convert irq vector # to hw int # */ | |
245 | irq -= GIC_PIN_TO_VEC_OFFSET; | |
246 | ||
247 | /* Set irq to use shadow set */ | |
5f68fea0 AB |
248 | gic_write(GIC_REG(VPE_LOCAL, GIC_VPE_EIC_SHADOW_SET_BASE) + |
249 | GIC_VPE_EIC_SS(irq), set); | |
98b67c37 SH |
250 | } |
251 | ||
39b8d525 RB |
252 | void gic_send_ipi(unsigned int intr) |
253 | { | |
53a7bc81 | 254 | gic_write(GIC_REG(SHARED, GIC_SH_WEDGE), GIC_SH_WEDGE_SET(intr)); |
39b8d525 RB |
255 | } |
256 | ||
e9de688d AB |
257 | int gic_get_c0_compare_int(void) |
258 | { | |
259 | if (!gic_local_irq_is_routable(GIC_LOCAL_INT_TIMER)) | |
260 | return MIPS_CPU_IRQ_BASE + cp0_compare_irq; | |
261 | return irq_create_mapping(gic_irq_domain, | |
262 | GIC_LOCAL_TO_HWIRQ(GIC_LOCAL_INT_TIMER)); | |
263 | } | |
264 | ||
265 | int gic_get_c0_perfcount_int(void) | |
266 | { | |
267 | if (!gic_local_irq_is_routable(GIC_LOCAL_INT_PERFCTR)) { | |
7e3e6cb2 | 268 | /* Is the performance counter shared with the timer? */ |
e9de688d AB |
269 | if (cp0_perfcount_irq < 0) |
270 | return -1; | |
271 | return MIPS_CPU_IRQ_BASE + cp0_perfcount_irq; | |
272 | } | |
273 | return irq_create_mapping(gic_irq_domain, | |
274 | GIC_LOCAL_TO_HWIRQ(GIC_LOCAL_INT_PERFCTR)); | |
275 | } | |
276 | ||
6429e2b6 JH |
277 | int gic_get_c0_fdc_int(void) |
278 | { | |
279 | if (!gic_local_irq_is_routable(GIC_LOCAL_INT_FDC)) { | |
280 | /* Is the FDC IRQ even present? */ | |
281 | if (cp0_fdc_irq < 0) | |
282 | return -1; | |
283 | return MIPS_CPU_IRQ_BASE + cp0_fdc_irq; | |
284 | } | |
285 | ||
6429e2b6 JH |
286 | return irq_create_mapping(gic_irq_domain, |
287 | GIC_LOCAL_TO_HWIRQ(GIC_LOCAL_INT_FDC)); | |
288 | } | |
289 | ||
1b3ed367 | 290 | static void gic_handle_shared_int(bool chained) |
39b8d525 | 291 | { |
c3f57f02 | 292 | unsigned int i, intr, virq, gic_reg_step = mips_cm_is64 ? 8 : 4; |
8f5ee79c | 293 | unsigned long *pcpu_mask; |
5f68fea0 | 294 | unsigned long pending_reg, intrmask_reg; |
8f5ee79c AB |
295 | DECLARE_BITMAP(pending, GIC_MAX_INTRS); |
296 | DECLARE_BITMAP(intrmask, GIC_MAX_INTRS); | |
39b8d525 RB |
297 | |
298 | /* Get per-cpu bitmaps */ | |
39b8d525 RB |
299 | pcpu_mask = pcpu_masks[smp_processor_id()].pcpu_mask; |
300 | ||
824f3f7f AB |
301 | pending_reg = GIC_REG(SHARED, GIC_SH_PEND); |
302 | intrmask_reg = GIC_REG(SHARED, GIC_SH_MASK); | |
39b8d525 | 303 | |
fbd55241 | 304 | for (i = 0; i < BITS_TO_LONGS(gic_shared_intrs); i++) { |
5f68fea0 AB |
305 | pending[i] = gic_read(pending_reg); |
306 | intrmask[i] = gic_read(intrmask_reg); | |
c3f57f02 MC |
307 | pending_reg += gic_reg_step; |
308 | intrmask_reg += gic_reg_step; | |
39b8d525 RB |
309 | } |
310 | ||
fbd55241 AB |
311 | bitmap_and(pending, pending, intrmask, gic_shared_intrs); |
312 | bitmap_and(pending, pending, pcpu_mask, gic_shared_intrs); | |
39b8d525 | 313 | |
d7eb4f2e QY |
314 | intr = find_first_bit(pending, gic_shared_intrs); |
315 | while (intr != gic_shared_intrs) { | |
316 | virq = irq_linear_revmap(gic_irq_domain, | |
317 | GIC_SHARED_TO_HWIRQ(intr)); | |
1b3ed367 RV |
318 | if (chained) |
319 | generic_handle_irq(virq); | |
320 | else | |
321 | do_IRQ(virq); | |
d7eb4f2e QY |
322 | |
323 | /* go to next pending bit */ | |
324 | bitmap_clear(pending, intr, 1); | |
325 | intr = find_first_bit(pending, gic_shared_intrs); | |
326 | } | |
39b8d525 RB |
327 | } |
328 | ||
161d049e | 329 | static void gic_mask_irq(struct irq_data *d) |
39b8d525 | 330 | { |
5f68fea0 | 331 | gic_reset_mask(GIC_HWIRQ_TO_SHARED(d->hwirq)); |
39b8d525 RB |
332 | } |
333 | ||
161d049e | 334 | static void gic_unmask_irq(struct irq_data *d) |
39b8d525 | 335 | { |
5f68fea0 | 336 | gic_set_mask(GIC_HWIRQ_TO_SHARED(d->hwirq)); |
39b8d525 RB |
337 | } |
338 | ||
5561c9e4 AB |
339 | static void gic_ack_irq(struct irq_data *d) |
340 | { | |
e9de688d | 341 | unsigned int irq = GIC_HWIRQ_TO_SHARED(d->hwirq); |
c49581a4 | 342 | |
53a7bc81 | 343 | gic_write(GIC_REG(SHARED, GIC_SH_WEDGE), GIC_SH_WEDGE_CLR(irq)); |
5561c9e4 AB |
344 | } |
345 | ||
95150ae8 AB |
346 | static int gic_set_type(struct irq_data *d, unsigned int type) |
347 | { | |
e9de688d | 348 | unsigned int irq = GIC_HWIRQ_TO_SHARED(d->hwirq); |
95150ae8 AB |
349 | unsigned long flags; |
350 | bool is_edge; | |
351 | ||
352 | spin_lock_irqsave(&gic_lock, flags); | |
353 | switch (type & IRQ_TYPE_SENSE_MASK) { | |
354 | case IRQ_TYPE_EDGE_FALLING: | |
5f68fea0 AB |
355 | gic_set_polarity(irq, GIC_POL_NEG); |
356 | gic_set_trigger(irq, GIC_TRIG_EDGE); | |
357 | gic_set_dual_edge(irq, GIC_TRIG_DUAL_DISABLE); | |
95150ae8 AB |
358 | is_edge = true; |
359 | break; | |
360 | case IRQ_TYPE_EDGE_RISING: | |
5f68fea0 AB |
361 | gic_set_polarity(irq, GIC_POL_POS); |
362 | gic_set_trigger(irq, GIC_TRIG_EDGE); | |
363 | gic_set_dual_edge(irq, GIC_TRIG_DUAL_DISABLE); | |
95150ae8 AB |
364 | is_edge = true; |
365 | break; | |
366 | case IRQ_TYPE_EDGE_BOTH: | |
367 | /* polarity is irrelevant in this case */ | |
5f68fea0 AB |
368 | gic_set_trigger(irq, GIC_TRIG_EDGE); |
369 | gic_set_dual_edge(irq, GIC_TRIG_DUAL_ENABLE); | |
95150ae8 AB |
370 | is_edge = true; |
371 | break; | |
372 | case IRQ_TYPE_LEVEL_LOW: | |
5f68fea0 AB |
373 | gic_set_polarity(irq, GIC_POL_NEG); |
374 | gic_set_trigger(irq, GIC_TRIG_LEVEL); | |
375 | gic_set_dual_edge(irq, GIC_TRIG_DUAL_DISABLE); | |
95150ae8 AB |
376 | is_edge = false; |
377 | break; | |
378 | case IRQ_TYPE_LEVEL_HIGH: | |
379 | default: | |
5f68fea0 AB |
380 | gic_set_polarity(irq, GIC_POL_POS); |
381 | gic_set_trigger(irq, GIC_TRIG_LEVEL); | |
382 | gic_set_dual_edge(irq, GIC_TRIG_DUAL_DISABLE); | |
95150ae8 AB |
383 | is_edge = false; |
384 | break; | |
385 | } | |
386 | ||
387 | if (is_edge) { | |
4a6a3ea3 AB |
388 | __irq_set_chip_handler_name_locked(d->irq, |
389 | &gic_edge_irq_controller, | |
390 | handle_edge_irq, NULL); | |
95150ae8 | 391 | } else { |
4a6a3ea3 AB |
392 | __irq_set_chip_handler_name_locked(d->irq, |
393 | &gic_level_irq_controller, | |
394 | handle_level_irq, NULL); | |
95150ae8 AB |
395 | } |
396 | spin_unlock_irqrestore(&gic_lock, flags); | |
39b8d525 | 397 | |
95150ae8 AB |
398 | return 0; |
399 | } | |
400 | ||
401 | #ifdef CONFIG_SMP | |
161d049e TG |
402 | static int gic_set_affinity(struct irq_data *d, const struct cpumask *cpumask, |
403 | bool force) | |
39b8d525 | 404 | { |
e9de688d | 405 | unsigned int irq = GIC_HWIRQ_TO_SHARED(d->hwirq); |
39b8d525 RB |
406 | cpumask_t tmp = CPU_MASK_NONE; |
407 | unsigned long flags; | |
408 | int i; | |
409 | ||
0de26520 | 410 | cpumask_and(&tmp, cpumask, cpu_online_mask); |
f9b531fe | 411 | if (cpumask_empty(&tmp)) |
14d160ab | 412 | return -EINVAL; |
39b8d525 RB |
413 | |
414 | /* Assumption : cpumask refers to a single CPU */ | |
415 | spin_lock_irqsave(&gic_lock, flags); | |
39b8d525 | 416 | |
c214c035 | 417 | /* Re-route this IRQ */ |
f9b531fe | 418 | gic_map_to_vpe(irq, cpumask_first(&tmp)); |
c214c035 TW |
419 | |
420 | /* Update the pcpu_masks */ | |
421 | for (i = 0; i < NR_CPUS; i++) | |
422 | clear_bit(irq, pcpu_masks[i].pcpu_mask); | |
f9b531fe | 423 | set_bit(irq, pcpu_masks[cpumask_first(&tmp)].pcpu_mask); |
39b8d525 | 424 | |
161d049e | 425 | cpumask_copy(d->affinity, cpumask); |
39b8d525 RB |
426 | spin_unlock_irqrestore(&gic_lock, flags); |
427 | ||
161d049e | 428 | return IRQ_SET_MASK_OK_NOCOPY; |
39b8d525 RB |
429 | } |
430 | #endif | |
431 | ||
4a6a3ea3 AB |
432 | static struct irq_chip gic_level_irq_controller = { |
433 | .name = "MIPS GIC", | |
434 | .irq_mask = gic_mask_irq, | |
435 | .irq_unmask = gic_unmask_irq, | |
436 | .irq_set_type = gic_set_type, | |
437 | #ifdef CONFIG_SMP | |
438 | .irq_set_affinity = gic_set_affinity, | |
439 | #endif | |
440 | }; | |
441 | ||
442 | static struct irq_chip gic_edge_irq_controller = { | |
161d049e | 443 | .name = "MIPS GIC", |
5561c9e4 | 444 | .irq_ack = gic_ack_irq, |
161d049e | 445 | .irq_mask = gic_mask_irq, |
161d049e | 446 | .irq_unmask = gic_unmask_irq, |
95150ae8 | 447 | .irq_set_type = gic_set_type, |
39b8d525 | 448 | #ifdef CONFIG_SMP |
161d049e | 449 | .irq_set_affinity = gic_set_affinity, |
39b8d525 RB |
450 | #endif |
451 | }; | |
452 | ||
1b3ed367 | 453 | static void gic_handle_local_int(bool chained) |
e9de688d AB |
454 | { |
455 | unsigned long pending, masked; | |
d7eb4f2e | 456 | unsigned int intr, virq; |
e9de688d | 457 | |
c3f57f02 MC |
458 | pending = gic_read32(GIC_REG(VPE_LOCAL, GIC_VPE_PEND)); |
459 | masked = gic_read32(GIC_REG(VPE_LOCAL, GIC_VPE_MASK)); | |
e9de688d AB |
460 | |
461 | bitmap_and(&pending, &pending, &masked, GIC_NUM_LOCAL_INTRS); | |
462 | ||
d7eb4f2e QY |
463 | intr = find_first_bit(&pending, GIC_NUM_LOCAL_INTRS); |
464 | while (intr != GIC_NUM_LOCAL_INTRS) { | |
465 | virq = irq_linear_revmap(gic_irq_domain, | |
466 | GIC_LOCAL_TO_HWIRQ(intr)); | |
1b3ed367 RV |
467 | if (chained) |
468 | generic_handle_irq(virq); | |
469 | else | |
470 | do_IRQ(virq); | |
d7eb4f2e QY |
471 | |
472 | /* go to next pending bit */ | |
473 | bitmap_clear(&pending, intr, 1); | |
474 | intr = find_first_bit(&pending, GIC_NUM_LOCAL_INTRS); | |
475 | } | |
e9de688d AB |
476 | } |
477 | ||
478 | static void gic_mask_local_irq(struct irq_data *d) | |
479 | { | |
480 | int intr = GIC_HWIRQ_TO_LOCAL(d->hwirq); | |
481 | ||
c3f57f02 | 482 | gic_write32(GIC_REG(VPE_LOCAL, GIC_VPE_RMASK), 1 << intr); |
e9de688d AB |
483 | } |
484 | ||
485 | static void gic_unmask_local_irq(struct irq_data *d) | |
486 | { | |
487 | int intr = GIC_HWIRQ_TO_LOCAL(d->hwirq); | |
488 | ||
c3f57f02 | 489 | gic_write32(GIC_REG(VPE_LOCAL, GIC_VPE_SMASK), 1 << intr); |
e9de688d AB |
490 | } |
491 | ||
492 | static struct irq_chip gic_local_irq_controller = { | |
493 | .name = "MIPS GIC Local", | |
494 | .irq_mask = gic_mask_local_irq, | |
495 | .irq_unmask = gic_unmask_local_irq, | |
496 | }; | |
497 | ||
498 | static void gic_mask_local_irq_all_vpes(struct irq_data *d) | |
499 | { | |
500 | int intr = GIC_HWIRQ_TO_LOCAL(d->hwirq); | |
501 | int i; | |
502 | unsigned long flags; | |
503 | ||
504 | spin_lock_irqsave(&gic_lock, flags); | |
505 | for (i = 0; i < gic_vpes; i++) { | |
5f68fea0 | 506 | gic_write(GIC_REG(VPE_LOCAL, GIC_VPE_OTHER_ADDR), i); |
c3f57f02 | 507 | gic_write32(GIC_REG(VPE_OTHER, GIC_VPE_RMASK), 1 << intr); |
e9de688d AB |
508 | } |
509 | spin_unlock_irqrestore(&gic_lock, flags); | |
510 | } | |
511 | ||
512 | static void gic_unmask_local_irq_all_vpes(struct irq_data *d) | |
513 | { | |
514 | int intr = GIC_HWIRQ_TO_LOCAL(d->hwirq); | |
515 | int i; | |
516 | unsigned long flags; | |
517 | ||
518 | spin_lock_irqsave(&gic_lock, flags); | |
519 | for (i = 0; i < gic_vpes; i++) { | |
5f68fea0 | 520 | gic_write(GIC_REG(VPE_LOCAL, GIC_VPE_OTHER_ADDR), i); |
c3f57f02 | 521 | gic_write32(GIC_REG(VPE_OTHER, GIC_VPE_SMASK), 1 << intr); |
e9de688d AB |
522 | } |
523 | spin_unlock_irqrestore(&gic_lock, flags); | |
524 | } | |
525 | ||
526 | static struct irq_chip gic_all_vpes_local_irq_controller = { | |
527 | .name = "MIPS GIC Local", | |
528 | .irq_mask = gic_mask_local_irq_all_vpes, | |
529 | .irq_unmask = gic_unmask_local_irq_all_vpes, | |
530 | }; | |
531 | ||
18743d27 | 532 | static void __gic_irq_dispatch(void) |
39b8d525 | 533 | { |
1b3ed367 RV |
534 | gic_handle_local_int(false); |
535 | gic_handle_shared_int(false); | |
18743d27 | 536 | } |
39b8d525 | 537 | |
18743d27 AB |
538 | static void gic_irq_dispatch(unsigned int irq, struct irq_desc *desc) |
539 | { | |
1b3ed367 RV |
540 | gic_handle_local_int(true); |
541 | gic_handle_shared_int(true); | |
18743d27 AB |
542 | } |
543 | ||
544 | #ifdef CONFIG_MIPS_GIC_IPI | |
545 | static int gic_resched_int_base; | |
546 | static int gic_call_int_base; | |
547 | ||
548 | unsigned int plat_ipi_resched_int_xlate(unsigned int cpu) | |
549 | { | |
550 | return gic_resched_int_base + cpu; | |
551 | } | |
39b8d525 | 552 | |
18743d27 AB |
553 | unsigned int plat_ipi_call_int_xlate(unsigned int cpu) |
554 | { | |
555 | return gic_call_int_base + cpu; | |
556 | } | |
39b8d525 | 557 | |
18743d27 AB |
558 | static irqreturn_t ipi_resched_interrupt(int irq, void *dev_id) |
559 | { | |
560 | scheduler_ipi(); | |
561 | ||
562 | return IRQ_HANDLED; | |
563 | } | |
564 | ||
565 | static irqreturn_t ipi_call_interrupt(int irq, void *dev_id) | |
566 | { | |
4ace6139 | 567 | generic_smp_call_function_interrupt(); |
18743d27 AB |
568 | |
569 | return IRQ_HANDLED; | |
570 | } | |
b0a88ae5 | 571 | |
18743d27 AB |
572 | static struct irqaction irq_resched = { |
573 | .handler = ipi_resched_interrupt, | |
574 | .flags = IRQF_PERCPU, | |
575 | .name = "IPI resched" | |
576 | }; | |
577 | ||
578 | static struct irqaction irq_call = { | |
579 | .handler = ipi_call_interrupt, | |
580 | .flags = IRQF_PERCPU, | |
581 | .name = "IPI call" | |
582 | }; | |
583 | ||
584 | static __init void gic_ipi_init_one(unsigned int intr, int cpu, | |
585 | struct irqaction *action) | |
586 | { | |
e9de688d AB |
587 | int virq = irq_create_mapping(gic_irq_domain, |
588 | GIC_SHARED_TO_HWIRQ(intr)); | |
18743d27 AB |
589 | int i; |
590 | ||
5f68fea0 | 591 | gic_map_to_vpe(intr, cpu); |
c49581a4 AB |
592 | for (i = 0; i < NR_CPUS; i++) |
593 | clear_bit(intr, pcpu_masks[i].pcpu_mask); | |
b0a88ae5 JD |
594 | set_bit(intr, pcpu_masks[cpu].pcpu_mask); |
595 | ||
18743d27 AB |
596 | irq_set_irq_type(virq, IRQ_TYPE_EDGE_RISING); |
597 | ||
598 | irq_set_handler(virq, handle_percpu_irq); | |
599 | setup_irq(virq, action); | |
39b8d525 RB |
600 | } |
601 | ||
18743d27 | 602 | static __init void gic_ipi_init(void) |
39b8d525 | 603 | { |
18743d27 AB |
604 | int i; |
605 | ||
606 | /* Use last 2 * NR_CPUS interrupts as IPIs */ | |
fbd55241 | 607 | gic_resched_int_base = gic_shared_intrs - nr_cpu_ids; |
18743d27 AB |
608 | gic_call_int_base = gic_resched_int_base - nr_cpu_ids; |
609 | ||
610 | for (i = 0; i < nr_cpu_ids; i++) { | |
611 | gic_ipi_init_one(gic_call_int_base + i, i, &irq_call); | |
612 | gic_ipi_init_one(gic_resched_int_base + i, i, &irq_resched); | |
613 | } | |
614 | } | |
615 | #else | |
616 | static inline void gic_ipi_init(void) | |
617 | { | |
618 | } | |
619 | #endif | |
620 | ||
e9de688d | 621 | static void __init gic_basic_init(void) |
18743d27 AB |
622 | { |
623 | unsigned int i; | |
98b67c37 SH |
624 | |
625 | board_bind_eic_interrupt = &gic_bind_eic_interrupt; | |
39b8d525 RB |
626 | |
627 | /* Setup defaults */ | |
fbd55241 | 628 | for (i = 0; i < gic_shared_intrs; i++) { |
5f68fea0 AB |
629 | gic_set_polarity(i, GIC_POL_POS); |
630 | gic_set_trigger(i, GIC_TRIG_LEVEL); | |
631 | gic_reset_mask(i); | |
39b8d525 RB |
632 | } |
633 | ||
e9de688d AB |
634 | for (i = 0; i < gic_vpes; i++) { |
635 | unsigned int j; | |
636 | ||
5f68fea0 | 637 | gic_write(GIC_REG(VPE_LOCAL, GIC_VPE_OTHER_ADDR), i); |
e9de688d AB |
638 | for (j = 0; j < GIC_NUM_LOCAL_INTRS; j++) { |
639 | if (!gic_local_irq_is_routable(j)) | |
640 | continue; | |
c3f57f02 | 641 | gic_write32(GIC_REG(VPE_OTHER, GIC_VPE_RMASK), 1 << j); |
e9de688d AB |
642 | } |
643 | } | |
39b8d525 RB |
644 | } |
645 | ||
e9de688d AB |
646 | static int gic_local_irq_domain_map(struct irq_domain *d, unsigned int virq, |
647 | irq_hw_number_t hw) | |
c49581a4 | 648 | { |
e9de688d AB |
649 | int intr = GIC_HWIRQ_TO_LOCAL(hw); |
650 | int ret = 0; | |
651 | int i; | |
652 | unsigned long flags; | |
653 | ||
654 | if (!gic_local_irq_is_routable(intr)) | |
655 | return -EPERM; | |
656 | ||
657 | /* | |
658 | * HACK: These are all really percpu interrupts, but the rest | |
659 | * of the MIPS kernel code does not use the percpu IRQ API for | |
660 | * the CP0 timer and performance counter interrupts. | |
661 | */ | |
b720fd8b JH |
662 | switch (intr) { |
663 | case GIC_LOCAL_INT_TIMER: | |
664 | case GIC_LOCAL_INT_PERFCTR: | |
665 | case GIC_LOCAL_INT_FDC: | |
666 | irq_set_chip_and_handler(virq, | |
667 | &gic_all_vpes_local_irq_controller, | |
668 | handle_percpu_irq); | |
669 | break; | |
670 | default: | |
e9de688d AB |
671 | irq_set_chip_and_handler(virq, |
672 | &gic_local_irq_controller, | |
673 | handle_percpu_devid_irq); | |
674 | irq_set_percpu_devid(virq); | |
b720fd8b | 675 | break; |
e9de688d AB |
676 | } |
677 | ||
678 | spin_lock_irqsave(&gic_lock, flags); | |
679 | for (i = 0; i < gic_vpes; i++) { | |
680 | u32 val = GIC_MAP_TO_PIN_MSK | gic_cpu_pin; | |
681 | ||
5f68fea0 | 682 | gic_write(GIC_REG(VPE_LOCAL, GIC_VPE_OTHER_ADDR), i); |
e9de688d AB |
683 | |
684 | switch (intr) { | |
685 | case GIC_LOCAL_INT_WD: | |
c3f57f02 | 686 | gic_write32(GIC_REG(VPE_OTHER, GIC_VPE_WD_MAP), val); |
e9de688d AB |
687 | break; |
688 | case GIC_LOCAL_INT_COMPARE: | |
c3f57f02 MC |
689 | gic_write32(GIC_REG(VPE_OTHER, GIC_VPE_COMPARE_MAP), |
690 | val); | |
e9de688d AB |
691 | break; |
692 | case GIC_LOCAL_INT_TIMER: | |
1b6af71a JH |
693 | /* CONFIG_MIPS_CMP workaround (see __gic_init) */ |
694 | val = GIC_MAP_TO_PIN_MSK | timer_cpu_pin; | |
c3f57f02 MC |
695 | gic_write32(GIC_REG(VPE_OTHER, GIC_VPE_TIMER_MAP), |
696 | val); | |
e9de688d AB |
697 | break; |
698 | case GIC_LOCAL_INT_PERFCTR: | |
c3f57f02 MC |
699 | gic_write32(GIC_REG(VPE_OTHER, GIC_VPE_PERFCTR_MAP), |
700 | val); | |
e9de688d AB |
701 | break; |
702 | case GIC_LOCAL_INT_SWINT0: | |
c3f57f02 MC |
703 | gic_write32(GIC_REG(VPE_OTHER, GIC_VPE_SWINT0_MAP), |
704 | val); | |
e9de688d AB |
705 | break; |
706 | case GIC_LOCAL_INT_SWINT1: | |
c3f57f02 MC |
707 | gic_write32(GIC_REG(VPE_OTHER, GIC_VPE_SWINT1_MAP), |
708 | val); | |
e9de688d AB |
709 | break; |
710 | case GIC_LOCAL_INT_FDC: | |
c3f57f02 | 711 | gic_write32(GIC_REG(VPE_OTHER, GIC_VPE_FDC_MAP), val); |
e9de688d AB |
712 | break; |
713 | default: | |
714 | pr_err("Invalid local IRQ %d\n", intr); | |
715 | ret = -EINVAL; | |
716 | break; | |
717 | } | |
718 | } | |
719 | spin_unlock_irqrestore(&gic_lock, flags); | |
720 | ||
721 | return ret; | |
722 | } | |
723 | ||
724 | static int gic_shared_irq_domain_map(struct irq_domain *d, unsigned int virq, | |
725 | irq_hw_number_t hw) | |
726 | { | |
727 | int intr = GIC_HWIRQ_TO_SHARED(hw); | |
c49581a4 AB |
728 | unsigned long flags; |
729 | ||
4a6a3ea3 AB |
730 | irq_set_chip_and_handler(virq, &gic_level_irq_controller, |
731 | handle_level_irq); | |
c49581a4 AB |
732 | |
733 | spin_lock_irqsave(&gic_lock, flags); | |
5f68fea0 | 734 | gic_map_to_pin(intr, gic_cpu_pin); |
c49581a4 | 735 | /* Map to VPE 0 by default */ |
5f68fea0 | 736 | gic_map_to_vpe(intr, 0); |
e9de688d | 737 | set_bit(intr, pcpu_masks[0].pcpu_mask); |
c49581a4 AB |
738 | spin_unlock_irqrestore(&gic_lock, flags); |
739 | ||
740 | return 0; | |
741 | } | |
742 | ||
e9de688d AB |
743 | static int gic_irq_domain_map(struct irq_domain *d, unsigned int virq, |
744 | irq_hw_number_t hw) | |
745 | { | |
746 | if (GIC_HWIRQ_TO_LOCAL(hw) < GIC_NUM_LOCAL_INTRS) | |
747 | return gic_local_irq_domain_map(d, virq, hw); | |
748 | return gic_shared_irq_domain_map(d, virq, hw); | |
749 | } | |
750 | ||
a7057270 AB |
751 | static int gic_irq_domain_xlate(struct irq_domain *d, struct device_node *ctrlr, |
752 | const u32 *intspec, unsigned int intsize, | |
753 | irq_hw_number_t *out_hwirq, | |
754 | unsigned int *out_type) | |
755 | { | |
756 | if (intsize != 3) | |
757 | return -EINVAL; | |
758 | ||
759 | if (intspec[0] == GIC_SHARED) | |
760 | *out_hwirq = GIC_SHARED_TO_HWIRQ(intspec[1]); | |
761 | else if (intspec[0] == GIC_LOCAL) | |
762 | *out_hwirq = GIC_LOCAL_TO_HWIRQ(intspec[1]); | |
763 | else | |
764 | return -EINVAL; | |
765 | *out_type = intspec[2] & IRQ_TYPE_SENSE_MASK; | |
766 | ||
767 | return 0; | |
768 | } | |
769 | ||
96009736 | 770 | static const struct irq_domain_ops gic_irq_domain_ops = { |
c49581a4 | 771 | .map = gic_irq_domain_map, |
a7057270 | 772 | .xlate = gic_irq_domain_xlate, |
c49581a4 AB |
773 | }; |
774 | ||
a7057270 AB |
775 | static void __init __gic_init(unsigned long gic_base_addr, |
776 | unsigned long gic_addrspace_size, | |
777 | unsigned int cpu_vec, unsigned int irqbase, | |
778 | struct device_node *node) | |
39b8d525 RB |
779 | { |
780 | unsigned int gicconfig; | |
781 | ||
5f68fea0 | 782 | gic_base = ioremap_nocache(gic_base_addr, gic_addrspace_size); |
39b8d525 | 783 | |
5f68fea0 | 784 | gicconfig = gic_read(GIC_REG(SHARED, GIC_SH_CONFIG)); |
fbd55241 | 785 | gic_shared_intrs = (gicconfig & GIC_SH_CONFIG_NUMINTRS_MSK) >> |
39b8d525 | 786 | GIC_SH_CONFIG_NUMINTRS_SHF; |
fbd55241 | 787 | gic_shared_intrs = ((gic_shared_intrs + 1) * 8); |
39b8d525 | 788 | |
e9de688d | 789 | gic_vpes = (gicconfig & GIC_SH_CONFIG_NUMVPES_MSK) >> |
39b8d525 | 790 | GIC_SH_CONFIG_NUMVPES_SHF; |
e9de688d | 791 | gic_vpes = gic_vpes + 1; |
39b8d525 | 792 | |
18743d27 AB |
793 | if (cpu_has_veic) { |
794 | /* Always use vector 1 in EIC mode */ | |
795 | gic_cpu_pin = 0; | |
1b6af71a | 796 | timer_cpu_pin = gic_cpu_pin; |
18743d27 AB |
797 | set_vi_handler(gic_cpu_pin + GIC_PIN_TO_VEC_OFFSET, |
798 | __gic_irq_dispatch); | |
799 | } else { | |
800 | gic_cpu_pin = cpu_vec - GIC_CPU_PIN_OFFSET; | |
801 | irq_set_chained_handler(MIPS_CPU_IRQ_BASE + cpu_vec, | |
802 | gic_irq_dispatch); | |
1b6af71a JH |
803 | /* |
804 | * With the CMP implementation of SMP (deprecated), other CPUs | |
805 | * are started by the bootloader and put into a timer based | |
806 | * waiting poll loop. We must not re-route those CPU's local | |
807 | * timer interrupts as the wait instruction will never finish, | |
808 | * so just handle whatever CPU interrupt it is routed to by | |
809 | * default. | |
810 | * | |
811 | * This workaround should be removed when CMP support is | |
812 | * dropped. | |
813 | */ | |
814 | if (IS_ENABLED(CONFIG_MIPS_CMP) && | |
815 | gic_local_irq_is_routable(GIC_LOCAL_INT_TIMER)) { | |
c3f57f02 | 816 | timer_cpu_pin = gic_read32(GIC_REG(VPE_LOCAL, |
1b6af71a JH |
817 | GIC_VPE_TIMER_MAP)) & |
818 | GIC_MAP_MSK; | |
819 | irq_set_chained_handler(MIPS_CPU_IRQ_BASE + | |
820 | GIC_CPU_PIN_OFFSET + | |
821 | timer_cpu_pin, | |
822 | gic_irq_dispatch); | |
823 | } else { | |
824 | timer_cpu_pin = gic_cpu_pin; | |
825 | } | |
18743d27 AB |
826 | } |
827 | ||
a7057270 | 828 | gic_irq_domain = irq_domain_add_simple(node, GIC_NUM_LOCAL_INTRS + |
e9de688d | 829 | gic_shared_intrs, irqbase, |
c49581a4 AB |
830 | &gic_irq_domain_ops, NULL); |
831 | if (!gic_irq_domain) | |
832 | panic("Failed to add GIC IRQ domain"); | |
0b271f56 | 833 | |
e9de688d | 834 | gic_basic_init(); |
18743d27 AB |
835 | |
836 | gic_ipi_init(); | |
39b8d525 | 837 | } |
a7057270 AB |
838 | |
839 | void __init gic_init(unsigned long gic_base_addr, | |
840 | unsigned long gic_addrspace_size, | |
841 | unsigned int cpu_vec, unsigned int irqbase) | |
842 | { | |
843 | __gic_init(gic_base_addr, gic_addrspace_size, cpu_vec, irqbase, NULL); | |
844 | } | |
845 | ||
846 | static int __init gic_of_init(struct device_node *node, | |
847 | struct device_node *parent) | |
848 | { | |
849 | struct resource res; | |
850 | unsigned int cpu_vec, i = 0, reserved = 0; | |
851 | phys_addr_t gic_base; | |
852 | size_t gic_len; | |
853 | ||
854 | /* Find the first available CPU vector. */ | |
855 | while (!of_property_read_u32_index(node, "mti,reserved-cpu-vectors", | |
856 | i++, &cpu_vec)) | |
857 | reserved |= BIT(cpu_vec); | |
858 | for (cpu_vec = 2; cpu_vec < 8; cpu_vec++) { | |
859 | if (!(reserved & BIT(cpu_vec))) | |
860 | break; | |
861 | } | |
862 | if (cpu_vec == 8) { | |
863 | pr_err("No CPU vectors available for GIC\n"); | |
864 | return -ENODEV; | |
865 | } | |
866 | ||
867 | if (of_address_to_resource(node, 0, &res)) { | |
868 | /* | |
869 | * Probe the CM for the GIC base address if not specified | |
870 | * in the device-tree. | |
871 | */ | |
872 | if (mips_cm_present()) { | |
873 | gic_base = read_gcr_gic_base() & | |
874 | ~CM_GCR_GIC_BASE_GICEN_MSK; | |
875 | gic_len = 0x20000; | |
876 | } else { | |
877 | pr_err("Failed to get GIC memory range\n"); | |
878 | return -ENODEV; | |
879 | } | |
880 | } else { | |
881 | gic_base = res.start; | |
882 | gic_len = resource_size(&res); | |
883 | } | |
884 | ||
885 | if (mips_cm_present()) | |
886 | write_gcr_gic_base(gic_base | CM_GCR_GIC_BASE_GICEN_MSK); | |
887 | gic_present = true; | |
888 | ||
889 | __gic_init(gic_base, gic_len, cpu_vec, 0, node); | |
890 | ||
891 | return 0; | |
892 | } | |
893 | IRQCHIP_DECLARE(mips_gic, "mti,gic", gic_of_init); |