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Commit | Line | Data |
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2299c49d SH |
1 | /* |
2 | * This file is subject to the terms and conditions of the GNU General Public | |
3 | * License. See the file "COPYING" in the main directory of this archive | |
4 | * for more details. | |
5 | * | |
6 | * Copyright (C) 2008 Ralf Baechle (ralf@linux-mips.org) | |
7 | * Copyright (C) 2012 MIPS Technologies, Inc. All rights reserved. | |
8 | */ | |
39b8d525 | 9 | #include <linux/bitmap.h> |
fb8f7be1 | 10 | #include <linux/clocksource.h> |
39b8d525 | 11 | #include <linux/init.h> |
18743d27 | 12 | #include <linux/interrupt.h> |
fb8f7be1 | 13 | #include <linux/irq.h> |
41a83e06 | 14 | #include <linux/irqchip.h> |
4060bbe9 | 15 | #include <linux/irqchip/mips-gic.h> |
a7057270 | 16 | #include <linux/of_address.h> |
18743d27 | 17 | #include <linux/sched.h> |
631330f5 | 18 | #include <linux/smp.h> |
39b8d525 | 19 | |
a7057270 | 20 | #include <asm/mips-cm.h> |
98b67c37 SH |
21 | #include <asm/setup.h> |
22 | #include <asm/traps.h> | |
39b8d525 | 23 | |
a7057270 AB |
24 | #include <dt-bindings/interrupt-controller/mips-gic.h> |
25 | ||
ff86714f | 26 | unsigned int gic_present; |
98b67c37 | 27 | |
822350bc | 28 | struct gic_pcpu_mask { |
fbd55241 | 29 | DECLARE_BITMAP(pcpu_mask, GIC_MAX_INTRS); |
822350bc JD |
30 | }; |
31 | ||
2af70a96 QY |
32 | struct gic_irq_spec { |
33 | enum { | |
34 | GIC_DEVICE, | |
35 | GIC_IPI | |
36 | } type; | |
37 | ||
38 | union { | |
39 | struct cpumask *ipimask; | |
40 | unsigned int hwirq; | |
41 | }; | |
42 | }; | |
43 | ||
c0a9f72c | 44 | static unsigned long __gic_base_addr; |
2af70a96 | 45 | |
5f68fea0 | 46 | static void __iomem *gic_base; |
0b271f56 | 47 | static struct gic_pcpu_mask pcpu_masks[NR_CPUS]; |
95150ae8 | 48 | static DEFINE_SPINLOCK(gic_lock); |
c49581a4 | 49 | static struct irq_domain *gic_irq_domain; |
c98c1822 | 50 | static struct irq_domain *gic_dev_domain; |
2af70a96 | 51 | static struct irq_domain *gic_ipi_domain; |
fbd55241 | 52 | static int gic_shared_intrs; |
e9de688d | 53 | static int gic_vpes; |
3263d085 | 54 | static unsigned int gic_cpu_pin; |
1b6af71a | 55 | static unsigned int timer_cpu_pin; |
4a6a3ea3 | 56 | static struct irq_chip gic_level_irq_controller, gic_edge_irq_controller; |
2af70a96 | 57 | DECLARE_BITMAP(ipi_resrv, GIC_MAX_INTRS); |
39b8d525 | 58 | |
18743d27 AB |
59 | static void __gic_irq_dispatch(void); |
60 | ||
c3f57f02 | 61 | static inline u32 gic_read32(unsigned int reg) |
5f68fea0 AB |
62 | { |
63 | return __raw_readl(gic_base + reg); | |
64 | } | |
65 | ||
c3f57f02 | 66 | static inline u64 gic_read64(unsigned int reg) |
5f68fea0 | 67 | { |
c3f57f02 | 68 | return __raw_readq(gic_base + reg); |
5f68fea0 AB |
69 | } |
70 | ||
c3f57f02 | 71 | static inline unsigned long gic_read(unsigned int reg) |
5f68fea0 | 72 | { |
c3f57f02 MC |
73 | if (!mips_cm_is64) |
74 | return gic_read32(reg); | |
75 | else | |
76 | return gic_read64(reg); | |
77 | } | |
78 | ||
79 | static inline void gic_write32(unsigned int reg, u32 val) | |
80 | { | |
81 | return __raw_writel(val, gic_base + reg); | |
82 | } | |
83 | ||
84 | static inline void gic_write64(unsigned int reg, u64 val) | |
85 | { | |
86 | return __raw_writeq(val, gic_base + reg); | |
87 | } | |
88 | ||
89 | static inline void gic_write(unsigned int reg, unsigned long val) | |
90 | { | |
91 | if (!mips_cm_is64) | |
92 | return gic_write32(reg, (u32)val); | |
93 | else | |
94 | return gic_write64(reg, (u64)val); | |
95 | } | |
96 | ||
97 | static inline void gic_update_bits(unsigned int reg, unsigned long mask, | |
98 | unsigned long val) | |
99 | { | |
100 | unsigned long regval; | |
5f68fea0 AB |
101 | |
102 | regval = gic_read(reg); | |
103 | regval &= ~mask; | |
104 | regval |= val; | |
105 | gic_write(reg, regval); | |
106 | } | |
107 | ||
108 | static inline void gic_reset_mask(unsigned int intr) | |
109 | { | |
110 | gic_write(GIC_REG(SHARED, GIC_SH_RMASK) + GIC_INTR_OFS(intr), | |
c3f57f02 | 111 | 1ul << GIC_INTR_BIT(intr)); |
5f68fea0 AB |
112 | } |
113 | ||
114 | static inline void gic_set_mask(unsigned int intr) | |
115 | { | |
116 | gic_write(GIC_REG(SHARED, GIC_SH_SMASK) + GIC_INTR_OFS(intr), | |
c3f57f02 | 117 | 1ul << GIC_INTR_BIT(intr)); |
5f68fea0 AB |
118 | } |
119 | ||
120 | static inline void gic_set_polarity(unsigned int intr, unsigned int pol) | |
121 | { | |
122 | gic_update_bits(GIC_REG(SHARED, GIC_SH_SET_POLARITY) + | |
c3f57f02 MC |
123 | GIC_INTR_OFS(intr), 1ul << GIC_INTR_BIT(intr), |
124 | (unsigned long)pol << GIC_INTR_BIT(intr)); | |
5f68fea0 AB |
125 | } |
126 | ||
127 | static inline void gic_set_trigger(unsigned int intr, unsigned int trig) | |
128 | { | |
129 | gic_update_bits(GIC_REG(SHARED, GIC_SH_SET_TRIGGER) + | |
c3f57f02 MC |
130 | GIC_INTR_OFS(intr), 1ul << GIC_INTR_BIT(intr), |
131 | (unsigned long)trig << GIC_INTR_BIT(intr)); | |
5f68fea0 AB |
132 | } |
133 | ||
134 | static inline void gic_set_dual_edge(unsigned int intr, unsigned int dual) | |
135 | { | |
136 | gic_update_bits(GIC_REG(SHARED, GIC_SH_SET_DUAL) + GIC_INTR_OFS(intr), | |
c3f57f02 MC |
137 | 1ul << GIC_INTR_BIT(intr), |
138 | (unsigned long)dual << GIC_INTR_BIT(intr)); | |
5f68fea0 AB |
139 | } |
140 | ||
141 | static inline void gic_map_to_pin(unsigned int intr, unsigned int pin) | |
142 | { | |
c3f57f02 MC |
143 | gic_write32(GIC_REG(SHARED, GIC_SH_INTR_MAP_TO_PIN_BASE) + |
144 | GIC_SH_MAP_TO_PIN(intr), GIC_MAP_TO_PIN_MSK | pin); | |
5f68fea0 AB |
145 | } |
146 | ||
147 | static inline void gic_map_to_vpe(unsigned int intr, unsigned int vpe) | |
148 | { | |
149 | gic_write(GIC_REG(SHARED, GIC_SH_INTR_MAP_TO_VPE_BASE) + | |
150 | GIC_SH_MAP_TO_VPE_REG_OFF(intr, vpe), | |
151 | GIC_SH_MAP_TO_VPE_REG_BIT(vpe)); | |
152 | } | |
153 | ||
a331ce63 | 154 | #ifdef CONFIG_CLKSRC_MIPS_GIC |
dfa762e1 SH |
155 | cycle_t gic_read_count(void) |
156 | { | |
157 | unsigned int hi, hi2, lo; | |
158 | ||
6f50c835 MC |
159 | if (mips_cm_is64) |
160 | return (cycle_t)gic_read(GIC_REG(SHARED, GIC_SH_COUNTER)); | |
161 | ||
dfa762e1 | 162 | do { |
c3f57f02 MC |
163 | hi = gic_read32(GIC_REG(SHARED, GIC_SH_COUNTER_63_32)); |
164 | lo = gic_read32(GIC_REG(SHARED, GIC_SH_COUNTER_31_00)); | |
165 | hi2 = gic_read32(GIC_REG(SHARED, GIC_SH_COUNTER_63_32)); | |
dfa762e1 SH |
166 | } while (hi2 != hi); |
167 | ||
168 | return (((cycle_t) hi) << 32) + lo; | |
169 | } | |
0ab2b7d0 | 170 | |
387904ff AB |
171 | unsigned int gic_get_count_width(void) |
172 | { | |
173 | unsigned int bits, config; | |
174 | ||
5f68fea0 | 175 | config = gic_read(GIC_REG(SHARED, GIC_SH_CONFIG)); |
387904ff AB |
176 | bits = 32 + 4 * ((config & GIC_SH_CONFIG_COUNTBITS_MSK) >> |
177 | GIC_SH_CONFIG_COUNTBITS_SHF); | |
178 | ||
179 | return bits; | |
180 | } | |
181 | ||
0ab2b7d0 RG |
182 | void gic_write_compare(cycle_t cnt) |
183 | { | |
6f50c835 MC |
184 | if (mips_cm_is64) { |
185 | gic_write(GIC_REG(VPE_LOCAL, GIC_VPE_COMPARE), cnt); | |
186 | } else { | |
187 | gic_write32(GIC_REG(VPE_LOCAL, GIC_VPE_COMPARE_HI), | |
188 | (int)(cnt >> 32)); | |
189 | gic_write32(GIC_REG(VPE_LOCAL, GIC_VPE_COMPARE_LO), | |
190 | (int)(cnt & 0xffffffff)); | |
191 | } | |
0ab2b7d0 RG |
192 | } |
193 | ||
414408d0 PB |
194 | void gic_write_cpu_compare(cycle_t cnt, int cpu) |
195 | { | |
196 | unsigned long flags; | |
197 | ||
198 | local_irq_save(flags); | |
199 | ||
5f68fea0 | 200 | gic_write(GIC_REG(VPE_LOCAL, GIC_VPE_OTHER_ADDR), cpu); |
6f50c835 MC |
201 | |
202 | if (mips_cm_is64) { | |
203 | gic_write(GIC_REG(VPE_OTHER, GIC_VPE_COMPARE), cnt); | |
204 | } else { | |
205 | gic_write32(GIC_REG(VPE_OTHER, GIC_VPE_COMPARE_HI), | |
206 | (int)(cnt >> 32)); | |
207 | gic_write32(GIC_REG(VPE_OTHER, GIC_VPE_COMPARE_LO), | |
208 | (int)(cnt & 0xffffffff)); | |
209 | } | |
414408d0 PB |
210 | |
211 | local_irq_restore(flags); | |
212 | } | |
213 | ||
0ab2b7d0 RG |
214 | cycle_t gic_read_compare(void) |
215 | { | |
216 | unsigned int hi, lo; | |
217 | ||
6f50c835 MC |
218 | if (mips_cm_is64) |
219 | return (cycle_t)gic_read(GIC_REG(VPE_LOCAL, GIC_VPE_COMPARE)); | |
220 | ||
c3f57f02 MC |
221 | hi = gic_read32(GIC_REG(VPE_LOCAL, GIC_VPE_COMPARE_HI)); |
222 | lo = gic_read32(GIC_REG(VPE_LOCAL, GIC_VPE_COMPARE_LO)); | |
0ab2b7d0 RG |
223 | |
224 | return (((cycle_t) hi) << 32) + lo; | |
225 | } | |
8fa4b930 MC |
226 | |
227 | void gic_start_count(void) | |
228 | { | |
229 | u32 gicconfig; | |
230 | ||
231 | /* Start the counter */ | |
232 | gicconfig = gic_read(GIC_REG(SHARED, GIC_SH_CONFIG)); | |
233 | gicconfig &= ~(1 << GIC_SH_CONFIG_COUNTSTOP_SHF); | |
234 | gic_write(GIC_REG(SHARED, GIC_SH_CONFIG), gicconfig); | |
235 | } | |
236 | ||
237 | void gic_stop_count(void) | |
238 | { | |
239 | u32 gicconfig; | |
240 | ||
241 | /* Stop the counter */ | |
242 | gicconfig = gic_read(GIC_REG(SHARED, GIC_SH_CONFIG)); | |
243 | gicconfig |= 1 << GIC_SH_CONFIG_COUNTSTOP_SHF; | |
244 | gic_write(GIC_REG(SHARED, GIC_SH_CONFIG), gicconfig); | |
245 | } | |
246 | ||
dfa762e1 SH |
247 | #endif |
248 | ||
e9de688d AB |
249 | static bool gic_local_irq_is_routable(int intr) |
250 | { | |
251 | u32 vpe_ctl; | |
252 | ||
253 | /* All local interrupts are routable in EIC mode. */ | |
254 | if (cpu_has_veic) | |
255 | return true; | |
256 | ||
c3f57f02 | 257 | vpe_ctl = gic_read32(GIC_REG(VPE_LOCAL, GIC_VPE_CTL)); |
e9de688d AB |
258 | switch (intr) { |
259 | case GIC_LOCAL_INT_TIMER: | |
260 | return vpe_ctl & GIC_VPE_CTL_TIMER_RTBL_MSK; | |
261 | case GIC_LOCAL_INT_PERFCTR: | |
262 | return vpe_ctl & GIC_VPE_CTL_PERFCNT_RTBL_MSK; | |
263 | case GIC_LOCAL_INT_FDC: | |
264 | return vpe_ctl & GIC_VPE_CTL_FDC_RTBL_MSK; | |
265 | case GIC_LOCAL_INT_SWINT0: | |
266 | case GIC_LOCAL_INT_SWINT1: | |
267 | return vpe_ctl & GIC_VPE_CTL_SWINT_RTBL_MSK; | |
268 | default: | |
269 | return true; | |
270 | } | |
271 | } | |
272 | ||
3263d085 | 273 | static void gic_bind_eic_interrupt(int irq, int set) |
98b67c37 SH |
274 | { |
275 | /* Convert irq vector # to hw int # */ | |
276 | irq -= GIC_PIN_TO_VEC_OFFSET; | |
277 | ||
278 | /* Set irq to use shadow set */ | |
5f68fea0 AB |
279 | gic_write(GIC_REG(VPE_LOCAL, GIC_VPE_EIC_SHADOW_SET_BASE) + |
280 | GIC_VPE_EIC_SS(irq), set); | |
98b67c37 SH |
281 | } |
282 | ||
39b8d525 RB |
283 | void gic_send_ipi(unsigned int intr) |
284 | { | |
53a7bc81 | 285 | gic_write(GIC_REG(SHARED, GIC_SH_WEDGE), GIC_SH_WEDGE_SET(intr)); |
39b8d525 RB |
286 | } |
287 | ||
e9de688d AB |
288 | int gic_get_c0_compare_int(void) |
289 | { | |
290 | if (!gic_local_irq_is_routable(GIC_LOCAL_INT_TIMER)) | |
291 | return MIPS_CPU_IRQ_BASE + cp0_compare_irq; | |
292 | return irq_create_mapping(gic_irq_domain, | |
293 | GIC_LOCAL_TO_HWIRQ(GIC_LOCAL_INT_TIMER)); | |
294 | } | |
295 | ||
296 | int gic_get_c0_perfcount_int(void) | |
297 | { | |
298 | if (!gic_local_irq_is_routable(GIC_LOCAL_INT_PERFCTR)) { | |
7e3e6cb2 | 299 | /* Is the performance counter shared with the timer? */ |
e9de688d AB |
300 | if (cp0_perfcount_irq < 0) |
301 | return -1; | |
302 | return MIPS_CPU_IRQ_BASE + cp0_perfcount_irq; | |
303 | } | |
304 | return irq_create_mapping(gic_irq_domain, | |
305 | GIC_LOCAL_TO_HWIRQ(GIC_LOCAL_INT_PERFCTR)); | |
306 | } | |
307 | ||
6429e2b6 JH |
308 | int gic_get_c0_fdc_int(void) |
309 | { | |
310 | if (!gic_local_irq_is_routable(GIC_LOCAL_INT_FDC)) { | |
311 | /* Is the FDC IRQ even present? */ | |
312 | if (cp0_fdc_irq < 0) | |
313 | return -1; | |
314 | return MIPS_CPU_IRQ_BASE + cp0_fdc_irq; | |
315 | } | |
316 | ||
6429e2b6 JH |
317 | return irq_create_mapping(gic_irq_domain, |
318 | GIC_LOCAL_TO_HWIRQ(GIC_LOCAL_INT_FDC)); | |
319 | } | |
320 | ||
c0a9f72c AS |
321 | int gic_get_usm_range(struct resource *gic_usm_res) |
322 | { | |
323 | if (!gic_present) | |
324 | return -1; | |
325 | ||
326 | gic_usm_res->start = __gic_base_addr + USM_VISIBLE_SECTION_OFS; | |
327 | gic_usm_res->end = gic_usm_res->start + (USM_VISIBLE_SECTION_SIZE - 1); | |
328 | ||
329 | return 0; | |
330 | } | |
331 | ||
1b3ed367 | 332 | static void gic_handle_shared_int(bool chained) |
39b8d525 | 333 | { |
c3f57f02 | 334 | unsigned int i, intr, virq, gic_reg_step = mips_cm_is64 ? 8 : 4; |
8f5ee79c | 335 | unsigned long *pcpu_mask; |
5f68fea0 | 336 | unsigned long pending_reg, intrmask_reg; |
8f5ee79c AB |
337 | DECLARE_BITMAP(pending, GIC_MAX_INTRS); |
338 | DECLARE_BITMAP(intrmask, GIC_MAX_INTRS); | |
39b8d525 RB |
339 | |
340 | /* Get per-cpu bitmaps */ | |
39b8d525 RB |
341 | pcpu_mask = pcpu_masks[smp_processor_id()].pcpu_mask; |
342 | ||
824f3f7f AB |
343 | pending_reg = GIC_REG(SHARED, GIC_SH_PEND); |
344 | intrmask_reg = GIC_REG(SHARED, GIC_SH_MASK); | |
39b8d525 | 345 | |
fbd55241 | 346 | for (i = 0; i < BITS_TO_LONGS(gic_shared_intrs); i++) { |
5f68fea0 AB |
347 | pending[i] = gic_read(pending_reg); |
348 | intrmask[i] = gic_read(intrmask_reg); | |
c3f57f02 MC |
349 | pending_reg += gic_reg_step; |
350 | intrmask_reg += gic_reg_step; | |
d77d5ac9 PB |
351 | |
352 | if (!config_enabled(CONFIG_64BIT) || mips_cm_is64) | |
353 | continue; | |
354 | ||
355 | pending[i] |= (u64)gic_read(pending_reg) << 32; | |
356 | intrmask[i] |= (u64)gic_read(intrmask_reg) << 32; | |
357 | pending_reg += gic_reg_step; | |
358 | intrmask_reg += gic_reg_step; | |
39b8d525 RB |
359 | } |
360 | ||
fbd55241 AB |
361 | bitmap_and(pending, pending, intrmask, gic_shared_intrs); |
362 | bitmap_and(pending, pending, pcpu_mask, gic_shared_intrs); | |
39b8d525 | 363 | |
d7eb4f2e QY |
364 | intr = find_first_bit(pending, gic_shared_intrs); |
365 | while (intr != gic_shared_intrs) { | |
366 | virq = irq_linear_revmap(gic_irq_domain, | |
367 | GIC_SHARED_TO_HWIRQ(intr)); | |
1b3ed367 RV |
368 | if (chained) |
369 | generic_handle_irq(virq); | |
370 | else | |
371 | do_IRQ(virq); | |
d7eb4f2e QY |
372 | |
373 | /* go to next pending bit */ | |
374 | bitmap_clear(pending, intr, 1); | |
375 | intr = find_first_bit(pending, gic_shared_intrs); | |
376 | } | |
39b8d525 RB |
377 | } |
378 | ||
161d049e | 379 | static void gic_mask_irq(struct irq_data *d) |
39b8d525 | 380 | { |
5f68fea0 | 381 | gic_reset_mask(GIC_HWIRQ_TO_SHARED(d->hwirq)); |
39b8d525 RB |
382 | } |
383 | ||
161d049e | 384 | static void gic_unmask_irq(struct irq_data *d) |
39b8d525 | 385 | { |
5f68fea0 | 386 | gic_set_mask(GIC_HWIRQ_TO_SHARED(d->hwirq)); |
39b8d525 RB |
387 | } |
388 | ||
5561c9e4 AB |
389 | static void gic_ack_irq(struct irq_data *d) |
390 | { | |
e9de688d | 391 | unsigned int irq = GIC_HWIRQ_TO_SHARED(d->hwirq); |
c49581a4 | 392 | |
53a7bc81 | 393 | gic_write(GIC_REG(SHARED, GIC_SH_WEDGE), GIC_SH_WEDGE_CLR(irq)); |
5561c9e4 AB |
394 | } |
395 | ||
95150ae8 AB |
396 | static int gic_set_type(struct irq_data *d, unsigned int type) |
397 | { | |
e9de688d | 398 | unsigned int irq = GIC_HWIRQ_TO_SHARED(d->hwirq); |
95150ae8 AB |
399 | unsigned long flags; |
400 | bool is_edge; | |
401 | ||
402 | spin_lock_irqsave(&gic_lock, flags); | |
403 | switch (type & IRQ_TYPE_SENSE_MASK) { | |
404 | case IRQ_TYPE_EDGE_FALLING: | |
5f68fea0 AB |
405 | gic_set_polarity(irq, GIC_POL_NEG); |
406 | gic_set_trigger(irq, GIC_TRIG_EDGE); | |
407 | gic_set_dual_edge(irq, GIC_TRIG_DUAL_DISABLE); | |
95150ae8 AB |
408 | is_edge = true; |
409 | break; | |
410 | case IRQ_TYPE_EDGE_RISING: | |
5f68fea0 AB |
411 | gic_set_polarity(irq, GIC_POL_POS); |
412 | gic_set_trigger(irq, GIC_TRIG_EDGE); | |
413 | gic_set_dual_edge(irq, GIC_TRIG_DUAL_DISABLE); | |
95150ae8 AB |
414 | is_edge = true; |
415 | break; | |
416 | case IRQ_TYPE_EDGE_BOTH: | |
417 | /* polarity is irrelevant in this case */ | |
5f68fea0 AB |
418 | gic_set_trigger(irq, GIC_TRIG_EDGE); |
419 | gic_set_dual_edge(irq, GIC_TRIG_DUAL_ENABLE); | |
95150ae8 AB |
420 | is_edge = true; |
421 | break; | |
422 | case IRQ_TYPE_LEVEL_LOW: | |
5f68fea0 AB |
423 | gic_set_polarity(irq, GIC_POL_NEG); |
424 | gic_set_trigger(irq, GIC_TRIG_LEVEL); | |
425 | gic_set_dual_edge(irq, GIC_TRIG_DUAL_DISABLE); | |
95150ae8 AB |
426 | is_edge = false; |
427 | break; | |
428 | case IRQ_TYPE_LEVEL_HIGH: | |
429 | default: | |
5f68fea0 AB |
430 | gic_set_polarity(irq, GIC_POL_POS); |
431 | gic_set_trigger(irq, GIC_TRIG_LEVEL); | |
432 | gic_set_dual_edge(irq, GIC_TRIG_DUAL_DISABLE); | |
95150ae8 AB |
433 | is_edge = false; |
434 | break; | |
435 | } | |
436 | ||
a595fc51 TG |
437 | if (is_edge) |
438 | irq_set_chip_handler_name_locked(d, &gic_edge_irq_controller, | |
439 | handle_edge_irq, NULL); | |
440 | else | |
441 | irq_set_chip_handler_name_locked(d, &gic_level_irq_controller, | |
442 | handle_level_irq, NULL); | |
95150ae8 | 443 | spin_unlock_irqrestore(&gic_lock, flags); |
39b8d525 | 444 | |
95150ae8 AB |
445 | return 0; |
446 | } | |
447 | ||
448 | #ifdef CONFIG_SMP | |
161d049e TG |
449 | static int gic_set_affinity(struct irq_data *d, const struct cpumask *cpumask, |
450 | bool force) | |
39b8d525 | 451 | { |
e9de688d | 452 | unsigned int irq = GIC_HWIRQ_TO_SHARED(d->hwirq); |
39b8d525 RB |
453 | cpumask_t tmp = CPU_MASK_NONE; |
454 | unsigned long flags; | |
455 | int i; | |
456 | ||
0de26520 | 457 | cpumask_and(&tmp, cpumask, cpu_online_mask); |
f9b531fe | 458 | if (cpumask_empty(&tmp)) |
14d160ab | 459 | return -EINVAL; |
39b8d525 RB |
460 | |
461 | /* Assumption : cpumask refers to a single CPU */ | |
462 | spin_lock_irqsave(&gic_lock, flags); | |
39b8d525 | 463 | |
c214c035 | 464 | /* Re-route this IRQ */ |
ab41f6c8 | 465 | gic_map_to_vpe(irq, mips_cm_vp_id(cpumask_first(&tmp))); |
c214c035 TW |
466 | |
467 | /* Update the pcpu_masks */ | |
2a078705 | 468 | for (i = 0; i < gic_vpes; i++) |
c214c035 | 469 | clear_bit(irq, pcpu_masks[i].pcpu_mask); |
f9b531fe | 470 | set_bit(irq, pcpu_masks[cpumask_first(&tmp)].pcpu_mask); |
39b8d525 | 471 | |
72f86db4 | 472 | cpumask_copy(irq_data_get_affinity_mask(d), cpumask); |
39b8d525 RB |
473 | spin_unlock_irqrestore(&gic_lock, flags); |
474 | ||
161d049e | 475 | return IRQ_SET_MASK_OK_NOCOPY; |
39b8d525 RB |
476 | } |
477 | #endif | |
478 | ||
4a6a3ea3 AB |
479 | static struct irq_chip gic_level_irq_controller = { |
480 | .name = "MIPS GIC", | |
481 | .irq_mask = gic_mask_irq, | |
482 | .irq_unmask = gic_unmask_irq, | |
483 | .irq_set_type = gic_set_type, | |
484 | #ifdef CONFIG_SMP | |
485 | .irq_set_affinity = gic_set_affinity, | |
486 | #endif | |
487 | }; | |
488 | ||
489 | static struct irq_chip gic_edge_irq_controller = { | |
161d049e | 490 | .name = "MIPS GIC", |
5561c9e4 | 491 | .irq_ack = gic_ack_irq, |
161d049e | 492 | .irq_mask = gic_mask_irq, |
161d049e | 493 | .irq_unmask = gic_unmask_irq, |
95150ae8 | 494 | .irq_set_type = gic_set_type, |
39b8d525 | 495 | #ifdef CONFIG_SMP |
161d049e | 496 | .irq_set_affinity = gic_set_affinity, |
39b8d525 RB |
497 | #endif |
498 | }; | |
499 | ||
1b3ed367 | 500 | static void gic_handle_local_int(bool chained) |
e9de688d AB |
501 | { |
502 | unsigned long pending, masked; | |
d7eb4f2e | 503 | unsigned int intr, virq; |
e9de688d | 504 | |
c3f57f02 MC |
505 | pending = gic_read32(GIC_REG(VPE_LOCAL, GIC_VPE_PEND)); |
506 | masked = gic_read32(GIC_REG(VPE_LOCAL, GIC_VPE_MASK)); | |
e9de688d AB |
507 | |
508 | bitmap_and(&pending, &pending, &masked, GIC_NUM_LOCAL_INTRS); | |
509 | ||
d7eb4f2e QY |
510 | intr = find_first_bit(&pending, GIC_NUM_LOCAL_INTRS); |
511 | while (intr != GIC_NUM_LOCAL_INTRS) { | |
512 | virq = irq_linear_revmap(gic_irq_domain, | |
513 | GIC_LOCAL_TO_HWIRQ(intr)); | |
1b3ed367 RV |
514 | if (chained) |
515 | generic_handle_irq(virq); | |
516 | else | |
517 | do_IRQ(virq); | |
d7eb4f2e QY |
518 | |
519 | /* go to next pending bit */ | |
520 | bitmap_clear(&pending, intr, 1); | |
521 | intr = find_first_bit(&pending, GIC_NUM_LOCAL_INTRS); | |
522 | } | |
e9de688d AB |
523 | } |
524 | ||
525 | static void gic_mask_local_irq(struct irq_data *d) | |
526 | { | |
527 | int intr = GIC_HWIRQ_TO_LOCAL(d->hwirq); | |
528 | ||
c3f57f02 | 529 | gic_write32(GIC_REG(VPE_LOCAL, GIC_VPE_RMASK), 1 << intr); |
e9de688d AB |
530 | } |
531 | ||
532 | static void gic_unmask_local_irq(struct irq_data *d) | |
533 | { | |
534 | int intr = GIC_HWIRQ_TO_LOCAL(d->hwirq); | |
535 | ||
c3f57f02 | 536 | gic_write32(GIC_REG(VPE_LOCAL, GIC_VPE_SMASK), 1 << intr); |
e9de688d AB |
537 | } |
538 | ||
539 | static struct irq_chip gic_local_irq_controller = { | |
540 | .name = "MIPS GIC Local", | |
541 | .irq_mask = gic_mask_local_irq, | |
542 | .irq_unmask = gic_unmask_local_irq, | |
543 | }; | |
544 | ||
545 | static void gic_mask_local_irq_all_vpes(struct irq_data *d) | |
546 | { | |
547 | int intr = GIC_HWIRQ_TO_LOCAL(d->hwirq); | |
548 | int i; | |
549 | unsigned long flags; | |
550 | ||
551 | spin_lock_irqsave(&gic_lock, flags); | |
552 | for (i = 0; i < gic_vpes; i++) { | |
5f68fea0 | 553 | gic_write(GIC_REG(VPE_LOCAL, GIC_VPE_OTHER_ADDR), i); |
c3f57f02 | 554 | gic_write32(GIC_REG(VPE_OTHER, GIC_VPE_RMASK), 1 << intr); |
e9de688d AB |
555 | } |
556 | spin_unlock_irqrestore(&gic_lock, flags); | |
557 | } | |
558 | ||
559 | static void gic_unmask_local_irq_all_vpes(struct irq_data *d) | |
560 | { | |
561 | int intr = GIC_HWIRQ_TO_LOCAL(d->hwirq); | |
562 | int i; | |
563 | unsigned long flags; | |
564 | ||
565 | spin_lock_irqsave(&gic_lock, flags); | |
566 | for (i = 0; i < gic_vpes; i++) { | |
5f68fea0 | 567 | gic_write(GIC_REG(VPE_LOCAL, GIC_VPE_OTHER_ADDR), i); |
c3f57f02 | 568 | gic_write32(GIC_REG(VPE_OTHER, GIC_VPE_SMASK), 1 << intr); |
e9de688d AB |
569 | } |
570 | spin_unlock_irqrestore(&gic_lock, flags); | |
571 | } | |
572 | ||
573 | static struct irq_chip gic_all_vpes_local_irq_controller = { | |
574 | .name = "MIPS GIC Local", | |
575 | .irq_mask = gic_mask_local_irq_all_vpes, | |
576 | .irq_unmask = gic_unmask_local_irq_all_vpes, | |
577 | }; | |
578 | ||
18743d27 | 579 | static void __gic_irq_dispatch(void) |
39b8d525 | 580 | { |
1b3ed367 RV |
581 | gic_handle_local_int(false); |
582 | gic_handle_shared_int(false); | |
18743d27 | 583 | } |
39b8d525 | 584 | |
bd0b9ac4 | 585 | static void gic_irq_dispatch(struct irq_desc *desc) |
18743d27 | 586 | { |
1b3ed367 RV |
587 | gic_handle_local_int(true); |
588 | gic_handle_shared_int(true); | |
18743d27 AB |
589 | } |
590 | ||
591 | #ifdef CONFIG_MIPS_GIC_IPI | |
592 | static int gic_resched_int_base; | |
593 | static int gic_call_int_base; | |
594 | ||
595 | unsigned int plat_ipi_resched_int_xlate(unsigned int cpu) | |
596 | { | |
597 | return gic_resched_int_base + cpu; | |
598 | } | |
39b8d525 | 599 | |
18743d27 AB |
600 | unsigned int plat_ipi_call_int_xlate(unsigned int cpu) |
601 | { | |
602 | return gic_call_int_base + cpu; | |
603 | } | |
39b8d525 | 604 | |
18743d27 AB |
605 | static irqreturn_t ipi_resched_interrupt(int irq, void *dev_id) |
606 | { | |
607 | scheduler_ipi(); | |
608 | ||
609 | return IRQ_HANDLED; | |
610 | } | |
611 | ||
612 | static irqreturn_t ipi_call_interrupt(int irq, void *dev_id) | |
613 | { | |
4ace6139 | 614 | generic_smp_call_function_interrupt(); |
18743d27 AB |
615 | |
616 | return IRQ_HANDLED; | |
617 | } | |
b0a88ae5 | 618 | |
18743d27 AB |
619 | static struct irqaction irq_resched = { |
620 | .handler = ipi_resched_interrupt, | |
621 | .flags = IRQF_PERCPU, | |
622 | .name = "IPI resched" | |
623 | }; | |
624 | ||
625 | static struct irqaction irq_call = { | |
626 | .handler = ipi_call_interrupt, | |
627 | .flags = IRQF_PERCPU, | |
628 | .name = "IPI call" | |
629 | }; | |
630 | ||
631 | static __init void gic_ipi_init_one(unsigned int intr, int cpu, | |
632 | struct irqaction *action) | |
633 | { | |
e9de688d AB |
634 | int virq = irq_create_mapping(gic_irq_domain, |
635 | GIC_SHARED_TO_HWIRQ(intr)); | |
18743d27 AB |
636 | int i; |
637 | ||
ab41f6c8 | 638 | gic_map_to_vpe(intr, mips_cm_vp_id(cpu)); |
c49581a4 AB |
639 | for (i = 0; i < NR_CPUS; i++) |
640 | clear_bit(intr, pcpu_masks[i].pcpu_mask); | |
b0a88ae5 JD |
641 | set_bit(intr, pcpu_masks[cpu].pcpu_mask); |
642 | ||
18743d27 AB |
643 | irq_set_irq_type(virq, IRQ_TYPE_EDGE_RISING); |
644 | ||
645 | irq_set_handler(virq, handle_percpu_irq); | |
646 | setup_irq(virq, action); | |
39b8d525 RB |
647 | } |
648 | ||
18743d27 | 649 | static __init void gic_ipi_init(void) |
39b8d525 | 650 | { |
18743d27 AB |
651 | int i; |
652 | ||
653 | /* Use last 2 * NR_CPUS interrupts as IPIs */ | |
fbd55241 | 654 | gic_resched_int_base = gic_shared_intrs - nr_cpu_ids; |
18743d27 AB |
655 | gic_call_int_base = gic_resched_int_base - nr_cpu_ids; |
656 | ||
657 | for (i = 0; i < nr_cpu_ids; i++) { | |
658 | gic_ipi_init_one(gic_call_int_base + i, i, &irq_call); | |
659 | gic_ipi_init_one(gic_resched_int_base + i, i, &irq_resched); | |
660 | } | |
661 | } | |
662 | #else | |
663 | static inline void gic_ipi_init(void) | |
664 | { | |
665 | } | |
666 | #endif | |
667 | ||
e9de688d | 668 | static void __init gic_basic_init(void) |
18743d27 AB |
669 | { |
670 | unsigned int i; | |
98b67c37 SH |
671 | |
672 | board_bind_eic_interrupt = &gic_bind_eic_interrupt; | |
39b8d525 RB |
673 | |
674 | /* Setup defaults */ | |
fbd55241 | 675 | for (i = 0; i < gic_shared_intrs; i++) { |
5f68fea0 AB |
676 | gic_set_polarity(i, GIC_POL_POS); |
677 | gic_set_trigger(i, GIC_TRIG_LEVEL); | |
678 | gic_reset_mask(i); | |
39b8d525 RB |
679 | } |
680 | ||
e9de688d AB |
681 | for (i = 0; i < gic_vpes; i++) { |
682 | unsigned int j; | |
683 | ||
5f68fea0 | 684 | gic_write(GIC_REG(VPE_LOCAL, GIC_VPE_OTHER_ADDR), i); |
e9de688d AB |
685 | for (j = 0; j < GIC_NUM_LOCAL_INTRS; j++) { |
686 | if (!gic_local_irq_is_routable(j)) | |
687 | continue; | |
c3f57f02 | 688 | gic_write32(GIC_REG(VPE_OTHER, GIC_VPE_RMASK), 1 << j); |
e9de688d AB |
689 | } |
690 | } | |
39b8d525 RB |
691 | } |
692 | ||
e9de688d AB |
693 | static int gic_local_irq_domain_map(struct irq_domain *d, unsigned int virq, |
694 | irq_hw_number_t hw) | |
c49581a4 | 695 | { |
e9de688d AB |
696 | int intr = GIC_HWIRQ_TO_LOCAL(hw); |
697 | int ret = 0; | |
698 | int i; | |
699 | unsigned long flags; | |
700 | ||
701 | if (!gic_local_irq_is_routable(intr)) | |
702 | return -EPERM; | |
703 | ||
704 | /* | |
705 | * HACK: These are all really percpu interrupts, but the rest | |
706 | * of the MIPS kernel code does not use the percpu IRQ API for | |
707 | * the CP0 timer and performance counter interrupts. | |
708 | */ | |
b720fd8b JH |
709 | switch (intr) { |
710 | case GIC_LOCAL_INT_TIMER: | |
711 | case GIC_LOCAL_INT_PERFCTR: | |
712 | case GIC_LOCAL_INT_FDC: | |
713 | irq_set_chip_and_handler(virq, | |
714 | &gic_all_vpes_local_irq_controller, | |
715 | handle_percpu_irq); | |
716 | break; | |
717 | default: | |
e9de688d AB |
718 | irq_set_chip_and_handler(virq, |
719 | &gic_local_irq_controller, | |
720 | handle_percpu_devid_irq); | |
721 | irq_set_percpu_devid(virq); | |
b720fd8b | 722 | break; |
e9de688d AB |
723 | } |
724 | ||
725 | spin_lock_irqsave(&gic_lock, flags); | |
726 | for (i = 0; i < gic_vpes; i++) { | |
727 | u32 val = GIC_MAP_TO_PIN_MSK | gic_cpu_pin; | |
728 | ||
5f68fea0 | 729 | gic_write(GIC_REG(VPE_LOCAL, GIC_VPE_OTHER_ADDR), i); |
e9de688d AB |
730 | |
731 | switch (intr) { | |
732 | case GIC_LOCAL_INT_WD: | |
c3f57f02 | 733 | gic_write32(GIC_REG(VPE_OTHER, GIC_VPE_WD_MAP), val); |
e9de688d AB |
734 | break; |
735 | case GIC_LOCAL_INT_COMPARE: | |
c3f57f02 MC |
736 | gic_write32(GIC_REG(VPE_OTHER, GIC_VPE_COMPARE_MAP), |
737 | val); | |
e9de688d AB |
738 | break; |
739 | case GIC_LOCAL_INT_TIMER: | |
1b6af71a JH |
740 | /* CONFIG_MIPS_CMP workaround (see __gic_init) */ |
741 | val = GIC_MAP_TO_PIN_MSK | timer_cpu_pin; | |
c3f57f02 MC |
742 | gic_write32(GIC_REG(VPE_OTHER, GIC_VPE_TIMER_MAP), |
743 | val); | |
e9de688d AB |
744 | break; |
745 | case GIC_LOCAL_INT_PERFCTR: | |
c3f57f02 MC |
746 | gic_write32(GIC_REG(VPE_OTHER, GIC_VPE_PERFCTR_MAP), |
747 | val); | |
e9de688d AB |
748 | break; |
749 | case GIC_LOCAL_INT_SWINT0: | |
c3f57f02 MC |
750 | gic_write32(GIC_REG(VPE_OTHER, GIC_VPE_SWINT0_MAP), |
751 | val); | |
e9de688d AB |
752 | break; |
753 | case GIC_LOCAL_INT_SWINT1: | |
c3f57f02 MC |
754 | gic_write32(GIC_REG(VPE_OTHER, GIC_VPE_SWINT1_MAP), |
755 | val); | |
e9de688d AB |
756 | break; |
757 | case GIC_LOCAL_INT_FDC: | |
c3f57f02 | 758 | gic_write32(GIC_REG(VPE_OTHER, GIC_VPE_FDC_MAP), val); |
e9de688d AB |
759 | break; |
760 | default: | |
761 | pr_err("Invalid local IRQ %d\n", intr); | |
762 | ret = -EINVAL; | |
763 | break; | |
764 | } | |
765 | } | |
766 | spin_unlock_irqrestore(&gic_lock, flags); | |
767 | ||
768 | return ret; | |
769 | } | |
770 | ||
771 | static int gic_shared_irq_domain_map(struct irq_domain *d, unsigned int virq, | |
2af70a96 | 772 | irq_hw_number_t hw, unsigned int vpe) |
e9de688d AB |
773 | { |
774 | int intr = GIC_HWIRQ_TO_SHARED(hw); | |
c49581a4 | 775 | unsigned long flags; |
78930f09 | 776 | int i; |
c49581a4 | 777 | |
4a6a3ea3 AB |
778 | irq_set_chip_and_handler(virq, &gic_level_irq_controller, |
779 | handle_level_irq); | |
c49581a4 AB |
780 | |
781 | spin_lock_irqsave(&gic_lock, flags); | |
5f68fea0 | 782 | gic_map_to_pin(intr, gic_cpu_pin); |
2af70a96 | 783 | gic_map_to_vpe(intr, vpe); |
78930f09 QY |
784 | for (i = 0; i < gic_vpes; i++) |
785 | clear_bit(intr, pcpu_masks[i].pcpu_mask); | |
2af70a96 | 786 | set_bit(intr, pcpu_masks[vpe].pcpu_mask); |
c49581a4 AB |
787 | spin_unlock_irqrestore(&gic_lock, flags); |
788 | ||
789 | return 0; | |
790 | } | |
791 | ||
e9de688d AB |
792 | static int gic_irq_domain_map(struct irq_domain *d, unsigned int virq, |
793 | irq_hw_number_t hw) | |
794 | { | |
795 | if (GIC_HWIRQ_TO_LOCAL(hw) < GIC_NUM_LOCAL_INTRS) | |
796 | return gic_local_irq_domain_map(d, virq, hw); | |
2af70a96 | 797 | return gic_shared_irq_domain_map(d, virq, hw, 0); |
e9de688d AB |
798 | } |
799 | ||
2af70a96 QY |
800 | static int gic_irq_domain_alloc(struct irq_domain *d, unsigned int virq, |
801 | unsigned int nr_irqs, void *arg) | |
802 | { | |
803 | struct gic_irq_spec *spec = arg; | |
804 | irq_hw_number_t hwirq, base_hwirq; | |
805 | int cpu, ret, i; | |
806 | ||
807 | if (spec->type == GIC_DEVICE) { | |
808 | /* verify that it doesn't conflict with an IPI irq */ | |
809 | if (test_bit(spec->hwirq, ipi_resrv)) | |
810 | return -EBUSY; | |
811 | } else { | |
812 | base_hwirq = find_first_bit(ipi_resrv, gic_shared_intrs); | |
813 | if (base_hwirq == gic_shared_intrs) { | |
814 | return -ENOMEM; | |
815 | } | |
816 | ||
817 | /* check that we have enough space */ | |
818 | for (i = base_hwirq; i < nr_irqs; i++) { | |
819 | if (!test_bit(i, ipi_resrv)) | |
820 | return -EBUSY; | |
821 | } | |
822 | bitmap_clear(ipi_resrv, base_hwirq, nr_irqs); | |
823 | ||
824 | /* map the hwirq for each cpu consecutively */ | |
825 | i = 0; | |
826 | for_each_cpu(cpu, spec->ipimask) { | |
827 | hwirq = GIC_SHARED_TO_HWIRQ(base_hwirq + i); | |
828 | ||
829 | ret = irq_domain_set_hwirq_and_chip(d, virq + i, hwirq, | |
830 | &gic_edge_irq_controller, | |
831 | NULL); | |
832 | if (ret) | |
833 | goto error; | |
834 | ||
835 | ret = gic_shared_irq_domain_map(d, virq + i, hwirq, cpu); | |
836 | if (ret) | |
837 | goto error; | |
838 | ||
839 | i++; | |
840 | } | |
841 | ||
842 | /* | |
843 | * tell the parent about the base hwirq we allocated so it can | |
844 | * set its own domain data | |
845 | */ | |
846 | spec->hwirq = base_hwirq; | |
847 | } | |
848 | ||
849 | return 0; | |
850 | error: | |
851 | bitmap_set(ipi_resrv, base_hwirq, nr_irqs); | |
852 | return ret; | |
853 | } | |
854 | ||
855 | void gic_irq_domain_free(struct irq_domain *d, unsigned int virq, | |
856 | unsigned int nr_irqs) | |
857 | { | |
858 | irq_hw_number_t base_hwirq; | |
859 | struct irq_data *data; | |
860 | ||
861 | data = irq_get_irq_data(virq); | |
862 | if (!data) | |
863 | return; | |
864 | ||
865 | base_hwirq = GIC_HWIRQ_TO_SHARED(irqd_to_hwirq(data)); | |
866 | bitmap_set(ipi_resrv, base_hwirq, nr_irqs); | |
867 | } | |
868 | ||
c98c1822 QY |
869 | int gic_irq_domain_match(struct irq_domain *d, struct device_node *node, |
870 | enum irq_domain_bus_token bus_token) | |
871 | { | |
872 | /* this domain should'nt be accessed directly */ | |
873 | return 0; | |
874 | } | |
875 | ||
96009736 | 876 | static const struct irq_domain_ops gic_irq_domain_ops = { |
c49581a4 | 877 | .map = gic_irq_domain_map, |
2af70a96 QY |
878 | .alloc = gic_irq_domain_alloc, |
879 | .free = gic_irq_domain_free, | |
c98c1822 QY |
880 | .match = gic_irq_domain_match, |
881 | }; | |
882 | ||
883 | static int gic_dev_domain_xlate(struct irq_domain *d, struct device_node *ctrlr, | |
884 | const u32 *intspec, unsigned int intsize, | |
885 | irq_hw_number_t *out_hwirq, | |
886 | unsigned int *out_type) | |
887 | { | |
888 | if (intsize != 3) | |
889 | return -EINVAL; | |
890 | ||
891 | if (intspec[0] == GIC_SHARED) | |
892 | *out_hwirq = GIC_SHARED_TO_HWIRQ(intspec[1]); | |
893 | else if (intspec[0] == GIC_LOCAL) | |
894 | *out_hwirq = GIC_LOCAL_TO_HWIRQ(intspec[1]); | |
895 | else | |
896 | return -EINVAL; | |
897 | *out_type = intspec[2] & IRQ_TYPE_SENSE_MASK; | |
898 | ||
899 | return 0; | |
900 | } | |
901 | ||
902 | static int gic_dev_domain_alloc(struct irq_domain *d, unsigned int virq, | |
903 | unsigned int nr_irqs, void *arg) | |
904 | { | |
905 | struct irq_fwspec *fwspec = arg; | |
906 | struct gic_irq_spec spec = { | |
907 | .type = GIC_DEVICE, | |
908 | .hwirq = fwspec->param[1], | |
909 | }; | |
910 | int i, ret; | |
911 | bool is_shared = fwspec->param[0] == GIC_SHARED; | |
912 | ||
913 | if (is_shared) { | |
914 | ret = irq_domain_alloc_irqs_parent(d, virq, nr_irqs, &spec); | |
915 | if (ret) | |
916 | return ret; | |
917 | } | |
918 | ||
919 | for (i = 0; i < nr_irqs; i++) { | |
920 | irq_hw_number_t hwirq; | |
921 | ||
922 | if (is_shared) | |
923 | hwirq = GIC_SHARED_TO_HWIRQ(spec.hwirq + i); | |
924 | else | |
925 | hwirq = GIC_LOCAL_TO_HWIRQ(spec.hwirq + i); | |
926 | ||
927 | ret = irq_domain_set_hwirq_and_chip(d, virq + i, | |
928 | hwirq, | |
929 | &gic_level_irq_controller, | |
930 | NULL); | |
931 | if (ret) | |
932 | return ret; | |
933 | } | |
934 | ||
935 | return 0; | |
936 | } | |
937 | ||
938 | void gic_dev_domain_free(struct irq_domain *d, unsigned int virq, | |
939 | unsigned int nr_irqs) | |
940 | { | |
941 | /* no real allocation is done for dev irqs, so no need to free anything */ | |
942 | return; | |
943 | } | |
944 | ||
945 | static struct irq_domain_ops gic_dev_domain_ops = { | |
946 | .xlate = gic_dev_domain_xlate, | |
947 | .alloc = gic_dev_domain_alloc, | |
948 | .free = gic_dev_domain_free, | |
2af70a96 QY |
949 | }; |
950 | ||
951 | static int gic_ipi_domain_xlate(struct irq_domain *d, struct device_node *ctrlr, | |
952 | const u32 *intspec, unsigned int intsize, | |
953 | irq_hw_number_t *out_hwirq, | |
954 | unsigned int *out_type) | |
955 | { | |
956 | /* | |
957 | * There's nothing to translate here. hwirq is dynamically allocated and | |
958 | * the irq type is always edge triggered. | |
959 | * */ | |
960 | *out_hwirq = 0; | |
961 | *out_type = IRQ_TYPE_EDGE_RISING; | |
962 | ||
963 | return 0; | |
964 | } | |
965 | ||
966 | static int gic_ipi_domain_alloc(struct irq_domain *d, unsigned int virq, | |
967 | unsigned int nr_irqs, void *arg) | |
968 | { | |
969 | struct cpumask *ipimask = arg; | |
970 | struct gic_irq_spec spec = { | |
971 | .type = GIC_IPI, | |
972 | .ipimask = ipimask | |
973 | }; | |
974 | int ret, i; | |
975 | ||
976 | ret = irq_domain_alloc_irqs_parent(d, virq, nr_irqs, &spec); | |
977 | if (ret) | |
978 | return ret; | |
979 | ||
980 | /* the parent should have set spec.hwirq to the base_hwirq it allocated */ | |
981 | for (i = 0; i < nr_irqs; i++) { | |
982 | ret = irq_domain_set_hwirq_and_chip(d, virq + i, | |
983 | GIC_SHARED_TO_HWIRQ(spec.hwirq + i), | |
984 | &gic_edge_irq_controller, | |
985 | NULL); | |
986 | if (ret) | |
987 | goto error; | |
988 | ||
989 | ret = irq_set_irq_type(virq + i, IRQ_TYPE_EDGE_RISING); | |
990 | if (ret) | |
991 | goto error; | |
992 | } | |
993 | ||
994 | return 0; | |
995 | error: | |
996 | irq_domain_free_irqs_parent(d, virq, nr_irqs); | |
997 | return ret; | |
998 | } | |
999 | ||
1000 | void gic_ipi_domain_free(struct irq_domain *d, unsigned int virq, | |
1001 | unsigned int nr_irqs) | |
1002 | { | |
1003 | irq_domain_free_irqs_parent(d, virq, nr_irqs); | |
1004 | } | |
1005 | ||
1006 | int gic_ipi_domain_match(struct irq_domain *d, struct device_node *node, | |
1007 | enum irq_domain_bus_token bus_token) | |
1008 | { | |
1009 | bool is_ipi; | |
1010 | ||
1011 | switch (bus_token) { | |
1012 | case DOMAIN_BUS_IPI: | |
1013 | is_ipi = d->bus_token == bus_token; | |
1014 | return to_of_node(d->fwnode) == node && is_ipi; | |
1015 | break; | |
1016 | default: | |
1017 | return 0; | |
1018 | } | |
1019 | } | |
1020 | ||
1021 | static struct irq_domain_ops gic_ipi_domain_ops = { | |
1022 | .xlate = gic_ipi_domain_xlate, | |
1023 | .alloc = gic_ipi_domain_alloc, | |
1024 | .free = gic_ipi_domain_free, | |
1025 | .match = gic_ipi_domain_match, | |
c49581a4 AB |
1026 | }; |
1027 | ||
a7057270 AB |
1028 | static void __init __gic_init(unsigned long gic_base_addr, |
1029 | unsigned long gic_addrspace_size, | |
1030 | unsigned int cpu_vec, unsigned int irqbase, | |
1031 | struct device_node *node) | |
39b8d525 RB |
1032 | { |
1033 | unsigned int gicconfig; | |
1034 | ||
c0a9f72c AS |
1035 | __gic_base_addr = gic_base_addr; |
1036 | ||
5f68fea0 | 1037 | gic_base = ioremap_nocache(gic_base_addr, gic_addrspace_size); |
39b8d525 | 1038 | |
5f68fea0 | 1039 | gicconfig = gic_read(GIC_REG(SHARED, GIC_SH_CONFIG)); |
fbd55241 | 1040 | gic_shared_intrs = (gicconfig & GIC_SH_CONFIG_NUMINTRS_MSK) >> |
39b8d525 | 1041 | GIC_SH_CONFIG_NUMINTRS_SHF; |
fbd55241 | 1042 | gic_shared_intrs = ((gic_shared_intrs + 1) * 8); |
39b8d525 | 1043 | |
e9de688d | 1044 | gic_vpes = (gicconfig & GIC_SH_CONFIG_NUMVPES_MSK) >> |
39b8d525 | 1045 | GIC_SH_CONFIG_NUMVPES_SHF; |
e9de688d | 1046 | gic_vpes = gic_vpes + 1; |
39b8d525 | 1047 | |
18743d27 AB |
1048 | if (cpu_has_veic) { |
1049 | /* Always use vector 1 in EIC mode */ | |
1050 | gic_cpu_pin = 0; | |
1b6af71a | 1051 | timer_cpu_pin = gic_cpu_pin; |
18743d27 AB |
1052 | set_vi_handler(gic_cpu_pin + GIC_PIN_TO_VEC_OFFSET, |
1053 | __gic_irq_dispatch); | |
1054 | } else { | |
1055 | gic_cpu_pin = cpu_vec - GIC_CPU_PIN_OFFSET; | |
1056 | irq_set_chained_handler(MIPS_CPU_IRQ_BASE + cpu_vec, | |
1057 | gic_irq_dispatch); | |
1b6af71a JH |
1058 | /* |
1059 | * With the CMP implementation of SMP (deprecated), other CPUs | |
1060 | * are started by the bootloader and put into a timer based | |
1061 | * waiting poll loop. We must not re-route those CPU's local | |
1062 | * timer interrupts as the wait instruction will never finish, | |
1063 | * so just handle whatever CPU interrupt it is routed to by | |
1064 | * default. | |
1065 | * | |
1066 | * This workaround should be removed when CMP support is | |
1067 | * dropped. | |
1068 | */ | |
1069 | if (IS_ENABLED(CONFIG_MIPS_CMP) && | |
1070 | gic_local_irq_is_routable(GIC_LOCAL_INT_TIMER)) { | |
c3f57f02 | 1071 | timer_cpu_pin = gic_read32(GIC_REG(VPE_LOCAL, |
1b6af71a JH |
1072 | GIC_VPE_TIMER_MAP)) & |
1073 | GIC_MAP_MSK; | |
1074 | irq_set_chained_handler(MIPS_CPU_IRQ_BASE + | |
1075 | GIC_CPU_PIN_OFFSET + | |
1076 | timer_cpu_pin, | |
1077 | gic_irq_dispatch); | |
1078 | } else { | |
1079 | timer_cpu_pin = gic_cpu_pin; | |
1080 | } | |
18743d27 AB |
1081 | } |
1082 | ||
a7057270 | 1083 | gic_irq_domain = irq_domain_add_simple(node, GIC_NUM_LOCAL_INTRS + |
e9de688d | 1084 | gic_shared_intrs, irqbase, |
c49581a4 AB |
1085 | &gic_irq_domain_ops, NULL); |
1086 | if (!gic_irq_domain) | |
1087 | panic("Failed to add GIC IRQ domain"); | |
0b271f56 | 1088 | |
c98c1822 QY |
1089 | gic_dev_domain = irq_domain_add_hierarchy(gic_irq_domain, 0, |
1090 | GIC_NUM_LOCAL_INTRS + gic_shared_intrs, | |
1091 | node, &gic_dev_domain_ops, NULL); | |
1092 | if (!gic_dev_domain) | |
1093 | panic("Failed to add GIC DEV domain"); | |
1094 | ||
2af70a96 QY |
1095 | gic_ipi_domain = irq_domain_add_hierarchy(gic_irq_domain, |
1096 | IRQ_DOMAIN_FLAG_IPI_PER_CPU, | |
1097 | GIC_NUM_LOCAL_INTRS + gic_shared_intrs, | |
1098 | node, &gic_ipi_domain_ops, NULL); | |
1099 | if (!gic_ipi_domain) | |
1100 | panic("Failed to add GIC IPI domain"); | |
1101 | ||
1102 | gic_ipi_domain->bus_token = DOMAIN_BUS_IPI; | |
1103 | ||
2a078705 QY |
1104 | /* Make the last 2 * gic_vpes available for IPIs */ |
1105 | bitmap_set(ipi_resrv, gic_shared_intrs - 2 * gic_vpes, 2 * gic_vpes); | |
2af70a96 | 1106 | |
e9de688d | 1107 | gic_basic_init(); |
18743d27 AB |
1108 | |
1109 | gic_ipi_init(); | |
39b8d525 | 1110 | } |
a7057270 AB |
1111 | |
1112 | void __init gic_init(unsigned long gic_base_addr, | |
1113 | unsigned long gic_addrspace_size, | |
1114 | unsigned int cpu_vec, unsigned int irqbase) | |
1115 | { | |
1116 | __gic_init(gic_base_addr, gic_addrspace_size, cpu_vec, irqbase, NULL); | |
1117 | } | |
1118 | ||
1119 | static int __init gic_of_init(struct device_node *node, | |
1120 | struct device_node *parent) | |
1121 | { | |
1122 | struct resource res; | |
1123 | unsigned int cpu_vec, i = 0, reserved = 0; | |
1124 | phys_addr_t gic_base; | |
1125 | size_t gic_len; | |
1126 | ||
1127 | /* Find the first available CPU vector. */ | |
1128 | while (!of_property_read_u32_index(node, "mti,reserved-cpu-vectors", | |
1129 | i++, &cpu_vec)) | |
1130 | reserved |= BIT(cpu_vec); | |
1131 | for (cpu_vec = 2; cpu_vec < 8; cpu_vec++) { | |
1132 | if (!(reserved & BIT(cpu_vec))) | |
1133 | break; | |
1134 | } | |
1135 | if (cpu_vec == 8) { | |
1136 | pr_err("No CPU vectors available for GIC\n"); | |
1137 | return -ENODEV; | |
1138 | } | |
1139 | ||
1140 | if (of_address_to_resource(node, 0, &res)) { | |
1141 | /* | |
1142 | * Probe the CM for the GIC base address if not specified | |
1143 | * in the device-tree. | |
1144 | */ | |
1145 | if (mips_cm_present()) { | |
1146 | gic_base = read_gcr_gic_base() & | |
1147 | ~CM_GCR_GIC_BASE_GICEN_MSK; | |
1148 | gic_len = 0x20000; | |
1149 | } else { | |
1150 | pr_err("Failed to get GIC memory range\n"); | |
1151 | return -ENODEV; | |
1152 | } | |
1153 | } else { | |
1154 | gic_base = res.start; | |
1155 | gic_len = resource_size(&res); | |
1156 | } | |
1157 | ||
1158 | if (mips_cm_present()) | |
1159 | write_gcr_gic_base(gic_base | CM_GCR_GIC_BASE_GICEN_MSK); | |
1160 | gic_present = true; | |
1161 | ||
1162 | __gic_init(gic_base, gic_len, cpu_vec, 0, node); | |
1163 | ||
1164 | return 0; | |
1165 | } | |
1166 | IRQCHIP_DECLARE(mips_gic, "mti,gic", gic_of_init); |