[mirror_ubuntu-artful-kernel.git] / drivers / irqchip / irq-mtk-sysirq.c

/*
 * Copyright (c) 2014 MediaTek Inc.
 * Author: Joe.C <yingjoe.chen@mediatek.com>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 */

#include <linux/irq.h>
#include <linux/irqdomain.h>
#include <linux/of.h>
#include <linux/of_irq.h>
#include <linux/of_address.h>
#include <linux/io.h>
#include <linux/slab.h>
#include <linux/spinlock.h>

#include "irqchip.h"

#define MT6577_SYS_INTPOL_NUM	(224)

struct mtk_sysirq_chip_data {
	spinlock_t lock;
	void __iomem *intpol_base;
};

static int mtk_sysirq_set_type(struct irq_data *data, unsigned int type)
{
	irq_hw_number_t hwirq = data->hwirq;
	struct mtk_sysirq_chip_data *chip_data = data->chip_data;
	u32 offset, reg_index, value;
	unsigned long flags;
	int ret;

	offset = hwirq & 0x1f;
	reg_index = hwirq >> 5;

	spin_lock_irqsave(&chip_data->lock, flags);
	value = readl_relaxed(chip_data->intpol_base + reg_index * 4);
	if (type == IRQ_TYPE_LEVEL_LOW || type == IRQ_TYPE_EDGE_FALLING) {
		if (type == IRQ_TYPE_LEVEL_LOW)
			type = IRQ_TYPE_LEVEL_HIGH;
		else
			type = IRQ_TYPE_EDGE_RISING;
		value |= (1 << offset);
	} else {
		value &= ~(1 << offset);
	}
	writel(value, chip_data->intpol_base + reg_index * 4);

	data = data->parent_data;
	ret = data->chip->irq_set_type(data, type);
	spin_unlock_irqrestore(&chip_data->lock, flags);
	return ret;
}

static struct irq_chip mtk_sysirq_chip = {
	.name			= "MT_SYSIRQ",
	.irq_mask		= irq_chip_mask_parent,
	.irq_unmask		= irq_chip_unmask_parent,
	.irq_eoi		= irq_chip_eoi_parent,
	.irq_set_type		= mtk_sysirq_set_type,
	.irq_retrigger		= irq_chip_retrigger_hierarchy,
	.irq_set_affinity	= irq_chip_set_affinity_parent,
};

static int mtk_sysirq_domain_xlate(struct irq_domain *d,
				   struct device_node *controller,
				   const u32 *intspec, unsigned int intsize,
				   unsigned long *out_hwirq,
				   unsigned int *out_type)
{
	if (intsize != 3)
		return -EINVAL;

	/* sysirq doesn't support PPI */
	if (intspec[0])
		return -EINVAL;

	*out_hwirq = intspec[1];
	*out_type = intspec[2] & IRQ_TYPE_SENSE_MASK;
	return 0;
}

static int mtk_sysirq_domain_alloc(struct irq_domain *domain, unsigned int virq,
				   unsigned int nr_irqs, void *arg)
{
	int i;
	irq_hw_number_t hwirq;
	struct of_phandle_args *irq_data = arg;
	struct of_phandle_args gic_data = *irq_data;

	if (irq_data->args_count != 3)
		return -EINVAL;

	/* sysirq doesn't support PPI */
	if (irq_data->args[0])
		return -EINVAL;

	hwirq = irq_data->args[1];
	for (i = 0; i < nr_irqs; i++)
		irq_domain_set_hwirq_and_chip(domain, virq + i, hwirq + i,
					      &mtk_sysirq_chip,
					      domain->host_data);

	gic_data.np = domain->parent->of_node;
	return irq_domain_alloc_irqs_parent(domain, virq, nr_irqs, &gic_data);
}

static struct irq_domain_ops sysirq_domain_ops = {
	.xlate = mtk_sysirq_domain_xlate,
	.alloc = mtk_sysirq_domain_alloc,
	.free = irq_domain_free_irqs_common,
};

static int __init mtk_sysirq_of_init(struct device_node *node,
				     struct device_node *parent)
{
	struct irq_domain *domain, *domain_parent;
	struct mtk_sysirq_chip_data *chip_data;
	int ret = 0;

	domain_parent = irq_find_host(parent);
	if (!domain_parent) {
		pr_err("mtk_sysirq: interrupt-parent not found\n");
		return -EINVAL;
	}

	chip_data = kzalloc(sizeof(*chip_data), GFP_KERNEL);
	if (!chip_data)
		return -ENOMEM;

	chip_data->intpol_base = of_io_request_and_map(node, 0, "intpol");
	if (IS_ERR(chip_data->intpol_base)) {
		pr_err("mtk_sysirq: unable to map sysirq register\n");
		ret = PTR_ERR(chip_data->intpol_base);
		goto out_free;
	}

	domain = irq_domain_add_hierarchy(domain_parent, 0,
					  MT6577_SYS_INTPOL_NUM, node,
					  &sysirq_domain_ops, chip_data);
	if (!domain) {
		ret = -ENOMEM;
		goto out_unmap;
	}
	spin_lock_init(&chip_data->lock);

	return 0;

out_unmap:
	iounmap(chip_data->intpol_base);
out_free:
	kfree(chip_data);
	return ret;
}
IRQCHIP_DECLARE(mtk_sysirq, "mediatek,mt6577-sysirq", mtk_sysirq_of_init);
Commit	Line	Data
5fe3bba3 YC	1	/*
	2	* Copyright (c) 2014 MediaTek Inc.
	3	* Author: Joe.C <yingjoe.chen@mediatek.com>
	4	*
	5	* This program is free software; you can redistribute it and/or modify
	6	* it under the terms of the GNU General Public License version 2 as
	7	* published by the Free Software Foundation.
	8	*
	9	* This program is distributed in the hope that it will be useful,
	10	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	11	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	12	* GNU General Public License for more details.
	13	*/
	14
	15	#include <linux/irq.h>
	16	#include <linux/irqdomain.h>
	17	#include <linux/of.h>
	18	#include <linux/of_irq.h>
	19	#include <linux/of_address.h>
	20	#include <linux/io.h>
	21	#include <linux/slab.h>
	22	#include <linux/spinlock.h>
	23
	24	#include "irqchip.h"
	25
	26	#define MT6577_SYS_INTPOL_NUM (224)
	27
	28	struct mtk_sysirq_chip_data {
	29	spinlock_t lock;
	30	void __iomem *intpol_base;
	31	};
	32
	33	static int mtk_sysirq_set_type(struct irq_data *data, unsigned int type)
	34	{
	35	irq_hw_number_t hwirq = data->hwirq;
	36	struct mtk_sysirq_chip_data *chip_data = data->chip_data;
	37	u32 offset, reg_index, value;
	38	unsigned long flags;
	39	int ret;
	40
	41	offset = hwirq & 0x1f;
	42	reg_index = hwirq >> 5;
	43
	44	spin_lock_irqsave(&chip_data->lock, flags);
	45	value = readl_relaxed(chip_data->intpol_base + reg_index * 4);
	46	if (type == IRQ_TYPE_LEVEL_LOW \|\| type == IRQ_TYPE_EDGE_FALLING) {
	47	if (type == IRQ_TYPE_LEVEL_LOW)
	48	type = IRQ_TYPE_LEVEL_HIGH;
	49	else
	50	type = IRQ_TYPE_EDGE_RISING;
	51	value \|= (1 << offset);
	52	} else {
	53	value &= ~(1 << offset);
	54	}
	55	writel(value, chip_data->intpol_base + reg_index * 4);
	56
	57	data = data->parent_data;
	58	ret = data->chip->irq_set_type(data, type);
	59	spin_unlock_irqrestore(&chip_data->lock, flags);
	60	return ret;
	61	}
	62
	63	static struct irq_chip mtk_sysirq_chip = {
	64	.name = "MT_SYSIRQ",
65	.irq_mask = irq_chip_mask_parent,
66	.irq_unmask = irq_chip_unmask_parent,
67	.irq_eoi = irq_chip_eoi_parent,
68	.irq_set_type = mtk_sysirq_set_type,
69	.irq_retrigger = irq_chip_retrigger_hierarchy,
70	.irq_set_affinity = irq_chip_set_affinity_parent,
71	};
72
73	static int mtk_sysirq_domain_xlate(struct irq_domain *d,
74	struct device_node *controller,
75	const u32 *intspec, unsigned int intsize,
76	unsigned long *out_hwirq,
77	unsigned int *out_type)
78	{
79	if (intsize != 3)
80	return -EINVAL;
81
82	/* sysirq doesn't support PPI */
83	if (intspec[0])
84	return -EINVAL;
85
86	*out_hwirq = intspec[1];
87	*out_type = intspec[2] & IRQ_TYPE_SENSE_MASK;
88	return 0;
89	}
90
91	static int mtk_sysirq_domain_alloc(struct irq_domain *domain, unsigned int virq,
92	unsigned int nr_irqs, void *arg)
93	{
94	int i;
95	irq_hw_number_t hwirq;
96	struct of_phandle_args *irq_data = arg;
97	struct of_phandle_args gic_data = *irq_data;
98
99	if (irq_data->args_count != 3)
100	return -EINVAL;
101
102	/* sysirq doesn't support PPI */
103	if (irq_data->args[0])
104	return -EINVAL;
105
106	hwirq = irq_data->args[1];
107	for (i = 0; i < nr_irqs; i++)
108	irq_domain_set_hwirq_and_chip(domain, virq + i, hwirq + i,
109	&mtk_sysirq_chip,
110	domain->host_data);
111
112	gic_data.np = domain->parent->of_node;
113	return irq_domain_alloc_irqs_parent(domain, virq, nr_irqs, &gic_data);
114	}
115
116	static struct irq_domain_ops sysirq_domain_ops = {
117	.xlate = mtk_sysirq_domain_xlate,
118	.alloc = mtk_sysirq_domain_alloc,
119	.free = irq_domain_free_irqs_common,
120	};
121
122	static int __init mtk_sysirq_of_init(struct device_node *node,
123	struct device_node *parent)
124	{
125	struct irq_domain domain, domain_parent;
126	struct mtk_sysirq_chip_data *chip_data;
127	int ret = 0;
128
129	domain_parent = irq_find_host(parent);
130	if (!domain_parent) {
131	pr_err("mtk_sysirq: interrupt-parent not found\n");
132	return -EINVAL;
133	}
134
135	chip_data = kzalloc(sizeof(*chip_data), GFP_KERNEL);
136	if (!chip_data)
137	return -ENOMEM;
138
139	chip_data->intpol_base = of_io_request_and_map(node, 0, "intpol");
596c4051	140	if (IS_ERR(chip_data->intpol_base)) {
5fe3bba3	141	pr_err("mtk_sysirq: unable to map sysirq register\n");
596c4051	142	ret = PTR_ERR(chip_data->intpol_base);
5fe3bba3 YC	143	goto out_free;
	144	}
	145
	146	domain = irq_domain_add_hierarchy(domain_parent, 0,
	147	MT6577_SYS_INTPOL_NUM, node,
	148	&sysirq_domain_ops, chip_data);
	149	if (!domain) {
	150	ret = -ENOMEM;
	151	goto out_unmap;
	152	}
	153	spin_lock_init(&chip_data->lock);
	154
	155	return 0;
	156
	157	out_unmap:
	158	iounmap(chip_data->intpol_base);
	159	out_free:
	160	kfree(chip_data);
	161	return ret;
	162	}
	163	IRQCHIP_DECLARE(mtk_sysirq, "mediatek,mt6577-sysirq", mtk_sysirq_of_init);