[mirror_ubuntu-jammy-kernel.git] / drivers / irqchip / irq-renesas-intc-irqpin.c

// SPDX-License-Identifier: GPL-2.0
/*
 * Renesas INTC External IRQ Pin Driver
 *
 *  Copyright (C) 2013 Magnus Damm
 */

#include <linux/init.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/spinlock.h>
#include <linux/interrupt.h>
#include <linux/ioport.h>
#include <linux/io.h>
#include <linux/irq.h>
#include <linux/irqdomain.h>
#include <linux/err.h>
#include <linux/slab.h>
#include <linux/module.h>
#include <linux/of_device.h>
#include <linux/pm_runtime.h>

#define INTC_IRQPIN_MAX 8 /* maximum 8 interrupts per driver instance */

#define INTC_IRQPIN_REG_SENSE 0 /* ICRn */
#define INTC_IRQPIN_REG_PRIO 1 /* INTPRInn */
#define INTC_IRQPIN_REG_SOURCE 2 /* INTREQnn */
#define INTC_IRQPIN_REG_MASK 3 /* INTMSKnn */
#define INTC_IRQPIN_REG_CLEAR 4 /* INTMSKCLRnn */
#define INTC_IRQPIN_REG_NR_MANDATORY 5
#define INTC_IRQPIN_REG_IRLM 5 /* ICR0 with IRLM bit (optional) */
#define INTC_IRQPIN_REG_NR 6

/* INTC external IRQ PIN hardware register access:
 *
 * SENSE is read-write 32-bit with 2-bits or 4-bits per IRQ (*)
 * PRIO is read-write 32-bit with 4-bits per IRQ (**)
 * SOURCE is read-only 32-bit or 8-bit with 1-bit per IRQ (***)
 * MASK is write-only 32-bit or 8-bit with 1-bit per IRQ (***)
 * CLEAR is write-only 32-bit or 8-bit with 1-bit per IRQ (***)
 *
 * (*) May be accessed by more than one driver instance - lock needed
 * (**) Read-modify-write access by one driver instance - lock needed
 * (***) Accessed by one driver instance only - no locking needed
 */

struct intc_irqpin_iomem {
	void __iomem *iomem;
	unsigned long (*read)(void __iomem *iomem);
	void (*write)(void __iomem *iomem, unsigned long data);
	int width;
};

struct intc_irqpin_irq {
	int hw_irq;
	int requested_irq;
	int domain_irq;
	struct intc_irqpin_priv *p;
};

struct intc_irqpin_priv {
	struct intc_irqpin_iomem iomem[INTC_IRQPIN_REG_NR];
	struct intc_irqpin_irq irq[INTC_IRQPIN_MAX];
	unsigned int sense_bitfield_width;
	struct platform_device *pdev;
	struct irq_chip irq_chip;
	struct irq_domain *irq_domain;
	atomic_t wakeup_path;
	unsigned shared_irqs:1;
	u8 shared_irq_mask;
};

struct intc_irqpin_config {
	unsigned int irlm_bit;
	unsigned needs_irlm:1;
};

static unsigned long intc_irqpin_read32(void __iomem *iomem)
{
	return ioread32(iomem);
}

static unsigned long intc_irqpin_read8(void __iomem *iomem)
{
	return ioread8(iomem);
}

static void intc_irqpin_write32(void __iomem *iomem, unsigned long data)
{
	iowrite32(data, iomem);
}

static void intc_irqpin_write8(void __iomem *iomem, unsigned long data)
{
	iowrite8(data, iomem);
}

static inline unsigned long intc_irqpin_read(struct intc_irqpin_priv *p,
					     int reg)
{
	struct intc_irqpin_iomem *i = &p->iomem[reg];

	return i->read(i->iomem);
}

static inline void intc_irqpin_write(struct intc_irqpin_priv *p,
				     int reg, unsigned long data)
{
	struct intc_irqpin_iomem *i = &p->iomem[reg];

	i->write(i->iomem, data);
}

static inline unsigned long intc_irqpin_hwirq_mask(struct intc_irqpin_priv *p,
						   int reg, int hw_irq)
{
	return BIT((p->iomem[reg].width - 1) - hw_irq);
}

static inline void intc_irqpin_irq_write_hwirq(struct intc_irqpin_priv *p,
					       int reg, int hw_irq)
{
	intc_irqpin_write(p, reg, intc_irqpin_hwirq_mask(p, reg, hw_irq));
}

static DEFINE_RAW_SPINLOCK(intc_irqpin_lock); /* only used by slow path */

static void intc_irqpin_read_modify_write(struct intc_irqpin_priv *p,
					  int reg, int shift,
					  int width, int value)
{
	unsigned long flags;
	unsigned long tmp;

	raw_spin_lock_irqsave(&intc_irqpin_lock, flags);

	tmp = intc_irqpin_read(p, reg);
	tmp &= ~(((1 << width) - 1) << shift);
	tmp |= value << shift;
	intc_irqpin_write(p, reg, tmp);

	raw_spin_unlock_irqrestore(&intc_irqpin_lock, flags);
}

static void intc_irqpin_mask_unmask_prio(struct intc_irqpin_priv *p,
					 int irq, int do_mask)
{
	/* The PRIO register is assumed to be 32-bit with fixed 4-bit fields. */
	int bitfield_width = 4;
	int shift = 32 - (irq + 1) * bitfield_width;

	intc_irqpin_read_modify_write(p, INTC_IRQPIN_REG_PRIO,
				      shift, bitfield_width,
				      do_mask ? 0 : (1 << bitfield_width) - 1);
}

static int intc_irqpin_set_sense(struct intc_irqpin_priv *p, int irq, int value)
{
	/* The SENSE register is assumed to be 32-bit. */
	int bitfield_width = p->sense_bitfield_width;
	int shift = 32 - (irq + 1) * bitfield_width;

	dev_dbg(&p->pdev->dev, "sense irq = %d, mode = %d\n", irq, value);

	if (value >= (1 << bitfield_width))
		return -EINVAL;

	intc_irqpin_read_modify_write(p, INTC_IRQPIN_REG_SENSE, shift,
				      bitfield_width, value);
	return 0;
}

static void intc_irqpin_dbg(struct intc_irqpin_irq *i, char *str)
{
	dev_dbg(&i->p->pdev->dev, "%s (%d:%d:%d)\n",
		str, i->requested_irq, i->hw_irq, i->domain_irq);
}

static void intc_irqpin_irq_enable(struct irq_data *d)
{
	struct intc_irqpin_priv *p = irq_data_get_irq_chip_data(d);
	int hw_irq = irqd_to_hwirq(d);

	intc_irqpin_dbg(&p->irq[hw_irq], "enable");
	intc_irqpin_irq_write_hwirq(p, INTC_IRQPIN_REG_CLEAR, hw_irq);
}

static void intc_irqpin_irq_disable(struct irq_data *d)
{
	struct intc_irqpin_priv *p = irq_data_get_irq_chip_data(d);
	int hw_irq = irqd_to_hwirq(d);

	intc_irqpin_dbg(&p->irq[hw_irq], "disable");
	intc_irqpin_irq_write_hwirq(p, INTC_IRQPIN_REG_MASK, hw_irq);
}

static void intc_irqpin_shared_irq_enable(struct irq_data *d)
{
	struct intc_irqpin_priv *p = irq_data_get_irq_chip_data(d);
	int hw_irq = irqd_to_hwirq(d);

	intc_irqpin_dbg(&p->irq[hw_irq], "shared enable");
	intc_irqpin_irq_write_hwirq(p, INTC_IRQPIN_REG_CLEAR, hw_irq);

	p->shared_irq_mask &= ~BIT(hw_irq);
}

static void intc_irqpin_shared_irq_disable(struct irq_data *d)
{
	struct intc_irqpin_priv *p = irq_data_get_irq_chip_data(d);
	int hw_irq = irqd_to_hwirq(d);

	intc_irqpin_dbg(&p->irq[hw_irq], "shared disable");
	intc_irqpin_irq_write_hwirq(p, INTC_IRQPIN_REG_MASK, hw_irq);

	p->shared_irq_mask |= BIT(hw_irq);
}

static void intc_irqpin_irq_enable_force(struct irq_data *d)
{
	struct intc_irqpin_priv *p = irq_data_get_irq_chip_data(d);
	int irq = p->irq[irqd_to_hwirq(d)].requested_irq;

	intc_irqpin_irq_enable(d);

	/* enable interrupt through parent interrupt controller,
	 * assumes non-shared interrupt with 1:1 mapping
	 * needed for busted IRQs on some SoCs like sh73a0
	 */
	irq_get_chip(irq)->irq_unmask(irq_get_irq_data(irq));
}

static void intc_irqpin_irq_disable_force(struct irq_data *d)
{
	struct intc_irqpin_priv *p = irq_data_get_irq_chip_data(d);
	int irq = p->irq[irqd_to_hwirq(d)].requested_irq;

	/* disable interrupt through parent interrupt controller,
	 * assumes non-shared interrupt with 1:1 mapping
	 * needed for busted IRQs on some SoCs like sh73a0
	 */
	irq_get_chip(irq)->irq_mask(irq_get_irq_data(irq));
	intc_irqpin_irq_disable(d);
}

#define INTC_IRQ_SENSE_VALID 0x10
#define INTC_IRQ_SENSE(x) (x + INTC_IRQ_SENSE_VALID)

static unsigned char intc_irqpin_sense[IRQ_TYPE_SENSE_MASK + 1] = {
	[IRQ_TYPE_EDGE_FALLING] = INTC_IRQ_SENSE(0x00),
	[IRQ_TYPE_EDGE_RISING] = INTC_IRQ_SENSE(0x01),
	[IRQ_TYPE_LEVEL_LOW] = INTC_IRQ_SENSE(0x02),
	[IRQ_TYPE_LEVEL_HIGH] = INTC_IRQ_SENSE(0x03),
	[IRQ_TYPE_EDGE_BOTH] = INTC_IRQ_SENSE(0x04),
};

static int intc_irqpin_irq_set_type(struct irq_data *d, unsigned int type)
{
	unsigned char value = intc_irqpin_sense[type & IRQ_TYPE_SENSE_MASK];
	struct intc_irqpin_priv *p = irq_data_get_irq_chip_data(d);

	if (!(value & INTC_IRQ_SENSE_VALID))
		return -EINVAL;

	return intc_irqpin_set_sense(p, irqd_to_hwirq(d),
				     value ^ INTC_IRQ_SENSE_VALID);
}

static int intc_irqpin_irq_set_wake(struct irq_data *d, unsigned int on)
{
	struct intc_irqpin_priv *p = irq_data_get_irq_chip_data(d);
	int hw_irq = irqd_to_hwirq(d);

	irq_set_irq_wake(p->irq[hw_irq].requested_irq, on);
	if (on)
		atomic_inc(&p->wakeup_path);
	else
		atomic_dec(&p->wakeup_path);

	return 0;
}

static irqreturn_t intc_irqpin_irq_handler(int irq, void *dev_id)
{
	struct intc_irqpin_irq *i = dev_id;
	struct intc_irqpin_priv *p = i->p;
	unsigned long bit;

	intc_irqpin_dbg(i, "demux1");
	bit = intc_irqpin_hwirq_mask(p, INTC_IRQPIN_REG_SOURCE, i->hw_irq);

	if (intc_irqpin_read(p, INTC_IRQPIN_REG_SOURCE) & bit) {
		intc_irqpin_write(p, INTC_IRQPIN_REG_SOURCE, ~bit);
		intc_irqpin_dbg(i, "demux2");
		generic_handle_irq(i->domain_irq);
		return IRQ_HANDLED;
	}
	return IRQ_NONE;
}

static irqreturn_t intc_irqpin_shared_irq_handler(int irq, void *dev_id)
{
	struct intc_irqpin_priv *p = dev_id;
	unsigned int reg_source = intc_irqpin_read(p, INTC_IRQPIN_REG_SOURCE);
	irqreturn_t status = IRQ_NONE;
	int k;

	for (k = 0; k < 8; k++) {
		if (reg_source & BIT(7 - k)) {
			if (BIT(k) & p->shared_irq_mask)
				continue;

			status |= intc_irqpin_irq_handler(irq, &p->irq[k]);
		}
	}

	return status;
}

/*
 * This lock class tells lockdep that INTC External IRQ Pin irqs are in a
 * different category than their parents, so it won't report false recursion.
 */
static struct lock_class_key intc_irqpin_irq_lock_class;

/* And this is for the request mutex */
static struct lock_class_key intc_irqpin_irq_request_class;

static int intc_irqpin_irq_domain_map(struct irq_domain *h, unsigned int virq,
				      irq_hw_number_t hw)
{
	struct intc_irqpin_priv *p = h->host_data;

	p->irq[hw].domain_irq = virq;
	p->irq[hw].hw_irq = hw;

	intc_irqpin_dbg(&p->irq[hw], "map");
	irq_set_chip_data(virq, h->host_data);
	irq_set_lockdep_class(virq, &intc_irqpin_irq_lock_class,
			      &intc_irqpin_irq_request_class);
	irq_set_chip_and_handler(virq, &p->irq_chip, handle_level_irq);
	return 0;
}

static const struct irq_domain_ops intc_irqpin_irq_domain_ops = {
	.map	= intc_irqpin_irq_domain_map,
	.xlate  = irq_domain_xlate_twocell,
};

static const struct intc_irqpin_config intc_irqpin_irlm_r8a777x = {
	.irlm_bit = 23, /* ICR0.IRLM0 */
	.needs_irlm = 1,
};

static const struct intc_irqpin_config intc_irqpin_rmobile = {
	.needs_irlm = 0,
};

static const struct of_device_id intc_irqpin_dt_ids[] = {
	{ .compatible = "renesas,intc-irqpin", },
	{ .compatible = "renesas,intc-irqpin-r8a7778",
	  .data = &intc_irqpin_irlm_r8a777x },
	{ .compatible = "renesas,intc-irqpin-r8a7779",
	  .data = &intc_irqpin_irlm_r8a777x },
	{ .compatible = "renesas,intc-irqpin-r8a7740",
	  .data = &intc_irqpin_rmobile },
	{ .compatible = "renesas,intc-irqpin-sh73a0",
	  .data = &intc_irqpin_rmobile },
	{},
};
MODULE_DEVICE_TABLE(of, intc_irqpin_dt_ids);

static int intc_irqpin_probe(struct platform_device *pdev)
{
	const struct intc_irqpin_config *config;
	struct device *dev = &pdev->dev;
	struct intc_irqpin_priv *p;
	struct intc_irqpin_iomem *i;
	struct resource *io[INTC_IRQPIN_REG_NR];
	struct resource *irq;
	struct irq_chip *irq_chip;
	void (*enable_fn)(struct irq_data *d);
	void (*disable_fn)(struct irq_data *d);
	const char *name = dev_name(dev);
	bool control_parent;
	unsigned int nirqs;
	int ref_irq;
	int ret;
	int k;

	p = devm_kzalloc(dev, sizeof(*p), GFP_KERNEL);
	if (!p) {
		dev_err(dev, "failed to allocate driver data\n");
		return -ENOMEM;
	}

	/* deal with driver instance configuration */
	of_property_read_u32(dev->of_node, "sense-bitfield-width",
			     &p->sense_bitfield_width);
	control_parent = of_property_read_bool(dev->of_node, "control-parent");
	if (!p->sense_bitfield_width)
		p->sense_bitfield_width = 4; /* default to 4 bits */

	p->pdev = pdev;
	platform_set_drvdata(pdev, p);

	config = of_device_get_match_data(dev);

	pm_runtime_enable(dev);
	pm_runtime_get_sync(dev);

	/* get hold of register banks */
	memset(io, 0, sizeof(io));
	for (k = 0; k < INTC_IRQPIN_REG_NR; k++) {
		io[k] = platform_get_resource(pdev, IORESOURCE_MEM, k);
		if (!io[k] && k < INTC_IRQPIN_REG_NR_MANDATORY) {
			dev_err(dev, "not enough IOMEM resources\n");
			ret = -EINVAL;
			goto err0;
		}
	}

	/* allow any number of IRQs between 1 and INTC_IRQPIN_MAX */
	for (k = 0; k < INTC_IRQPIN_MAX; k++) {
		irq = platform_get_resource(pdev, IORESOURCE_IRQ, k);
		if (!irq)
			break;

		p->irq[k].p = p;
		p->irq[k].requested_irq = irq->start;
	}

	nirqs = k;
	if (nirqs < 1) {
		dev_err(dev, "not enough IRQ resources\n");
		ret = -EINVAL;
		goto err0;
	}

	/* ioremap IOMEM and setup read/write callbacks */
	for (k = 0; k < INTC_IRQPIN_REG_NR; k++) {
		i = &p->iomem[k];

		/* handle optional registers */
		if (!io[k])
			continue;

		switch (resource_size(io[k])) {
		case 1:
			i->width = 8;
			i->read = intc_irqpin_read8;
			i->write = intc_irqpin_write8;
			break;
		case 4:
			i->width = 32;
			i->read = intc_irqpin_read32;
			i->write = intc_irqpin_write32;
			break;
		default:
			dev_err(dev, "IOMEM size mismatch\n");
			ret = -EINVAL;
			goto err0;
		}

		i->iomem = devm_ioremap_nocache(dev, io[k]->start,
						resource_size(io[k]));
		if (!i->iomem) {
			dev_err(dev, "failed to remap IOMEM\n");
			ret = -ENXIO;
			goto err0;
		}
	}

	/* configure "individual IRQ mode" where needed */
	if (config && config->needs_irlm) {
		if (io[INTC_IRQPIN_REG_IRLM])
			intc_irqpin_read_modify_write(p, INTC_IRQPIN_REG_IRLM,
						      config->irlm_bit, 1, 1);
		else
			dev_warn(dev, "unable to select IRLM mode\n");
	}

	/* mask all interrupts using priority */
	for (k = 0; k < nirqs; k++)
		intc_irqpin_mask_unmask_prio(p, k, 1);

	/* clear all pending interrupts */
	intc_irqpin_write(p, INTC_IRQPIN_REG_SOURCE, 0x0);

	/* scan for shared interrupt lines */
	ref_irq = p->irq[0].requested_irq;
	p->shared_irqs = 1;
	for (k = 1; k < nirqs; k++) {
		if (ref_irq != p->irq[k].requested_irq) {
			p->shared_irqs = 0;
			break;
		}
	}

	/* use more severe masking method if requested */
	if (control_parent) {
		enable_fn = intc_irqpin_irq_enable_force;
		disable_fn = intc_irqpin_irq_disable_force;
	} else if (!p->shared_irqs) {
		enable_fn = intc_irqpin_irq_enable;
		disable_fn = intc_irqpin_irq_disable;
	} else {
		enable_fn = intc_irqpin_shared_irq_enable;
		disable_fn = intc_irqpin_shared_irq_disable;
	}

	irq_chip = &p->irq_chip;
	irq_chip->name = name;
	irq_chip->irq_mask = disable_fn;
	irq_chip->irq_unmask = enable_fn;
	irq_chip->irq_set_type = intc_irqpin_irq_set_type;
	irq_chip->irq_set_wake = intc_irqpin_irq_set_wake;
	irq_chip->flags	= IRQCHIP_MASK_ON_SUSPEND;

	p->irq_domain = irq_domain_add_simple(dev->of_node, nirqs, 0,
					      &intc_irqpin_irq_domain_ops, p);
	if (!p->irq_domain) {
		ret = -ENXIO;
		dev_err(dev, "cannot initialize irq domain\n");
		goto err0;
	}

	if (p->shared_irqs) {
		/* request one shared interrupt */
		if (devm_request_irq(dev, p->irq[0].requested_irq,
				intc_irqpin_shared_irq_handler,
				IRQF_SHARED, name, p)) {
			dev_err(dev, "failed to request low IRQ\n");
			ret = -ENOENT;
			goto err1;
		}
	} else {
		/* request interrupts one by one */
		for (k = 0; k < nirqs; k++) {
			if (devm_request_irq(dev, p->irq[k].requested_irq,
					     intc_irqpin_irq_handler, 0, name,
					     &p->irq[k])) {
				dev_err(dev, "failed to request low IRQ\n");
				ret = -ENOENT;
				goto err1;
			}
		}
	}

	/* unmask all interrupts on prio level */
	for (k = 0; k < nirqs; k++)
		intc_irqpin_mask_unmask_prio(p, k, 0);

	dev_info(dev, "driving %d irqs\n", nirqs);

	return 0;

err1:
	irq_domain_remove(p->irq_domain);
err0:
	pm_runtime_put(dev);
	pm_runtime_disable(dev);
	return ret;
}

static int intc_irqpin_remove(struct platform_device *pdev)
{
	struct intc_irqpin_priv *p = platform_get_drvdata(pdev);

	irq_domain_remove(p->irq_domain);
	pm_runtime_put(&pdev->dev);
	pm_runtime_disable(&pdev->dev);
	return 0;
}

static int __maybe_unused intc_irqpin_suspend(struct device *dev)
{
	struct intc_irqpin_priv *p = dev_get_drvdata(dev);

	if (atomic_read(&p->wakeup_path))
		device_set_wakeup_path(dev);

	return 0;
}

static SIMPLE_DEV_PM_OPS(intc_irqpin_pm_ops, intc_irqpin_suspend, NULL);

static struct platform_driver intc_irqpin_device_driver = {
	.probe		= intc_irqpin_probe,
	.remove		= intc_irqpin_remove,
	.driver		= {
		.name	= "renesas_intc_irqpin",
		.of_match_table = intc_irqpin_dt_ids,
		.pm	= &intc_irqpin_pm_ops,
	}
};

static int __init intc_irqpin_init(void)
{
	return platform_driver_register(&intc_irqpin_device_driver);
}
postcore_initcall(intc_irqpin_init);

static void __exit intc_irqpin_exit(void)
{
	platform_driver_unregister(&intc_irqpin_device_driver);
}
module_exit(intc_irqpin_exit);

MODULE_AUTHOR("Magnus Damm");
MODULE_DESCRIPTION("Renesas INTC External IRQ Pin Driver");
MODULE_LICENSE("GPL v2");
Commit	Line	Data
bf973285	1	// SPDX-License-Identifier: GPL-2.0
44358048 MD	2	/*
	3	* Renesas INTC External IRQ Pin Driver
	4	*
	5	* Copyright (C) 2013 Magnus Damm
44358048 MD	6	*/
	7
	8	#include <linux/init.h>
894db164	9	#include <linux/of.h>
44358048 MD	10	#include <linux/platform_device.h>
	11	#include <linux/spinlock.h>
	12	#include <linux/interrupt.h>
	13	#include <linux/ioport.h>
	14	#include <linux/io.h>
	15	#include <linux/irq.h>
	16	#include <linux/irqdomain.h>
	17	#include <linux/err.h>
	18	#include <linux/slab.h>
	19	#include <linux/module.h>
e03f9088	20	#include <linux/of_device.h>
705bc96c	21	#include <linux/pm_runtime.h>
44358048 MD	22
	23	#define INTC_IRQPIN_MAX 8 /* maximum 8 interrupts per driver instance */
	24
	25	#define INTC_IRQPIN_REG_SENSE 0 /* ICRn */
	26	#define INTC_IRQPIN_REG_PRIO 1 /* INTPRInn */
	27	#define INTC_IRQPIN_REG_SOURCE 2 /* INTREQnn */
	28	#define INTC_IRQPIN_REG_MASK 3 /* INTMSKnn */
	29	#define INTC_IRQPIN_REG_CLEAR 4 /* INTMSKCLRnn */
e03f9088 MD	30	#define INTC_IRQPIN_REG_NR_MANDATORY 5
	31	#define INTC_IRQPIN_REG_IRLM 5 /* ICR0 with IRLM bit (optional) */
	32	#define INTC_IRQPIN_REG_NR 6
44358048 MD	33
	34	/* INTC external IRQ PIN hardware register access:
	35	*
	36	* SENSE is read-write 32-bit with 2-bits or 4-bits per IRQ (*)
	37	* PRIO is read-write 32-bit with 4-bits per IRQ (**)
	38	* SOURCE is read-only 32-bit or 8-bit with 1-bit per IRQ (***)
	39	* MASK is write-only 32-bit or 8-bit with 1-bit per IRQ (***)
	40	* CLEAR is write-only 32-bit or 8-bit with 1-bit per IRQ (***)
	41	*
	42	* (*) May be accessed by more than one driver instance - lock needed
	43	* (**) Read-modify-write access by one driver instance - lock needed
	44	* (***) Accessed by one driver instance only - no locking needed
	45	*/
	46
	47	struct intc_irqpin_iomem {
	48	void __iomem *iomem;
	49	unsigned long (read)(void __iomem iomem);
	50	void (write)(void __iomem iomem, unsigned long data);
	51	int width;
862d3098	52	};
44358048 MD	53
	54	struct intc_irqpin_irq {
	55	int hw_irq;
33f958f2 MD	56	int requested_irq;
33f958f2 MD	57	int domain_irq;
44358048	58	struct intc_irqpin_priv *p;
862d3098	59	};
44358048 MD	60
	61	struct intc_irqpin_priv {
	62	struct intc_irqpin_iomem iomem[INTC_IRQPIN_REG_NR];
	63	struct intc_irqpin_irq irq[INTC_IRQPIN_MAX];
f9551a9c	64	unsigned int sense_bitfield_width;
44358048 MD	65	struct platform_device *pdev;
	66	struct irq_chip irq_chip;
	67	struct irq_domain *irq_domain;
66bf8252	68	atomic_t wakeup_path;
86e57ca7	69	unsigned shared_irqs:1;
427cc720	70	u8 shared_irq_mask;
44358048 MD	71	};
44358048 MD	72
86e57ca7	73	struct intc_irqpin_config {
e03f9088	74	unsigned int irlm_bit;
86e57ca7	75	unsigned needs_irlm:1;
e03f9088 MD	76	};
e03f9088 MD	77
44358048 MD	78	static unsigned long intc_irqpin_read32(void __iomem *iomem)
	79	{
	80	return ioread32(iomem);
	81	}
	82
	83	static unsigned long intc_irqpin_read8(void __iomem *iomem)
	84	{
	85	return ioread8(iomem);
	86	}
	87
	88	static void intc_irqpin_write32(void __iomem *iomem, unsigned long data)
	89	{
	90	iowrite32(data, iomem);
	91	}
	92
	93	static void intc_irqpin_write8(void __iomem *iomem, unsigned long data)
	94	{
	95	iowrite8(data, iomem);
	96	}
	97
	98	static inline unsigned long intc_irqpin_read(struct intc_irqpin_priv *p,
	99	int reg)
	100	{
	101	struct intc_irqpin_iomem *i = &p->iomem[reg];
862d3098	102
44358048 MD	103	return i->read(i->iomem);
	104	}
	105
	106	static inline void intc_irqpin_write(struct intc_irqpin_priv *p,
	107	int reg, unsigned long data)
	108	{
	109	struct intc_irqpin_iomem *i = &p->iomem[reg];
862d3098	110
44358048 MD	111	i->write(i->iomem, data);
	112	}
	113
	114	static inline unsigned long intc_irqpin_hwirq_mask(struct intc_irqpin_priv *p,
	115	int reg, int hw_irq)
	116	{
	117	return BIT((p->iomem[reg].width - 1) - hw_irq);
	118	}
	119
	120	static inline void intc_irqpin_irq_write_hwirq(struct intc_irqpin_priv *p,
	121	int reg, int hw_irq)
	122	{
	123	intc_irqpin_write(p, reg, intc_irqpin_hwirq_mask(p, reg, hw_irq));
	124	}
	125
	126	static DEFINE_RAW_SPINLOCK(intc_irqpin_lock); /* only used by slow path */
	127
	128	static void intc_irqpin_read_modify_write(struct intc_irqpin_priv *p,
	129	int reg, int shift,
	130	int width, int value)
	131	{
	132	unsigned long flags;
	133	unsigned long tmp;
	134
	135	raw_spin_lock_irqsave(&intc_irqpin_lock, flags);
	136
	137	tmp = intc_irqpin_read(p, reg);
	138	tmp &= ~(((1 << width) - 1) << shift);
	139	tmp \|= value << shift;
	140	intc_irqpin_write(p, reg, tmp);
	141
	142	raw_spin_unlock_irqrestore(&intc_irqpin_lock, flags);
	143	}
	144
	145	static void intc_irqpin_mask_unmask_prio(struct intc_irqpin_priv *p,
	146	int irq, int do_mask)
	147	{
e55bc558 LP	148	/* The PRIO register is assumed to be 32-bit with fixed 4-bit fields. */
	149	int bitfield_width = 4;
	150	int shift = 32 - (irq + 1) * bitfield_width;
44358048 MD	151
	152	intc_irqpin_read_modify_write(p, INTC_IRQPIN_REG_PRIO,
	153	shift, bitfield_width,
	154	do_mask ? 0 : (1 << bitfield_width) - 1);
	155	}
	156
	157	static int intc_irqpin_set_sense(struct intc_irqpin_priv *p, int irq, int value)
	158	{
e55bc558	159	/* The SENSE register is assumed to be 32-bit. */
f9551a9c	160	int bitfield_width = p->sense_bitfield_width;
e55bc558	161	int shift = 32 - (irq + 1) * bitfield_width;
44358048 MD	162
	163	dev_dbg(&p->pdev->dev, "sense irq = %d, mode = %d\n", irq, value);
	164
	165	if (value >= (1 << bitfield_width))
	166	return -EINVAL;
	167
	168	intc_irqpin_read_modify_write(p, INTC_IRQPIN_REG_SENSE, shift,
	169	bitfield_width, value);
	170	return 0;
	171	}
	172
	173	static void intc_irqpin_dbg(struct intc_irqpin_irq i, char str)
	174	{
	175	dev_dbg(&i->p->pdev->dev, "%s (%d:%d:%d)\n",
33f958f2	176	str, i->requested_irq, i->hw_irq, i->domain_irq);
44358048 MD	177	}
	178
	179	static void intc_irqpin_irq_enable(struct irq_data *d)
	180	{
	181	struct intc_irqpin_priv *p = irq_data_get_irq_chip_data(d);
	182	int hw_irq = irqd_to_hwirq(d);
	183
	184	intc_irqpin_dbg(&p->irq[hw_irq], "enable");
	185	intc_irqpin_irq_write_hwirq(p, INTC_IRQPIN_REG_CLEAR, hw_irq);
	186	}
	187
	188	static void intc_irqpin_irq_disable(struct irq_data *d)
	189	{
	190	struct intc_irqpin_priv *p = irq_data_get_irq_chip_data(d);
	191	int hw_irq = irqd_to_hwirq(d);
	192
	193	intc_irqpin_dbg(&p->irq[hw_irq], "disable");
	194	intc_irqpin_irq_write_hwirq(p, INTC_IRQPIN_REG_MASK, hw_irq);
	195	}
	196
427cc720 BH	197	static void intc_irqpin_shared_irq_enable(struct irq_data *d)
	198	{
	199	struct intc_irqpin_priv *p = irq_data_get_irq_chip_data(d);
	200	int hw_irq = irqd_to_hwirq(d);
	201
	202	intc_irqpin_dbg(&p->irq[hw_irq], "shared enable");
	203	intc_irqpin_irq_write_hwirq(p, INTC_IRQPIN_REG_CLEAR, hw_irq);
	204
	205	p->shared_irq_mask &= ~BIT(hw_irq);
	206	}
	207
	208	static void intc_irqpin_shared_irq_disable(struct irq_data *d)
	209	{
	210	struct intc_irqpin_priv *p = irq_data_get_irq_chip_data(d);
	211	int hw_irq = irqd_to_hwirq(d);
	212
	213	intc_irqpin_dbg(&p->irq[hw_irq], "shared disable");
	214	intc_irqpin_irq_write_hwirq(p, INTC_IRQPIN_REG_MASK, hw_irq);
	215
	216	p->shared_irq_mask \|= BIT(hw_irq);
	217	}
	218
44358048 MD	219	static void intc_irqpin_irq_enable_force(struct irq_data *d)
	220	{
	221	struct intc_irqpin_priv *p = irq_data_get_irq_chip_data(d);
33f958f2	222	int irq = p->irq[irqd_to_hwirq(d)].requested_irq;
44358048 MD	223
44358048 MD	224	intc_irqpin_irq_enable(d);
d1b6aecd MD	225
	226	/* enable interrupt through parent interrupt controller,
	227	* assumes non-shared interrupt with 1:1 mapping
	228	* needed for busted IRQs on some SoCs like sh73a0
	229	*/
44358048 MD	230	irq_get_chip(irq)->irq_unmask(irq_get_irq_data(irq));
	231	}
	232
	233	static void intc_irqpin_irq_disable_force(struct irq_data *d)
	234	{
	235	struct intc_irqpin_priv *p = irq_data_get_irq_chip_data(d);
33f958f2	236	int irq = p->irq[irqd_to_hwirq(d)].requested_irq;
44358048	237
d1b6aecd MD	238	/* disable interrupt through parent interrupt controller,
	239	* assumes non-shared interrupt with 1:1 mapping
	240	* needed for busted IRQs on some SoCs like sh73a0
	241	*/
44358048 MD	242	irq_get_chip(irq)->irq_mask(irq_get_irq_data(irq));
	243	intc_irqpin_irq_disable(d);
	244	}
	245
	246	#define INTC_IRQ_SENSE_VALID 0x10
	247	#define INTC_IRQ_SENSE(x) (x + INTC_IRQ_SENSE_VALID)
	248
	249	static unsigned char intc_irqpin_sense[IRQ_TYPE_SENSE_MASK + 1] = {
	250	[IRQ_TYPE_EDGE_FALLING] = INTC_IRQ_SENSE(0x00),
	251	[IRQ_TYPE_EDGE_RISING] = INTC_IRQ_SENSE(0x01),
	252	[IRQ_TYPE_LEVEL_LOW] = INTC_IRQ_SENSE(0x02),
	253	[IRQ_TYPE_LEVEL_HIGH] = INTC_IRQ_SENSE(0x03),
	254	[IRQ_TYPE_EDGE_BOTH] = INTC_IRQ_SENSE(0x04),
	255	};
	256
	257	static int intc_irqpin_irq_set_type(struct irq_data *d, unsigned int type)
	258	{
	259	unsigned char value = intc_irqpin_sense[type & IRQ_TYPE_SENSE_MASK];
	260	struct intc_irqpin_priv *p = irq_data_get_irq_chip_data(d);
	261
	262	if (!(value & INTC_IRQ_SENSE_VALID))
	263	return -EINVAL;
	264
	265	return intc_irqpin_set_sense(p, irqd_to_hwirq(d),
	266	value ^ INTC_IRQ_SENSE_VALID);
	267	}
	268
705bc96c GU	269	static int intc_irqpin_irq_set_wake(struct irq_data *d, unsigned int on)
	270	{
	271	struct intc_irqpin_priv *p = irq_data_get_irq_chip_data(d);
f4e209cd GU	272	int hw_irq = irqd_to_hwirq(d);
	273
	274	irq_set_irq_wake(p->irq[hw_irq].requested_irq, on);
705bc96c	275	if (on)
66bf8252	276	atomic_inc(&p->wakeup_path);
705bc96c	277	else
66bf8252	278	atomic_dec(&p->wakeup_path);
705bc96c GU	279
	280	return 0;
	281	}
	282
44358048 MD	283	static irqreturn_t intc_irqpin_irq_handler(int irq, void *dev_id)
	284	{
	285	struct intc_irqpin_irq *i = dev_id;
	286	struct intc_irqpin_priv *p = i->p;
	287	unsigned long bit;
	288
	289	intc_irqpin_dbg(i, "demux1");
	290	bit = intc_irqpin_hwirq_mask(p, INTC_IRQPIN_REG_SOURCE, i->hw_irq);
	291
	292	if (intc_irqpin_read(p, INTC_IRQPIN_REG_SOURCE) & bit) {
	293	intc_irqpin_write(p, INTC_IRQPIN_REG_SOURCE, ~bit);
	294	intc_irqpin_dbg(i, "demux2");
33f958f2	295	generic_handle_irq(i->domain_irq);
44358048 MD	296	return IRQ_HANDLED;
	297	}
	298	return IRQ_NONE;
	299	}
	300
427cc720 BH	301	static irqreturn_t intc_irqpin_shared_irq_handler(int irq, void *dev_id)
	302	{
	303	struct intc_irqpin_priv *p = dev_id;
	304	unsigned int reg_source = intc_irqpin_read(p, INTC_IRQPIN_REG_SOURCE);
	305	irqreturn_t status = IRQ_NONE;
	306	int k;
	307
	308	for (k = 0; k < 8; k++) {
	309	if (reg_source & BIT(7 - k)) {
	310	if (BIT(k) & p->shared_irq_mask)
	311	continue;
	312
	313	status \|= intc_irqpin_irq_handler(irq, &p->irq[k]);
	314	}
	315	}
	316
	317	return status;
	318	}
	319
769b5cf7 GU	320	/*
	321	* This lock class tells lockdep that INTC External IRQ Pin irqs are in a
	322	* different category than their parents, so it won't report false recursion.
	323	*/
	324	static struct lock_class_key intc_irqpin_irq_lock_class;
	325
39c3fd58 AL	326	/* And this is for the request mutex */
	327	static struct lock_class_key intc_irqpin_irq_request_class;
	328
44358048 MD	329	static int intc_irqpin_irq_domain_map(struct irq_domain *h, unsigned int virq,
	330	irq_hw_number_t hw)
	331	{
	332	struct intc_irqpin_priv *p = h->host_data;
	333
33f958f2 MD	334	p->irq[hw].domain_irq = virq;
	335	p->irq[hw].hw_irq = hw;
	336
44358048 MD	337	intc_irqpin_dbg(&p->irq[hw], "map");
44358048 MD	338	irq_set_chip_data(virq, h->host_data);
39c3fd58 AL	339	irq_set_lockdep_class(virq, &intc_irqpin_irq_lock_class,
39c3fd58 AL	340	&intc_irqpin_irq_request_class);
44358048	341	irq_set_chip_and_handler(virq, &p->irq_chip, handle_level_irq);
44358048 MD	342	return 0;
	343	}
	344
96009736	345	static const struct irq_domain_ops intc_irqpin_irq_domain_ops = {
44358048	346	.map = intc_irqpin_irq_domain_map,
9d833bbe	347	.xlate = irq_domain_xlate_twocell,
44358048 MD	348	};
44358048 MD	349
86e57ca7	350	static const struct intc_irqpin_config intc_irqpin_irlm_r8a777x = {
e03f9088	351	.irlm_bit = 23, /* ICR0.IRLM0 */
86e57ca7	352	.needs_irlm = 1,
86e57ca7 GU	353	};
	354
	355	static const struct intc_irqpin_config intc_irqpin_rmobile = {
	356	.needs_irlm = 0,
e03f9088 MD	357	};
	358
	359	static const struct of_device_id intc_irqpin_dt_ids[] = {
	360	{ .compatible = "renesas,intc-irqpin", },
26c21dd9 UH	361	{ .compatible = "renesas,intc-irqpin-r8a7778",
26c21dd9 UH	362	.data = &intc_irqpin_irlm_r8a777x },
e03f9088	363	{ .compatible = "renesas,intc-irqpin-r8a7779",
26c21dd9	364	.data = &intc_irqpin_irlm_r8a777x },
86e57ca7 GU	365	{ .compatible = "renesas,intc-irqpin-r8a7740",
	366	.data = &intc_irqpin_rmobile },
	367	{ .compatible = "renesas,intc-irqpin-sh73a0",
	368	.data = &intc_irqpin_rmobile },
e03f9088 MD	369	{},
	370	};
	371	MODULE_DEVICE_TABLE(of, intc_irqpin_dt_ids);
	372
44358048 MD	373	static int intc_irqpin_probe(struct platform_device *pdev)
44358048 MD	374	{
42a5968c	375	const struct intc_irqpin_config *config;
36845f1b	376	struct device *dev = &pdev->dev;
44358048 MD	377	struct intc_irqpin_priv *p;
	378	struct intc_irqpin_iomem *i;
	379	struct resource *io[INTC_IRQPIN_REG_NR];
	380	struct resource *irq;
	381	struct irq_chip *irq_chip;
	382	void (enable_fn)(struct irq_data d);
	383	void (disable_fn)(struct irq_data d);
36845f1b	384	const char *name = dev_name(dev);
f9551a9c	385	bool control_parent;
1affe594	386	unsigned int nirqs;
427cc720	387	int ref_irq;
44358048 MD	388	int ret;
	389	int k;
	390
36845f1b	391	p = devm_kzalloc(dev, sizeof(*p), GFP_KERNEL);
44358048	392	if (!p) {
36845f1b	393	dev_err(dev, "failed to allocate driver data\n");
705bc96c	394	return -ENOMEM;
44358048 MD	395	}
	396
	397	/* deal with driver instance configuration */
f9551a9c GU	398	of_property_read_u32(dev->of_node, "sense-bitfield-width",
	399	&p->sense_bitfield_width);
	400	control_parent = of_property_read_bool(dev->of_node, "control-parent");
	401	if (!p->sense_bitfield_width)
	402	p->sense_bitfield_width = 4; /* default to 4 bits */
44358048 MD	403
	404	p->pdev = pdev;
	405	platform_set_drvdata(pdev, p);
	406
42a5968c	407	config = of_device_get_match_data(dev);
705bc96c GU	408
	409	pm_runtime_enable(dev);
	410	pm_runtime_get_sync(dev);
	411
e03f9088 MD	412	/* get hold of register banks */
e03f9088 MD	413	memset(io, 0, sizeof(io));
44358048 MD	414	for (k = 0; k < INTC_IRQPIN_REG_NR; k++) {
44358048 MD	415	io[k] = platform_get_resource(pdev, IORESOURCE_MEM, k);
e03f9088	416	if (!io[k] && k < INTC_IRQPIN_REG_NR_MANDATORY) {
36845f1b	417	dev_err(dev, "not enough IOMEM resources\n");
44358048	418	ret = -EINVAL;
08eba5ba	419	goto err0;
44358048 MD	420	}
	421	}
	422
	423	/* allow any number of IRQs between 1 and INTC_IRQPIN_MAX */
	424	for (k = 0; k < INTC_IRQPIN_MAX; k++) {
	425	irq = platform_get_resource(pdev, IORESOURCE_IRQ, k);
	426	if (!irq)
	427	break;
	428
44358048	429	p->irq[k].p = p;
33f958f2	430	p->irq[k].requested_irq = irq->start;
44358048 MD	431	}
44358048 MD	432
1affe594 GU	433	nirqs = k;
1affe594 GU	434	if (nirqs < 1) {
36845f1b	435	dev_err(dev, "not enough IRQ resources\n");
44358048	436	ret = -EINVAL;
08eba5ba	437	goto err0;
44358048 MD	438	}
	439
	440	/* ioremap IOMEM and setup read/write callbacks */
	441	for (k = 0; k < INTC_IRQPIN_REG_NR; k++) {
	442	i = &p->iomem[k];
	443
e03f9088 MD	444	/* handle optional registers */
	445	if (!io[k])
	446	continue;
	447
44358048 MD	448	switch (resource_size(io[k])) {
	449	case 1:
	450	i->width = 8;
	451	i->read = intc_irqpin_read8;
	452	i->write = intc_irqpin_write8;
	453	break;
	454	case 4:
	455	i->width = 32;
	456	i->read = intc_irqpin_read32;
	457	i->write = intc_irqpin_write32;
	458	break;
	459	default:
36845f1b	460	dev_err(dev, "IOMEM size mismatch\n");
44358048	461	ret = -EINVAL;
08eba5ba	462	goto err0;
44358048 MD	463	}
44358048 MD	464
36845f1b	465	i->iomem = devm_ioremap_nocache(dev, io[k]->start,
08eba5ba	466	resource_size(io[k]));
44358048	467	if (!i->iomem) {
36845f1b	468	dev_err(dev, "failed to remap IOMEM\n");
44358048	469	ret = -ENXIO;
08eba5ba	470	goto err0;
44358048 MD	471	}
	472	}
	473
e03f9088	474	/* configure "individual IRQ mode" where needed */
86e57ca7	475	if (config && config->needs_irlm) {
e03f9088 MD	476	if (io[INTC_IRQPIN_REG_IRLM])
e03f9088 MD	477	intc_irqpin_read_modify_write(p, INTC_IRQPIN_REG_IRLM,
86e57ca7	478	config->irlm_bit, 1, 1);
e03f9088 MD	479	else
	480	dev_warn(dev, "unable to select IRLM mode\n");
	481	}
	482
44358048	483	/* mask all interrupts using priority */
1affe594	484	for (k = 0; k < nirqs; k++)
44358048 MD	485	intc_irqpin_mask_unmask_prio(p, k, 1);
44358048 MD	486
427cc720 BH	487	/* clear all pending interrupts */
	488	intc_irqpin_write(p, INTC_IRQPIN_REG_SOURCE, 0x0);
	489
	490	/* scan for shared interrupt lines */
	491	ref_irq = p->irq[0].requested_irq;
86e57ca7	492	p->shared_irqs = 1;
1affe594	493	for (k = 1; k < nirqs; k++) {
427cc720	494	if (ref_irq != p->irq[k].requested_irq) {
86e57ca7	495	p->shared_irqs = 0;
427cc720 BH	496	break;
	497	}
	498	}
	499
44358048	500	/* use more severe masking method if requested */
f9551a9c	501	if (control_parent) {
44358048 MD	502	enable_fn = intc_irqpin_irq_enable_force;
44358048 MD	503	disable_fn = intc_irqpin_irq_disable_force;
427cc720	504	} else if (!p->shared_irqs) {
44358048 MD	505	enable_fn = intc_irqpin_irq_enable;
44358048 MD	506	disable_fn = intc_irqpin_irq_disable;
427cc720 BH	507	} else {
	508	enable_fn = intc_irqpin_shared_irq_enable;
	509	disable_fn = intc_irqpin_shared_irq_disable;
44358048 MD	510	}
	511
	512	irq_chip = &p->irq_chip;
	513	irq_chip->name = name;
	514	irq_chip->irq_mask = disable_fn;
	515	irq_chip->irq_unmask = enable_fn;
44358048	516	irq_chip->irq_set_type = intc_irqpin_irq_set_type;
705bc96c GU	517	irq_chip->irq_set_wake = intc_irqpin_irq_set_wake;
705bc96c GU	518	irq_chip->flags = IRQCHIP_MASK_ON_SUSPEND;
44358048	519
1affe594 GU	520	p->irq_domain = irq_domain_add_simple(dev->of_node, nirqs, 0,
1affe594 GU	521	&intc_irqpin_irq_domain_ops, p);
44358048 MD	522	if (!p->irq_domain) {
44358048 MD	523	ret = -ENXIO;
36845f1b	524	dev_err(dev, "cannot initialize irq domain\n");
08eba5ba	525	goto err0;
44358048 MD	526	}
44358048 MD	527
427cc720 BH	528	if (p->shared_irqs) {
427cc720 BH	529	/* request one shared interrupt */
36845f1b	530	if (devm_request_irq(dev, p->irq[0].requested_irq,
427cc720 BH	531	intc_irqpin_shared_irq_handler,
427cc720 BH	532	IRQF_SHARED, name, p)) {
36845f1b	533	dev_err(dev, "failed to request low IRQ\n");
44358048	534	ret = -ENOENT;
08eba5ba	535	goto err1;
44358048	536	}
427cc720 BH	537	} else {
427cc720 BH	538	/* request interrupts one by one */
1affe594	539	for (k = 0; k < nirqs; k++) {
36845f1b GU	540	if (devm_request_irq(dev, p->irq[k].requested_irq,
	541	intc_irqpin_irq_handler, 0, name,
	542	&p->irq[k])) {
	543	dev_err(dev, "failed to request low IRQ\n");
427cc720 BH	544	ret = -ENOENT;
	545	goto err1;
	546	}
	547	}
44358048 MD	548	}
44358048 MD	549
427cc720	550	/* unmask all interrupts on prio level */
1affe594	551	for (k = 0; k < nirqs; k++)
427cc720 BH	552	intc_irqpin_mask_unmask_prio(p, k, 0);
427cc720 BH	553
1affe594	554	dev_info(dev, "driving %d irqs\n", nirqs);
44358048	555
44358048 MD	556	return 0;
44358048 MD	557
44358048	558	err1:
08eba5ba	559	irq_domain_remove(p->irq_domain);
44358048	560	err0:
705bc96c GU	561	pm_runtime_put(dev);
705bc96c GU	562	pm_runtime_disable(dev);
44358048 MD	563	return ret;
	564	}
	565
	566	static int intc_irqpin_remove(struct platform_device *pdev)
	567	{
	568	struct intc_irqpin_priv *p = platform_get_drvdata(pdev);
44358048 MD	569
44358048 MD	570	irq_domain_remove(p->irq_domain);
705bc96c GU	571	pm_runtime_put(&pdev->dev);
705bc96c GU	572	pm_runtime_disable(&pdev->dev);
44358048 MD	573	return 0;
	574	}
	575
66bf8252 GU	576	static int __maybe_unused intc_irqpin_suspend(struct device *dev)
	577	{
	578	struct intc_irqpin_priv *p = dev_get_drvdata(dev);
	579
	580	if (atomic_read(&p->wakeup_path))
	581	device_set_wakeup_path(dev);
	582
	583	return 0;
	584	}
	585
	586	static SIMPLE_DEV_PM_OPS(intc_irqpin_pm_ops, intc_irqpin_suspend, NULL);
	587
44358048 MD	588	static struct platform_driver intc_irqpin_device_driver = {
	589	.probe = intc_irqpin_probe,
	590	.remove = intc_irqpin_remove,
	591	.driver = {
	592	.name = "renesas_intc_irqpin",
9d833bbe	593	.of_match_table = intc_irqpin_dt_ids,
66bf8252	594	.pm = &intc_irqpin_pm_ops,
44358048 MD	595	}
	596	};
	597
	598	static int __init intc_irqpin_init(void)
	599	{
	600	return platform_driver_register(&intc_irqpin_device_driver);
	601	}
	602	postcore_initcall(intc_irqpin_init);
	603
	604	static void __exit intc_irqpin_exit(void)
	605	{
	606	platform_driver_unregister(&intc_irqpin_device_driver);
	607	}
	608	module_exit(intc_irqpin_exit);
	609
	610	MODULE_AUTHOR("Magnus Damm");
	611	MODULE_DESCRIPTION("Renesas INTC External IRQ Pin Driver");
	612	MODULE_LICENSE("GPL v2");