[mirror_ubuntu-artful-kernel.git] / drivers / irqchip / irq-renesas-intc-irqpin.c

/*
 * Renesas INTC External IRQ Pin Driver
 *
 *  Copyright (C) 2013 Magnus Damm
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
 */

#include <linux/clk.h>
#include <linux/init.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/spinlock.h>
#include <linux/interrupt.h>
#include <linux/ioport.h>
#include <linux/io.h>
#include <linux/irq.h>
#include <linux/irqdomain.h>
#include <linux/err.h>
#include <linux/slab.h>
#include <linux/module.h>
#include <linux/of_device.h>
#include <linux/platform_data/irq-renesas-intc-irqpin.h>
#include <linux/pm_runtime.h>

#define INTC_IRQPIN_MAX 8 /* maximum 8 interrupts per driver instance */

#define INTC_IRQPIN_REG_SENSE 0 /* ICRn */
#define INTC_IRQPIN_REG_PRIO 1 /* INTPRInn */
#define INTC_IRQPIN_REG_SOURCE 2 /* INTREQnn */
#define INTC_IRQPIN_REG_MASK 3 /* INTMSKnn */
#define INTC_IRQPIN_REG_CLEAR 4 /* INTMSKCLRnn */
#define INTC_IRQPIN_REG_NR_MANDATORY 5
#define INTC_IRQPIN_REG_IRLM 5 /* ICR0 with IRLM bit (optional) */
#define INTC_IRQPIN_REG_NR 6

/* INTC external IRQ PIN hardware register access:
 *
 * SENSE is read-write 32-bit with 2-bits or 4-bits per IRQ (*)
 * PRIO is read-write 32-bit with 4-bits per IRQ (**)
 * SOURCE is read-only 32-bit or 8-bit with 1-bit per IRQ (***)
 * MASK is write-only 32-bit or 8-bit with 1-bit per IRQ (***)
 * CLEAR is write-only 32-bit or 8-bit with 1-bit per IRQ (***)
 *
 * (*) May be accessed by more than one driver instance - lock needed
 * (**) Read-modify-write access by one driver instance - lock needed
 * (***) Accessed by one driver instance only - no locking needed
 */

struct intc_irqpin_iomem {
	void __iomem *iomem;
	unsigned long (*read)(void __iomem *iomem);
	void (*write)(void __iomem *iomem, unsigned long data);
	int width;
};

struct intc_irqpin_irq {
	int hw_irq;
	int requested_irq;
	int domain_irq;
	struct intc_irqpin_priv *p;
};

struct intc_irqpin_priv {
	struct intc_irqpin_iomem iomem[INTC_IRQPIN_REG_NR];
	struct intc_irqpin_irq irq[INTC_IRQPIN_MAX];
	struct renesas_intc_irqpin_config config;
	unsigned int number_of_irqs;
	struct platform_device *pdev;
	struct irq_chip irq_chip;
	struct irq_domain *irq_domain;
	struct clk *clk;
	bool shared_irqs;
	u8 shared_irq_mask;
};

struct intc_irqpin_irlm_config {
	unsigned int irlm_bit;
};

static unsigned long intc_irqpin_read32(void __iomem *iomem)
{
	return ioread32(iomem);
}

static unsigned long intc_irqpin_read8(void __iomem *iomem)
{
	return ioread8(iomem);
}

static void intc_irqpin_write32(void __iomem *iomem, unsigned long data)
{
	iowrite32(data, iomem);
}

static void intc_irqpin_write8(void __iomem *iomem, unsigned long data)
{
	iowrite8(data, iomem);
}

static inline unsigned long intc_irqpin_read(struct intc_irqpin_priv *p,
					     int reg)
{
	struct intc_irqpin_iomem *i = &p->iomem[reg];

	return i->read(i->iomem);
}

static inline void intc_irqpin_write(struct intc_irqpin_priv *p,
				     int reg, unsigned long data)
{
	struct intc_irqpin_iomem *i = &p->iomem[reg];

	i->write(i->iomem, data);
}

static inline unsigned long intc_irqpin_hwirq_mask(struct intc_irqpin_priv *p,
						   int reg, int hw_irq)
{
	return BIT((p->iomem[reg].width - 1) - hw_irq);
}

static inline void intc_irqpin_irq_write_hwirq(struct intc_irqpin_priv *p,
					       int reg, int hw_irq)
{
	intc_irqpin_write(p, reg, intc_irqpin_hwirq_mask(p, reg, hw_irq));
}

static DEFINE_RAW_SPINLOCK(intc_irqpin_lock); /* only used by slow path */

static void intc_irqpin_read_modify_write(struct intc_irqpin_priv *p,
					  int reg, int shift,
					  int width, int value)
{
	unsigned long flags;
	unsigned long tmp;

	raw_spin_lock_irqsave(&intc_irqpin_lock, flags);

	tmp = intc_irqpin_read(p, reg);
	tmp &= ~(((1 << width) - 1) << shift);
	tmp |= value << shift;
	intc_irqpin_write(p, reg, tmp);

	raw_spin_unlock_irqrestore(&intc_irqpin_lock, flags);
}

static void intc_irqpin_mask_unmask_prio(struct intc_irqpin_priv *p,
					 int irq, int do_mask)
{
	/* The PRIO register is assumed to be 32-bit with fixed 4-bit fields. */
	int bitfield_width = 4;
	int shift = 32 - (irq + 1) * bitfield_width;

	intc_irqpin_read_modify_write(p, INTC_IRQPIN_REG_PRIO,
				      shift, bitfield_width,
				      do_mask ? 0 : (1 << bitfield_width) - 1);
}

static int intc_irqpin_set_sense(struct intc_irqpin_priv *p, int irq, int value)
{
	/* The SENSE register is assumed to be 32-bit. */
	int bitfield_width = p->config.sense_bitfield_width;
	int shift = 32 - (irq + 1) * bitfield_width;

	dev_dbg(&p->pdev->dev, "sense irq = %d, mode = %d\n", irq, value);

	if (value >= (1 << bitfield_width))
		return -EINVAL;

	intc_irqpin_read_modify_write(p, INTC_IRQPIN_REG_SENSE, shift,
				      bitfield_width, value);
	return 0;
}

static void intc_irqpin_dbg(struct intc_irqpin_irq *i, char *str)
{
	dev_dbg(&i->p->pdev->dev, "%s (%d:%d:%d)\n",
		str, i->requested_irq, i->hw_irq, i->domain_irq);
}

static void intc_irqpin_irq_enable(struct irq_data *d)
{
	struct intc_irqpin_priv *p = irq_data_get_irq_chip_data(d);
	int hw_irq = irqd_to_hwirq(d);

	intc_irqpin_dbg(&p->irq[hw_irq], "enable");
	intc_irqpin_irq_write_hwirq(p, INTC_IRQPIN_REG_CLEAR, hw_irq);
}

static void intc_irqpin_irq_disable(struct irq_data *d)
{
	struct intc_irqpin_priv *p = irq_data_get_irq_chip_data(d);
	int hw_irq = irqd_to_hwirq(d);

	intc_irqpin_dbg(&p->irq[hw_irq], "disable");
	intc_irqpin_irq_write_hwirq(p, INTC_IRQPIN_REG_MASK, hw_irq);
}

static void intc_irqpin_shared_irq_enable(struct irq_data *d)
{
	struct intc_irqpin_priv *p = irq_data_get_irq_chip_data(d);
	int hw_irq = irqd_to_hwirq(d);

	intc_irqpin_dbg(&p->irq[hw_irq], "shared enable");
	intc_irqpin_irq_write_hwirq(p, INTC_IRQPIN_REG_CLEAR, hw_irq);

	p->shared_irq_mask &= ~BIT(hw_irq);
}

static void intc_irqpin_shared_irq_disable(struct irq_data *d)
{
	struct intc_irqpin_priv *p = irq_data_get_irq_chip_data(d);
	int hw_irq = irqd_to_hwirq(d);

	intc_irqpin_dbg(&p->irq[hw_irq], "shared disable");
	intc_irqpin_irq_write_hwirq(p, INTC_IRQPIN_REG_MASK, hw_irq);

	p->shared_irq_mask |= BIT(hw_irq);
}

static void intc_irqpin_irq_enable_force(struct irq_data *d)
{
	struct intc_irqpin_priv *p = irq_data_get_irq_chip_data(d);
	int irq = p->irq[irqd_to_hwirq(d)].requested_irq;

	intc_irqpin_irq_enable(d);

	/* enable interrupt through parent interrupt controller,
	 * assumes non-shared interrupt with 1:1 mapping
	 * needed for busted IRQs on some SoCs like sh73a0
	 */
	irq_get_chip(irq)->irq_unmask(irq_get_irq_data(irq));
}

static void intc_irqpin_irq_disable_force(struct irq_data *d)
{
	struct intc_irqpin_priv *p = irq_data_get_irq_chip_data(d);
	int irq = p->irq[irqd_to_hwirq(d)].requested_irq;

	/* disable interrupt through parent interrupt controller,
	 * assumes non-shared interrupt with 1:1 mapping
	 * needed for busted IRQs on some SoCs like sh73a0
	 */
	irq_get_chip(irq)->irq_mask(irq_get_irq_data(irq));
	intc_irqpin_irq_disable(d);
}

#define INTC_IRQ_SENSE_VALID 0x10
#define INTC_IRQ_SENSE(x) (x + INTC_IRQ_SENSE_VALID)

static unsigned char intc_irqpin_sense[IRQ_TYPE_SENSE_MASK + 1] = {
	[IRQ_TYPE_EDGE_FALLING] = INTC_IRQ_SENSE(0x00),
	[IRQ_TYPE_EDGE_RISING] = INTC_IRQ_SENSE(0x01),
	[IRQ_TYPE_LEVEL_LOW] = INTC_IRQ_SENSE(0x02),
	[IRQ_TYPE_LEVEL_HIGH] = INTC_IRQ_SENSE(0x03),
	[IRQ_TYPE_EDGE_BOTH] = INTC_IRQ_SENSE(0x04),
};

static int intc_irqpin_irq_set_type(struct irq_data *d, unsigned int type)
{
	unsigned char value = intc_irqpin_sense[type & IRQ_TYPE_SENSE_MASK];
	struct intc_irqpin_priv *p = irq_data_get_irq_chip_data(d);

	if (!(value & INTC_IRQ_SENSE_VALID))
		return -EINVAL;

	return intc_irqpin_set_sense(p, irqd_to_hwirq(d),
				     value ^ INTC_IRQ_SENSE_VALID);
}

static int intc_irqpin_irq_set_wake(struct irq_data *d, unsigned int on)
{
	struct intc_irqpin_priv *p = irq_data_get_irq_chip_data(d);

	if (!p->clk)
		return 0;

	if (on)
		clk_enable(p->clk);
	else
		clk_disable(p->clk);

	return 0;
}

static irqreturn_t intc_irqpin_irq_handler(int irq, void *dev_id)
{
	struct intc_irqpin_irq *i = dev_id;
	struct intc_irqpin_priv *p = i->p;
	unsigned long bit;

	intc_irqpin_dbg(i, "demux1");
	bit = intc_irqpin_hwirq_mask(p, INTC_IRQPIN_REG_SOURCE, i->hw_irq);

	if (intc_irqpin_read(p, INTC_IRQPIN_REG_SOURCE) & bit) {
		intc_irqpin_write(p, INTC_IRQPIN_REG_SOURCE, ~bit);
		intc_irqpin_dbg(i, "demux2");
		generic_handle_irq(i->domain_irq);
		return IRQ_HANDLED;
	}
	return IRQ_NONE;
}

static irqreturn_t intc_irqpin_shared_irq_handler(int irq, void *dev_id)
{
	struct intc_irqpin_priv *p = dev_id;
	unsigned int reg_source = intc_irqpin_read(p, INTC_IRQPIN_REG_SOURCE);
	irqreturn_t status = IRQ_NONE;
	int k;

	for (k = 0; k < 8; k++) {
		if (reg_source & BIT(7 - k)) {
			if (BIT(k) & p->shared_irq_mask)
				continue;

			status |= intc_irqpin_irq_handler(irq, &p->irq[k]);
		}
	}

	return status;
}

static int intc_irqpin_irq_domain_map(struct irq_domain *h, unsigned int virq,
				      irq_hw_number_t hw)
{
	struct intc_irqpin_priv *p = h->host_data;

	p->irq[hw].domain_irq = virq;
	p->irq[hw].hw_irq = hw;

	intc_irqpin_dbg(&p->irq[hw], "map");
	irq_set_chip_data(virq, h->host_data);
	irq_set_chip_and_handler(virq, &p->irq_chip, handle_level_irq);
	set_irq_flags(virq, IRQF_VALID); /* kill me now */
	return 0;
}

static struct irq_domain_ops intc_irqpin_irq_domain_ops = {
	.map	= intc_irqpin_irq_domain_map,
	.xlate  = irq_domain_xlate_twocell,
};

static const struct intc_irqpin_irlm_config intc_irqpin_irlm_r8a7779 = {
	.irlm_bit = 23, /* ICR0.IRLM0 */
};

static const struct of_device_id intc_irqpin_dt_ids[] = {
	{ .compatible = "renesas,intc-irqpin", },
	{ .compatible = "renesas,intc-irqpin-r8a7779",
	  .data = &intc_irqpin_irlm_r8a7779 },
	{},
};
MODULE_DEVICE_TABLE(of, intc_irqpin_dt_ids);

static int intc_irqpin_probe(struct platform_device *pdev)
{
	struct device *dev = &pdev->dev;
	struct renesas_intc_irqpin_config *pdata = dev->platform_data;
	const struct of_device_id *of_id;
	struct intc_irqpin_priv *p;
	struct intc_irqpin_iomem *i;
	struct resource *io[INTC_IRQPIN_REG_NR];
	struct resource *irq;
	struct irq_chip *irq_chip;
	void (*enable_fn)(struct irq_data *d);
	void (*disable_fn)(struct irq_data *d);
	const char *name = dev_name(dev);
	int ref_irq;
	int ret;
	int k;

	p = devm_kzalloc(dev, sizeof(*p), GFP_KERNEL);
	if (!p) {
		dev_err(dev, "failed to allocate driver data\n");
		return -ENOMEM;
	}

	/* deal with driver instance configuration */
	if (pdata) {
		memcpy(&p->config, pdata, sizeof(*pdata));
	} else {
		of_property_read_u32(dev->of_node, "sense-bitfield-width",
				     &p->config.sense_bitfield_width);
		p->config.control_parent = of_property_read_bool(dev->of_node,
								 "control-parent");
	}
	if (!p->config.sense_bitfield_width)
		p->config.sense_bitfield_width = 4; /* default to 4 bits */

	p->pdev = pdev;
	platform_set_drvdata(pdev, p);

	p->clk = devm_clk_get(dev, NULL);
	if (IS_ERR(p->clk)) {
		dev_warn(dev, "unable to get clock\n");
		p->clk = NULL;
	}

	pm_runtime_enable(dev);
	pm_runtime_get_sync(dev);

	/* get hold of register banks */
	memset(io, 0, sizeof(io));
	for (k = 0; k < INTC_IRQPIN_REG_NR; k++) {
		io[k] = platform_get_resource(pdev, IORESOURCE_MEM, k);
		if (!io[k] && k < INTC_IRQPIN_REG_NR_MANDATORY) {
			dev_err(dev, "not enough IOMEM resources\n");
			ret = -EINVAL;
			goto err0;
		}
	}

	/* allow any number of IRQs between 1 and INTC_IRQPIN_MAX */
	for (k = 0; k < INTC_IRQPIN_MAX; k++) {
		irq = platform_get_resource(pdev, IORESOURCE_IRQ, k);
		if (!irq)
			break;

		p->irq[k].p = p;
		p->irq[k].requested_irq = irq->start;
	}

	p->number_of_irqs = k;
	if (p->number_of_irqs < 1) {
		dev_err(dev, "not enough IRQ resources\n");
		ret = -EINVAL;
		goto err0;
	}

	/* ioremap IOMEM and setup read/write callbacks */
	for (k = 0; k < INTC_IRQPIN_REG_NR; k++) {
		i = &p->iomem[k];

		/* handle optional registers */
		if (!io[k])
			continue;

		switch (resource_size(io[k])) {
		case 1:
			i->width = 8;
			i->read = intc_irqpin_read8;
			i->write = intc_irqpin_write8;
			break;
		case 4:
			i->width = 32;
			i->read = intc_irqpin_read32;
			i->write = intc_irqpin_write32;
			break;
		default:
			dev_err(dev, "IOMEM size mismatch\n");
			ret = -EINVAL;
			goto err0;
		}

		i->iomem = devm_ioremap_nocache(dev, io[k]->start,
						resource_size(io[k]));
		if (!i->iomem) {
			dev_err(dev, "failed to remap IOMEM\n");
			ret = -ENXIO;
			goto err0;
		}
	}

	/* configure "individual IRQ mode" where needed */
	of_id = of_match_device(intc_irqpin_dt_ids, dev);
	if (of_id && of_id->data) {
		const struct intc_irqpin_irlm_config *irlm_config = of_id->data;

		if (io[INTC_IRQPIN_REG_IRLM])
			intc_irqpin_read_modify_write(p, INTC_IRQPIN_REG_IRLM,
						      irlm_config->irlm_bit,
						      1, 1);
		else
			dev_warn(dev, "unable to select IRLM mode\n");
	}

	/* mask all interrupts using priority */
	for (k = 0; k < p->number_of_irqs; k++)
		intc_irqpin_mask_unmask_prio(p, k, 1);

	/* clear all pending interrupts */
	intc_irqpin_write(p, INTC_IRQPIN_REG_SOURCE, 0x0);

	/* scan for shared interrupt lines */
	ref_irq = p->irq[0].requested_irq;
	p->shared_irqs = true;
	for (k = 1; k < p->number_of_irqs; k++) {
		if (ref_irq != p->irq[k].requested_irq) {
			p->shared_irqs = false;
			break;
		}
	}

	/* use more severe masking method if requested */
	if (p->config.control_parent) {
		enable_fn = intc_irqpin_irq_enable_force;
		disable_fn = intc_irqpin_irq_disable_force;
	} else if (!p->shared_irqs) {
		enable_fn = intc_irqpin_irq_enable;
		disable_fn = intc_irqpin_irq_disable;
	} else {
		enable_fn = intc_irqpin_shared_irq_enable;
		disable_fn = intc_irqpin_shared_irq_disable;
	}

	irq_chip = &p->irq_chip;
	irq_chip->name = name;
	irq_chip->irq_mask = disable_fn;
	irq_chip->irq_unmask = enable_fn;
	irq_chip->irq_set_type = intc_irqpin_irq_set_type;
	irq_chip->irq_set_wake = intc_irqpin_irq_set_wake;
	irq_chip->flags	= IRQCHIP_MASK_ON_SUSPEND;

	p->irq_domain = irq_domain_add_simple(dev->of_node,
					      p->number_of_irqs,
					      p->config.irq_base,
					      &intc_irqpin_irq_domain_ops, p);
	if (!p->irq_domain) {
		ret = -ENXIO;
		dev_err(dev, "cannot initialize irq domain\n");
		goto err0;
	}

	if (p->shared_irqs) {
		/* request one shared interrupt */
		if (devm_request_irq(dev, p->irq[0].requested_irq,
				intc_irqpin_shared_irq_handler,
				IRQF_SHARED, name, p)) {
			dev_err(dev, "failed to request low IRQ\n");
			ret = -ENOENT;
			goto err1;
		}
	} else {
		/* request interrupts one by one */
		for (k = 0; k < p->number_of_irqs; k++) {
			if (devm_request_irq(dev, p->irq[k].requested_irq,
					     intc_irqpin_irq_handler, 0, name,
					     &p->irq[k])) {
				dev_err(dev, "failed to request low IRQ\n");
				ret = -ENOENT;
				goto err1;
			}
		}
	}

	/* unmask all interrupts on prio level */
	for (k = 0; k < p->number_of_irqs; k++)
		intc_irqpin_mask_unmask_prio(p, k, 0);

	dev_info(dev, "driving %d irqs\n", p->number_of_irqs);

	/* warn in case of mismatch if irq base is specified */
	if (p->config.irq_base) {
		if (p->config.irq_base != p->irq[0].domain_irq)
			dev_warn(dev, "irq base mismatch (%d/%d)\n",
				 p->config.irq_base, p->irq[0].domain_irq);
	}

	return 0;

err1:
	irq_domain_remove(p->irq_domain);
err0:
	pm_runtime_put(dev);
	pm_runtime_disable(dev);
	return ret;
}

static int intc_irqpin_remove(struct platform_device *pdev)
{
	struct intc_irqpin_priv *p = platform_get_drvdata(pdev);

	irq_domain_remove(p->irq_domain);
	pm_runtime_put(&pdev->dev);
	pm_runtime_disable(&pdev->dev);
	return 0;
}

static struct platform_driver intc_irqpin_device_driver = {
	.probe		= intc_irqpin_probe,
	.remove		= intc_irqpin_remove,
	.driver		= {
		.name	= "renesas_intc_irqpin",
		.of_match_table = intc_irqpin_dt_ids,
	}
};

static int __init intc_irqpin_init(void)
{
	return platform_driver_register(&intc_irqpin_device_driver);
}
postcore_initcall(intc_irqpin_init);

static void __exit intc_irqpin_exit(void)
{
	platform_driver_unregister(&intc_irqpin_device_driver);
}
module_exit(intc_irqpin_exit);

MODULE_AUTHOR("Magnus Damm");
MODULE_DESCRIPTION("Renesas INTC External IRQ Pin Driver");
MODULE_LICENSE("GPL v2");
Commit	Line	Data
44358048 MD	1	/*
	2	* Renesas INTC External IRQ Pin Driver
	3	*
	4	* Copyright (C) 2013 Magnus Damm
	5	*
	6	* This program is free software; you can redistribute it and/or modify
	7	* it under the terms of the GNU General Public License as published by
	8	* the Free Software Foundation; either version 2 of the License
	9	*
	10	* This program is distributed in the hope that it will be useful,
	11	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	12	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	13	* GNU General Public License for more details.
	14	*
	15	* You should have received a copy of the GNU General Public License
	16	* along with this program; if not, write to the Free Software
	17	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	18	*/
	19
705bc96c	20	#include <linux/clk.h>
44358048	21	#include <linux/init.h>
894db164	22	#include <linux/of.h>
44358048 MD	23	#include <linux/platform_device.h>
	24	#include <linux/spinlock.h>
	25	#include <linux/interrupt.h>
	26	#include <linux/ioport.h>
	27	#include <linux/io.h>
	28	#include <linux/irq.h>
	29	#include <linux/irqdomain.h>
	30	#include <linux/err.h>
	31	#include <linux/slab.h>
	32	#include <linux/module.h>
e03f9088	33	#include <linux/of_device.h>
44358048	34	#include <linux/platform_data/irq-renesas-intc-irqpin.h>
705bc96c	35	#include <linux/pm_runtime.h>
44358048 MD	36
	37	#define INTC_IRQPIN_MAX 8 /* maximum 8 interrupts per driver instance */
	38
	39	#define INTC_IRQPIN_REG_SENSE 0 /* ICRn */
	40	#define INTC_IRQPIN_REG_PRIO 1 /* INTPRInn */
	41	#define INTC_IRQPIN_REG_SOURCE 2 /* INTREQnn */
	42	#define INTC_IRQPIN_REG_MASK 3 /* INTMSKnn */
	43	#define INTC_IRQPIN_REG_CLEAR 4 /* INTMSKCLRnn */
e03f9088 MD	44	#define INTC_IRQPIN_REG_NR_MANDATORY 5
	45	#define INTC_IRQPIN_REG_IRLM 5 /* ICR0 with IRLM bit (optional) */
	46	#define INTC_IRQPIN_REG_NR 6
44358048 MD	47
	48	/* INTC external IRQ PIN hardware register access:
	49	*
	50	* SENSE is read-write 32-bit with 2-bits or 4-bits per IRQ (*)
	51	* PRIO is read-write 32-bit with 4-bits per IRQ (**)
	52	* SOURCE is read-only 32-bit or 8-bit with 1-bit per IRQ (***)
	53	* MASK is write-only 32-bit or 8-bit with 1-bit per IRQ (***)
	54	* CLEAR is write-only 32-bit or 8-bit with 1-bit per IRQ (***)
	55	*
	56	* (*) May be accessed by more than one driver instance - lock needed
	57	* (**) Read-modify-write access by one driver instance - lock needed
	58	* (***) Accessed by one driver instance only - no locking needed
	59	*/
	60
	61	struct intc_irqpin_iomem {
	62	void __iomem *iomem;
	63	unsigned long (read)(void __iomem iomem);
	64	void (write)(void __iomem iomem, unsigned long data);
	65	int width;
862d3098	66	};
44358048 MD	67
	68	struct intc_irqpin_irq {
	69	int hw_irq;
33f958f2 MD	70	int requested_irq;
33f958f2 MD	71	int domain_irq;
44358048	72	struct intc_irqpin_priv *p;
862d3098	73	};
44358048 MD	74
	75	struct intc_irqpin_priv {
	76	struct intc_irqpin_iomem iomem[INTC_IRQPIN_REG_NR];
	77	struct intc_irqpin_irq irq[INTC_IRQPIN_MAX];
	78	struct renesas_intc_irqpin_config config;
	79	unsigned int number_of_irqs;
	80	struct platform_device *pdev;
	81	struct irq_chip irq_chip;
	82	struct irq_domain *irq_domain;
705bc96c	83	struct clk *clk;
427cc720 BH	84	bool shared_irqs;
427cc720 BH	85	u8 shared_irq_mask;
44358048 MD	86	};
44358048 MD	87
e03f9088 MD	88	struct intc_irqpin_irlm_config {
	89	unsigned int irlm_bit;
	90	};
	91
44358048 MD	92	static unsigned long intc_irqpin_read32(void __iomem *iomem)
	93	{
	94	return ioread32(iomem);
	95	}
	96
	97	static unsigned long intc_irqpin_read8(void __iomem *iomem)
	98	{
	99	return ioread8(iomem);
	100	}
	101
	102	static void intc_irqpin_write32(void __iomem *iomem, unsigned long data)
	103	{
	104	iowrite32(data, iomem);
	105	}
	106
	107	static void intc_irqpin_write8(void __iomem *iomem, unsigned long data)
	108	{
	109	iowrite8(data, iomem);
	110	}
	111
	112	static inline unsigned long intc_irqpin_read(struct intc_irqpin_priv *p,
	113	int reg)
	114	{
	115	struct intc_irqpin_iomem *i = &p->iomem[reg];
862d3098	116
44358048 MD	117	return i->read(i->iomem);
	118	}
	119
	120	static inline void intc_irqpin_write(struct intc_irqpin_priv *p,
	121	int reg, unsigned long data)
	122	{
	123	struct intc_irqpin_iomem *i = &p->iomem[reg];
862d3098	124
44358048 MD	125	i->write(i->iomem, data);
	126	}
	127
	128	static inline unsigned long intc_irqpin_hwirq_mask(struct intc_irqpin_priv *p,
	129	int reg, int hw_irq)
	130	{
	131	return BIT((p->iomem[reg].width - 1) - hw_irq);
	132	}
	133
	134	static inline void intc_irqpin_irq_write_hwirq(struct intc_irqpin_priv *p,
	135	int reg, int hw_irq)
	136	{
	137	intc_irqpin_write(p, reg, intc_irqpin_hwirq_mask(p, reg, hw_irq));
	138	}
	139
	140	static DEFINE_RAW_SPINLOCK(intc_irqpin_lock); /* only used by slow path */
	141
	142	static void intc_irqpin_read_modify_write(struct intc_irqpin_priv *p,
	143	int reg, int shift,
	144	int width, int value)
	145	{
	146	unsigned long flags;
	147	unsigned long tmp;
	148
	149	raw_spin_lock_irqsave(&intc_irqpin_lock, flags);
	150
	151	tmp = intc_irqpin_read(p, reg);
	152	tmp &= ~(((1 << width) - 1) << shift);
	153	tmp \|= value << shift;
	154	intc_irqpin_write(p, reg, tmp);
	155
	156	raw_spin_unlock_irqrestore(&intc_irqpin_lock, flags);
	157	}
	158
	159	static void intc_irqpin_mask_unmask_prio(struct intc_irqpin_priv *p,
	160	int irq, int do_mask)
	161	{
e55bc558 LP	162	/* The PRIO register is assumed to be 32-bit with fixed 4-bit fields. */
	163	int bitfield_width = 4;
	164	int shift = 32 - (irq + 1) * bitfield_width;
44358048 MD	165
	166	intc_irqpin_read_modify_write(p, INTC_IRQPIN_REG_PRIO,
	167	shift, bitfield_width,
	168	do_mask ? 0 : (1 << bitfield_width) - 1);
	169	}
	170
	171	static int intc_irqpin_set_sense(struct intc_irqpin_priv *p, int irq, int value)
	172	{
e55bc558	173	/* The SENSE register is assumed to be 32-bit. */
44358048	174	int bitfield_width = p->config.sense_bitfield_width;
e55bc558	175	int shift = 32 - (irq + 1) * bitfield_width;
44358048 MD	176
	177	dev_dbg(&p->pdev->dev, "sense irq = %d, mode = %d\n", irq, value);
	178
	179	if (value >= (1 << bitfield_width))
	180	return -EINVAL;
	181
	182	intc_irqpin_read_modify_write(p, INTC_IRQPIN_REG_SENSE, shift,
	183	bitfield_width, value);
	184	return 0;
	185	}
	186
	187	static void intc_irqpin_dbg(struct intc_irqpin_irq i, char str)
	188	{
	189	dev_dbg(&i->p->pdev->dev, "%s (%d:%d:%d)\n",
33f958f2	190	str, i->requested_irq, i->hw_irq, i->domain_irq);
44358048 MD	191	}
	192
	193	static void intc_irqpin_irq_enable(struct irq_data *d)
	194	{
	195	struct intc_irqpin_priv *p = irq_data_get_irq_chip_data(d);
	196	int hw_irq = irqd_to_hwirq(d);
	197
	198	intc_irqpin_dbg(&p->irq[hw_irq], "enable");
	199	intc_irqpin_irq_write_hwirq(p, INTC_IRQPIN_REG_CLEAR, hw_irq);
	200	}
	201
	202	static void intc_irqpin_irq_disable(struct irq_data *d)
	203	{
	204	struct intc_irqpin_priv *p = irq_data_get_irq_chip_data(d);
	205	int hw_irq = irqd_to_hwirq(d);
	206
	207	intc_irqpin_dbg(&p->irq[hw_irq], "disable");
	208	intc_irqpin_irq_write_hwirq(p, INTC_IRQPIN_REG_MASK, hw_irq);
	209	}
	210
427cc720 BH	211	static void intc_irqpin_shared_irq_enable(struct irq_data *d)
	212	{
	213	struct intc_irqpin_priv *p = irq_data_get_irq_chip_data(d);
	214	int hw_irq = irqd_to_hwirq(d);
	215
	216	intc_irqpin_dbg(&p->irq[hw_irq], "shared enable");
	217	intc_irqpin_irq_write_hwirq(p, INTC_IRQPIN_REG_CLEAR, hw_irq);
	218
	219	p->shared_irq_mask &= ~BIT(hw_irq);
	220	}
	221
	222	static void intc_irqpin_shared_irq_disable(struct irq_data *d)
	223	{
	224	struct intc_irqpin_priv *p = irq_data_get_irq_chip_data(d);
	225	int hw_irq = irqd_to_hwirq(d);
	226
	227	intc_irqpin_dbg(&p->irq[hw_irq], "shared disable");
	228	intc_irqpin_irq_write_hwirq(p, INTC_IRQPIN_REG_MASK, hw_irq);
	229
	230	p->shared_irq_mask \|= BIT(hw_irq);
	231	}
	232
44358048 MD	233	static void intc_irqpin_irq_enable_force(struct irq_data *d)
	234	{
	235	struct intc_irqpin_priv *p = irq_data_get_irq_chip_data(d);
33f958f2	236	int irq = p->irq[irqd_to_hwirq(d)].requested_irq;
44358048 MD	237
44358048 MD	238	intc_irqpin_irq_enable(d);
d1b6aecd MD	239
	240	/* enable interrupt through parent interrupt controller,
	241	* assumes non-shared interrupt with 1:1 mapping
	242	* needed for busted IRQs on some SoCs like sh73a0
	243	*/
44358048 MD	244	irq_get_chip(irq)->irq_unmask(irq_get_irq_data(irq));
	245	}
	246
	247	static void intc_irqpin_irq_disable_force(struct irq_data *d)
	248	{
	249	struct intc_irqpin_priv *p = irq_data_get_irq_chip_data(d);
33f958f2	250	int irq = p->irq[irqd_to_hwirq(d)].requested_irq;
44358048	251
d1b6aecd MD	252	/* disable interrupt through parent interrupt controller,
	253	* assumes non-shared interrupt with 1:1 mapping
	254	* needed for busted IRQs on some SoCs like sh73a0
	255	*/
44358048 MD	256	irq_get_chip(irq)->irq_mask(irq_get_irq_data(irq));
	257	intc_irqpin_irq_disable(d);
	258	}
	259
	260	#define INTC_IRQ_SENSE_VALID 0x10
	261	#define INTC_IRQ_SENSE(x) (x + INTC_IRQ_SENSE_VALID)
	262
	263	static unsigned char intc_irqpin_sense[IRQ_TYPE_SENSE_MASK + 1] = {
	264	[IRQ_TYPE_EDGE_FALLING] = INTC_IRQ_SENSE(0x00),
	265	[IRQ_TYPE_EDGE_RISING] = INTC_IRQ_SENSE(0x01),
	266	[IRQ_TYPE_LEVEL_LOW] = INTC_IRQ_SENSE(0x02),
	267	[IRQ_TYPE_LEVEL_HIGH] = INTC_IRQ_SENSE(0x03),
	268	[IRQ_TYPE_EDGE_BOTH] = INTC_IRQ_SENSE(0x04),
	269	};
	270
	271	static int intc_irqpin_irq_set_type(struct irq_data *d, unsigned int type)
	272	{
	273	unsigned char value = intc_irqpin_sense[type & IRQ_TYPE_SENSE_MASK];
	274	struct intc_irqpin_priv *p = irq_data_get_irq_chip_data(d);
	275
	276	if (!(value & INTC_IRQ_SENSE_VALID))
	277	return -EINVAL;
	278
	279	return intc_irqpin_set_sense(p, irqd_to_hwirq(d),
	280	value ^ INTC_IRQ_SENSE_VALID);
	281	}
	282
705bc96c GU	283	static int intc_irqpin_irq_set_wake(struct irq_data *d, unsigned int on)
	284	{
	285	struct intc_irqpin_priv *p = irq_data_get_irq_chip_data(d);
	286
	287	if (!p->clk)
	288	return 0;
	289
	290	if (on)
	291	clk_enable(p->clk);
	292	else
	293	clk_disable(p->clk);
	294
	295	return 0;
	296	}
	297
44358048 MD	298	static irqreturn_t intc_irqpin_irq_handler(int irq, void *dev_id)
	299	{
	300	struct intc_irqpin_irq *i = dev_id;
	301	struct intc_irqpin_priv *p = i->p;
	302	unsigned long bit;
	303
	304	intc_irqpin_dbg(i, "demux1");
	305	bit = intc_irqpin_hwirq_mask(p, INTC_IRQPIN_REG_SOURCE, i->hw_irq);
	306
	307	if (intc_irqpin_read(p, INTC_IRQPIN_REG_SOURCE) & bit) {
	308	intc_irqpin_write(p, INTC_IRQPIN_REG_SOURCE, ~bit);
	309	intc_irqpin_dbg(i, "demux2");
33f958f2	310	generic_handle_irq(i->domain_irq);
44358048 MD	311	return IRQ_HANDLED;
	312	}
	313	return IRQ_NONE;
	314	}
	315
427cc720 BH	316	static irqreturn_t intc_irqpin_shared_irq_handler(int irq, void *dev_id)
	317	{
	318	struct intc_irqpin_priv *p = dev_id;
	319	unsigned int reg_source = intc_irqpin_read(p, INTC_IRQPIN_REG_SOURCE);
	320	irqreturn_t status = IRQ_NONE;
	321	int k;
	322
	323	for (k = 0; k < 8; k++) {
	324	if (reg_source & BIT(7 - k)) {
	325	if (BIT(k) & p->shared_irq_mask)
	326	continue;
	327
	328	status \|= intc_irqpin_irq_handler(irq, &p->irq[k]);
	329	}
	330	}
	331
	332	return status;
	333	}
	334
44358048 MD	335	static int intc_irqpin_irq_domain_map(struct irq_domain *h, unsigned int virq,
	336	irq_hw_number_t hw)
	337	{
	338	struct intc_irqpin_priv *p = h->host_data;
	339
33f958f2 MD	340	p->irq[hw].domain_irq = virq;
	341	p->irq[hw].hw_irq = hw;
	342
44358048 MD	343	intc_irqpin_dbg(&p->irq[hw], "map");
	344	irq_set_chip_data(virq, h->host_data);
	345	irq_set_chip_and_handler(virq, &p->irq_chip, handle_level_irq);
	346	set_irq_flags(virq, IRQF_VALID); /* kill me now */
	347	return 0;
	348	}
	349
	350	static struct irq_domain_ops intc_irqpin_irq_domain_ops = {
	351	.map = intc_irqpin_irq_domain_map,
9d833bbe	352	.xlate = irq_domain_xlate_twocell,
44358048 MD	353	};
44358048 MD	354
e03f9088 MD	355	static const struct intc_irqpin_irlm_config intc_irqpin_irlm_r8a7779 = {
	356	.irlm_bit = 23, /* ICR0.IRLM0 */
	357	};
	358
	359	static const struct of_device_id intc_irqpin_dt_ids[] = {
	360	{ .compatible = "renesas,intc-irqpin", },
	361	{ .compatible = "renesas,intc-irqpin-r8a7779",
	362	.data = &intc_irqpin_irlm_r8a7779 },
	363	{},
	364	};
	365	MODULE_DEVICE_TABLE(of, intc_irqpin_dt_ids);
	366
44358048 MD	367	static int intc_irqpin_probe(struct platform_device *pdev)
44358048 MD	368	{
36845f1b GU	369	struct device *dev = &pdev->dev;
36845f1b GU	370	struct renesas_intc_irqpin_config *pdata = dev->platform_data;
e03f9088	371	const struct of_device_id *of_id;
44358048 MD	372	struct intc_irqpin_priv *p;
	373	struct intc_irqpin_iomem *i;
	374	struct resource *io[INTC_IRQPIN_REG_NR];
	375	struct resource *irq;
	376	struct irq_chip *irq_chip;
	377	void (enable_fn)(struct irq_data d);
	378	void (disable_fn)(struct irq_data d);
36845f1b	379	const char *name = dev_name(dev);
427cc720	380	int ref_irq;
44358048 MD	381	int ret;
	382	int k;
	383
36845f1b	384	p = devm_kzalloc(dev, sizeof(*p), GFP_KERNEL);
44358048	385	if (!p) {
36845f1b	386	dev_err(dev, "failed to allocate driver data\n");
705bc96c	387	return -ENOMEM;
44358048 MD	388	}
	389
	390	/* deal with driver instance configuration */
c4fa4946	391	if (pdata) {
44358048	392	memcpy(&p->config, pdata, sizeof(*pdata));
c4fa4946	393	} else {
36845f1b	394	of_property_read_u32(dev->of_node, "sense-bitfield-width",
894db164	395	&p->config.sense_bitfield_width);
36845f1b	396	p->config.control_parent = of_property_read_bool(dev->of_node,
c4fa4946 GL	397	"control-parent");
c4fa4946 GL	398	}
44358048 MD	399	if (!p->config.sense_bitfield_width)
	400	p->config.sense_bitfield_width = 4; /* default to 4 bits */
	401
	402	p->pdev = pdev;
	403	platform_set_drvdata(pdev, p);
	404
705bc96c GU	405	p->clk = devm_clk_get(dev, NULL);
	406	if (IS_ERR(p->clk)) {
	407	dev_warn(dev, "unable to get clock\n");
	408	p->clk = NULL;
	409	}
	410
	411	pm_runtime_enable(dev);
	412	pm_runtime_get_sync(dev);
	413
e03f9088 MD	414	/* get hold of register banks */
e03f9088 MD	415	memset(io, 0, sizeof(io));
44358048 MD	416	for (k = 0; k < INTC_IRQPIN_REG_NR; k++) {
44358048 MD	417	io[k] = platform_get_resource(pdev, IORESOURCE_MEM, k);
e03f9088	418	if (!io[k] && k < INTC_IRQPIN_REG_NR_MANDATORY) {
36845f1b	419	dev_err(dev, "not enough IOMEM resources\n");
44358048	420	ret = -EINVAL;
08eba5ba	421	goto err0;
44358048 MD	422	}
	423	}
	424
	425	/* allow any number of IRQs between 1 and INTC_IRQPIN_MAX */
	426	for (k = 0; k < INTC_IRQPIN_MAX; k++) {
	427	irq = platform_get_resource(pdev, IORESOURCE_IRQ, k);
	428	if (!irq)
	429	break;
	430
44358048	431	p->irq[k].p = p;
33f958f2	432	p->irq[k].requested_irq = irq->start;
44358048 MD	433	}
	434
	435	p->number_of_irqs = k;
	436	if (p->number_of_irqs < 1) {
36845f1b	437	dev_err(dev, "not enough IRQ resources\n");
44358048	438	ret = -EINVAL;
08eba5ba	439	goto err0;
44358048 MD	440	}
	441
	442	/* ioremap IOMEM and setup read/write callbacks */
	443	for (k = 0; k < INTC_IRQPIN_REG_NR; k++) {
	444	i = &p->iomem[k];
	445
e03f9088 MD	446	/* handle optional registers */
	447	if (!io[k])
	448	continue;
	449
44358048 MD	450	switch (resource_size(io[k])) {
	451	case 1:
	452	i->width = 8;
	453	i->read = intc_irqpin_read8;
	454	i->write = intc_irqpin_write8;
	455	break;
	456	case 4:
	457	i->width = 32;
	458	i->read = intc_irqpin_read32;
	459	i->write = intc_irqpin_write32;
	460	break;
	461	default:
36845f1b	462	dev_err(dev, "IOMEM size mismatch\n");
44358048	463	ret = -EINVAL;
08eba5ba	464	goto err0;
44358048 MD	465	}
44358048 MD	466
36845f1b	467	i->iomem = devm_ioremap_nocache(dev, io[k]->start,
08eba5ba	468	resource_size(io[k]));
44358048	469	if (!i->iomem) {
36845f1b	470	dev_err(dev, "failed to remap IOMEM\n");
44358048	471	ret = -ENXIO;
08eba5ba	472	goto err0;
44358048 MD	473	}
	474	}
	475
e03f9088 MD	476	/* configure "individual IRQ mode" where needed */
	477	of_id = of_match_device(intc_irqpin_dt_ids, dev);
	478	if (of_id && of_id->data) {
	479	const struct intc_irqpin_irlm_config *irlm_config = of_id->data;
	480
	481	if (io[INTC_IRQPIN_REG_IRLM])
	482	intc_irqpin_read_modify_write(p, INTC_IRQPIN_REG_IRLM,
	483	irlm_config->irlm_bit,
	484	1, 1);
	485	else
	486	dev_warn(dev, "unable to select IRLM mode\n");
	487	}
	488
44358048 MD	489	/* mask all interrupts using priority */
	490	for (k = 0; k < p->number_of_irqs; k++)
	491	intc_irqpin_mask_unmask_prio(p, k, 1);
	492
427cc720 BH	493	/* clear all pending interrupts */
	494	intc_irqpin_write(p, INTC_IRQPIN_REG_SOURCE, 0x0);
	495
	496	/* scan for shared interrupt lines */
	497	ref_irq = p->irq[0].requested_irq;
	498	p->shared_irqs = true;
	499	for (k = 1; k < p->number_of_irqs; k++) {
	500	if (ref_irq != p->irq[k].requested_irq) {
	501	p->shared_irqs = false;
	502	break;
	503	}
	504	}
	505
44358048 MD	506	/* use more severe masking method if requested */
	507	if (p->config.control_parent) {
	508	enable_fn = intc_irqpin_irq_enable_force;
	509	disable_fn = intc_irqpin_irq_disable_force;
427cc720	510	} else if (!p->shared_irqs) {
44358048 MD	511	enable_fn = intc_irqpin_irq_enable;
44358048 MD	512	disable_fn = intc_irqpin_irq_disable;
427cc720 BH	513	} else {
	514	enable_fn = intc_irqpin_shared_irq_enable;
	515	disable_fn = intc_irqpin_shared_irq_disable;
44358048 MD	516	}
	517
	518	irq_chip = &p->irq_chip;
	519	irq_chip->name = name;
	520	irq_chip->irq_mask = disable_fn;
	521	irq_chip->irq_unmask = enable_fn;
44358048	522	irq_chip->irq_set_type = intc_irqpin_irq_set_type;
705bc96c GU	523	irq_chip->irq_set_wake = intc_irqpin_irq_set_wake;
705bc96c GU	524	irq_chip->flags = IRQCHIP_MASK_ON_SUSPEND;
44358048	525
36845f1b	526	p->irq_domain = irq_domain_add_simple(dev->of_node,
44358048 MD	527	p->number_of_irqs,
	528	p->config.irq_base,
	529	&intc_irqpin_irq_domain_ops, p);
	530	if (!p->irq_domain) {
	531	ret = -ENXIO;
36845f1b	532	dev_err(dev, "cannot initialize irq domain\n");
08eba5ba	533	goto err0;
44358048 MD	534	}
44358048 MD	535
427cc720 BH	536	if (p->shared_irqs) {
427cc720 BH	537	/* request one shared interrupt */
36845f1b	538	if (devm_request_irq(dev, p->irq[0].requested_irq,
427cc720 BH	539	intc_irqpin_shared_irq_handler,
427cc720 BH	540	IRQF_SHARED, name, p)) {
36845f1b	541	dev_err(dev, "failed to request low IRQ\n");
44358048	542	ret = -ENOENT;
08eba5ba	543	goto err1;
44358048	544	}
427cc720 BH	545	} else {
	546	/* request interrupts one by one */
	547	for (k = 0; k < p->number_of_irqs; k++) {
36845f1b GU	548	if (devm_request_irq(dev, p->irq[k].requested_irq,
	549	intc_irqpin_irq_handler, 0, name,
	550	&p->irq[k])) {
	551	dev_err(dev, "failed to request low IRQ\n");
427cc720 BH	552	ret = -ENOENT;
	553	goto err1;
	554	}
	555	}
44358048 MD	556	}
44358048 MD	557
427cc720 BH	558	/* unmask all interrupts on prio level */
	559	for (k = 0; k < p->number_of_irqs; k++)
	560	intc_irqpin_mask_unmask_prio(p, k, 0);
	561
36845f1b	562	dev_info(dev, "driving %d irqs\n", p->number_of_irqs);
44358048 MD	563
	564	/* warn in case of mismatch if irq base is specified */
	565	if (p->config.irq_base) {
33f958f2	566	if (p->config.irq_base != p->irq[0].domain_irq)
36845f1b	567	dev_warn(dev, "irq base mismatch (%d/%d)\n",
33f958f2	568	p->config.irq_base, p->irq[0].domain_irq);
44358048	569	}
862d3098	570
44358048 MD	571	return 0;
44358048 MD	572
44358048	573	err1:
08eba5ba	574	irq_domain_remove(p->irq_domain);
44358048	575	err0:
705bc96c GU	576	pm_runtime_put(dev);
705bc96c GU	577	pm_runtime_disable(dev);
44358048 MD	578	return ret;
	579	}
	580
	581	static int intc_irqpin_remove(struct platform_device *pdev)
	582	{
	583	struct intc_irqpin_priv *p = platform_get_drvdata(pdev);
44358048 MD	584
44358048 MD	585	irq_domain_remove(p->irq_domain);
705bc96c GU	586	pm_runtime_put(&pdev->dev);
705bc96c GU	587	pm_runtime_disable(&pdev->dev);
44358048 MD	588	return 0;
	589	}
	590
	591	static struct platform_driver intc_irqpin_device_driver = {
	592	.probe = intc_irqpin_probe,
	593	.remove = intc_irqpin_remove,
	594	.driver = {
	595	.name = "renesas_intc_irqpin",
9d833bbe	596	.of_match_table = intc_irqpin_dt_ids,
44358048 MD	597	}
	598	};
	599
	600	static int __init intc_irqpin_init(void)
	601	{
	602	return platform_driver_register(&intc_irqpin_device_driver);
	603	}
	604	postcore_initcall(intc_irqpin_init);
	605
	606	static void __exit intc_irqpin_exit(void)
	607	{
	608	platform_driver_unregister(&intc_irqpin_device_driver);
	609	}
	610	module_exit(intc_irqpin_exit);
	611
	612	MODULE_AUTHOR("Magnus Damm");
	613	MODULE_DESCRIPTION("Renesas INTC External IRQ Pin Driver");
	614	MODULE_LICENSE("GPL v2");