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irqchip: s3c24xx: add irq_set_type callback for basic interrupt types
[mirror_ubuntu-zesty-kernel.git] / drivers / irqchip / irq-s3c24xx.c
CommitLineData
1f629b7a
HS		 1/*
2 * S3C24XX IRQ handling
a21765a7 3 *
e02f8664 4 * Copyright (c) 2003-2004 Simtec Electronics
a21765a7 5 * Ben Dooks <ben@simtec.co.uk>
1f629b7a 6 * Copyright (c) 2012 Heiko Stuebner <heiko@sntech.de>
a21765a7
BD		 7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
a21765a7
BD		 17*/
18
19#include <linux/init.h>
1f629b7a 20#include <linux/slab.h>
a21765a7 21#include <linux/module.h>
1f629b7a
HS		 22#include <linux/io.h>
23#include <linux/err.h>
a21765a7
BD		 24#include <linux/interrupt.h>
25#include <linux/ioport.h>
edbaa603 26#include <linux/device.h>
1f629b7a 27#include <linux/irqdomain.h>
a21765a7 28
17453dd2 29#include <asm/exception.h>
a21765a7
BD		 30#include <asm/mach/irq.h>
31
1f629b7a
HS		 32#include <mach/regs-irq.h>
33#include <mach/regs-gpio.h>
a21765a7 34
a2b7ba9c 35#include <plat/cpu.h>
1f629b7a 36#include <plat/regs-irqtype.h>
a2b7ba9c 37#include <plat/pm.h>
a21765a7 38
1f629b7a
HS		 39#define S3C_IRQTYPE_NONE 0
40#define S3C_IRQTYPE_EINT 1
41#define S3C_IRQTYPE_EDGE 2
42#define S3C_IRQTYPE_LEVEL 3
a21765a7 43
1f629b7a
HS		 44struct s3c_irq_data {
45 unsigned int type;
46 unsigned long parent_irq;
a21765a7 47
1f629b7a
HS		 48 /* data gets filled during init */
49 struct s3c_irq_intc *intc;
50 unsigned long sub_bits;
51 struct s3c_irq_intc *sub_intc;
a21765a7
BD		 52};
53
1f629b7a
HS		 54/*
55 * Sructure holding the controller data
56 * @reg_pending register holding pending irqs
57 * @reg_intpnd special register intpnd in main intc
58 * @reg_mask mask register
59 * @domain irq_domain of the controller
60 * @parent parent controller for ext and sub irqs
61 * @irqs irq-data, always s3c_irq_data[32]
62 */
63struct s3c_irq_intc {
64 void __iomem *reg_pending;
65 void __iomem *reg_intpnd;
66 void __iomem *reg_mask;
67 struct irq_domain *domain;
68 struct s3c_irq_intc *parent;
69 struct s3c_irq_data *irqs;
a21765a7
BD		 70};
71
1f629b7a 72static void s3c_irq_mask(struct irq_data *data)
a21765a7 73{
1f629b7a
HS		 74 struct s3c_irq_intc *intc = data->domain->host_data;
75 struct s3c_irq_intc *parent_intc = intc->parent;
76 struct s3c_irq_data *irq_data = &intc->irqs[data->hwirq];
77 struct s3c_irq_data *parent_data;
a21765a7 78 unsigned long mask;
1f629b7a
HS		 79 unsigned int irqno;
80
81 mask = __raw_readl(intc->reg_mask);
82 mask |= (1UL << data->hwirq);
83 __raw_writel(mask, intc->reg_mask);
84
0fe3cb1e 85 if (parent_intc) {
1f629b7a 86 parent_data = &parent_intc->irqs[irq_data->parent_irq];
a21765a7 87
1f629b7a
HS		 88 /* check to see if we need to mask the parent IRQ */
89 if ((mask & parent_data->sub_bits) == parent_data->sub_bits) {
90 irqno = irq_find_mapping(parent_intc->domain,
91 irq_data->parent_irq);
92 s3c_irq_mask(irq_get_irq_data(irqno));
93 }
94 }
a21765a7
BD		 95}
96
1f629b7a 97static void s3c_irq_unmask(struct irq_data *data)
a21765a7 98{
1f629b7a
HS		 99 struct s3c_irq_intc *intc = data->domain->host_data;
100 struct s3c_irq_intc *parent_intc = intc->parent;
101 struct s3c_irq_data *irq_data = &intc->irqs[data->hwirq];
a21765a7 102 unsigned long mask;
1f629b7a 103 unsigned int irqno;
a21765a7 104
1f629b7a
HS		 105 mask = __raw_readl(intc->reg_mask);
106 mask &= ~(1UL << data->hwirq);
107 __raw_writel(mask, intc->reg_mask);
a21765a7 108
0fe3cb1e 109 if (parent_intc) {
1f629b7a
HS		 110 irqno = irq_find_mapping(parent_intc->domain,
111 irq_data->parent_irq);
112 s3c_irq_unmask(irq_get_irq_data(irqno));
a21765a7
BD		 113 }
114}
115
1f629b7a 116static inline void s3c_irq_ack(struct irq_data *data)
a21765a7 117{
1f629b7a
HS		 118 struct s3c_irq_intc *intc = data->domain->host_data;
119 unsigned long bitval = 1UL << data->hwirq;
a21765a7 120
1f629b7a
HS		 121 __raw_writel(bitval, intc->reg_pending);
122 if (intc->reg_intpnd)
123 __raw_writel(bitval, intc->reg_intpnd);
a21765a7
BD		 124}
125
bd7c0da2
HS		 126static int s3c_irq_type(struct irq_data *data, unsigned int type)
127{
128 switch (type) {
129 case IRQ_TYPE_NONE:
130 break;
131 case IRQ_TYPE_EDGE_RISING:
132 case IRQ_TYPE_EDGE_FALLING:
133 case IRQ_TYPE_EDGE_BOTH:
134 irq_set_handler(data->irq, handle_edge_irq);
135 break;
136 case IRQ_TYPE_LEVEL_LOW:
137 case IRQ_TYPE_LEVEL_HIGH:
138 irq_set_handler(data->irq, handle_level_irq);
139 break;
140 default:
141 pr_err("No such irq type %d", type);
142 return -EINVAL;
143 }
144
145 return 0;
146}
147
1f629b7a
HS		 148static int s3c_irqext_type_set(void __iomem *gpcon_reg,
149 void __iomem *extint_reg,
150 unsigned long gpcon_offset,
151 unsigned long extint_offset,
152 unsigned int type)
a21765a7 153{
a21765a7
BD		 154 unsigned long newvalue = 0, value;
155
a21765a7
BD		 156 /* Set the GPIO to external interrupt mode */
157 value = __raw_readl(gpcon_reg);
158 value = (value & ~(3 << gpcon_offset)) | (0x02 << gpcon_offset);
159 __raw_writel(value, gpcon_reg);
160
161 /* Set the external interrupt to pointed trigger type */
162 switch (type)
163 {
6cab4860 164 case IRQ_TYPE_NONE:
1f629b7a 165 pr_warn("No edge setting!\n");
a21765a7
BD		 166 break;
167
6cab4860 168 case IRQ_TYPE_EDGE_RISING:
a21765a7
BD		 169 newvalue = S3C2410_EXTINT_RISEEDGE;
170 break;
171
6cab4860 172 case IRQ_TYPE_EDGE_FALLING:
a21765a7
BD		 173 newvalue = S3C2410_EXTINT_FALLEDGE;
174 break;
175
6cab4860 176 case IRQ_TYPE_EDGE_BOTH:
a21765a7
BD		 177 newvalue = S3C2410_EXTINT_BOTHEDGE;
178 break;
179
6cab4860 180 case IRQ_TYPE_LEVEL_LOW:
a21765a7
BD		 181 newvalue = S3C2410_EXTINT_LOWLEV;
182 break;
183
6cab4860 184 case IRQ_TYPE_LEVEL_HIGH:
a21765a7
BD		 185 newvalue = S3C2410_EXTINT_HILEV;
186 break;
187
188 default:
1f629b7a
HS		 189 pr_err("No such irq type %d", type);
190 return -EINVAL;
a21765a7
BD		 191 }
192
193 value = __raw_readl(extint_reg);
194 value = (value & ~(7 << extint_offset)) | (newvalue << extint_offset);
195 __raw_writel(value, extint_reg);
196
197 return 0;
198}
199
dc1a3538 200static int s3c_irqext_type(struct irq_data *data, unsigned int type)
a21765a7 201{
1f629b7a
HS		 202 void __iomem *extint_reg;
203 void __iomem *gpcon_reg;
204 unsigned long gpcon_offset, extint_offset;
a21765a7 205
1f629b7a
HS		 206 if ((data->hwirq >= 4) && (data->hwirq <= 7)) {
207 gpcon_reg = S3C2410_GPFCON;
208 extint_reg = S3C24XX_EXTINT0;
209 gpcon_offset = (data->hwirq) * 2;
210 extint_offset = (data->hwirq) * 4;
211 } else if ((data->hwirq >= 8) && (data->hwirq <= 15)) {
212 gpcon_reg = S3C2410_GPGCON;
213 extint_reg = S3C24XX_EXTINT1;
214 gpcon_offset = (data->hwirq - 8) * 2;
215 extint_offset = (data->hwirq - 8) * 4;
216 } else if ((data->hwirq >= 16) && (data->hwirq <= 23)) {
217 gpcon_reg = S3C2410_GPGCON;
218 extint_reg = S3C24XX_EXTINT2;
219 gpcon_offset = (data->hwirq - 8) * 2;
220 extint_offset = (data->hwirq - 16) * 4;
221 } else {
222 return -EINVAL;
223 }
a21765a7 224
1f629b7a
HS		 225 return s3c_irqext_type_set(gpcon_reg, extint_reg, gpcon_offset,
226 extint_offset, type);
a21765a7
BD		 227}
228
1f629b7a 229static int s3c_irqext0_type(struct irq_data *data, unsigned int type)
a21765a7 230{
1f629b7a
HS		 231 void __iomem *extint_reg;
232 void __iomem *gpcon_reg;
233 unsigned long gpcon_offset, extint_offset;
a21765a7 234
1f629b7a
HS		 235 if ((data->hwirq >= 0) && (data->hwirq <= 3)) {
236 gpcon_reg = S3C2410_GPFCON;
237 extint_reg = S3C24XX_EXTINT0;
238 gpcon_offset = (data->hwirq) * 2;
239 extint_offset = (data->hwirq) * 4;
240 } else {
241 return -EINVAL;
242 }
a21765a7 243
1f629b7a
HS		 244 return s3c_irqext_type_set(gpcon_reg, extint_reg, gpcon_offset,
245 extint_offset, type);
a21765a7
BD		 246}
247
dc1a3538 248static struct irq_chip s3c_irq_chip = {
1f629b7a
HS		 249 .name = "s3c",
250 .irq_ack = s3c_irq_ack,
251 .irq_mask = s3c_irq_mask,
252 .irq_unmask = s3c_irq_unmask,
bd7c0da2 253 .irq_set_type = s3c_irq_type,
1f629b7a 254 .irq_set_wake = s3c_irq_wake
a21765a7
BD		 255};
256
dc1a3538 257static struct irq_chip s3c_irq_level_chip = {
1f629b7a
HS		 258 .name = "s3c-level",
259 .irq_mask = s3c_irq_mask,
260 .irq_unmask = s3c_irq_unmask,
261 .irq_ack = s3c_irq_ack,
bd7c0da2 262 .irq_set_type = s3c_irq_type,
a21765a7
BD		 263};
264
1f629b7a
HS		 265static struct irq_chip s3c_irqext_chip = {
266 .name = "s3c-ext",
267 .irq_mask = s3c_irq_mask,
268 .irq_unmask = s3c_irq_unmask,
269 .irq_ack = s3c_irq_ack,
270 .irq_set_type = s3c_irqext_type,
271 .irq_set_wake = s3c_irqext_wake
a21765a7
BD		 272};
273
1f629b7a
HS		 274static struct irq_chip s3c_irq_eint0t4 = {
275 .name = "s3c-ext0",
276 .irq_ack = s3c_irq_ack,
277 .irq_mask = s3c_irq_mask,
278 .irq_unmask = s3c_irq_unmask,
279 .irq_set_wake = s3c_irq_wake,
280 .irq_set_type = s3c_irqext0_type,
281};
a21765a7 282
1f629b7a 283static void s3c_irq_demux(unsigned int irq, struct irq_desc *desc)
a21765a7 284{
1f629b7a
HS		 285 struct irq_chip *chip = irq_desc_get_chip(desc);
286 struct s3c_irq_intc *intc = desc->irq_data.domain->host_data;
287 struct s3c_irq_data *irq_data = &intc->irqs[desc->irq_data.hwirq];
288 struct s3c_irq_intc *sub_intc = irq_data->sub_intc;
289 unsigned long src;
290 unsigned long msk;
291 unsigned int n;
292
293 chained_irq_enter(chip, desc);
294
295 src = __raw_readl(sub_intc->reg_pending);
296 msk = __raw_readl(sub_intc->reg_mask);
297
298 src &= ~msk;
299 src &= irq_data->sub_bits;
300
301 while (src) {
302 n = __ffs(src);
303 src &= ~(1 << n);
304 generic_handle_irq(irq_find_mapping(sub_intc->domain, n));
a21765a7
BD		 305 }
306
1f629b7a 307 chained_irq_exit(chip, desc);
a21765a7
BD		 308}
309
17453dd2
HS		 310static struct s3c_irq_intc *main_intc;
311static struct s3c_irq_intc *main_intc2;
312
313static inline int s3c24xx_handle_intc(struct s3c_irq_intc *intc,
314 struct pt_regs *regs)
315{
316 int pnd;
317 int offset;
318 int irq;
319
320 pnd = __raw_readl(intc->reg_intpnd);
321 if (!pnd)
322 return false;
323
324 /* We have a problem that the INTOFFSET register does not always
325 * show one interrupt. Occasionally we get two interrupts through
326 * the prioritiser, and this causes the INTOFFSET register to show
327 * what looks like the logical-or of the two interrupt numbers.
328 *
329 * Thanks to Klaus, Shannon, et al for helping to debug this problem
330 */
331 offset = __raw_readl(intc->reg_intpnd + 4);
332
333 /* Find the bit manually, when the offset is wrong.
334 * The pending register only ever contains the one bit of the next
335 * interrupt to handle.
336 */
337 if (!(pnd & (1 << offset)))
338 offset = __ffs(pnd);
339
340 irq = irq_find_mapping(intc->domain, offset);
341 handle_IRQ(irq, regs);
342 return true;
343}
344
345asmlinkage void __exception_irq_entry s3c24xx_handle_irq(struct pt_regs *regs)
346{
347 do {
348 if (likely(main_intc))
349 if (s3c24xx_handle_intc(main_intc, regs))
350 continue;
351
352 if (main_intc2)
353 if (s3c24xx_handle_intc(main_intc2, regs))
354 continue;
355
356 break;
357 } while (1);
358}
359
229fd8ff
BD		 360#ifdef CONFIG_FIQ
361/**
362 * s3c24xx_set_fiq - set the FIQ routing
363 * @irq: IRQ number to route to FIQ on processor.
364 * @on: Whether to route @irq to the FIQ, or to remove the FIQ routing.
365 *
366 * Change the state of the IRQ to FIQ routing depending on @irq and @on. If
367 * @on is true, the @irq is checked to see if it can be routed and the
368 * interrupt controller updated to route the IRQ. If @on is false, the FIQ
369 * routing is cleared, regardless of which @irq is specified.
370 */
371int s3c24xx_set_fiq(unsigned int irq, bool on)
372{
373 u32 intmod;
374 unsigned offs;
375
376 if (on) {
377 offs = irq - FIQ_START;
378 if (offs > 31)
379 return -EINVAL;
380
381 intmod = 1 << offs;
382 } else {
383 intmod = 0;
384 }
385
386 __raw_writel(intmod, S3C2410_INTMOD);
387 return 0;
388}
0f13c824
BD		 389
390EXPORT_SYMBOL_GPL(s3c24xx_set_fiq);
229fd8ff
BD		 391#endif
392
1f629b7a
HS		 393static int s3c24xx_irq_map(struct irq_domain *h, unsigned int virq,
394 irq_hw_number_t hw)
a21765a7 395{
1f629b7a
HS		 396 struct s3c_irq_intc *intc = h->host_data;
397 struct s3c_irq_data *irq_data = &intc->irqs[hw];
398 struct s3c_irq_intc *parent_intc;
399 struct s3c_irq_data *parent_irq_data;
400 unsigned int irqno;
401
1f629b7a
HS		 402 /* attach controller pointer to irq_data */
403 irq_data->intc = intc;
a21765a7 404
0fe3cb1e
HS		 405 parent_intc = intc->parent;
406
1f629b7a
HS		 407 /* set handler and flags */
408 switch (irq_data->type) {
409 case S3C_IRQTYPE_NONE:
410 return 0;
411 case S3C_IRQTYPE_EINT:
1c8408e3
HS		 412 /* On the S3C2412, the EINT0to3 have a parent irq
413 * but need the s3c_irq_eint0t4 chip
414 */
0fe3cb1e 415 if (parent_intc && (!soc_is_s3c2412() || hw >= 4))
1f629b7a
HS		 416 irq_set_chip_and_handler(virq, &s3c_irqext_chip,
417 handle_edge_irq);
418 else
419 irq_set_chip_and_handler(virq, &s3c_irq_eint0t4,
420 handle_edge_irq);
421 break;
422 case S3C_IRQTYPE_EDGE:
0fe3cb1e 423 if (parent_intc || intc->reg_pending == S3C2416_SRCPND2)
1f629b7a
HS		 424 irq_set_chip_and_handler(virq, &s3c_irq_level_chip,
425 handle_edge_irq);
426 else
427 irq_set_chip_and_handler(virq, &s3c_irq_chip,
428 handle_edge_irq);
429 break;
430 case S3C_IRQTYPE_LEVEL:
0fe3cb1e 431 if (parent_intc)
1f629b7a
HS		 432 irq_set_chip_and_handler(virq, &s3c_irq_level_chip,
433 handle_level_irq);
434 else
435 irq_set_chip_and_handler(virq, &s3c_irq_chip,
436 handle_level_irq);
437 break;
438 default:
439 pr_err("irq-s3c24xx: unsupported irqtype %d\n", irq_data->type);
440 return -EINVAL;
a21765a7 441 }
1f629b7a
HS		 442 set_irq_flags(virq, IRQF_VALID);
443
0fe3cb1e 444 if (parent_intc && irq_data->type != S3C_IRQTYPE_NONE) {
502a2989
HS		 445 if (irq_data->parent_irq > 31) {
446 pr_err("irq-s3c24xx: parent irq %lu is out of range\n",
447 irq_data->parent_irq);
1f629b7a
HS		 448 goto err;
449 }
a21765a7 450
502a2989 451 parent_irq_data = &parent_intc->irqs[irq_data->parent_irq];
1f629b7a
HS		 452 parent_irq_data->sub_intc = intc;
453 parent_irq_data->sub_bits |= (1UL << hw);
a21765a7 454
1f629b7a
HS		 455 /* attach the demuxer to the parent irq */
456 irqno = irq_find_mapping(parent_intc->domain,
457 irq_data->parent_irq);
458 if (!irqno) {
459 pr_err("irq-s3c24xx: could not find mapping for parent irq %lu\n",
460 irq_data->parent_irq);
461 goto err;
462 }
463 irq_set_chained_handler(irqno, s3c_irq_demux);
a21765a7
BD		 464 }
465
1f629b7a 466 return 0;
a21765a7 467
1f629b7a
HS		 468err:
469 set_irq_flags(virq, 0);
a21765a7 470
1f629b7a
HS		 471 /* the only error can result from bad mapping data*/
472 return -EINVAL;
473}
a21765a7 474
1f629b7a
HS		 475static struct irq_domain_ops s3c24xx_irq_ops = {
476 .map = s3c24xx_irq_map,
477 .xlate = irq_domain_xlate_twocell,
478};
a21765a7 479
1f629b7a
HS		 480static void s3c24xx_clear_intc(struct s3c_irq_intc *intc)
481{
482 void __iomem *reg_source;
483 unsigned long pend;
484 unsigned long last;
485 int i;
a21765a7 486
1f629b7a
HS		 487 /* if intpnd is set, read the next pending irq from there */
488 reg_source = intc->reg_intpnd ? intc->reg_intpnd : intc->reg_pending;
a21765a7 489
1f629b7a
HS		 490 last = 0;
491 for (i = 0; i < 4; i++) {
492 pend = __raw_readl(reg_source);
a21765a7 493
1f629b7a 494 if (pend == 0 || pend == last)
a21765a7
BD		 495 break;
496
1f629b7a
HS		 497 __raw_writel(pend, intc->reg_pending);
498 if (intc->reg_intpnd)
499 __raw_writel(pend, intc->reg_intpnd);
a21765a7 500
1f629b7a
HS		 501 pr_info("irq: clearing pending status %08x\n", (int)pend);
502 last = pend;
a21765a7 503 }
1f629b7a 504}
a21765a7 505
3d3eb5a4 506static struct s3c_irq_intc *s3c24xx_init_intc(struct device_node *np,
1f629b7a
HS		 507 struct s3c_irq_data *irq_data,
508 struct s3c_irq_intc *parent,
509 unsigned long address)
510{
511 struct s3c_irq_intc *intc;
512 void __iomem *base = (void *)0xf6000000; /* static mapping */
513 int irq_num;
514 int irq_start;
1f629b7a
HS		 515 int ret;
516
517 intc = kzalloc(sizeof(struct s3c_irq_intc), GFP_KERNEL);
518 if (!intc)
519 return ERR_PTR(-ENOMEM);
520
521 intc->irqs = irq_data;
522
523 if (parent)
524 intc->parent = parent;
525
526 /* select the correct data for the controller.
527 * Need to hard code the irq num start and offset
528 * to preserve the static mapping for now
529 */
530 switch (address) {
531 case 0x4a000000:
532 pr_debug("irq: found main intc\n");
533 intc->reg_pending = base;
534 intc->reg_mask = base + 0x08;
535 intc->reg_intpnd = base + 0x10;
536 irq_num = 32;
537 irq_start = S3C2410_IRQ(0);
1f629b7a
HS		 538 break;
539 case 0x4a000018:
540 pr_debug("irq: found subintc\n");
541 intc->reg_pending = base + 0x18;
542 intc->reg_mask = base + 0x1c;
543 irq_num = 29;
544 irq_start = S3C2410_IRQSUB(0);
1f629b7a
HS		 545 break;
546 case 0x4a000040:
547 pr_debug("irq: found intc2\n");
548 intc->reg_pending = base + 0x40;
549 intc->reg_mask = base + 0x48;
550 intc->reg_intpnd = base + 0x50;
551 irq_num = 8;
552 irq_start = S3C2416_IRQ(0);
1f629b7a
HS		 553 break;
554 case 0x560000a4:
555 pr_debug("irq: found eintc\n");
556 base = (void *)0xfd000000;
557
558 intc->reg_mask = base + 0xa4;
559 intc->reg_pending = base + 0x08;
5424f218 560 irq_num = 24;
1f629b7a 561 irq_start = S3C2410_IRQ(32);
1f629b7a
HS		 562 break;
563 default:
564 pr_err("irq: unsupported controller address\n");
565 ret = -EINVAL;
566 goto err;
567 }
a21765a7 568
1f629b7a
HS		 569 /* now that all the data is complete, init the irq-domain */
570 s3c24xx_clear_intc(intc);
571 intc->domain = irq_domain_add_legacy(np, irq_num, irq_start,
5424f218 572 0, &s3c24xx_irq_ops,
1f629b7a
HS		 573 intc);
574 if (!intc->domain) {
575 pr_err("irq: could not create irq-domain\n");
576 ret = -EINVAL;
577 goto err;
578 }
a21765a7 579
17453dd2
HS		 580 if (address == 0x4a000000)
581 main_intc = intc;
582 else if (address == 0x4a000040)
583 main_intc2 = intc;
584
585 set_handle_irq(s3c24xx_handle_irq);
586
1f629b7a 587 return intc;
a21765a7 588
1f629b7a
HS		 589err:
590 kfree(intc);
591 return ERR_PTR(ret);
592}
a21765a7 593
f182aa1d
HS		 594static struct s3c_irq_data init_eint[32] = {
595 { .type = S3C_IRQTYPE_NONE, }, /* reserved */
596 { .type = S3C_IRQTYPE_NONE, }, /* reserved */
597 { .type = S3C_IRQTYPE_NONE, }, /* reserved */
598 { .type = S3C_IRQTYPE_NONE, }, /* reserved */
599 { .type = S3C_IRQTYPE_EINT, .parent_irq = 4 }, /* EINT4 */
600 { .type = S3C_IRQTYPE_EINT, .parent_irq = 4 }, /* EINT5 */
601 { .type = S3C_IRQTYPE_EINT, .parent_irq = 4 }, /* EINT6 */
602 { .type = S3C_IRQTYPE_EINT, .parent_irq = 4 }, /* EINT7 */
603 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT8 */
604 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT9 */
605 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT10 */
606 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT11 */
607 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT12 */
608 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT13 */
609 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT14 */
610 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT15 */
611 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT16 */
612 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT17 */
613 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT18 */
614 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT19 */
615 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT20 */
616 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT21 */
617 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT22 */
618 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT23 */
619};
a21765a7 620
f182aa1d
HS		 621#ifdef CONFIG_CPU_S3C2410
622static struct s3c_irq_data init_s3c2410base[32] = {
1f629b7a
HS		 623 { .type = S3C_IRQTYPE_EINT, }, /* EINT0 */
624 { .type = S3C_IRQTYPE_EINT, }, /* EINT1 */
625 { .type = S3C_IRQTYPE_EINT, }, /* EINT2 */
626 { .type = S3C_IRQTYPE_EINT, }, /* EINT3 */
627 { .type = S3C_IRQTYPE_LEVEL, }, /* EINT4to7 */
628 { .type = S3C_IRQTYPE_LEVEL, }, /* EINT8to23 */
629 { .type = S3C_IRQTYPE_NONE, }, /* reserved */
630 { .type = S3C_IRQTYPE_EDGE, }, /* nBATT_FLT */
631 { .type = S3C_IRQTYPE_EDGE, }, /* TICK */
632 { .type = S3C_IRQTYPE_EDGE, }, /* WDT */
633 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER0 */
634 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER1 */
635 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER2 */
636 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER3 */
637 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER4 */
638 { .type = S3C_IRQTYPE_LEVEL, }, /* UART2 */
639 { .type = S3C_IRQTYPE_EDGE, }, /* LCD */
640 { .type = S3C_IRQTYPE_EDGE, }, /* DMA0 */
641 { .type = S3C_IRQTYPE_EDGE, }, /* DMA1 */
642 { .type = S3C_IRQTYPE_EDGE, }, /* DMA2 */
643 { .type = S3C_IRQTYPE_EDGE, }, /* DMA3 */
644 { .type = S3C_IRQTYPE_EDGE, }, /* SDI */
645 { .type = S3C_IRQTYPE_EDGE, }, /* SPI0 */
646 { .type = S3C_IRQTYPE_LEVEL, }, /* UART1 */
647 { .type = S3C_IRQTYPE_NONE, }, /* reserved */
648 { .type = S3C_IRQTYPE_EDGE, }, /* USBD */
649 { .type = S3C_IRQTYPE_EDGE, }, /* USBH */
650 { .type = S3C_IRQTYPE_EDGE, }, /* IIC */
651 { .type = S3C_IRQTYPE_LEVEL, }, /* UART0 */
652 { .type = S3C_IRQTYPE_EDGE, }, /* SPI1 */
653 { .type = S3C_IRQTYPE_EDGE, }, /* RTC */
654 { .type = S3C_IRQTYPE_LEVEL, }, /* ADCPARENT */
655};
a21765a7 656
f182aa1d 657static struct s3c_irq_data init_s3c2410subint[32] = {
1f629b7a
HS		 658 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-RX */
659 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-TX */
660 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-ERR */
661 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-RX */
662 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-TX */
663 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-ERR */
664 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-RX */
665 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-TX */
666 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-ERR */
667 { .type = S3C_IRQTYPE_EDGE, .parent_irq = 31 }, /* TC */
668 { .type = S3C_IRQTYPE_EDGE, .parent_irq = 31 }, /* ADC */
669};
a21765a7 670
f182aa1d 671void __init s3c2410_init_irq(void)
1f629b7a
HS		 672{
673 struct s3c_irq_intc *main_intc;
a21765a7 674
1f629b7a
HS		 675#ifdef CONFIG_FIQ
676 init_FIQ(FIQ_START);
677#endif
a21765a7 678
f182aa1d 679 main_intc = s3c24xx_init_intc(NULL, &init_s3c2410base[0], NULL, 0x4a000000);
1f629b7a
HS		 680 if (IS_ERR(main_intc)) {
681 pr_err("irq: could not create main interrupt controller\n");
682 return;
a21765a7
BD		 683 }
684
f182aa1d 685 s3c24xx_init_intc(NULL, &init_s3c2410subint[0], main_intc, 0x4a000018);
1f629b7a 686 s3c24xx_init_intc(NULL, &init_eint[0], main_intc, 0x560000a4);
a21765a7 687}
f182aa1d 688#endif
ef602eb5 689
d3d5a2c9 690#ifdef CONFIG_CPU_S3C2412
4245944c 691static struct s3c_irq_data init_s3c2412base[32] = {
1c8408e3
HS		 692 { .type = S3C_IRQTYPE_LEVEL, }, /* EINT0 */
693 { .type = S3C_IRQTYPE_LEVEL, }, /* EINT1 */
694 { .type = S3C_IRQTYPE_LEVEL, }, /* EINT2 */
695 { .type = S3C_IRQTYPE_LEVEL, }, /* EINT3 */
4245944c
HS		 696 { .type = S3C_IRQTYPE_LEVEL, }, /* EINT4to7 */
697 { .type = S3C_IRQTYPE_LEVEL, }, /* EINT8to23 */
698 { .type = S3C_IRQTYPE_NONE, }, /* reserved */
699 { .type = S3C_IRQTYPE_EDGE, }, /* nBATT_FLT */
700 { .type = S3C_IRQTYPE_EDGE, }, /* TICK */
701 { .type = S3C_IRQTYPE_EDGE, }, /* WDT */
702 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER0 */
703 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER1 */
704 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER2 */
705 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER3 */
706 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER4 */
707 { .type = S3C_IRQTYPE_LEVEL, }, /* UART2 */
708 { .type = S3C_IRQTYPE_EDGE, }, /* LCD */
709 { .type = S3C_IRQTYPE_EDGE, }, /* DMA0 */
710 { .type = S3C_IRQTYPE_EDGE, }, /* DMA1 */
711 { .type = S3C_IRQTYPE_EDGE, }, /* DMA2 */
712 { .type = S3C_IRQTYPE_EDGE, }, /* DMA3 */
713 { .type = S3C_IRQTYPE_LEVEL, }, /* SDI/CF */
714 { .type = S3C_IRQTYPE_EDGE, }, /* SPI0 */
715 { .type = S3C_IRQTYPE_LEVEL, }, /* UART1 */
716 { .type = S3C_IRQTYPE_NONE, }, /* reserved */
717 { .type = S3C_IRQTYPE_EDGE, }, /* USBD */
718 { .type = S3C_IRQTYPE_EDGE, }, /* USBH */
719 { .type = S3C_IRQTYPE_EDGE, }, /* IIC */
720 { .type = S3C_IRQTYPE_LEVEL, }, /* UART0 */
721 { .type = S3C_IRQTYPE_EDGE, }, /* SPI1 */
722 { .type = S3C_IRQTYPE_EDGE, }, /* RTC */
723 { .type = S3C_IRQTYPE_LEVEL, }, /* ADCPARENT */
724};
d3d5a2c9 725
1c8408e3
HS		 726static struct s3c_irq_data init_s3c2412eint[32] = {
727 { .type = S3C_IRQTYPE_EINT, .parent_irq = 0 }, /* EINT0 */
728 { .type = S3C_IRQTYPE_EINT, .parent_irq = 1 }, /* EINT1 */
729 { .type = S3C_IRQTYPE_EINT, .parent_irq = 2 }, /* EINT2 */
730 { .type = S3C_IRQTYPE_EINT, .parent_irq = 3 }, /* EINT3 */
731 { .type = S3C_IRQTYPE_EINT, .parent_irq = 4 }, /* EINT4 */
732 { .type = S3C_IRQTYPE_EINT, .parent_irq = 4 }, /* EINT5 */
733 { .type = S3C_IRQTYPE_EINT, .parent_irq = 4 }, /* EINT6 */
734 { .type = S3C_IRQTYPE_EINT, .parent_irq = 4 }, /* EINT7 */
735 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT8 */
736 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT9 */
737 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT10 */
738 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT11 */
739 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT12 */
740 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT13 */
741 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT14 */
742 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT15 */
743 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT16 */
744 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT17 */
745 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT18 */
746 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT19 */
747 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT20 */
748 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT21 */
749 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT22 */
750 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT23 */
751};
752
4245944c
HS		 753static struct s3c_irq_data init_s3c2412subint[32] = {
754 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-RX */
755 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-TX */
756 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-ERR */
757 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-RX */
758 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-TX */
759 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-ERR */
760 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-RX */
761 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-TX */
762 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-ERR */
763 { .type = S3C_IRQTYPE_EDGE, .parent_irq = 31 }, /* TC */
764 { .type = S3C_IRQTYPE_EDGE, .parent_irq = 31 }, /* ADC */
765 { .type = S3C_IRQTYPE_NONE, },
766 { .type = S3C_IRQTYPE_NONE, },
767 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 21 }, /* SDI */
768 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 21 }, /* CF */
769};
d3d5a2c9 770
4245944c 771void s3c2412_init_irq(void)
d3d5a2c9 772{
4245944c 773 struct s3c_irq_intc *main_intc;
d3d5a2c9 774
4245944c 775 pr_info("S3C2412: IRQ Support\n");
d3d5a2c9 776
4245944c
HS		 777#ifdef CONFIG_FIQ
778 init_FIQ(FIQ_START);
779#endif
d3d5a2c9 780
4245944c
HS		 781 main_intc = s3c24xx_init_intc(NULL, &init_s3c2412base[0], NULL, 0x4a000000);
782 if (IS_ERR(main_intc)) {
783 pr_err("irq: could not create main interrupt controller\n");
784 return;
785 }
d3d5a2c9 786
1c8408e3 787 s3c24xx_init_intc(NULL, &init_s3c2412eint[0], main_intc, 0x560000a4);
4245944c 788 s3c24xx_init_intc(NULL, &init_s3c2412subint[0], main_intc, 0x4a000018);
d3d5a2c9 789}
d3d5a2c9
HS		 790#endif
791
ef602eb5 792#ifdef CONFIG_CPU_S3C2416
20f6c781
HS		 793static struct s3c_irq_data init_s3c2416base[32] = {
794 { .type = S3C_IRQTYPE_EINT, }, /* EINT0 */
795 { .type = S3C_IRQTYPE_EINT, }, /* EINT1 */
796 { .type = S3C_IRQTYPE_EINT, }, /* EINT2 */
797 { .type = S3C_IRQTYPE_EINT, }, /* EINT3 */
798 { .type = S3C_IRQTYPE_LEVEL, }, /* EINT4to7 */
799 { .type = S3C_IRQTYPE_LEVEL, }, /* EINT8to23 */
800 { .type = S3C_IRQTYPE_NONE, }, /* reserved */
801 { .type = S3C_IRQTYPE_EDGE, }, /* nBATT_FLT */
802 { .type = S3C_IRQTYPE_EDGE, }, /* TICK */
803 { .type = S3C_IRQTYPE_LEVEL, }, /* WDT/AC97 */
804 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER0 */
805 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER1 */
806 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER2 */
807 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER3 */
808 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER4 */
809 { .type = S3C_IRQTYPE_LEVEL, }, /* UART2 */
810 { .type = S3C_IRQTYPE_LEVEL, }, /* LCD */
811 { .type = S3C_IRQTYPE_LEVEL, }, /* DMA */
812 { .type = S3C_IRQTYPE_LEVEL, }, /* UART3 */
813 { .type = S3C_IRQTYPE_NONE, }, /* reserved */
814 { .type = S3C_IRQTYPE_EDGE, }, /* SDI1 */
815 { .type = S3C_IRQTYPE_EDGE, }, /* SDI0 */
816 { .type = S3C_IRQTYPE_EDGE, }, /* SPI0 */
817 { .type = S3C_IRQTYPE_LEVEL, }, /* UART1 */
818 { .type = S3C_IRQTYPE_EDGE, }, /* NAND */
819 { .type = S3C_IRQTYPE_EDGE, }, /* USBD */
820 { .type = S3C_IRQTYPE_EDGE, }, /* USBH */
821 { .type = S3C_IRQTYPE_EDGE, }, /* IIC */
822 { .type = S3C_IRQTYPE_LEVEL, }, /* UART0 */
823 { .type = S3C_IRQTYPE_NONE, },
824 { .type = S3C_IRQTYPE_EDGE, }, /* RTC */
825 { .type = S3C_IRQTYPE_LEVEL, }, /* ADCPARENT */
ef602eb5
HS		 826};
827
20f6c781
HS		 828static struct s3c_irq_data init_s3c2416subint[32] = {
829 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-RX */
830 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-TX */
831 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-ERR */
832 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-RX */
833 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-TX */
834 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-ERR */
835 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-RX */
836 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-TX */
837 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-ERR */
838 { .type = S3C_IRQTYPE_EDGE, .parent_irq = 31 }, /* TC */
839 { .type = S3C_IRQTYPE_EDGE, .parent_irq = 31 }, /* ADC */
840 { .type = S3C_IRQTYPE_NONE }, /* reserved */
841 { .type = S3C_IRQTYPE_NONE }, /* reserved */
842 { .type = S3C_IRQTYPE_NONE }, /* reserved */
843 { .type = S3C_IRQTYPE_NONE }, /* reserved */
844 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 16 }, /* LCD2 */
845 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 16 }, /* LCD3 */
846 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 16 }, /* LCD4 */
847 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA0 */
848 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA1 */
849 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA2 */
850 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA3 */
851 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA4 */
852 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA5 */
853 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 18 }, /* UART3-RX */
854 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 18 }, /* UART3-TX */
855 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 18 }, /* UART3-ERR */
856 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 9 }, /* WDT */
857 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 9 }, /* AC97 */
ef602eb5
HS		 858};
859
20f6c781
HS		 860static struct s3c_irq_data init_s3c2416_second[32] = {
861 { .type = S3C_IRQTYPE_EDGE }, /* 2D */
1ebc7e83 862 { .type = S3C_IRQTYPE_NONE }, /* reserved */
20f6c781
HS		 863 { .type = S3C_IRQTYPE_NONE }, /* reserved */
864 { .type = S3C_IRQTYPE_NONE }, /* reserved */
865 { .type = S3C_IRQTYPE_EDGE }, /* PCM0 */
1ebc7e83 866 { .type = S3C_IRQTYPE_NONE }, /* reserved */
20f6c781 867 { .type = S3C_IRQTYPE_EDGE }, /* I2S0 */
ef602eb5
HS		 868};
869
4a282dd3 870void __init s3c2416_init_irq(void)
ef602eb5 871{
20f6c781 872 struct s3c_irq_intc *main_intc;
ef602eb5 873
20f6c781 874 pr_info("S3C2416: IRQ Support\n");
ef602eb5 875
20f6c781
HS		 876#ifdef CONFIG_FIQ
877 init_FIQ(FIQ_START);
878#endif
ef602eb5 879
20f6c781
HS		 880 main_intc = s3c24xx_init_intc(NULL, &init_s3c2416base[0], NULL, 0x4a000000);
881 if (IS_ERR(main_intc)) {
882 pr_err("irq: could not create main interrupt controller\n");
883 return;
884 }
ef602eb5 885
20f6c781
HS		 886 s3c24xx_init_intc(NULL, &init_eint[0], main_intc, 0x560000a4);
887 s3c24xx_init_intc(NULL, &init_s3c2416subint[0], main_intc, 0x4a000018);
ef602eb5 888
20f6c781 889 s3c24xx_init_intc(NULL, &init_s3c2416_second[0], NULL, 0x4a000040);
ef602eb5
HS		 890}
891
ef602eb5 892#endif
6b628917 893
ce6c164b 894#ifdef CONFIG_CPU_S3C2440
f0301673
HS		 895static struct s3c_irq_data init_s3c2440base[32] = {
896 { .type = S3C_IRQTYPE_EINT, }, /* EINT0 */
897 { .type = S3C_IRQTYPE_EINT, }, /* EINT1 */
898 { .type = S3C_IRQTYPE_EINT, }, /* EINT2 */
899 { .type = S3C_IRQTYPE_EINT, }, /* EINT3 */
900 { .type = S3C_IRQTYPE_LEVEL, }, /* EINT4to7 */
901 { .type = S3C_IRQTYPE_LEVEL, }, /* EINT8to23 */
902 { .type = S3C_IRQTYPE_LEVEL, }, /* CAM */
903 { .type = S3C_IRQTYPE_EDGE, }, /* nBATT_FLT */
904 { .type = S3C_IRQTYPE_EDGE, }, /* TICK */
905 { .type = S3C_IRQTYPE_LEVEL, }, /* WDT/AC97 */
906 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER0 */
907 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER1 */
908 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER2 */
909 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER3 */
910 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER4 */
911 { .type = S3C_IRQTYPE_LEVEL, }, /* UART2 */
912 { .type = S3C_IRQTYPE_EDGE, }, /* LCD */
913 { .type = S3C_IRQTYPE_EDGE, }, /* DMA0 */
914 { .type = S3C_IRQTYPE_EDGE, }, /* DMA1 */
915 { .type = S3C_IRQTYPE_EDGE, }, /* DMA2 */
916 { .type = S3C_IRQTYPE_EDGE, }, /* DMA3 */
917 { .type = S3C_IRQTYPE_EDGE, }, /* SDI */
918 { .type = S3C_IRQTYPE_EDGE, }, /* SPI0 */
919 { .type = S3C_IRQTYPE_LEVEL, }, /* UART1 */
920 { .type = S3C_IRQTYPE_LEVEL, }, /* NFCON */
921 { .type = S3C_IRQTYPE_EDGE, }, /* USBD */
922 { .type = S3C_IRQTYPE_EDGE, }, /* USBH */
923 { .type = S3C_IRQTYPE_EDGE, }, /* IIC */
924 { .type = S3C_IRQTYPE_LEVEL, }, /* UART0 */
925 { .type = S3C_IRQTYPE_EDGE, }, /* SPI1 */
926 { .type = S3C_IRQTYPE_EDGE, }, /* RTC */
927 { .type = S3C_IRQTYPE_LEVEL, }, /* ADCPARENT */
928};
2286cf46 929
f0301673
HS		 930static struct s3c_irq_data init_s3c2440subint[32] = {
931 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-RX */
932 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-TX */
933 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-ERR */
934 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-RX */
935 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-TX */
936 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-ERR */
937 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-RX */
938 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-TX */
939 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-ERR */
940 { .type = S3C_IRQTYPE_EDGE, .parent_irq = 31 }, /* TC */
941 { .type = S3C_IRQTYPE_EDGE, .parent_irq = 31 }, /* ADC */
e2714f79
HS		 942 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 6 }, /* CAM_C */
943 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 6 }, /* CAM_P */
f0301673
HS		 944 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 9 }, /* WDT */
945 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 9 }, /* AC97 */
2286cf46
HS		 946};
947
7cefed5e 948void __init s3c2440_init_irq(void)
2286cf46 949{
f0301673 950 struct s3c_irq_intc *main_intc;
6f8d7ea2 951
f0301673 952 pr_info("S3C2440: IRQ Support\n");
6f8d7ea2 953
f0301673
HS		 954#ifdef CONFIG_FIQ
955 init_FIQ(FIQ_START);
956#endif
6f8d7ea2 957
f0301673
HS		 958 main_intc = s3c24xx_init_intc(NULL, &init_s3c2440base[0], NULL, 0x4a000000);
959 if (IS_ERR(main_intc)) {
960 pr_err("irq: could not create main interrupt controller\n");
961 return;
6f8d7ea2 962 }
7cefed5e 963
f0301673
HS		 964 s3c24xx_init_intc(NULL, &init_eint[0], main_intc, 0x560000a4);
965 s3c24xx_init_intc(NULL, &init_s3c2440subint[0], main_intc, 0x4a000018);
6f8d7ea2 966}
ce6c164b 967#endif
6f8d7ea2 968
ce6c164b 969#ifdef CONFIG_CPU_S3C2442
70644ade
HS		 970static struct s3c_irq_data init_s3c2442base[32] = {
971 { .type = S3C_IRQTYPE_EINT, }, /* EINT0 */
972 { .type = S3C_IRQTYPE_EINT, }, /* EINT1 */
973 { .type = S3C_IRQTYPE_EINT, }, /* EINT2 */
974 { .type = S3C_IRQTYPE_EINT, }, /* EINT3 */
975 { .type = S3C_IRQTYPE_LEVEL, }, /* EINT4to7 */
976 { .type = S3C_IRQTYPE_LEVEL, }, /* EINT8to23 */
977 { .type = S3C_IRQTYPE_LEVEL, }, /* CAM */
978 { .type = S3C_IRQTYPE_EDGE, }, /* nBATT_FLT */
979 { .type = S3C_IRQTYPE_EDGE, }, /* TICK */
980 { .type = S3C_IRQTYPE_EDGE, }, /* WDT */
981 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER0 */
982 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER1 */
983 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER2 */
984 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER3 */
985 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER4 */
986 { .type = S3C_IRQTYPE_LEVEL, }, /* UART2 */
987 { .type = S3C_IRQTYPE_EDGE, }, /* LCD */
988 { .type = S3C_IRQTYPE_EDGE, }, /* DMA0 */
989 { .type = S3C_IRQTYPE_EDGE, }, /* DMA1 */
990 { .type = S3C_IRQTYPE_EDGE, }, /* DMA2 */
991 { .type = S3C_IRQTYPE_EDGE, }, /* DMA3 */
992 { .type = S3C_IRQTYPE_EDGE, }, /* SDI */
993 { .type = S3C_IRQTYPE_EDGE, }, /* SPI0 */
994 { .type = S3C_IRQTYPE_LEVEL, }, /* UART1 */
995 { .type = S3C_IRQTYPE_LEVEL, }, /* NFCON */
996 { .type = S3C_IRQTYPE_EDGE, }, /* USBD */
997 { .type = S3C_IRQTYPE_EDGE, }, /* USBH */
998 { .type = S3C_IRQTYPE_EDGE, }, /* IIC */
999 { .type = S3C_IRQTYPE_LEVEL, }, /* UART0 */
1000 { .type = S3C_IRQTYPE_EDGE, }, /* SPI1 */
1001 { .type = S3C_IRQTYPE_EDGE, }, /* RTC */
1002 { .type = S3C_IRQTYPE_LEVEL, }, /* ADCPARENT */
1003};
6f8d7ea2 1004
70644ade
HS		 1005static struct s3c_irq_data init_s3c2442subint[32] = {
1006 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-RX */
1007 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-TX */
1008 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-ERR */
1009 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-RX */
1010 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-TX */
1011 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-ERR */
1012 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-RX */
1013 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-TX */
1014 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-ERR */
1015 { .type = S3C_IRQTYPE_EDGE, .parent_irq = 31 }, /* TC */
1016 { .type = S3C_IRQTYPE_EDGE, .parent_irq = 31 }, /* ADC */
e2714f79
HS		 1017 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 6 }, /* CAM_C */
1018 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 6 }, /* CAM_P */
70644ade 1019};
6f8d7ea2 1020
70644ade
HS		 1021void __init s3c2442_init_irq(void)
1022{
1023 struct s3c_irq_intc *main_intc;
6f8d7ea2 1024
70644ade 1025 pr_info("S3C2442: IRQ Support\n");
6f8d7ea2 1026
70644ade
HS		 1027#ifdef CONFIG_FIQ
1028 init_FIQ(FIQ_START);
1029#endif
ce6c164b 1030
70644ade
HS		 1031 main_intc = s3c24xx_init_intc(NULL, &init_s3c2442base[0], NULL, 0x4a000000);
1032 if (IS_ERR(main_intc)) {
1033 pr_err("irq: could not create main interrupt controller\n");
1034 return;
ce6c164b 1035 }
70644ade
HS		 1036
1037 s3c24xx_init_intc(NULL, &init_eint[0], main_intc, 0x560000a4);
1038 s3c24xx_init_intc(NULL, &init_s3c2442subint[0], main_intc, 0x4a000018);
6f8d7ea2 1039}
ce6c164b 1040#endif
6f8d7ea2 1041
6b628917 1042#ifdef CONFIG_CPU_S3C2443
f44ddba3
HS		 1043static struct s3c_irq_data init_s3c2443base[32] = {
1044 { .type = S3C_IRQTYPE_EINT, }, /* EINT0 */
1045 { .type = S3C_IRQTYPE_EINT, }, /* EINT1 */
1046 { .type = S3C_IRQTYPE_EINT, }, /* EINT2 */
1047 { .type = S3C_IRQTYPE_EINT, }, /* EINT3 */
1048 { .type = S3C_IRQTYPE_LEVEL, }, /* EINT4to7 */
1049 { .type = S3C_IRQTYPE_LEVEL, }, /* EINT8to23 */
1050 { .type = S3C_IRQTYPE_LEVEL, }, /* CAM */
1051 { .type = S3C_IRQTYPE_EDGE, }, /* nBATT_FLT */
1052 { .type = S3C_IRQTYPE_EDGE, }, /* TICK */
1053 { .type = S3C_IRQTYPE_LEVEL, }, /* WDT/AC97 */
1054 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER0 */
1055 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER1 */
1056 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER2 */
1057 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER3 */
1058 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER4 */
1059 { .type = S3C_IRQTYPE_LEVEL, }, /* UART2 */
1060 { .type = S3C_IRQTYPE_LEVEL, }, /* LCD */
1061 { .type = S3C_IRQTYPE_LEVEL, }, /* DMA */
1062 { .type = S3C_IRQTYPE_LEVEL, }, /* UART3 */
1063 { .type = S3C_IRQTYPE_EDGE, }, /* CFON */
1064 { .type = S3C_IRQTYPE_EDGE, }, /* SDI1 */
1065 { .type = S3C_IRQTYPE_EDGE, }, /* SDI0 */
1066 { .type = S3C_IRQTYPE_EDGE, }, /* SPI0 */
1067 { .type = S3C_IRQTYPE_LEVEL, }, /* UART1 */
1068 { .type = S3C_IRQTYPE_EDGE, }, /* NAND */
1069 { .type = S3C_IRQTYPE_EDGE, }, /* USBD */
1070 { .type = S3C_IRQTYPE_EDGE, }, /* USBH */
1071 { .type = S3C_IRQTYPE_EDGE, }, /* IIC */
1072 { .type = S3C_IRQTYPE_LEVEL, }, /* UART0 */
1073 { .type = S3C_IRQTYPE_EDGE, }, /* SPI1 */
1074 { .type = S3C_IRQTYPE_EDGE, }, /* RTC */
1075 { .type = S3C_IRQTYPE_LEVEL, }, /* ADCPARENT */
6b628917
HS		 1076};
1077
6b628917 1078
f44ddba3
HS		 1079static struct s3c_irq_data init_s3c2443subint[32] = {
1080 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-RX */
1081 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-TX */
1082 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-ERR */
1083 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-RX */
1084 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-TX */
1085 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-ERR */
1086 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-RX */
1087 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-TX */
1088 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-ERR */
1089 { .type = S3C_IRQTYPE_EDGE, .parent_irq = 31 }, /* TC */
1090 { .type = S3C_IRQTYPE_EDGE, .parent_irq = 31 }, /* ADC */
1091 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 6 }, /* CAM_C */
1092 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 6 }, /* CAM_P */
1093 { .type = S3C_IRQTYPE_NONE }, /* reserved */
1094 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 16 }, /* LCD1 */
1095 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 16 }, /* LCD2 */
1096 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 16 }, /* LCD3 */
1097 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 16 }, /* LCD4 */
1098 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA0 */
1099 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA1 */
1100 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA2 */
1101 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA3 */
1102 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA4 */
1103 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA5 */
1104 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 18 }, /* UART3-RX */
1105 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 18 }, /* UART3-TX */
1106 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 18 }, /* UART3-ERR */
1107 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 9 }, /* WDT */
1108 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 9 }, /* AC97 */
6b628917
HS		 1109};
1110
b499b7a8 1111void __init s3c2443_init_irq(void)
6b628917 1112{
f44ddba3 1113 struct s3c_irq_intc *main_intc;
6b628917 1114
f44ddba3 1115 pr_info("S3C2443: IRQ Support\n");
6b628917 1116
f44ddba3
HS		 1117#ifdef CONFIG_FIQ
1118 init_FIQ(FIQ_START);
1119#endif
6b628917 1120
f44ddba3
HS		 1121 main_intc = s3c24xx_init_intc(NULL, &init_s3c2443base[0], NULL, 0x4a000000);
1122 if (IS_ERR(main_intc)) {
1123 pr_err("irq: could not create main interrupt controller\n");
1124 return;
1125 }
6b628917 1126
f44ddba3
HS		 1127 s3c24xx_init_intc(NULL, &init_eint[0], main_intc, 0x560000a4);
1128 s3c24xx_init_intc(NULL, &init_s3c2443subint[0], main_intc, 0x4a000018);
6b628917 1129}
6b628917 1130#endif
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