[mirror_ubuntu-artful-kernel.git] / drivers / irqchip / irq-sirfsoc.c

/*
 * interrupt controller support for CSR SiRFprimaII
 *
 * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company.
 *
 * Licensed under GPLv2 or later.
 */

#include <linux/init.h>
#include <linux/io.h>
#include <linux/irq.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/irqdomain.h>
#include <linux/syscore_ops.h>
#include <asm/mach/irq.h>
#include <asm/exception.h>
#include "irqchip.h"

#define SIRFSOC_INT_RISC_MASK0          0x0018
#define SIRFSOC_INT_RISC_MASK1          0x001C
#define SIRFSOC_INT_RISC_LEVEL0         0x0020
#define SIRFSOC_INT_RISC_LEVEL1         0x0024
#define SIRFSOC_INIT_IRQ_ID		0x0038

#define SIRFSOC_NUM_IRQS		64

static struct irq_domain *sirfsoc_irqdomain;

static __init void
sirfsoc_alloc_gc(void __iomem *base, unsigned int irq_start, unsigned int num)
{
	struct irq_chip_generic *gc;
	struct irq_chip_type *ct;
	int ret;
	unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN;
	unsigned int set = IRQ_LEVEL;

	ret = irq_alloc_domain_generic_chips(sirfsoc_irqdomain, num, 1, "irq_sirfsoc",
		handle_level_irq, clr, set, IRQ_GC_INIT_MASK_CACHE);

	gc = irq_get_domain_generic_chip(sirfsoc_irqdomain, irq_start);
	gc->reg_base = base;
	ct = gc->chip_types;
	ct->chip.irq_mask = irq_gc_mask_clr_bit;
	ct->chip.irq_unmask = irq_gc_mask_set_bit;
	ct->regs.mask = SIRFSOC_INT_RISC_MASK0;
}

static void __exception_irq_entry sirfsoc_handle_irq(struct pt_regs *regs)
{
	void __iomem *base = sirfsoc_irqdomain->host_data;
	u32 irqstat;

	irqstat = readl_relaxed(base + SIRFSOC_INIT_IRQ_ID);
	handle_domain_irq(sirfsoc_irqdomain, irqstat & 0xff, regs);
}

static int __init sirfsoc_irq_init(struct device_node *np,
	struct device_node *parent)
{
	void __iomem *base = of_iomap(np, 0);
	if (!base)
		panic("unable to map intc cpu registers\n");

	sirfsoc_irqdomain = irq_domain_add_linear(np, SIRFSOC_NUM_IRQS,
		&irq_generic_chip_ops, base);

	sirfsoc_alloc_gc(base, 0, 32);
	sirfsoc_alloc_gc(base + 4, 32, SIRFSOC_NUM_IRQS - 32);

	writel_relaxed(0, base + SIRFSOC_INT_RISC_LEVEL0);
	writel_relaxed(0, base + SIRFSOC_INT_RISC_LEVEL1);

	writel_relaxed(0, base + SIRFSOC_INT_RISC_MASK0);
	writel_relaxed(0, base + SIRFSOC_INT_RISC_MASK1);

	set_handle_irq(sirfsoc_handle_irq);

	return 0;
}
IRQCHIP_DECLARE(sirfsoc_intc, "sirf,prima2-intc", sirfsoc_irq_init);

struct sirfsoc_irq_status {
	u32 mask0;
	u32 mask1;
	u32 level0;
	u32 level1;
};

static struct sirfsoc_irq_status sirfsoc_irq_st;

static int sirfsoc_irq_suspend(void)
{
	void __iomem *base = sirfsoc_irqdomain->host_data;

	sirfsoc_irq_st.mask0 = readl_relaxed(base + SIRFSOC_INT_RISC_MASK0);
	sirfsoc_irq_st.mask1 = readl_relaxed(base + SIRFSOC_INT_RISC_MASK1);
	sirfsoc_irq_st.level0 = readl_relaxed(base + SIRFSOC_INT_RISC_LEVEL0);
	sirfsoc_irq_st.level1 = readl_relaxed(base + SIRFSOC_INT_RISC_LEVEL1);

	return 0;
}

static void sirfsoc_irq_resume(void)
{
	void __iomem *base = sirfsoc_irqdomain->host_data;

	writel_relaxed(sirfsoc_irq_st.mask0, base + SIRFSOC_INT_RISC_MASK0);
	writel_relaxed(sirfsoc_irq_st.mask1, base + SIRFSOC_INT_RISC_MASK1);
	writel_relaxed(sirfsoc_irq_st.level0, base + SIRFSOC_INT_RISC_LEVEL0);
	writel_relaxed(sirfsoc_irq_st.level1, base + SIRFSOC_INT_RISC_LEVEL1);
}

static struct syscore_ops sirfsoc_irq_syscore_ops = {
	.suspend	= sirfsoc_irq_suspend,
	.resume		= sirfsoc_irq_resume,
};

static int __init sirfsoc_irq_pm_init(void)
{
	if (!sirfsoc_irqdomain)
		return 0;

	register_syscore_ops(&sirfsoc_irq_syscore_ops);
	return 0;
}
device_initcall(sirfsoc_irq_pm_init);
Commit	Line	Data
60dbd768 AB	1	/*
	2	* interrupt controller support for CSR SiRFprimaII
	3	*
	4	* Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company.
	5	*
	6	* Licensed under GPLv2 or later.
	7	*/
	8
	9	#include <linux/init.h>
	10	#include <linux/io.h>
	11	#include <linux/irq.h>
	12	#include <linux/of.h>
	13	#include <linux/of_address.h>
	14	#include <linux/irqdomain.h>
	15	#include <linux/syscore_ops.h>
	16	#include <asm/mach/irq.h>
	17	#include <asm/exception.h>
	18	#include "irqchip.h"
	19
	20	#define SIRFSOC_INT_RISC_MASK0 0x0018
	21	#define SIRFSOC_INT_RISC_MASK1 0x001C
	22	#define SIRFSOC_INT_RISC_LEVEL0 0x0020
	23	#define SIRFSOC_INT_RISC_LEVEL1 0x0024
	24	#define SIRFSOC_INIT_IRQ_ID 0x0038
	25
29eb51a7	26	#define SIRFSOC_NUM_IRQS 64
60dbd768 AB	27
	28	static struct irq_domain *sirfsoc_irqdomain;
	29
	30	static __init void
	31	sirfsoc_alloc_gc(void __iomem *base, unsigned int irq_start, unsigned int num)
	32	{
	33	struct irq_chip_generic *gc;
	34	struct irq_chip_type *ct;
29eb51a7 BS	35	int ret;
29eb51a7 BS	36	unsigned int clr = IRQ_NOREQUEST \| IRQ_NOPROBE \| IRQ_NOAUTOEN;
a87010ef	37	unsigned int set = IRQ_LEVEL;
60dbd768	38
29eb51a7	39	ret = irq_alloc_domain_generic_chips(sirfsoc_irqdomain, num, 1, "irq_sirfsoc",
a87010ef	40	handle_level_irq, clr, set, IRQ_GC_INIT_MASK_CACHE);
60dbd768	41
29eb51a7 BS	42	gc = irq_get_domain_generic_chip(sirfsoc_irqdomain, irq_start);
	43	gc->reg_base = base;
	44	ct = gc->chip_types;
60dbd768 AB	45	ct->chip.irq_mask = irq_gc_mask_clr_bit;
	46	ct->chip.irq_unmask = irq_gc_mask_set_bit;
	47	ct->regs.mask = SIRFSOC_INT_RISC_MASK0;
60dbd768 AB	48	}
60dbd768 AB	49
8783dd3a	50	static void __exception_irq_entry sirfsoc_handle_irq(struct pt_regs *regs)
60dbd768 AB	51	{
60dbd768 AB	52	void __iomem *base = sirfsoc_irqdomain->host_data;
c15018e9	53	u32 irqstat;
60dbd768 AB	54
60dbd768 AB	55	irqstat = readl_relaxed(base + SIRFSOC_INIT_IRQ_ID);
c15018e9	56	handle_domain_irq(sirfsoc_irqdomain, irqstat & 0xff, regs);
60dbd768 AB	57	}
60dbd768 AB	58
7caf6852 BS	59	static int __init sirfsoc_irq_init(struct device_node *np,
7caf6852 BS	60	struct device_node *parent)
60dbd768 AB	61	{
	62	void __iomem *base = of_iomap(np, 0);
	63	if (!base)
	64	panic("unable to map intc cpu registers\n");
	65
29eb51a7 BS	66	sirfsoc_irqdomain = irq_domain_add_linear(np, SIRFSOC_NUM_IRQS,
29eb51a7 BS	67	&irq_generic_chip_ops, base);
60dbd768 AB	68
	69	sirfsoc_alloc_gc(base, 0, 32);
	70	sirfsoc_alloc_gc(base + 4, 32, SIRFSOC_NUM_IRQS - 32);
	71
	72	writel_relaxed(0, base + SIRFSOC_INT_RISC_LEVEL0);
	73	writel_relaxed(0, base + SIRFSOC_INT_RISC_LEVEL1);
	74
	75	writel_relaxed(0, base + SIRFSOC_INT_RISC_MASK0);
	76	writel_relaxed(0, base + SIRFSOC_INT_RISC_MASK1);
	77
	78	set_handle_irq(sirfsoc_handle_irq);
	79
	80	return 0;
	81	}
	82	IRQCHIP_DECLARE(sirfsoc_intc, "sirf,prima2-intc", sirfsoc_irq_init);
	83
	84	struct sirfsoc_irq_status {
	85	u32 mask0;
	86	u32 mask1;
	87	u32 level0;
	88	u32 level1;
	89	};
	90
	91	static struct sirfsoc_irq_status sirfsoc_irq_st;
	92
	93	static int sirfsoc_irq_suspend(void)
	94	{
	95	void __iomem *base = sirfsoc_irqdomain->host_data;
	96
	97	sirfsoc_irq_st.mask0 = readl_relaxed(base + SIRFSOC_INT_RISC_MASK0);
	98	sirfsoc_irq_st.mask1 = readl_relaxed(base + SIRFSOC_INT_RISC_MASK1);
	99	sirfsoc_irq_st.level0 = readl_relaxed(base + SIRFSOC_INT_RISC_LEVEL0);
	100	sirfsoc_irq_st.level1 = readl_relaxed(base + SIRFSOC_INT_RISC_LEVEL1);
	101
	102	return 0;
	103	}
	104
	105	static void sirfsoc_irq_resume(void)
	106	{
	107	void __iomem *base = sirfsoc_irqdomain->host_data;
	108
	109	writel_relaxed(sirfsoc_irq_st.mask0, base + SIRFSOC_INT_RISC_MASK0);
	110	writel_relaxed(sirfsoc_irq_st.mask1, base + SIRFSOC_INT_RISC_MASK1);
	111	writel_relaxed(sirfsoc_irq_st.level0, base + SIRFSOC_INT_RISC_LEVEL0);
	112	writel_relaxed(sirfsoc_irq_st.level1, base + SIRFSOC_INT_RISC_LEVEL1);
	113	}
	114
	115	static struct syscore_ops sirfsoc_irq_syscore_ops = {
	116	.suspend = sirfsoc_irq_suspend,
	117	.resume = sirfsoc_irq_resume,
	118	};
	119
	120	static int __init sirfsoc_irq_pm_init(void)
	121	{
	122	if (!sirfsoc_irqdomain)
	123	return 0;
	124
	125	register_syscore_ops(&sirfsoc_irq_syscore_ops);
	126	return 0;
	127	}
	128	device_initcall(sirfsoc_irq_pm_init);