[mirror_ubuntu-zesty-kernel.git] / drivers / irqchip / irq-sirfsoc.c

/*
 * interrupt controller support for CSR SiRFprimaII
 *
 * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company.
 *
 * Licensed under GPLv2 or later.
 */

#include <linux/init.h>
#include <linux/io.h>
#include <linux/irq.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/irqchip.h>
#include <linux/irqdomain.h>
#include <linux/syscore_ops.h>
#include <asm/mach/irq.h>
#include <asm/exception.h>

#define SIRFSOC_INT_RISC_MASK0		0x0018
#define SIRFSOC_INT_RISC_MASK1		0x001C
#define SIRFSOC_INT_RISC_LEVEL0		0x0020
#define SIRFSOC_INT_RISC_LEVEL1		0x0024
#define SIRFSOC_INIT_IRQ_ID		0x0038
#define SIRFSOC_INT_BASE_OFFSET		0x0004

#define SIRFSOC_NUM_IRQS		64
#define SIRFSOC_NUM_BANKS		(SIRFSOC_NUM_IRQS / 32)

static struct irq_domain *sirfsoc_irqdomain;

static void __iomem *sirfsoc_irq_get_regbase(void)
{
	return (void __iomem __force *)sirfsoc_irqdomain->host_data;
}

static __init void sirfsoc_alloc_gc(void __iomem *base)
{
	unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN;
	unsigned int set = IRQ_LEVEL;
	struct irq_chip_generic *gc;
	struct irq_chip_type *ct;
	int i;

	irq_alloc_domain_generic_chips(sirfsoc_irqdomain, 32, 1, "irq_sirfsoc",
				       handle_level_irq, clr, set,
				       IRQ_GC_INIT_MASK_CACHE);

	for (i = 0; i < SIRFSOC_NUM_BANKS; i++) {
		gc = irq_get_domain_generic_chip(sirfsoc_irqdomain, i * 32);
		gc->reg_base = base + i * SIRFSOC_INT_BASE_OFFSET;
		ct = gc->chip_types;
		ct->chip.irq_mask = irq_gc_mask_clr_bit;
		ct->chip.irq_unmask = irq_gc_mask_set_bit;
		ct->regs.mask = SIRFSOC_INT_RISC_MASK0;
	}
}

static void __exception_irq_entry sirfsoc_handle_irq(struct pt_regs *regs)
{
	void __iomem *base = sirfsoc_irq_get_regbase();
	u32 irqstat;

	irqstat = readl_relaxed(base + SIRFSOC_INIT_IRQ_ID);
	handle_domain_irq(sirfsoc_irqdomain, irqstat & 0xff, regs);
}

static int __init sirfsoc_irq_init(struct device_node *np,
	struct device_node *parent)
{
	void __iomem *base = of_iomap(np, 0);
	if (!base)
		panic("unable to map intc cpu registers\n");

	sirfsoc_irqdomain = irq_domain_add_linear(np, SIRFSOC_NUM_IRQS,
						  &irq_generic_chip_ops, base);
	sirfsoc_alloc_gc(base);

	writel_relaxed(0, base + SIRFSOC_INT_RISC_LEVEL0);
	writel_relaxed(0, base + SIRFSOC_INT_RISC_LEVEL1);

	writel_relaxed(0, base + SIRFSOC_INT_RISC_MASK0);
	writel_relaxed(0, base + SIRFSOC_INT_RISC_MASK1);

	set_handle_irq(sirfsoc_handle_irq);

	return 0;
}
IRQCHIP_DECLARE(sirfsoc_intc, "sirf,prima2-intc", sirfsoc_irq_init);

struct sirfsoc_irq_status {
	u32 mask0;
	u32 mask1;
	u32 level0;
	u32 level1;
};

static struct sirfsoc_irq_status sirfsoc_irq_st;

static int sirfsoc_irq_suspend(void)
{
	void __iomem *base = sirfsoc_irq_get_regbase();

	sirfsoc_irq_st.mask0 = readl_relaxed(base + SIRFSOC_INT_RISC_MASK0);
	sirfsoc_irq_st.mask1 = readl_relaxed(base + SIRFSOC_INT_RISC_MASK1);
	sirfsoc_irq_st.level0 = readl_relaxed(base + SIRFSOC_INT_RISC_LEVEL0);
	sirfsoc_irq_st.level1 = readl_relaxed(base + SIRFSOC_INT_RISC_LEVEL1);

	return 0;
}

static void sirfsoc_irq_resume(void)
{
	void __iomem *base = sirfsoc_irq_get_regbase();

	writel_relaxed(sirfsoc_irq_st.mask0, base + SIRFSOC_INT_RISC_MASK0);
	writel_relaxed(sirfsoc_irq_st.mask1, base + SIRFSOC_INT_RISC_MASK1);
	writel_relaxed(sirfsoc_irq_st.level0, base + SIRFSOC_INT_RISC_LEVEL0);
	writel_relaxed(sirfsoc_irq_st.level1, base + SIRFSOC_INT_RISC_LEVEL1);
}

static struct syscore_ops sirfsoc_irq_syscore_ops = {
	.suspend	= sirfsoc_irq_suspend,
	.resume		= sirfsoc_irq_resume,
};

static int __init sirfsoc_irq_pm_init(void)
{
	if (!sirfsoc_irqdomain)
		return 0;

	register_syscore_ops(&sirfsoc_irq_syscore_ops);
	return 0;
}
device_initcall(sirfsoc_irq_pm_init);
Commit	Line	Data
60dbd768 AB	1	/*
	2	* interrupt controller support for CSR SiRFprimaII
	3	*
	4	* Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company.
	5	*
	6	* Licensed under GPLv2 or later.
	7	*/
	8
	9	#include <linux/init.h>
	10	#include <linux/io.h>
	11	#include <linux/irq.h>
	12	#include <linux/of.h>
	13	#include <linux/of_address.h>
41a83e06	14	#include <linux/irqchip.h>
60dbd768 AB	15	#include <linux/irqdomain.h>
	16	#include <linux/syscore_ops.h>
	17	#include <asm/mach/irq.h>
	18	#include <asm/exception.h>
60dbd768	19
d452bca8 TG	20	#define SIRFSOC_INT_RISC_MASK0 0x0018
	21	#define SIRFSOC_INT_RISC_MASK1 0x001C
	22	#define SIRFSOC_INT_RISC_LEVEL0 0x0020
	23	#define SIRFSOC_INT_RISC_LEVEL1 0x0024
60dbd768	24	#define SIRFSOC_INIT_IRQ_ID 0x0038
d452bca8	25	#define SIRFSOC_INT_BASE_OFFSET 0x0004
60dbd768	26
29eb51a7	27	#define SIRFSOC_NUM_IRQS 64
d452bca8	28	#define SIRFSOC_NUM_BANKS (SIRFSOC_NUM_IRQS / 32)
60dbd768 AB	29
	30	static struct irq_domain *sirfsoc_irqdomain;
	31
4a3691cc BD	32	static void __iomem *sirfsoc_irq_get_regbase(void)
	33	{
	34	return (void __iomem __force *)sirfsoc_irqdomain->host_data;
	35	}
	36
d452bca8	37	static __init void sirfsoc_alloc_gc(void __iomem *base)
60dbd768	38	{
29eb51a7	39	unsigned int clr = IRQ_NOREQUEST \| IRQ_NOPROBE \| IRQ_NOAUTOEN;
a87010ef	40	unsigned int set = IRQ_LEVEL;
d452bca8 TG	41	struct irq_chip_generic *gc;
	42	struct irq_chip_type *ct;
	43	int i;
	44
	45	irq_alloc_domain_generic_chips(sirfsoc_irqdomain, 32, 1, "irq_sirfsoc",
	46	handle_level_irq, clr, set,
	47	IRQ_GC_INIT_MASK_CACHE);
	48
	49	for (i = 0; i < SIRFSOC_NUM_BANKS; i++) {
	50	gc = irq_get_domain_generic_chip(sirfsoc_irqdomain, i * 32);
	51	gc->reg_base = base + i * SIRFSOC_INT_BASE_OFFSET;
	52	ct = gc->chip_types;
	53	ct->chip.irq_mask = irq_gc_mask_clr_bit;
	54	ct->chip.irq_unmask = irq_gc_mask_set_bit;
	55	ct->regs.mask = SIRFSOC_INT_RISC_MASK0;
	56	}
60dbd768 AB	57	}
60dbd768 AB	58
8783dd3a	59	static void __exception_irq_entry sirfsoc_handle_irq(struct pt_regs *regs)
60dbd768	60	{
4a3691cc	61	void __iomem *base = sirfsoc_irq_get_regbase();
c15018e9	62	u32 irqstat;
60dbd768 AB	63
60dbd768 AB	64	irqstat = readl_relaxed(base + SIRFSOC_INIT_IRQ_ID);
c15018e9	65	handle_domain_irq(sirfsoc_irqdomain, irqstat & 0xff, regs);
60dbd768 AB	66	}
60dbd768 AB	67
7caf6852 BS	68	static int __init sirfsoc_irq_init(struct device_node *np,
7caf6852 BS	69	struct device_node *parent)
60dbd768 AB	70	{
	71	void __iomem *base = of_iomap(np, 0);
	72	if (!base)
	73	panic("unable to map intc cpu registers\n");
	74
29eb51a7	75	sirfsoc_irqdomain = irq_domain_add_linear(np, SIRFSOC_NUM_IRQS,
d452bca8 TG	76	&irq_generic_chip_ops, base);
d452bca8 TG	77	sirfsoc_alloc_gc(base);
60dbd768 AB	78
	79	writel_relaxed(0, base + SIRFSOC_INT_RISC_LEVEL0);
	80	writel_relaxed(0, base + SIRFSOC_INT_RISC_LEVEL1);
	81
	82	writel_relaxed(0, base + SIRFSOC_INT_RISC_MASK0);
	83	writel_relaxed(0, base + SIRFSOC_INT_RISC_MASK1);
	84
	85	set_handle_irq(sirfsoc_handle_irq);
	86
	87	return 0;
	88	}
	89	IRQCHIP_DECLARE(sirfsoc_intc, "sirf,prima2-intc", sirfsoc_irq_init);
	90
	91	struct sirfsoc_irq_status {
	92	u32 mask0;
	93	u32 mask1;
	94	u32 level0;
	95	u32 level1;
	96	};
	97
	98	static struct sirfsoc_irq_status sirfsoc_irq_st;
	99
	100	static int sirfsoc_irq_suspend(void)
	101	{
4a3691cc	102	void __iomem *base = sirfsoc_irq_get_regbase();
60dbd768 AB	103
	104	sirfsoc_irq_st.mask0 = readl_relaxed(base + SIRFSOC_INT_RISC_MASK0);
	105	sirfsoc_irq_st.mask1 = readl_relaxed(base + SIRFSOC_INT_RISC_MASK1);
	106	sirfsoc_irq_st.level0 = readl_relaxed(base + SIRFSOC_INT_RISC_LEVEL0);
	107	sirfsoc_irq_st.level1 = readl_relaxed(base + SIRFSOC_INT_RISC_LEVEL1);
	108
	109	return 0;
	110	}
	111
	112	static void sirfsoc_irq_resume(void)
	113	{
4a3691cc	114	void __iomem *base = sirfsoc_irq_get_regbase();
60dbd768 AB	115
	116	writel_relaxed(sirfsoc_irq_st.mask0, base + SIRFSOC_INT_RISC_MASK0);
	117	writel_relaxed(sirfsoc_irq_st.mask1, base + SIRFSOC_INT_RISC_MASK1);
	118	writel_relaxed(sirfsoc_irq_st.level0, base + SIRFSOC_INT_RISC_LEVEL0);
	119	writel_relaxed(sirfsoc_irq_st.level1, base + SIRFSOC_INT_RISC_LEVEL1);
	120	}
	121
	122	static struct syscore_ops sirfsoc_irq_syscore_ops = {
	123	.suspend = sirfsoc_irq_suspend,
	124	.resume = sirfsoc_irq_resume,
	125	};
	126
	127	static int __init sirfsoc_irq_pm_init(void)
	128	{
	129	if (!sirfsoc_irqdomain)
	130	return 0;
	131
	132	register_syscore_ops(&sirfsoc_irq_syscore_ops);
	133	return 0;
	134	}
	135	device_initcall(sirfsoc_irq_pm_init);