[mirror_ubuntu-jammy-kernel.git] / drivers / irqchip / irq-tb10x.c

// SPDX-License-Identifier: GPL-2.0-only
/*
 * Abilis Systems interrupt controller driver
 *
 * Copyright (C) Abilis Systems 2012
 *
 * Author: Christian Ruppert <christian.ruppert@abilis.com>
 */

#include <linux/interrupt.h>
#include <linux/irqdomain.h>
#include <linux/irq.h>
#include <linux/irqchip.h>
#include <linux/of_irq.h>
#include <linux/of_address.h>
#include <linux/of_platform.h>
#include <linux/io.h>
#include <linux/slab.h>
#include <linux/bitops.h>

#define AB_IRQCTL_INT_ENABLE   0x00
#define AB_IRQCTL_INT_STATUS   0x04
#define AB_IRQCTL_SRC_MODE     0x08
#define AB_IRQCTL_SRC_POLARITY 0x0C
#define AB_IRQCTL_INT_MODE     0x10
#define AB_IRQCTL_INT_POLARITY 0x14
#define AB_IRQCTL_INT_FORCE    0x18

#define AB_IRQCTL_MAXIRQ       32

static inline void ab_irqctl_writereg(struct irq_chip_generic *gc, u32 reg,
	u32 val)
{
	irq_reg_writel(gc, val, reg);
}

static inline u32 ab_irqctl_readreg(struct irq_chip_generic *gc, u32 reg)
{
	return irq_reg_readl(gc, reg);
}

static int tb10x_irq_set_type(struct irq_data *data, unsigned int flow_type)
{
	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(data);
	uint32_t im, mod, pol;

	im = data->mask;

	irq_gc_lock(gc);

	mod = ab_irqctl_readreg(gc, AB_IRQCTL_SRC_MODE) | im;
	pol = ab_irqctl_readreg(gc, AB_IRQCTL_SRC_POLARITY) | im;

	switch (flow_type & IRQF_TRIGGER_MASK) {
	case IRQ_TYPE_EDGE_FALLING:
		pol ^= im;
		break;
	case IRQ_TYPE_LEVEL_HIGH:
		mod ^= im;
		break;
	case IRQ_TYPE_NONE:
		flow_type = IRQ_TYPE_LEVEL_LOW;
		fallthrough;
	case IRQ_TYPE_LEVEL_LOW:
		mod ^= im;
		pol ^= im;
		break;
	case IRQ_TYPE_EDGE_RISING:
		break;
	default:
		irq_gc_unlock(gc);
		pr_err("%s: Cannot assign multiple trigger modes to IRQ %d.\n",
			__func__, data->irq);
		return -EBADR;
	}

	irqd_set_trigger_type(data, flow_type);
	irq_setup_alt_chip(data, flow_type);

	ab_irqctl_writereg(gc, AB_IRQCTL_SRC_MODE, mod);
	ab_irqctl_writereg(gc, AB_IRQCTL_SRC_POLARITY, pol);
	ab_irqctl_writereg(gc, AB_IRQCTL_INT_STATUS, im);

	irq_gc_unlock(gc);

	return IRQ_SET_MASK_OK;
}

static void tb10x_irq_cascade(struct irq_desc *desc)
{
	struct irq_domain *domain = irq_desc_get_handler_data(desc);
	unsigned int irq = irq_desc_get_irq(desc);

	generic_handle_domain_irq(domain, irq);
}

static int __init of_tb10x_init_irq(struct device_node *ictl,
					struct device_node *parent)
{
	int i, ret, nrirqs = of_irq_count(ictl);
	struct resource mem;
	struct irq_chip_generic *gc;
	struct irq_domain *domain;
	void __iomem *reg_base;

	if (of_address_to_resource(ictl, 0, &mem)) {
		pr_err("%pOFn: No registers declared in DeviceTree.\n",
			ictl);
		return -EINVAL;
	}

	if (!request_mem_region(mem.start, resource_size(&mem),
		ictl->full_name)) {
		pr_err("%pOFn: Request mem region failed.\n", ictl);
		return -EBUSY;
	}

	reg_base = ioremap(mem.start, resource_size(&mem));
	if (!reg_base) {
		ret = -EBUSY;
		pr_err("%pOFn: ioremap failed.\n", ictl);
		goto ioremap_fail;
	}

	domain = irq_domain_add_linear(ictl, AB_IRQCTL_MAXIRQ,
					&irq_generic_chip_ops, NULL);
	if (!domain) {
		ret = -ENOMEM;
		pr_err("%pOFn: Could not register interrupt domain.\n",
			ictl);
		goto irq_domain_add_fail;
	}

	ret = irq_alloc_domain_generic_chips(domain, AB_IRQCTL_MAXIRQ,
				2, ictl->name, handle_level_irq,
				IRQ_NOREQUEST, IRQ_NOPROBE,
				IRQ_GC_INIT_MASK_CACHE);
	if (ret) {
		pr_err("%pOFn: Could not allocate generic interrupt chip.\n",
			ictl);
		goto gc_alloc_fail;
	}

	gc = domain->gc->gc[0];
	gc->reg_base                         = reg_base;

	gc->chip_types[0].type               = IRQ_TYPE_LEVEL_MASK;
	gc->chip_types[0].chip.irq_mask      = irq_gc_mask_clr_bit;
	gc->chip_types[0].chip.irq_unmask    = irq_gc_mask_set_bit;
	gc->chip_types[0].chip.irq_set_type  = tb10x_irq_set_type;
	gc->chip_types[0].regs.mask          = AB_IRQCTL_INT_ENABLE;

	gc->chip_types[1].type               = IRQ_TYPE_EDGE_BOTH;
	gc->chip_types[1].chip.name          = gc->chip_types[0].chip.name;
	gc->chip_types[1].chip.irq_ack       = irq_gc_ack_set_bit;
	gc->chip_types[1].chip.irq_mask      = irq_gc_mask_clr_bit;
	gc->chip_types[1].chip.irq_unmask    = irq_gc_mask_set_bit;
	gc->chip_types[1].chip.irq_set_type  = tb10x_irq_set_type;
	gc->chip_types[1].regs.ack           = AB_IRQCTL_INT_STATUS;
	gc->chip_types[1].regs.mask          = AB_IRQCTL_INT_ENABLE;
	gc->chip_types[1].handler            = handle_edge_irq;

	for (i = 0; i < nrirqs; i++) {
		unsigned int irq = irq_of_parse_and_map(ictl, i);

		irq_set_chained_handler_and_data(irq, tb10x_irq_cascade,
						 domain);
	}

	ab_irqctl_writereg(gc, AB_IRQCTL_INT_ENABLE, 0);
	ab_irqctl_writereg(gc, AB_IRQCTL_INT_MODE, 0);
	ab_irqctl_writereg(gc, AB_IRQCTL_INT_POLARITY, 0);
	ab_irqctl_writereg(gc, AB_IRQCTL_INT_STATUS, ~0UL);

	return 0;

gc_alloc_fail:
	irq_domain_remove(domain);
irq_domain_add_fail:
	iounmap(reg_base);
ioremap_fail:
	release_mem_region(mem.start, resource_size(&mem));
	return ret;
}
IRQCHIP_DECLARE(tb10x_intc, "abilis,tb10x-ictl", of_tb10x_init_irq);
Commit	Line	Data
45051539	1	// SPDX-License-Identifier: GPL-2.0-only
b06eb017 CR	2	/*
	3	* Abilis Systems interrupt controller driver
	4	*
	5	* Copyright (C) Abilis Systems 2012
	6	*
	7	* Author: Christian Ruppert <christian.ruppert@abilis.com>
b06eb017 CR	8	*/
	9
	10	#include <linux/interrupt.h>
	11	#include <linux/irqdomain.h>
	12	#include <linux/irq.h>
41a83e06	13	#include <linux/irqchip.h>
b06eb017 CR	14	#include <linux/of_irq.h>
	15	#include <linux/of_address.h>
	16	#include <linux/of_platform.h>
	17	#include <linux/io.h>
	18	#include <linux/slab.h>
	19	#include <linux/bitops.h>
b06eb017 CR	20
	21	#define AB_IRQCTL_INT_ENABLE 0x00
	22	#define AB_IRQCTL_INT_STATUS 0x04
	23	#define AB_IRQCTL_SRC_MODE 0x08
	24	#define AB_IRQCTL_SRC_POLARITY 0x0C
	25	#define AB_IRQCTL_INT_MODE 0x10
	26	#define AB_IRQCTL_INT_POLARITY 0x14
	27	#define AB_IRQCTL_INT_FORCE 0x18
	28
	29	#define AB_IRQCTL_MAXIRQ 32
	30
	31	static inline void ab_irqctl_writereg(struct irq_chip_generic *gc, u32 reg,
	32	u32 val)
	33	{
332fd7c4	34	irq_reg_writel(gc, val, reg);
b06eb017 CR	35	}
	36
	37	static inline u32 ab_irqctl_readreg(struct irq_chip_generic *gc, u32 reg)
	38	{
332fd7c4	39	return irq_reg_readl(gc, reg);
b06eb017 CR	40	}
	41
	42	static int tb10x_irq_set_type(struct irq_data *data, unsigned int flow_type)
	43	{
	44	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(data);
	45	uint32_t im, mod, pol;
	46
	47	im = data->mask;
	48
	49	irq_gc_lock(gc);
	50
	51	mod = ab_irqctl_readreg(gc, AB_IRQCTL_SRC_MODE) \| im;
	52	pol = ab_irqctl_readreg(gc, AB_IRQCTL_SRC_POLARITY) \| im;
	53
	54	switch (flow_type & IRQF_TRIGGER_MASK) {
	55	case IRQ_TYPE_EDGE_FALLING:
	56	pol ^= im;
	57	break;
	58	case IRQ_TYPE_LEVEL_HIGH:
	59	mod ^= im;
	60	break;
	61	case IRQ_TYPE_NONE:
	62	flow_type = IRQ_TYPE_LEVEL_LOW;
a6992bbe	63	fallthrough;
b06eb017 CR	64	case IRQ_TYPE_LEVEL_LOW:
	65	mod ^= im;
	66	pol ^= im;
	67	break;
	68	case IRQ_TYPE_EDGE_RISING:
	69	break;
	70	default:
	71	irq_gc_unlock(gc);
	72	pr_err("%s: Cannot assign multiple trigger modes to IRQ %d.\n",
	73	__func__, data->irq);
	74	return -EBADR;
	75	}
	76
	77	irqd_set_trigger_type(data, flow_type);
	78	irq_setup_alt_chip(data, flow_type);
	79
	80	ab_irqctl_writereg(gc, AB_IRQCTL_SRC_MODE, mod);
	81	ab_irqctl_writereg(gc, AB_IRQCTL_SRC_POLARITY, pol);
	82	ab_irqctl_writereg(gc, AB_IRQCTL_INT_STATUS, im);
	83
	84	irq_gc_unlock(gc);
	85
	86	return IRQ_SET_MASK_OK;
	87	}
	88
bd0b9ac4	89	static void tb10x_irq_cascade(struct irq_desc *desc)
b06eb017 CR	90	{
b06eb017 CR	91	struct irq_domain *domain = irq_desc_get_handler_data(desc);
e616e9af	92	unsigned int irq = irq_desc_get_irq(desc);
b06eb017	93
046a6ee2	94	generic_handle_domain_irq(domain, irq);
b06eb017 CR	95	}
	96
	97	static int __init of_tb10x_init_irq(struct device_node *ictl,
	98	struct device_node *parent)
	99	{
	100	int i, ret, nrirqs = of_irq_count(ictl);
	101	struct resource mem;
	102	struct irq_chip_generic *gc;
	103	struct irq_domain *domain;
	104	void __iomem *reg_base;
	105
	106	if (of_address_to_resource(ictl, 0, &mem)) {
2ef790dc RH	107	pr_err("%pOFn: No registers declared in DeviceTree.\n",
2ef790dc RH	108	ictl);
b06eb017 CR	109	return -EINVAL;
	110	}
	111
	112	if (!request_mem_region(mem.start, resource_size(&mem),
2ef790dc RH	113	ictl->full_name)) {
2ef790dc RH	114	pr_err("%pOFn: Request mem region failed.\n", ictl);
b06eb017 CR	115	return -EBUSY;
	116	}
	117
	118	reg_base = ioremap(mem.start, resource_size(&mem));
	119	if (!reg_base) {
	120	ret = -EBUSY;
2ef790dc	121	pr_err("%pOFn: ioremap failed.\n", ictl);
b06eb017 CR	122	goto ioremap_fail;
	123	}
	124
	125	domain = irq_domain_add_linear(ictl, AB_IRQCTL_MAXIRQ,
	126	&irq_generic_chip_ops, NULL);
	127	if (!domain) {
	128	ret = -ENOMEM;
2ef790dc RH	129	pr_err("%pOFn: Could not register interrupt domain.\n",
2ef790dc RH	130	ictl);
b06eb017 CR	131	goto irq_domain_add_fail;
	132	}
	133
	134	ret = irq_alloc_domain_generic_chips(domain, AB_IRQCTL_MAXIRQ,
	135	2, ictl->name, handle_level_irq,
	136	IRQ_NOREQUEST, IRQ_NOPROBE,
	137	IRQ_GC_INIT_MASK_CACHE);
	138	if (ret) {
2ef790dc RH	139	pr_err("%pOFn: Could not allocate generic interrupt chip.\n",
2ef790dc RH	140	ictl);
b06eb017 CR	141	goto gc_alloc_fail;
	142	}
	143
	144	gc = domain->gc->gc[0];
	145	gc->reg_base = reg_base;
	146
	147	gc->chip_types[0].type = IRQ_TYPE_LEVEL_MASK;
	148	gc->chip_types[0].chip.irq_mask = irq_gc_mask_clr_bit;
	149	gc->chip_types[0].chip.irq_unmask = irq_gc_mask_set_bit;
	150	gc->chip_types[0].chip.irq_set_type = tb10x_irq_set_type;
	151	gc->chip_types[0].regs.mask = AB_IRQCTL_INT_ENABLE;
	152
	153	gc->chip_types[1].type = IRQ_TYPE_EDGE_BOTH;
	154	gc->chip_types[1].chip.name = gc->chip_types[0].chip.name;
	155	gc->chip_types[1].chip.irq_ack = irq_gc_ack_set_bit;
	156	gc->chip_types[1].chip.irq_mask = irq_gc_mask_clr_bit;
	157	gc->chip_types[1].chip.irq_unmask = irq_gc_mask_set_bit;
	158	gc->chip_types[1].chip.irq_set_type = tb10x_irq_set_type;
	159	gc->chip_types[1].regs.ack = AB_IRQCTL_INT_STATUS;
	160	gc->chip_types[1].regs.mask = AB_IRQCTL_INT_ENABLE;
	161	gc->chip_types[1].handler = handle_edge_irq;
	162
	163	for (i = 0; i < nrirqs; i++) {
	164	unsigned int irq = irq_of_parse_and_map(ictl, i);
	165
22890b0d TG	166	irq_set_chained_handler_and_data(irq, tb10x_irq_cascade,
22890b0d TG	167	domain);
b06eb017 CR	168	}
	169
	170	ab_irqctl_writereg(gc, AB_IRQCTL_INT_ENABLE, 0);
	171	ab_irqctl_writereg(gc, AB_IRQCTL_INT_MODE, 0);
	172	ab_irqctl_writereg(gc, AB_IRQCTL_INT_POLARITY, 0);
	173	ab_irqctl_writereg(gc, AB_IRQCTL_INT_STATUS, ~0UL);
	174
	175	return 0;
	176
	177	gc_alloc_fail:
	178	irq_domain_remove(domain);
	179	irq_domain_add_fail:
	180	iounmap(reg_base);
	181	ioremap_fail:
	182	release_mem_region(mem.start, resource_size(&mem));
	183	return ret;
	184	}
	185	IRQCHIP_DECLARE(tb10x_intc, "abilis,tb10x-ictl", of_tb10x_init_irq);