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eedbdab9 | 1 | /* |
968674bd MS |
2 | * Copyright (C) 2007-2013 Michal Simek <monstr@monstr.eu> |
3 | * Copyright (C) 2012-2013 Xilinx, Inc. | |
eedbdab9 MS |
4 | * Copyright (C) 2007-2009 PetaLogix |
5 | * Copyright (C) 2006 Atmark Techno, Inc. | |
6 | * | |
7 | * This file is subject to the terms and conditions of the GNU General Public | |
8 | * License. See the file "COPYING" in the main directory of this archive | |
9 | * for more details. | |
10 | */ | |
11 | ||
2462bacd | 12 | #include <linux/irqdomain.h> |
eedbdab9 | 13 | #include <linux/irq.h> |
fd4b267b | 14 | #include <linux/irqchip.h> |
9689c99e | 15 | #include <linux/irqchip/chained_irq.h> |
bcff661d | 16 | #include <linux/of_address.h> |
eedbdab9 | 17 | #include <linux/io.h> |
591db74b | 18 | #include <linux/jump_label.h> |
892ee92b | 19 | #include <linux/bug.h> |
9689c99e | 20 | #include <linux/of_irq.h> |
eedbdab9 | 21 | |
eedbdab9 MS |
22 | /* No one else should require these constants, so define them locally here. */ |
23 | #define ISR 0x00 /* Interrupt Status Register */ | |
24 | #define IPR 0x04 /* Interrupt Pending Register */ | |
25 | #define IER 0x08 /* Interrupt Enable Register */ | |
26 | #define IAR 0x0c /* Interrupt Acknowledge Register */ | |
27 | #define SIE 0x10 /* Set Interrupt Enable bits */ | |
28 | #define CIE 0x14 /* Clear Interrupt Enable bits */ | |
29 | #define IVR 0x18 /* Interrupt Vector Register */ | |
30 | #define MER 0x1c /* Master Enable Register */ | |
31 | ||
32 | #define MER_ME (1<<0) | |
33 | #define MER_HIE (1<<1) | |
34 | ||
591db74b | 35 | static DEFINE_STATIC_KEY_FALSE(xintc_is_be); |
1aa1243c | 36 | |
591db74b ZLK |
37 | struct xintc_irq_chip { |
38 | void __iomem *base; | |
39 | struct irq_domain *root_domain; | |
40 | u32 intr_mask; | |
41 | }; | |
1aa1243c | 42 | |
591db74b | 43 | static struct xintc_irq_chip *xintc_irqc; |
1aa1243c | 44 | |
591db74b | 45 | static void xintc_write(int reg, u32 data) |
1aa1243c | 46 | { |
591db74b ZLK |
47 | if (static_branch_unlikely(&xintc_is_be)) |
48 | iowrite32be(data, xintc_irqc->base + reg); | |
49 | else | |
50 | iowrite32(data, xintc_irqc->base + reg); | |
1aa1243c MS |
51 | } |
52 | ||
591db74b | 53 | static unsigned int xintc_read(int reg) |
1aa1243c | 54 | { |
591db74b ZLK |
55 | if (static_branch_unlikely(&xintc_is_be)) |
56 | return ioread32be(xintc_irqc->base + reg); | |
57 | else | |
58 | return ioread32(xintc_irqc->base + reg); | |
1aa1243c MS |
59 | } |
60 | ||
6f205a4c | 61 | static void intc_enable_or_unmask(struct irq_data *d) |
eedbdab9 | 62 | { |
6c7a2676 MS |
63 | unsigned long mask = 1 << d->hwirq; |
64 | ||
a5734de2 | 65 | pr_debug("irq-xilinx: enable_or_unmask: %ld\n", d->hwirq); |
33d9ff59 | 66 | |
67 | /* ack level irqs because they can't be acked during | |
68 | * ack function since the handle_level_irq function | |
69 | * acks the irq before calling the interrupt handler | |
70 | */ | |
4adc192e | 71 | if (irqd_is_level_type(d)) |
591db74b | 72 | xintc_write(IAR, mask); |
7958a689 | 73 | |
591db74b | 74 | xintc_write(SIE, mask); |
eedbdab9 MS |
75 | } |
76 | ||
6f205a4c | 77 | static void intc_disable_or_mask(struct irq_data *d) |
eedbdab9 | 78 | { |
a5734de2 | 79 | pr_debug("irq-xilinx: disable: %ld\n", d->hwirq); |
591db74b | 80 | xintc_write(CIE, 1 << d->hwirq); |
eedbdab9 MS |
81 | } |
82 | ||
6f205a4c | 83 | static void intc_ack(struct irq_data *d) |
eedbdab9 | 84 | { |
a5734de2 | 85 | pr_debug("irq-xilinx: ack: %ld\n", d->hwirq); |
591db74b | 86 | xintc_write(IAR, 1 << d->hwirq); |
eedbdab9 MS |
87 | } |
88 | ||
6f205a4c | 89 | static void intc_mask_ack(struct irq_data *d) |
eedbdab9 | 90 | { |
6c7a2676 MS |
91 | unsigned long mask = 1 << d->hwirq; |
92 | ||
a5734de2 | 93 | pr_debug("irq-xilinx: disable_and_ack: %ld\n", d->hwirq); |
591db74b ZLK |
94 | xintc_write(CIE, mask); |
95 | xintc_write(IAR, mask); | |
eedbdab9 MS |
96 | } |
97 | ||
eedbdab9 MS |
98 | static struct irq_chip intc_dev = { |
99 | .name = "Xilinx INTC", | |
6f205a4c TG |
100 | .irq_unmask = intc_enable_or_unmask, |
101 | .irq_mask = intc_disable_or_mask, | |
102 | .irq_ack = intc_ack, | |
103 | .irq_mask_ack = intc_mask_ack, | |
eedbdab9 MS |
104 | }; |
105 | ||
2120a435 | 106 | unsigned int xintc_get_irq(void) |
eedbdab9 | 107 | { |
2462bacd | 108 | unsigned int hwirq, irq = -1; |
eedbdab9 | 109 | |
591db74b | 110 | hwirq = xintc_read(IVR); |
2462bacd | 111 | if (hwirq != -1U) |
591db74b | 112 | irq = irq_find_mapping(xintc_irqc->root_domain, hwirq); |
2462bacd | 113 | |
a5734de2 | 114 | pr_debug("irq-xilinx: hwirq=%d, irq=%d\n", hwirq, irq); |
eedbdab9 MS |
115 | |
116 | return irq; | |
117 | } | |
118 | ||
c0d997fb | 119 | static int xintc_map(struct irq_domain *d, unsigned int irq, irq_hw_number_t hw) |
2462bacd | 120 | { |
591db74b | 121 | if (xintc_irqc->intr_mask & (1 << hw)) { |
2462bacd GL |
122 | irq_set_chip_and_handler_name(irq, &intc_dev, |
123 | handle_edge_irq, "edge"); | |
124 | irq_clear_status_flags(irq, IRQ_LEVEL); | |
125 | } else { | |
126 | irq_set_chip_and_handler_name(irq, &intc_dev, | |
127 | handle_level_irq, "level"); | |
128 | irq_set_status_flags(irq, IRQ_LEVEL); | |
129 | } | |
130 | return 0; | |
131 | } | |
132 | ||
133 | static const struct irq_domain_ops xintc_irq_domain_ops = { | |
134 | .xlate = irq_domain_xlate_onetwocell, | |
135 | .map = xintc_map, | |
136 | }; | |
137 | ||
9689c99e ZLK |
138 | static void xil_intc_irq_handler(struct irq_desc *desc) |
139 | { | |
140 | struct irq_chip *chip = irq_desc_get_chip(desc); | |
141 | u32 pending; | |
142 | ||
143 | chained_irq_enter(chip, desc); | |
144 | do { | |
145 | pending = xintc_get_irq(); | |
146 | if (pending == -1U) | |
147 | break; | |
148 | generic_handle_irq(pending); | |
149 | } while (true); | |
150 | chained_irq_exit(chip, desc); | |
151 | } | |
152 | ||
8a9e90a1 MS |
153 | static int __init xilinx_intc_of_init(struct device_node *intc, |
154 | struct device_node *parent) | |
eedbdab9 | 155 | { |
591db74b | 156 | u32 nr_irq; |
9689c99e | 157 | int ret, irq; |
591db74b | 158 | struct xintc_irq_chip *irqc; |
eedbdab9 | 159 | |
591db74b ZLK |
160 | if (xintc_irqc) { |
161 | pr_err("irq-xilinx: Multiple instances aren't supported\n"); | |
162 | return -EINVAL; | |
163 | } | |
164 | ||
165 | irqc = kzalloc(sizeof(*irqc), GFP_KERNEL); | |
166 | if (!irqc) | |
167 | return -ENOMEM; | |
168 | ||
169 | xintc_irqc = irqc; | |
170 | ||
171 | irqc->base = of_iomap(intc, 0); | |
172 | BUG_ON(!irqc->base); | |
bcff661d MS |
173 | |
174 | ret = of_property_read_u32(intc, "xlnx,num-intr-inputs", &nr_irq); | |
175 | if (ret < 0) { | |
a5734de2 | 176 | pr_err("irq-xilinx: unable to read xlnx,num-intr-inputs\n"); |
591db74b | 177 | goto err_alloc; |
bcff661d MS |
178 | } |
179 | ||
591db74b | 180 | ret = of_property_read_u32(intc, "xlnx,kind-of-intr", &irqc->intr_mask); |
bcff661d | 181 | if (ret < 0) { |
8a11da59 ZLK |
182 | pr_warn("irq-xilinx: unable to read xlnx,kind-of-intr\n"); |
183 | irqc->intr_mask = 0; | |
bcff661d | 184 | } |
eedbdab9 | 185 | |
591db74b | 186 | if (irqc->intr_mask >> nr_irq) |
a5734de2 | 187 | pr_warn("irq-xilinx: mismatch in kind-of-intr param\n"); |
eedbdab9 | 188 | |
a5734de2 | 189 | pr_info("irq-xilinx: %s: num_irq=%d, edge=0x%x\n", |
591db74b | 190 | intc->full_name, nr_irq, irqc->intr_mask); |
eedbdab9 | 191 | |
1aa1243c | 192 | |
eedbdab9 MS |
193 | /* |
194 | * Disable all external interrupts until they are | |
195 | * explicity requested. | |
196 | */ | |
591db74b | 197 | xintc_write(IER, 0); |
eedbdab9 MS |
198 | |
199 | /* Acknowledge any pending interrupts just in case. */ | |
591db74b | 200 | xintc_write(IAR, 0xffffffff); |
eedbdab9 MS |
201 | |
202 | /* Turn on the Master Enable. */ | |
591db74b ZLK |
203 | xintc_write(MER, MER_HIE | MER_ME); |
204 | if (!(xintc_read(MER) & (MER_HIE | MER_ME))) { | |
205 | static_branch_enable(&xintc_is_be); | |
206 | xintc_write(MER, MER_HIE | MER_ME); | |
1aa1243c | 207 | } |
eedbdab9 | 208 | |
591db74b ZLK |
209 | irqc->root_domain = irq_domain_add_linear(intc, nr_irq, |
210 | &xintc_irq_domain_ops, irqc); | |
211 | if (!irqc->root_domain) { | |
212 | pr_err("irq-xilinx: Unable to create IRQ domain\n"); | |
213 | goto err_alloc; | |
214 | } | |
7c2c8513 | 215 | |
9689c99e ZLK |
216 | if (parent) { |
217 | irq = irq_of_parse_and_map(intc, 0); | |
218 | if (irq) { | |
219 | irq_set_chained_handler_and_data(irq, | |
220 | xil_intc_irq_handler, | |
221 | irqc); | |
222 | } else { | |
223 | pr_err("irq-xilinx: interrupts property not in DT\n"); | |
224 | ret = -EINVAL; | |
225 | goto err_alloc; | |
226 | } | |
227 | } else { | |
228 | irq_set_default_host(irqc->root_domain); | |
229 | } | |
8a9e90a1 MS |
230 | |
231 | return 0; | |
591db74b ZLK |
232 | |
233 | err_alloc: | |
234 | xintc_irqc = NULL; | |
235 | kfree(irqc); | |
236 | return ret; | |
237 | ||
eedbdab9 | 238 | } |
8a9e90a1 | 239 | |
8328255f ZLK |
240 | IRQCHIP_DECLARE(xilinx_intc_xps, "xlnx,xps-intc-1.00.a", xilinx_intc_of_init); |
241 | IRQCHIP_DECLARE(xilinx_intc_opb, "xlnx,opb-intc-1.00.c", xilinx_intc_of_init); |