[mirror_ubuntu-hirsute-kernel.git] / drivers / irqchip / qcom-irq-combiner.c

// SPDX-License-Identifier: GPL-2.0-only
/* Copyright (c) 2015-2018, The Linux Foundation. All rights reserved.
 */

/*
 * Driver for interrupt combiners in the Top-level Control and Status
 * Registers (TCSR) hardware block in Qualcomm Technologies chips.
 * An interrupt combiner in this block combines a set of interrupts by
 * OR'ing the individual interrupt signals into a summary interrupt
 * signal routed to a parent interrupt controller, and provides read-
 * only, 32-bit registers to query the status of individual interrupts.
 * The status bit for IRQ n is bit (n % 32) within register (n / 32)
 * of the given combiner. Thus, each combiner can be described as a set
 * of register offsets and the number of IRQs managed.
 */

#define pr_fmt(fmt) "QCOM80B1:" fmt

#include <linux/acpi.h>
#include <linux/irqchip/chained_irq.h>
#include <linux/irqdomain.h>
#include <linux/platform_device.h>

#define REG_SIZE 32

struct combiner_reg {
	void __iomem *addr;
	unsigned long enabled;
};

struct combiner {
	struct irq_domain   *domain;
	int                 parent_irq;
	u32                 nirqs;
	u32                 nregs;
	struct combiner_reg regs[0];
};

static inline int irq_nr(u32 reg, u32 bit)
{
	return reg * REG_SIZE + bit;
}

/*
 * Handler for the cascaded IRQ.
 */
static void combiner_handle_irq(struct irq_desc *desc)
{
	struct combiner *combiner = irq_desc_get_handler_data(desc);
	struct irq_chip *chip = irq_desc_get_chip(desc);
	u32 reg;

	chained_irq_enter(chip, desc);

	for (reg = 0; reg < combiner->nregs; reg++) {
		int virq;
		int hwirq;
		u32 bit;
		u32 status;

		bit = readl_relaxed(combiner->regs[reg].addr);
		status = bit & combiner->regs[reg].enabled;
		if (bit && !status)
			pr_warn_ratelimited("Unexpected IRQ on CPU%d: (%08x %08lx %p)\n",
					    smp_processor_id(), bit,
					    combiner->regs[reg].enabled,
					    combiner->regs[reg].addr);

		while (status) {
			bit = __ffs(status);
			status &= ~(1 << bit);
			hwirq = irq_nr(reg, bit);
			virq = irq_find_mapping(combiner->domain, hwirq);
			if (virq > 0)
				generic_handle_irq(virq);

		}
	}

	chained_irq_exit(chip, desc);
}

static void combiner_irq_chip_mask_irq(struct irq_data *data)
{
	struct combiner *combiner = irq_data_get_irq_chip_data(data);
	struct combiner_reg *reg = combiner->regs + data->hwirq / REG_SIZE;

	clear_bit(data->hwirq % REG_SIZE, &reg->enabled);
}

static void combiner_irq_chip_unmask_irq(struct irq_data *data)
{
	struct combiner *combiner = irq_data_get_irq_chip_data(data);
	struct combiner_reg *reg = combiner->regs + data->hwirq / REG_SIZE;

	set_bit(data->hwirq % REG_SIZE, &reg->enabled);
}

static struct irq_chip irq_chip = {
	.irq_mask = combiner_irq_chip_mask_irq,
	.irq_unmask = combiner_irq_chip_unmask_irq,
	.name = "qcom-irq-combiner"
};

static int combiner_irq_map(struct irq_domain *domain, unsigned int irq,
				   irq_hw_number_t hwirq)
{
	irq_set_chip_and_handler(irq, &irq_chip, handle_level_irq);
	irq_set_chip_data(irq, domain->host_data);
	irq_set_noprobe(irq);
	return 0;
}

static void combiner_irq_unmap(struct irq_domain *domain, unsigned int irq)
{
	irq_domain_reset_irq_data(irq_get_irq_data(irq));
}

static int combiner_irq_translate(struct irq_domain *d, struct irq_fwspec *fws,
				  unsigned long *hwirq, unsigned int *type)
{
	struct combiner *combiner = d->host_data;

	if (is_acpi_node(fws->fwnode)) {
		if (WARN_ON((fws->param_count != 2) ||
			    (fws->param[0] >= combiner->nirqs) ||
			    (fws->param[1] & IORESOURCE_IRQ_LOWEDGE) ||
			    (fws->param[1] & IORESOURCE_IRQ_HIGHEDGE)))
			return -EINVAL;

		*hwirq = fws->param[0];
		*type = fws->param[1];
		return 0;
	}

	return -EINVAL;
}

static const struct irq_domain_ops domain_ops = {
	.map = combiner_irq_map,
	.unmap = combiner_irq_unmap,
	.translate = combiner_irq_translate
};

static acpi_status count_registers_cb(struct acpi_resource *ares, void *context)
{
	int *count = context;

	if (ares->type == ACPI_RESOURCE_TYPE_GENERIC_REGISTER)
		++(*count);
	return AE_OK;
}

static int count_registers(struct platform_device *pdev)
{
	acpi_handle ahandle = ACPI_HANDLE(&pdev->dev);
	acpi_status status;
	int count = 0;

	if (!acpi_has_method(ahandle, METHOD_NAME__CRS))
		return -EINVAL;

	status = acpi_walk_resources(ahandle, METHOD_NAME__CRS,
				     count_registers_cb, &count);
	if (ACPI_FAILURE(status))
		return -EINVAL;
	return count;
}

struct get_registers_context {
	struct device *dev;
	struct combiner *combiner;
	int err;
};

static acpi_status get_registers_cb(struct acpi_resource *ares, void *context)
{
	struct get_registers_context *ctx = context;
	struct acpi_resource_generic_register *reg;
	phys_addr_t paddr;
	void __iomem *vaddr;

	if (ares->type != ACPI_RESOURCE_TYPE_GENERIC_REGISTER)
		return AE_OK;

	reg = &ares->data.generic_reg;
	paddr = reg->address;
	if ((reg->space_id != ACPI_SPACE_MEM) ||
	    (reg->bit_offset != 0) ||
	    (reg->bit_width > REG_SIZE)) {
		dev_err(ctx->dev, "Bad register resource @%pa\n", &paddr);
		ctx->err = -EINVAL;
		return AE_ERROR;
	}

	vaddr = devm_ioremap(ctx->dev, reg->address, REG_SIZE);
	if (!vaddr) {
		dev_err(ctx->dev, "Can't map register @%pa\n", &paddr);
		ctx->err = -ENOMEM;
		return AE_ERROR;
	}

	ctx->combiner->regs[ctx->combiner->nregs].addr = vaddr;
	ctx->combiner->nirqs += reg->bit_width;
	ctx->combiner->nregs++;
	return AE_OK;
}

static int get_registers(struct platform_device *pdev, struct combiner *comb)
{
	acpi_handle ahandle = ACPI_HANDLE(&pdev->dev);
	acpi_status status;
	struct get_registers_context ctx;

	if (!acpi_has_method(ahandle, METHOD_NAME__CRS))
		return -EINVAL;

	ctx.dev = &pdev->dev;
	ctx.combiner = comb;
	ctx.err = 0;

	status = acpi_walk_resources(ahandle, METHOD_NAME__CRS,
				     get_registers_cb, &ctx);
	if (ACPI_FAILURE(status))
		return ctx.err;
	return 0;
}

static int __init combiner_probe(struct platform_device *pdev)
{
	struct combiner *combiner;
	int nregs;
	int err;

	nregs = count_registers(pdev);
	if (nregs <= 0) {
		dev_err(&pdev->dev, "Error reading register resources\n");
		return -EINVAL;
	}

	combiner = devm_kzalloc(&pdev->dev, struct_size(combiner, regs, nregs),
				GFP_KERNEL);
	if (!combiner)
		return -ENOMEM;

	err = get_registers(pdev, combiner);
	if (err < 0)
		return err;

	combiner->parent_irq = platform_get_irq(pdev, 0);
	if (combiner->parent_irq <= 0)
		return -EPROBE_DEFER;

	combiner->domain = irq_domain_create_linear(pdev->dev.fwnode, combiner->nirqs,
						    &domain_ops, combiner);
	if (!combiner->domain)
		/* Errors printed by irq_domain_create_linear */
		return -ENODEV;

	irq_set_chained_handler_and_data(combiner->parent_irq,
					 combiner_handle_irq, combiner);

	dev_info(&pdev->dev, "Initialized with [p=%d,n=%d,r=%p]\n",
		 combiner->parent_irq, combiner->nirqs, combiner->regs[0].addr);
	return 0;
}

static const struct acpi_device_id qcom_irq_combiner_ids[] = {
	{ "QCOM80B1", },
	{ }
};

static struct platform_driver qcom_irq_combiner_probe = {
	.driver = {
		.name = "qcom-irq-combiner",
		.acpi_match_table = ACPI_PTR(qcom_irq_combiner_ids),
	},
	.probe = combiner_probe,
};
builtin_platform_driver(qcom_irq_combiner_probe);
Commit	Line	Data
97fb5e8d	1	// SPDX-License-Identifier: GPL-2.0-only
1bc2463c	2	/* Copyright (c) 2015-2018, The Linux Foundation. All rights reserved.
f20cc9b0 AVF	3	*/
	4
	5	/*
	6	* Driver for interrupt combiners in the Top-level Control and Status
	7	* Registers (TCSR) hardware block in Qualcomm Technologies chips.
	8	* An interrupt combiner in this block combines a set of interrupts by
	9	* OR'ing the individual interrupt signals into a summary interrupt
	10	* signal routed to a parent interrupt controller, and provides read-
	11	* only, 32-bit registers to query the status of individual interrupts.
	12	* The status bit for IRQ n is bit (n % 32) within register (n / 32)
	13	* of the given combiner. Thus, each combiner can be described as a set
	14	* of register offsets and the number of IRQs managed.
	15	*/
	16
	17	#define pr_fmt(fmt) "QCOM80B1:" fmt
	18
	19	#include <linux/acpi.h>
	20	#include <linux/irqchip/chained_irq.h>
	21	#include <linux/irqdomain.h>
	22	#include <linux/platform_device.h>
	23
	24	#define REG_SIZE 32
	25
	26	struct combiner_reg {
	27	void __iomem *addr;
	28	unsigned long enabled;
	29	};
	30
	31	struct combiner {
	32	struct irq_domain *domain;
	33	int parent_irq;
	34	u32 nirqs;
	35	u32 nregs;
	36	struct combiner_reg regs[0];
	37	};
	38
	39	static inline int irq_nr(u32 reg, u32 bit)
	40	{
	41	return reg * REG_SIZE + bit;
	42	}
	43
	44	/*
	45	* Handler for the cascaded IRQ.
	46	*/
	47	static void combiner_handle_irq(struct irq_desc *desc)
	48	{
	49	struct combiner *combiner = irq_desc_get_handler_data(desc);
	50	struct irq_chip *chip = irq_desc_get_chip(desc);
	51	u32 reg;
	52
	53	chained_irq_enter(chip, desc);
	54
	55	for (reg = 0; reg < combiner->nregs; reg++) {
	56	int virq;
	57	int hwirq;
	58	u32 bit;
	59	u32 status;
	60
	61	bit = readl_relaxed(combiner->regs[reg].addr);
	62	status = bit & combiner->regs[reg].enabled;
1bc2463c	63	if (bit && !status)
f20cc9b0 AVF	64	pr_warn_ratelimited("Unexpected IRQ on CPU%d: (%08x %08lx %p)\n",
	65	smp_processor_id(), bit,
	66	combiner->regs[reg].enabled,
	67	combiner->regs[reg].addr);
	68
	69	while (status) {
	70	bit = __ffs(status);
	71	status &= ~(1 << bit);
	72	hwirq = irq_nr(reg, bit);
	73	virq = irq_find_mapping(combiner->domain, hwirq);
	74	if (virq > 0)
	75	generic_handle_irq(virq);
	76
	77	}
	78	}
	79
	80	chained_irq_exit(chip, desc);
	81	}
	82
	83	static void combiner_irq_chip_mask_irq(struct irq_data *data)
	84	{
	85	struct combiner *combiner = irq_data_get_irq_chip_data(data);
	86	struct combiner_reg *reg = combiner->regs + data->hwirq / REG_SIZE;
	87
	88	clear_bit(data->hwirq % REG_SIZE, &reg->enabled);
	89	}
	90
	91	static void combiner_irq_chip_unmask_irq(struct irq_data *data)
	92	{
	93	struct combiner *combiner = irq_data_get_irq_chip_data(data);
	94	struct combiner_reg *reg = combiner->regs + data->hwirq / REG_SIZE;
	95
	96	set_bit(data->hwirq % REG_SIZE, &reg->enabled);
	97	}
	98
	99	static struct irq_chip irq_chip = {
	100	.irq_mask = combiner_irq_chip_mask_irq,
	101	.irq_unmask = combiner_irq_chip_unmask_irq,
	102	.name = "qcom-irq-combiner"
	103	};
	104
	105	static int combiner_irq_map(struct irq_domain *domain, unsigned int irq,
	106	irq_hw_number_t hwirq)
	107	{
	108	irq_set_chip_and_handler(irq, &irq_chip, handle_level_irq);
	109	irq_set_chip_data(irq, domain->host_data);
	110	irq_set_noprobe(irq);
	111	return 0;
	112	}
	113
	114	static void combiner_irq_unmap(struct irq_domain *domain, unsigned int irq)
	115	{
	116	irq_domain_reset_irq_data(irq_get_irq_data(irq));
	117	}
	118
	119	static int combiner_irq_translate(struct irq_domain d, struct irq_fwspec fws,
	120	unsigned long hwirq, unsigned int type)
	121	{
	122	struct combiner *combiner = d->host_data;
	123
	124	if (is_acpi_node(fws->fwnode)) {
	125	if (WARN_ON((fws->param_count != 2) \|\|
	126	(fws->param[0] >= combiner->nirqs) \|\|
	127	(fws->param[1] & IORESOURCE_IRQ_LOWEDGE) \|\|
128	(fws->param[1] & IORESOURCE_IRQ_HIGHEDGE)))
129	return -EINVAL;
130
131	*hwirq = fws->param[0];
132	*type = fws->param[1];
133	return 0;
134	}
135
136	return -EINVAL;
137	}
138
139	static const struct irq_domain_ops domain_ops = {
140	.map = combiner_irq_map,
141	.unmap = combiner_irq_unmap,
142	.translate = combiner_irq_translate
143	};
144
145	static acpi_status count_registers_cb(struct acpi_resource ares, void context)
146	{
147	int *count = context;
148
149	if (ares->type == ACPI_RESOURCE_TYPE_GENERIC_REGISTER)
150	++(*count);
151	return AE_OK;
152	}
153
154	static int count_registers(struct platform_device *pdev)
155	{
156	acpi_handle ahandle = ACPI_HANDLE(&pdev->dev);
157	acpi_status status;
158	int count = 0;
159
160	if (!acpi_has_method(ahandle, METHOD_NAME__CRS))
161	return -EINVAL;
162
163	status = acpi_walk_resources(ahandle, METHOD_NAME__CRS,
164	count_registers_cb, &count);
165	if (ACPI_FAILURE(status))
166	return -EINVAL;
167	return count;
168	}
169
170	struct get_registers_context {
171	struct device *dev;
172	struct combiner *combiner;
173	int err;
174	};
175
176	static acpi_status get_registers_cb(struct acpi_resource ares, void context)
177	{
178	struct get_registers_context *ctx = context;
179	struct acpi_resource_generic_register *reg;
180	phys_addr_t paddr;
181	void __iomem *vaddr;
182
183	if (ares->type != ACPI_RESOURCE_TYPE_GENERIC_REGISTER)
184	return AE_OK;
185
186	reg = &ares->data.generic_reg;
187	paddr = reg->address;
188	if ((reg->space_id != ACPI_SPACE_MEM) \|\|
189	(reg->bit_offset != 0) \|\|
190	(reg->bit_width > REG_SIZE)) {
191	dev_err(ctx->dev, "Bad register resource @%pa\n", &paddr);
192	ctx->err = -EINVAL;
193	return AE_ERROR;
194	}
195
196	vaddr = devm_ioremap(ctx->dev, reg->address, REG_SIZE);
3900dea4	197	if (!vaddr) {
f20cc9b0	198	dev_err(ctx->dev, "Can't map register @%pa\n", &paddr);
3900dea4	199	ctx->err = -ENOMEM;
f20cc9b0 AVF	200	return AE_ERROR;
	201	}
	202
	203	ctx->combiner->regs[ctx->combiner->nregs].addr = vaddr;
	204	ctx->combiner->nirqs += reg->bit_width;
	205	ctx->combiner->nregs++;
	206	return AE_OK;
	207	}
	208
	209	static int get_registers(struct platform_device pdev, struct combiner comb)
	210	{
	211	acpi_handle ahandle = ACPI_HANDLE(&pdev->dev);
	212	acpi_status status;
	213	struct get_registers_context ctx;
	214
	215	if (!acpi_has_method(ahandle, METHOD_NAME__CRS))
	216	return -EINVAL;
	217
	218	ctx.dev = &pdev->dev;
	219	ctx.combiner = comb;
	220	ctx.err = 0;
	221
	222	status = acpi_walk_resources(ahandle, METHOD_NAME__CRS,
	223	get_registers_cb, &ctx);
	224	if (ACPI_FAILURE(status))
	225	return ctx.err;
	226	return 0;
	227	}
	228
	229	static int __init combiner_probe(struct platform_device *pdev)
	230	{
	231	struct combiner *combiner;
e9990d70	232	int nregs;
f20cc9b0 AVF	233	int err;
	234
	235	nregs = count_registers(pdev);
	236	if (nregs <= 0) {
	237	dev_err(&pdev->dev, "Error reading register resources\n");
	238	return -EINVAL;
	239	}
	240
b744c3bc GS	241	combiner = devm_kzalloc(&pdev->dev, struct_size(combiner, regs, nregs),
b744c3bc GS	242	GFP_KERNEL);
f20cc9b0 AVF	243	if (!combiner)
	244	return -ENOMEM;
	245
	246	err = get_registers(pdev, combiner);
	247	if (err < 0)
	248	return err;
	249
	250	combiner->parent_irq = platform_get_irq(pdev, 0);
6c9050a7	251	if (combiner->parent_irq <= 0)
f20cc9b0	252	return -EPROBE_DEFER;
f20cc9b0 AVF	253
	254	combiner->domain = irq_domain_create_linear(pdev->dev.fwnode, combiner->nirqs,
	255	&domain_ops, combiner);
	256	if (!combiner->domain)
	257	/* Errors printed by irq_domain_create_linear */
	258	return -ENODEV;
	259
	260	irq_set_chained_handler_and_data(combiner->parent_irq,
	261	combiner_handle_irq, combiner);
	262
	263	dev_info(&pdev->dev, "Initialized with [p=%d,n=%d,r=%p]\n",
	264	combiner->parent_irq, combiner->nirqs, combiner->regs[0].addr);
	265	return 0;
	266	}
	267
	268	static const struct acpi_device_id qcom_irq_combiner_ids[] = {
	269	{ "QCOM80B1", },
	270	{ }
	271	};
	272
	273	static struct platform_driver qcom_irq_combiner_probe = {
	274	.driver = {
	275	.name = "qcom-irq-combiner",
	276	.acpi_match_table = ACPI_PTR(qcom_irq_combiner_ids),
	277	},
	278	.probe = combiner_probe,
	279	};
a1628366	280	builtin_platform_driver(qcom_irq_combiner_probe);